JP2008205738A - Operational amplifier - Google Patents

Operational amplifier Download PDF

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JP2008205738A
JP2008205738A JP2007038477A JP2007038477A JP2008205738A JP 2008205738 A JP2008205738 A JP 2008205738A JP 2007038477 A JP2007038477 A JP 2007038477A JP 2007038477 A JP2007038477 A JP 2007038477A JP 2008205738 A JP2008205738 A JP 2008205738A
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input terminal
voltage
transistor
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Kazuhiro Takatori
和宏 高鳥
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To accelerate a slew rate, and increase a pulse response speed when an input differential speed exceeds a predetermined value. <P>SOLUTION: The operational amplifier is provided with a differential input circuit (Q1, Q2, I1 to I3) connected to a non-inverting input terminal IN+ and an inverting input terminal IN-, an output circuit (Q3 to Q6, R1, R2, V1) which performs current discharge/absorption according to the polarity and size of input differential voltage to the normal input terminal and the inverting input terminal of the differential circuit, and a capacitor Cc which performs charge/discharge according to (current discharge)/(current absorption) of the output circuit. It is provided with a discharge current addition circuit (QA2, QA3, QA5, QA7) which supplies additional absorption current to the capacitor Cc if voltage of the non-inverting input terminal IN+ becomes higher beyond a predetermined value from voltage of the inverting input terminal IN-, and an absorption current addition circuit (QA1, QA4, QA6, QA8) which supplies an additional absorption current to the capacitor Cc if the voltage of the non-inverting input terminal IN+ becomes lower beyond a predetermined value from the voltage of the inverting input terminal IN-. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、高レベルのパルス信号が入力する際に高スルーレートを実現した演算増幅器に関するものである。   The present invention relates to an operational amplifier that realizes a high slew rate when a high-level pulse signal is input.

図６に従来例の演算増幅器２０の構成を示す。Ｑ１，Ｑ２，Ｑ５，Ｑ６はＰＮＰトランジスタ、Ｑ３，Ｑ４はＮＰＮトランジスタ、Ｒ１，Ｒ２は抵抗、Ｃｃはコンデンサ、Ｉ１，Ｉ２，Ｉ３は電流源（Ｉ１＝Ｉ２＝Ｉ３）、Ｖ１は電圧源、Ｘ１はバッファである。Ｖ＋およびＶ−はそれぞれ第１電源および第２電源、ＩＮ＋は正転入力端子、ＩＮ−は反転入力端子、ＯＵＴは出力端子である。   FIG. 6 shows a configuration of a conventional operational amplifier 20. Q1, Q2, Q5, Q6 are PNP transistors, Q3, Q4 are NPN transistors, R1, R2 are resistors, Cc is a capacitor, I1, I2, I3 are current sources (I1 = I2 = I3), V1 is a voltage source, X1 Is a buffer. V + and V− are a first power supply and a second power supply, IN + is a normal input terminal, IN− is an inverting input terminal, and OUT is an output terminal.

トランジスタＱ１，Ｑ２と電流源Ｉ３は差動入力回路を構成する。トランジスタＱ３，Ｑ４は電圧Ｖ１で固定バイアスされたベース接地回路であり、前記差動入力回路の出力信号で駆動され、カレントミラー回路（ミラー比＝１）を構成するＱ５，Ｑ６と共に出力回路を構成する。抵抗Ｒ１，Ｒ２は負荷用、コンデンサＣｃは位相補償用である。   Transistors Q1, Q2 and current source I3 constitute a differential input circuit. Transistors Q3 and Q4 are grounded base circuits that are fixedly biased at voltage V1 and are driven by the output signal of the differential input circuit to form an output circuit together with Q5 and Q6 constituting a current mirror circuit (mirror ratio = 1). To do. The resistors R1 and R2 are for loads, and the capacitor Cc is for phase compensation.

この演算増幅器２０を、図２に示すように、反転入力端子ＩＮ−を出力端子ＯＵＴに接続してボルテージホロワ回路を構成し、正転入力端子ＩＮ＋に、低電圧ＶＬと高電圧ＶＨの間で変化するパルス信号Ｓ１を入力させたときの動作を説明する。   As shown in FIG. 2, the operational amplifier 20 is connected to the inverting input terminal IN− to the output terminal OUT to form a voltage follower circuit, and between the low voltage VL and the high voltage VH is connected to the normal input terminal IN +. The operation when the pulse signal S1 that changes in (1) is input will be described.

最初、パルス信号Ｓ１が低電圧ＶＬの時は、両入力端子ＩＮ＋とＩＮ−は同電圧（＝ＶＬ）である。次に、正転入力端子ＩＮ＋に高電圧ＶＨが任意の傾斜をもって印加されると、トランジスタＱ２がオフ状態となり、トランジスタＱ１がオン状態となり、電流源Ｉ３の全電流がトランジスタＱ１のコレクタに流れる。一方、トランジスタＱ２のコレクタ電流はゼロとなる。このとき、電流源Ｉ１のノードＮ１の電圧は＋Ｖ方向に上昇し、電流源Ｉ２のノードＮ２の電圧は−Ｖ方向に下降する。   Initially, when the pulse signal S1 is at a low voltage VL, both input terminals IN + and IN- are at the same voltage (= VL). Next, when the high voltage VH is applied to the normal input terminal IN + with an arbitrary slope, the transistor Q2 is turned off, the transistor Q1 is turned on, and the entire current of the current source I3 flows to the collector of the transistor Q1. On the other hand, the collector current of the transistor Q2 is zero. At this time, the voltage at the node N1 of the current source I1 increases in the + V direction, and the voltage at the node N2 of the current source I2 decreases in the -V direction.

よって、ベース接地回路のトランジスタＱ３のベース・エミッタ間電圧ＶＢＥ３は増加し、トランジスタＱ４のベース・エミッタ間電圧ＶＢＥ４は減少し、結果として電流源Ｉ２の電流Ｉ２は、トランジスタＱ５とＱ６によって構成されたカレントミラー回路によってミラーされ、トランジスタＱ６のコレクタに流れる。一方、トランジスタＱ４は相補の動作によりそのコレクタ電流はゼロである。 Therefore, the base-emitter voltage V BE3 of the transistor Q3 of the grounded base circuit increases, the base-emitter voltage V BE4 of the transistor Q4 decreases, and as a result, the current I2 of the current source I2 is constituted by the transistors Q5 and Q6. Is mirrored by the current mirror circuit and flows to the collector of the transistor Q6. On the other hand, transistor Q4 has a collector current of zero due to complementary operation.

ここで、電流源Ｉ１，Ｉ２，Ｉ３については、前記したようにＩ１＝Ｉ２＝Ｉ３であるので、結果として、ノードＮ３には電流はＩ３が吐き出されることなる。よって、ノードＮ３において、トランジスタＱ６のコレクタ電流Ｉ３とトランジスタＱ４のコレクタ電流ゼロのインピーダンス変換により、ノードＮ３の電圧は上昇する。ノードＮ３と出力端子ＯＵＴとの間はバッファＸ１が接続されているので、最終的には、本演算増幅器２０の出力端子ＯＵＴの電圧は、入力端子ＩＮ＋と同じ高電圧ＶＨになる。   Here, since the current sources I1, I2, and I3 are I1 = I2 = I3 as described above, as a result, the current I3 is discharged to the node N3. Therefore, at node N3, the voltage at node N3 rises due to impedance conversion between collector current I3 of transistor Q6 and collector current zero of transistor Q4. Since the buffer X1 is connected between the node N3 and the output terminal OUT, the voltage of the output terminal OUT of the operational amplifier 20 finally becomes the same high voltage VH as that of the input terminal IN +.

この間、ノードＮ３の電圧と出力端子ＯＵＴの電圧の変化は傾斜を持ち、スルーレートＳＲは、電流Ｉ３がコンデンサＣｃを充電する次の式で定義される。
ＳＲ＝Ｉ３／Ｃｃ (1)
なお、この種の演算増幅器は、例えば特許文献１にも記載されている。
実開平５−５９９４６号公報 During this time, the change in the voltage at the node N3 and the voltage at the output terminal OUT has a slope, and the slew rate SR is defined by the following equation in which the current I3 charges the capacitor Cc.
SR = I3 / Cc (1)
This type of operational amplifier is also described in Patent Document 1, for example.
Japanese Utility Model Publication No. 5-59946

ところが、図６に示した従来の演算増幅器２０の回路では、パルス応答速度は（１）式で示されるように、電流Ｉ３で規定されるスルーレートによって制限されるという問題があった。   However, the circuit of the conventional operational amplifier 20 shown in FIG. 6 has a problem that the pulse response speed is limited by the slew rate defined by the current I3, as shown by the equation (1).

本発明の目的は、正転入力端子と反転入力端子との間に印加する入力差動電圧が所定値を超えるとき、スルーレートを加速させ、従来では制限されていたパルス応答速度をさらに高速化できるようにした演算増幅器を提供することである。   The object of the present invention is to accelerate the slew rate when the input differential voltage applied between the normal input terminal and the inverted input terminal exceeds a predetermined value, and further increase the pulse response speed that has been limited in the past. It is an object of the present invention to provide an operational amplifier that can be used.

上記目的を達成するために、請求項１にかかる発明の演算増幅器は、正転入力端子および反転入力端子に接続され、前記正転入力端子の電圧が前記反転入力端子の電圧より高くなるとき第１の極性の信号を出力し、前記正転入力端子の電圧が前記反転入力端子の電圧より低くなるとき前記第１の極性と反対の第２の極性の信号を出力する差動入力回路と、該差動入力回路から前記第１の極性の信号が出力するとき前記第１の極性の信号に応じた大きさの電流を吐き出し、前記差動入力回路から前記第２の極性の信号が出力するとき前記第２の極性の信号に応じた大きさの電流を吸い込む出力回路と、該出力回路の電流吐き出し／電流吸い込みに応じて充電／放電が行われるコンデンサとを備えた演算増幅回路において、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上高くなるとき、前記コンデンサに対して追加の吐き出し電流を供給する吐き出し電流追加回路と、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上低くなるとき、前記コンデンサに対して追加の吸い込み電流を供給する吸い込み電流追加回路と、を設けたことを特徴とする。
請求項２にかかる発明は、請求項１に記載の演算増幅器において、前記吐き出し電流追加回路は、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上高くなったとき検出信号を出力する第１の検出部と、該第１の検出部が検出信号を出力したとき動作する第１のカレントミラー回路とからなり、該第１のカレントミラー回路から前記吐き出し電流が供給され、前記吸い込み電流追加回路は、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上低くなったとき検出信号を出力する第２の検出部と、該第１の検出部が検出信号を出力したとき動作する第２のカレントミラー回路とからなり、該第２のカレントミラー回路から前記吸い込み電流が供給される、ことを特徴とする。
請求項３にかかる発明は、請求項１に記載の演算増幅器において、前記吐き出し電流追加回路は、前記正転入力端子にベース又はゲートが接続された第１の極性の第２のトランジスタと、前記反転入力端子にベース又はゲートが接続された第２の極性の第３のトランジスタと、前記第２のトランジスタおよび前記第３のトランジスタと直列接続された第２の極性の第５のトランジスタと、該第５のトランジスタとカレントミラー接続され、前記吐き出し電流を供給する第２の極性の第７のトランジスタとからなり、前記吸い込み電流追加回路は、前記反転入力端子にベース又はゲートが接続された第１の極性の第１のトランジスタと、前記正転入力端子にベース又はゲートが接続された第２の極性の第４のトランジスタと、前記第１のトランジスタおよび前記第４のトランジスタと直列接続された第１の極性の第６のトランジスタと、該第６のトランジスタとカレントミラー接続され、前記吸い込み電流を供給する第１の極性の第８のトランジスタとからなる、ことを特徴とする。 In order to achieve the above object, an operational amplifier according to a first aspect of the present invention is connected to a non-inverting input terminal and an inverting input terminal, and the operational amplifier is connected when the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal. A differential input circuit that outputs a signal having a polarity of 1 and outputs a signal having a second polarity opposite to the first polarity when the voltage of the normal input terminal is lower than the voltage of the inverting input terminal; When the signal of the first polarity is output from the differential input circuit, a current having a magnitude corresponding to the signal of the first polarity is discharged, and the signal of the second polarity is output from the differential input circuit. An operational amplifier circuit comprising: an output circuit that sucks a current having a magnitude according to the signal of the second polarity; and a capacitor that is charged / discharged according to current discharge / current sink of the output circuit, Forward input terminal power Is higher than a voltage of the inverting input terminal by a predetermined value or more, a discharge current adding circuit for supplying an additional discharge current to the capacitor, and the voltage of the normal input terminal is a predetermined value higher than the voltage of the inverting input terminal A sink current adding circuit for supplying an additional sink current to the capacitor when the voltage becomes lower is provided.
According to a second aspect of the present invention, in the operational amplifier according to the first aspect, the discharge current adding circuit outputs a detection signal when the voltage at the normal input terminal is higher than the voltage at the reverse input terminal by a predetermined value or more. A first detection unit that outputs and a first current mirror circuit that operates when the first detection unit outputs a detection signal, and the discharge current is supplied from the first current mirror circuit; The sink current adding circuit includes a second detection unit that outputs a detection signal when the voltage at the normal input terminal is lower than the voltage at the inverting input terminal by a predetermined value or more, and the first detection unit outputs the detection signal. It comprises a second current mirror circuit that operates when output, and the sink current is supplied from the second current mirror circuit.
According to a third aspect of the present invention, in the operational amplifier according to the first aspect, the discharge current adding circuit includes a second transistor having a first polarity with a base or a gate connected to the normal input terminal, A third transistor having a second polarity with a base or gate connected to the inverting input terminal; a fifth transistor having a second polarity connected in series with the second transistor and the third transistor; The sink current adding circuit includes a seventh transistor having a second polarity which is connected to a fifth transistor in a current mirror and supplies the discharge current. The sink current adding circuit includes a first or a first base having a base or a gate connected to the inverting input terminal. A first transistor having a polarity, a fourth transistor having a second polarity with a base or gate connected to the normal input terminal, and the first transistor A sixth transistor of the first polarity connected in series with the first transistor and the fourth transistor, and an eighth transistor of the first polarity connected to the sixth transistor in a current mirror connection and supplying the sink current It consists of.

本発明によれば、正転入力端子と反転入力端子との間に印加する入力差動電圧が所定値を超えるとスルーレートが増大するので、高速動作させることが可能となる。また、高速動作時は消費電流が増大するものの、それ以外では従来と同様に動作し、このとき消費する電流が従来と同じである。   According to the present invention, when the input differential voltage applied between the non-inverting input terminal and the inverting input terminal exceeds a predetermined value, the slew rate increases, so that high speed operation is possible. In addition, the current consumption increases during high-speed operation, but otherwise it operates in the same manner as in the prior art, and the current consumed at this time is the same as in the prior art.

図１は本発明の実施例の演算増幅器１０の構成を示す回路図である。Ｑ１，Ｑ２，Ｑ５，Ｑ６，ＱＡ３，ＱＡ４，ＱＡ５，ＱＡ７はＰＮＰトランジスタ、Ｑ３，Ｑ４，ＱＡ１，ＱＡ２，ＱＡ６，ＱＡ８はＮＰＮトランジスタ、Ｒ１，Ｒ２，ＲＡ１，ＲＡ２，ＲＡ３，ＲＡ４は抵抗、Ｃｃはコンデンサ、Ｉ１，Ｉ２，Ｉ３は電流源（Ｉ１＝Ｉ２＝Ｉ３）、Ｖ１は電圧源、Ｘ１はバッファである。Ｖ＋およびＶ−はそれぞれ第１電源および第２電源、ＩＮ＋は正転入力端子、ＩＮ−は反転入力端子、ＯＵＴは出力端子である。トランジスタＱ５とＱ６、ＱＡ５とＱＡ７、ＱＡ６とＱＡ８は、それぞれカレントミラー回路を構成する。   FIG. 1 is a circuit diagram showing a configuration of an operational amplifier 10 according to an embodiment of the present invention. Q1, Q2, Q5, Q6, QA3, QA4, QA5, QA7 are PNP transistors, Q3, Q4, QA1, QA2, QA6, QA8 are NPN transistors, R1, R2, RA1, RA2, RA3, RA4 are resistors, and Cc is Capacitors, I1, I2, and I3 are current sources (I1 = I2 = I3), V1 is a voltage source, and X1 is a buffer. V + and V− are a first power supply and a second power supply, IN + is a normal input terminal, IN− is an inverting input terminal, and OUT is an output terminal. Transistors Q5 and Q6, QA5 and QA7, QA6 and QA8 constitute a current mirror circuit, respectively.

なお、本実施例では、請求項の差動入力回路は、トランジスタＱ１，Ｑ２、電流源Ｉ１，Ｉ２，Ｉ３により構成されている。また、請求項の出力回路は、トランジスタＱ３〜Ｑ６と電圧源Ｖ１と抵抗Ｒ１，Ｒ２により構成されている。また、請求項の吐き出し電流追加回路は、トランジスタＱＡ２，ＱＡ３と抵抗ＲＡ１からなる検出部と、トランジスタＱＡ５，ＱＡ７と抵抗ＲＡ３からなるカレントミラー回路により構成されている。また、請求項の吸い込み電流追加回路は、トランジスタＱＡ１，ＱＡ４と抵抗ＲＡ２からなる検出部と、トランジスタＱＡ６，ＱＡ８と抵抗ＲＡ４からなるカレントミラー回路（ミラー比＝１）により構成されている。   In the present embodiment, the claimed differential input circuit includes transistors Q1 and Q2 and current sources I1, I2 and I3. The output circuit according to the claims includes transistors Q3 to Q6, a voltage source V1, and resistors R1 and R2. In addition, the discharge current adding circuit of the claims is configured by a detection unit including transistors QA2 and QA3 and a resistor RA1, and a current mirror circuit including transistors QA5 and QA7 and a resistor RA3. In addition, the sink current addition circuit of the claims is configured by a detection unit including transistors QA1 and QA4 and a resistor RA2, and a current mirror circuit (mirror ratio = 1) including transistors QA6 and QA8 and a resistor RA4.

本実施例の演算増幅器１０は、図６の演算増幅器２０に対して、上記した吐き出し電流追加回路と、吸い込み電流追加回路を追加接続したものである。これらの回路を接続することで、図６の演算増幅器２０で電流Ｉ３のみがコンデンサＣｃを充電する式(１)で定義されたスルーレートの傾斜をより急峻にし、高速応答化を実現できる。   The operational amplifier 10 of this embodiment is obtained by additionally connecting the above-described discharge current adding circuit and the sink current adding circuit to the operational amplifier 20 of FIG. By connecting these circuits, the slope of the slew rate defined by the equation (1) in which only the current I3 charges the capacitor Cc in the operational amplifier 20 of FIG. 6 can be made steeper, and high-speed response can be realized.

さて、電流源について、前記したように、Ｉ１＝Ｉ２＝Ｉ３が成立している。よって、正転入力端子ＩＮ＋の電圧と反転入力端子ＩＮ−の電圧が同一のときは、トランジスタＱ１，Ｑ２，Ｑ４，Ｑ６に流れる電流は、全て等しく、Ｉ３／２となり、コンデンサＣｃには電流は流れない。   As described above, I1 = I2 = I3 holds for the current source. Therefore, when the voltage at the non-inverting input terminal IN + and the voltage at the inverting input terminal IN- are the same, the currents flowing through the transistors Q1, Q2, Q4, and Q6 are all equal to I3 / 2, and the current flowing through the capacitor Cc is Not flowing.

この演算増幅器１０を、図２に示すように、反転入力端子ＩＮ−を出力端子ＯＵＴに接続してボルテージホロワ回路を構成し、正転入力端子ＩＮ＋に、低電圧ＶＬと高電圧ＶＨの間で変化するパルス信号Ｓ１を入力させたときの動作を説明する。   As shown in FIG. 2, the operational amplifier 10 is connected to the inverting input terminal IN− to the output terminal OUT to form a voltage follower circuit, and is connected between the low voltage VL and the high voltage VH at the normal input terminal IN +. The operation when the pulse signal S1 that changes in (1) is input will be described.

最初、両入力端子ＩＮ＋とＩＮ−は同じ低電圧ＶＬである。次に、正転入力端子ＩＮ＋に高電圧ＶＨが任意の傾斜をもって印加されると、トランジスタＱ２がオフ状態となり、Ｑ１がオン状態となり、電流源Ｉ３の全電流がトランジスタＱ１のコレクタに流れる。一方、トランジスタＱ２のコレクタ電流はゼロとなる。トランジスタＱ１のコレクタ電流Ｉ３は電流源Ｉ１の電流Ｉ１と等しいため、ベース接地回路のトランジスタＱ４に対して電流の引き込みが発生しない。逆に、トランジスタＱ２のコレクタ電流はゼロであるため、ベース接地回路のトランジスタＱ３のエミッタ電流は、電流源Ｉ２の電流Ｉ２（＝Ｉ３）となる。この電流Ｉ３は、ベース接地で構成されたカレントミラー回路によってミラーされ、トランジスタＱ６に流れる。   Initially, both input terminals IN + and IN- are at the same low voltage VL. Next, when the high voltage VH is applied to the normal input terminal IN + with an arbitrary inclination, the transistor Q2 is turned off, Q1 is turned on, and the entire current of the current source I3 flows to the collector of the transistor Q1. On the other hand, the collector current of the transistor Q2 is zero. Since the collector current I3 of the transistor Q1 is equal to the current I1 of the current source I1, no current is drawn into the transistor Q4 of the base ground circuit. On the contrary, since the collector current of the transistor Q2 is zero, the emitter current of the transistor Q3 of the grounded base circuit is the current I2 (= I3) of the current source I2. This current I3 is mirrored by a current mirror circuit constituted by a base and flows to the transistor Q6.

そして、図３で示すように、入力端子ＩＮ＋と入力端子ＩＮ−の端子間の入力差動電圧ΔＶＩＮが、
ΔＶＩＮ≧ＶＢＥＡ２＋ＶＢＥＡ３ (2)
になる（ＶＢＥＡ２はトランジスタＱＡ２のベース・エミッタ間電圧、ＶＢＥＡ３はトランジスＱＡ３のベース・エミッタ間電圧）と、トランジスタＱＡ２，ＱＡ３がオン状態になる。トランジスタＱＡ１、ＱＡ４がオフ状態のままである。このときオン状態のトランジスタＱＡ２、ＱＡ３に流れる電流Ｉａは、
Ｉａ＝｛ΔＶＩＮ−（ＶＢＥＡ２＋ＶＢＥＡ３）｝／ＲＡ１ (3)
となる。この電流ＩａはトランジスタＱＡ５，ＱＡ７のカレントミラー回路によりトランジスタＡＱ７側にミラーされ、ノードＮ３で電流Ｉ３に加算されて、コンデンサＣｃに供給される。 As shown in FIG. 3, the input differential voltage ΔVIN between the input terminal IN + and the input terminal IN− is
ΔVIN ≧ V BEA2 + V BEA3 (2)
To become (V BEA2 the base-emitter voltage of the transistor QA2, V BEA3 the transistor base-emitter voltage of QA3) and the transistors QA2, QA3 is turned on. Transistors QA1 and QA4 remain off. At this time, the current Ia flowing through the transistors QA2 and QA3 in the on state is
Ia = {ΔVIN− (V BEA2 + V BEA3 )} / RA1 (3)
It becomes. The current Ia is mirrored to the transistor AQ7 side by the current mirror circuit of the transistors QA5 and QA7, added to the current I3 at the node N3, and supplied to the capacitor Cc.

よって、このときのスルーレートＳＲは、
ＳＲ＝（Ｉ３＋Ｉａ）／Ｃｃ (4)
で表される。この式(4)のスルーレートは、前記した式(1)のスルーレートに比較して、Ｉａ／Ｃｃ分だけ高くなることが分かる。 Therefore, the slew rate SR at this time is
SR = (I3 + Ia) / Cc (4)
It is represented by It can be seen that the slew rate of the equation (4) is higher by Ia / Cc than the slew rate of the equation (1).

このように、本実施例の演算増幅器１０は、入力差動電圧ΔＶＩＮが所定値以上になると出力電流が増大して高速動作を行うが、トランジスタＱＡ２，ＱＡ３がオンしない通常動作時に流れる電流の総計は、図６に示した演算増幅器２０の動作時に流れる電流の総計と全く同じである。また、小振幅信号のパルス動作やアナログ動作を実施させるときは、図６に示した演算増幅器２０と全く同様に、安定的に動作する。   As described above, the operational amplifier 10 according to the present embodiment performs a high-speed operation by increasing the output current when the input differential voltage ΔVIN becomes equal to or higher than a predetermined value. Is exactly the same as the total amount of current that flows during operation of the operational amplifier 20 shown in FIG. Further, when performing a pulse operation or an analog operation of a small amplitude signal, it operates stably in the same manner as the operational amplifier 20 shown in FIG.

図３に図１、図６の演算増幅器１０，２０の応答波形を、図４に同演算増幅器１０，２０のコンデンサＣｃに供給される電流の変化を示す。図３では、入力電圧ＶＩＮ＋を点線で、図１の演算増幅器１０の出力電圧ＶＯＵＴを実線で、図６の演算増幅器２０の出力電圧ＶＯＵＴを破線で示した。図４では図１の演算増幅器１０のコンデンサＣｃに供給される電流を実線で、図６の演算増幅器２０のコンデンサＣｃに供給される電流を破線で示した。   FIG. 3 shows response waveforms of the operational amplifiers 10 and 20 shown in FIGS. 1 and 6, and FIG. 4 shows changes in current supplied to the capacitor Cc of the operational amplifiers 10 and 20. FIG. 3, the input voltage VIN + is indicated by a dotted line, the output voltage VOUT of the operational amplifier 10 in FIG. 1 is indicated by a solid line, and the output voltage VOUT of the operational amplifier 20 in FIG. 6 is indicated by a broken line. 4, the current supplied to the capacitor Cc of the operational amplifier 10 in FIG. 1 is indicated by a solid line, and the current supplied to the capacitor Cc of the operational amplifier 20 in FIG. 6 is indicated by a broken line.

本実施例の演算増幅器１０では、コンデンサＣｃに供給される電流は、入力電圧ＶＩＮ＋が低電圧ＶＬのときはゼロであるが、時刻ｔ１で入力電圧ＶＩＮ＋が高電圧ＶＨに向けて立ち上がると増大を開始し、電流Ｉ３になる。さらに、時刻ｔ２に至るとトランジスタＱＡ２，ＱＡ３がオンして、コンデンサＣｃに供給される電流は「Ｉ３＋Ｉａ」に増大し、出力電圧ＶＯＵＴが高電圧ＶＨに近づく時刻ｔ３でトランジスタＱＡ２，ＱＡ３がオフして電流Ｉ３に戻り、この後の時刻ｔ４で電流はゼロに戻る。入力電圧ＶＩＮ＋が低電圧ＶＬに向けて立ち下がる時は、今度は上記と逆の動作となり、コンデンサＣｃの電荷が放電される。このときは、トランジスタＱＡ１，ＱＡ４、ＱＡ８が途中で一時的にオン状態となり、トランジスタＱＡ８による吸い込み電流を追加して、コンデンサＣｃの放電電流を一時的に増大させる。   In the operational amplifier 10 of the present embodiment, the current supplied to the capacitor Cc is zero when the input voltage VIN + is the low voltage VL, but increases when the input voltage VIN + rises toward the high voltage VH at time t1. It starts and becomes current I3. Further, when the time t2 is reached, the transistors QA2 and QA3 are turned on, the current supplied to the capacitor Cc increases to “I3 + Ia”, and at the time t3 when the output voltage VOUT approaches the high voltage VH, the transistors QA2 and QA3 are turned off. The current returns to the current I3, and then returns to zero at time t4. When the input voltage VIN + falls toward the low voltage VL, this time, the operation is the reverse of the above, and the capacitor Cc is discharged. At this time, the transistors QA1, QA4, and QA8 are temporarily turned on in the middle, and the sink current from the transistor QA8 is added to temporarily increase the discharge current of the capacitor Cc.

図５に、図２のようにボルテージホロワ接続したときの演算増幅器１０，２０の応答特性のシミュレーション結果を示す。(a)は図１の本実施例の演算増幅器１０、(b)は図６の従来の演算増幅器２０についてである。いずれも、演算増幅器１０，２０の電圧増幅度Ｇｖ＝１、抵抗ＲＴ＝５０Ω、抵抗ＲＬ＝１５０Ω、コンデンサＣＬ＝１０ｐＦの条件である。(a)の応答特性が(b)に比べて高速応答を示していることが確認できる。   FIG. 5 shows a simulation result of the response characteristics of the operational amplifiers 10 and 20 when the voltage follower is connected as shown in FIG. (a) is about the operational amplifier 10 of this embodiment of FIG. 1, and (b) is about the conventional operational amplifier 20 of FIG. In either case, the operational amplifiers 10 and 20 have the voltage amplification degree Gv = 1, the resistance RT = 50Ω, the resistance RL = 150Ω, and the capacitor CL = 10 pF. It can be confirmed that the response characteristic of (a) shows a higher speed response than that of (b).

なお、以上説明した実施例は本発明の一例であり、種々変形が可能である。例えば、図１で示したトランジスタの導電型（ＰＮＰ，ＮＰＮ）は反対にすることができることは勿論である。また、バイポーラトランジスタに代えて電界効果トランジスタを使用することもできる。また、差動入力回路や出力回路には別の構成の回路を使用することができる。   The embodiment described above is an example of the present invention, and various modifications can be made. For example, it is needless to say that the conductivity types (PNP, NPN) of the transistor shown in FIG. 1 can be reversed. Further, a field effect transistor can be used instead of the bipolar transistor. Further, a circuit having a different configuration can be used for the differential input circuit and the output circuit.

本発明の１つの実施例の演算増幅器の回路図である。1 is a circuit diagram of an operational amplifier according to one embodiment of the present invention. 本実施例および従来例の演算増幅器をボルテージホロワとして構成した回路図である。It is the circuit diagram which comprised the operational amplifier of a present Example and the prior art example as a voltage follower. 本実施例および従来例の演算増幅器を図２のボルテージホロワで動作させたときの応答特性図である。FIG. 3 is a response characteristic diagram when the operational amplifiers of the present example and the conventional example are operated by the voltage follower of FIG. 2. 本実施例および従来例の演算増幅器を図２のボルテージホロワで動作させたときのコンデンサＣｃに流れる電流の特性図である。FIG. 3 is a characteristic diagram of current flowing in a capacitor Cc when the operational amplifiers of the present example and the conventional example are operated by the voltage follower of FIG. 2. 本実施例および従来例の演算増幅器のシミュレーション結果の応答特性図である。It is a response characteristic figure of the simulation result of the operational amplifier of a present Example and a prior art example. 従来の演算増幅器の回路図である。It is a circuit diagram of a conventional operational amplifier.

符号の説明Explanation of symbols

１０，２０：演算増幅器   10, 20: operational amplifier

Claims (3)

正転入力端子および反転入力端子に接続され、前記正転入力端子の電圧が前記反転入力端子の電圧より高くなるとき第１の極性の信号を出力し、前記正転入力端子の電圧が前記反転入力端子の電圧より低くなるとき前記第１の極性と反対の第２の極性の信号を出力する差動入力回路と、該差動入力回路から前記第１の極性の信号が出力するとき前記第１の極性の信号に応じた大きさの電流を吐き出し、前記差動入力回路から前記第２の極性の信号が出力するとき前記第２の極性の信号に応じた大きさの電流を吸い込む出力回路と、該出力回路の電流吐き出し／電流吸い込みに応じて充電／放電が行われるコンデンサとを備えた演算増幅回路において、
前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上高くなるとき、前記コンデンサに対して追加の吐き出し電流を供給する吐き出し電流追加回路と、
前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上低くなるとき、前記コンデンサに対して追加の吸い込み電流を供給する吸い込み電流追加回路と、
を設けたことを特徴とする演算増幅器。 A signal of the first polarity is output when the voltage of the normal input terminal is connected to the normal input terminal and the inverted input terminal, and the voltage of the normal input terminal becomes higher than the voltage of the inverted input terminal. A differential input circuit that outputs a signal having a second polarity opposite to the first polarity when the voltage is lower than a voltage of the input terminal; and a first input signal that outputs the signal having the first polarity from the differential input circuit. An output circuit that discharges a current having a magnitude corresponding to a signal having a polarity of 1, and sucks a current having a magnitude corresponding to the signal having the second polarity when the signal having the second polarity is output from the differential input circuit. And an operational amplifier circuit comprising a capacitor that is charged / discharged in response to current discharge / current sink of the output circuit,
A discharge current addition circuit for supplying an additional discharge current to the capacitor when the voltage of the normal input terminal is higher than a voltage of the inverting input terminal by a predetermined value or more;
A sink current adding circuit for supplying an additional sink current to the capacitor when the voltage at the normal input terminal is lower than the voltage at the inverting input terminal by a predetermined value or more;
And an operational amplifier. 請求項１に記載の演算増幅器において、
前記吐き出し電流追加回路は、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上高くなったとき検出信号を出力する第１の検出部と、該第１の検出部が検出信号を出力したとき動作する第１のカレントミラー回路とからなり、該第１のカレントミラー回路から前記吐き出し電流が供給され、
前記吸い込み電流追加回路は、前記正転入力端子の電圧が前記反転入力端子の電圧より所定値以上低くなったとき検出信号を出力する第２の検出部と、該第１の検出部が検出信号を出力したとき動作する第２のカレントミラー回路とからなり、該第２のカレントミラー回路から前記吸い込み電流が供給される、
ことを特徴とする演算増幅器。 The operational amplifier according to claim 1,
The discharge current adding circuit includes a first detection unit that outputs a detection signal when the voltage at the normal input terminal is higher than the voltage at the inverting input terminal by a predetermined value or more, and the first detection unit detects the detection signal. A first current mirror circuit that operates when the output current is output, and the discharge current is supplied from the first current mirror circuit,
The sink current addition circuit includes a second detection unit that outputs a detection signal when the voltage at the normal input terminal is lower than the voltage at the inverting input terminal by a predetermined value or more, and the first detection unit detects the detection signal. A second current mirror circuit that operates when the current is output, and the sink current is supplied from the second current mirror circuit.
An operational amplifier characterized by that. 請求項１に記載の演算増幅器において、
前記吐き出し電流追加回路は、前記正転入力端子にベース又はゲートが接続された第１の極性の第２のトランジスタと、前記反転入力端子にベース又はゲートが接続された第２の極性の第３のトランジスタと、前記第２のトランジスタおよび前記第３のトランジスタと直列接続された第２の極性の第５のトランジスタと、該第５のトランジスタとカレントミラー接続され、前記吐き出し電流を供給する第２の極性の第７のトランジスタとからなり、
前記吸い込み電流追加回路は、前記反転入力端子にベース又はゲートが接続された第１の極性の第１のトランジスタと、前記正転入力端子にベース又はゲートが接続された第２の極性の第４のトランジスタと、前記第１のトランジスタおよび前記第４のトランジスタと直列接続された第１の極性の第６のトランジスタと、該第６のトランジスタとカレントミラー接続され、前記吸い込み電流を供給する第１の極性の第８のトランジスタとからなる、
ことを特徴とする演算増幅器。 The operational amplifier according to claim 1,
The discharge current adding circuit includes a second transistor having a first polarity with a base or a gate connected to the normal input terminal, and a second polarity having a base or a gate connected to the inverting input terminal. Transistor, a second transistor of the second polarity connected in series with the second transistor and the third transistor, a second mirror connected to the fifth transistor in a current mirror connection, and supplying the discharge current A seventh transistor of the polarity
The sink current adding circuit includes a first transistor having a first polarity with a base or gate connected to the inverting input terminal, and a fourth transistor having a second polarity with a base or gate connected to the normal input terminal. Transistor, a first transistor of the first polarity connected in series with the first transistor and the fourth transistor, and a first mirror connected to the sixth transistor for current sinking. An eighth transistor of the polarity
An operational amplifier characterized by that.
JP2007038477A 2007-02-19 2007-02-19 Operational amplifier Pending JP2008205738A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011166573A (en) * 2010-02-12 2011-08-25 New Japan Radio Co Ltd Operational amplifier
JP2011182188A (en) * 2010-03-01 2011-09-15 Semiconductor Technology Academic Research Center Comparator circuit
JP2011182240A (en) * 2010-03-02 2011-09-15 New Japan Radio Co Ltd Operational amplifier

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JPH0288318U (en) * 1988-12-23 1990-07-12
JPH02220506A (en) * 1988-12-23 1990-09-03 Raytheon Co Differential amplifier
JPH0438003A (en) * 1990-06-04 1992-02-07 Nec Corp Mos operational amplifier circuit
JPH0927721A (en) * 1995-05-11 1997-01-28 Matsushita Electric Ind Co Ltd Operational amplifyier device
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JP2002311063A (en) * 2001-04-19 2002-10-23 Nanopower Solution Kk Adaptive control circuit

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Publication number Priority date Publication date Assignee Title
JPS62111508A (en) * 1985-11-11 1987-05-22 Nec Corp Operational amplifier
JPH0288318U (en) * 1988-12-23 1990-07-12
JPH02220506A (en) * 1988-12-23 1990-09-03 Raytheon Co Differential amplifier
JPH0438003A (en) * 1990-06-04 1992-02-07 Nec Corp Mos operational amplifier circuit
JPH0927721A (en) * 1995-05-11 1997-01-28 Matsushita Electric Ind Co Ltd Operational amplifyier device
JPH11340753A (en) * 1998-02-23 1999-12-10 Canon Inc Arithmetic amplifier
JP2002311063A (en) * 2001-04-19 2002-10-23 Nanopower Solution Kk Adaptive control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011166573A (en) * 2010-02-12 2011-08-25 New Japan Radio Co Ltd Operational amplifier
JP2011182188A (en) * 2010-03-01 2011-09-15 Semiconductor Technology Academic Research Center Comparator circuit
JP2011182240A (en) * 2010-03-02 2011-09-15 New Japan Radio Co Ltd Operational amplifier

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