JP2008164696A

JP2008164696A - Display apparatus

Info

Publication number: JP2008164696A
Application number: JP2006351331A
Authority: JP
Inventors: Kenta Endo; 健太遠藤
Original assignee: Hitachi Displays Ltd
Current assignee: Japan Display Inc
Priority date: 2006-12-27
Filing date: 2006-12-27
Publication date: 2008-07-17

Abstract

PROBLEM TO BE SOLVED: To reduce the variation in a maximum gradation reference voltage and a minimum gradation reference voltage. SOLUTION: A high potential voltage of a potential higher than a maximum gradation reference voltage and a low potential voltage of a lower potential than minimum gradation reference voltage are input to a video line driving circuit. The video line driving circuit has a gradation voltage generation circuit. The gradation voltage generation circuit has a plurality of voltage division circuits connected between the adjacent two gradation reference voltages, a first resistance connected between the maximum gradation reference voltage and the high potential voltage, and a second resistance connected between the minimum gradation reference voltage and the low potential voltage. The resistance value of each voltage division circuit connected between the adjustment two gradation reference voltages, the resistance value of the first resistance connected between the maximum gradation reference voltages and the high potential voltage and the resistance value of the second resistance connected between the minimum gradation reference voltage and the low potential voltage are set at the resistance value nearly proportional to the potential difference between the respective gradation reference voltages, the potential difference between the maximum gradation reference voltages and the high potential voltage and the potential difference between the minimum gradation reference voltage and the low potential voltage. COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、表示装置に係り、特に、多階調の表示が可能な液晶表示装置などに適用して有効な技術に関する。 The present invention relates to a display device, and more particularly, to a technique effective when applied to a liquid crystal display device capable of multi-tone display.

アクティブ素子として薄膜トランジスタを使用するＴＦＴ方式の液晶表示モジュールは高精細な画像を表示できるため、テレビ、パソコン用ディスプレイ等の表示装置として使用されている。
一般に、液晶表示モジュールでは、隣接する２本の走査線（ゲート線ともいう。）と、隣接する２本の映像線（ソース線またはドレイン線ともいう。）とで囲まれる領域に、走査線からの走査信号によってオンする薄膜トランジスタと、映像線からの映像信号が前述の薄膜トランジスタを介して供給される画素電極とが形成されて、所謂、サブピクセルが構成される。
ここで、各映像線は、液晶表示パネルの一方の辺側（長辺側）に配置される映像線駆動回路に接続され、各走査線は、液晶表示パネルの他方の辺側（短辺側）に配置される走査線駆動回路に接続される。
映像線駆動回路は、階調電圧生成回路を有し、当該階調電圧生成回路は、例えば、外部から入力された１２値の階調基準電圧（Ｖ１−Ｖ１２）の各階調基準電圧間を、抵抗分圧回路により分圧して、正極性の２５６階調の階調電圧と、負極性の２５６階調の階調電圧を生成する。（下記、特許文献１、特許文献２，特許文献３参照） A TFT liquid crystal display module using a thin film transistor as an active element can display a high-definition image, and is therefore used as a display device such as a television or a personal computer display.
In general, in a liquid crystal display module, an area surrounded by two adjacent scanning lines (also referred to as gate lines) and two adjacent video lines (also referred to as source lines or drain lines) is separated from the scanning lines. A thin film transistor that is turned on by the scanning signal and a pixel electrode to which the video signal from the video line is supplied through the thin film transistor are formed to form a so-called sub-pixel.
Here, each video line is connected to a video line driving circuit disposed on one side (long side) of the liquid crystal display panel, and each scanning line is connected to the other side (short side) of the liquid crystal display panel. ) Is connected to the scanning line driving circuit.
The video line driver circuit includes a gradation voltage generation circuit, and the gradation voltage generation circuit, for example, between each gradation reference voltage of 12-value gradation reference voltages (V1 to V12) input from the outside, The voltage is divided by the resistance voltage dividing circuit to generate a positive gradation voltage of 256 gradations and a negative gradation voltage of 256 gradations. (See Patent Document 1, Patent Document 2, and Patent Document 3 below)

なお、本願発明に関連する先行技術文献としては以下のものがある。
特開２００１−１３４７８号公報特開２００２−３６６１１５号公報特開２００３−３１６３３３号公報 As prior art documents related to the invention of the present application, there are the following.
JP 2001-13478 A JP 2002-366115 A JP 2003-316333 A

一般に液晶層に印加する電圧と透過率との関係は、リニアではなく、透過率の高いところ及び低いところでは、液晶層に印加する電圧に対する透過率の変化は少なく、その中間となるところで透過率の変化が大きい。
このため、２５６階調の多色表示が可能な液晶表示装置において、２５６階調をリニアに表示するためには、映像線駆動回路の階調電圧生成回路に入力する階調基準電圧値は、等間隔ではなく、中間調付近（例えば、Ｖ３〜Ｖ５，Ｖ８〜Ｖ１０）で差が小さく、中間調以外（例えば、Ｖ１〜Ｖ３，Ｖ１０〜Ｖ１２）で大きくしなければならない。
そのため、階調電圧生成回路の抵抗分圧回路において、各階調基準電圧の間に接続される抵抗を一定の抵抗値にすると、中間調付近の階調基準電圧の間に流れる電流と、中間調以の外階調基準電圧の間に流れる電流との間に差が生じ、電流値が不連続となる抵抗分圧回路の階調基準電圧の供給端子から電流が流入・流出し、階調電圧生成回路に流れる電流が多くなる為、映像線駆動回路の消費電力が増大するという問題があった。 In general, the relationship between the voltage applied to the liquid crystal layer and the transmittance is not linear, and there is little change in the transmittance with respect to the voltage applied to the liquid crystal layer where the transmittance is high and low, and the transmittance is in the middle. The change is large.
For this reason, in a liquid crystal display device capable of multi-color display of 256 gradations, in order to display 256 gradations linearly, the gradation reference voltage value input to the gradation voltage generation circuit of the video line driving circuit is: The difference should be small in the vicinity of the halftone (for example, V3 to V5, V8 to V10) and not large in the middle tone (for example, V1 to V3, V10 to V12).
Therefore, in the resistance voltage dividing circuit of the gradation voltage generation circuit, if the resistance connected between the gradation reference voltages is set to a certain resistance value, the current flowing between the gradation reference voltages near the halftone and the halftone The current flows in and out of the gradation reference voltage supply terminal of the resistor voltage divider circuit in which the current value becomes discontinuous and the current value becomes discontinuous. There is a problem that the power consumption of the video line driving circuit increases because the current flowing through the generation circuit increases.

前述した問題点を解決するために、階調電圧生成回路内の抵抗分圧回路の抵抗値を、各階調基準電圧間の抵抗値が各階調基準電圧間の電位差に比例するように設定するようにしている。
この方法によれば、最大の階調基準電圧と最小の階調基準電圧とが供給される供給端子以外からの電流の流入、流出はほとんど「０」となり、映像線駆動回路の消費電力を低減することが可能となる。
しかしながら、階調基準電圧の供給端子から流入、流出する電流の電流値が大きくなるほど、階調基準電圧の出力電圧精度が悪くなるので、最大の階調基準電圧と最小の階調基準電圧の出力電圧精度が他の階調基準電圧の出力電圧精度よりも悪くなる。
液晶表示パネルが、ノーマリブラック特性の場合、最大の階調基準電圧と最小の階調基準電圧は、「白」表示のための階調電圧であり、これがばらつくということは、白輝度（ピーク輝度）がばらつくことになる。さらに、最大の階調基準電圧と最小の階調基準電圧がばらつくということは、γ補正カーブ全体にも影響を及ぼすことになるので、好ましくない。
本発明は、前記従来技術の問題点を解決するためになされたものであり、本発明の目的は、表示装置において、最大の階調基準電圧と最小の階調基準電圧のバラツキを低減することが可能となる技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかにする。 In order to solve the above-described problem, the resistance value of the resistance voltage dividing circuit in the gradation voltage generation circuit is set so that the resistance value between the gradation reference voltages is proportional to the potential difference between the gradation reference voltages. I have to.
According to this method, the inflow and outflow of current from other than the supply terminal to which the maximum gradation reference voltage and the minimum gradation reference voltage are supplied are almost “0”, thereby reducing the power consumption of the video line driving circuit. It becomes possible to do.
However, as the current value of the current flowing in and out of the gray scale reference voltage supply terminal increases, the output voltage accuracy of the gray scale reference voltage deteriorates, so that the maximum gray scale reference voltage and the minimum gray scale reference voltage are output. The voltage accuracy is worse than the output voltage accuracy of other gradation reference voltages.
When the liquid crystal display panel has a normally black characteristic, the maximum gradation reference voltage and the minimum gradation reference voltage are gradation voltages for “white” display. (Luminance) will vary. Furthermore, it is not preferable that the maximum gradation reference voltage and the minimum gradation reference voltage vary because it affects the entire γ correction curve.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to reduce variations in the maximum gradation reference voltage and the minimum gradation reference voltage in a display device. It is to provide a technology that makes it possible.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の通りである。
（１）複数のサブピクセルを有する表示パネルと、前記複数のサブピクセルに、複数の電位の階調電圧から選択した電圧を出力する映像線駆動回路と、複数の電位の階調基準電圧を生成し、前記映像線駆動回路に出力する階調基準電圧生成回路とを備える表示装置であって、前記階調基準電圧生成回路で生成される前記複数の階調基準電圧は、最大の階調基準電圧、最小の階調基準電圧および当該最大と最小の階調基準電圧以外の階調基準電圧を有し、前記映像線駆動回路には、前記最大の階調基準電圧よりも高電位の高電位電圧と、前記最小の階調基準電圧よりも低電位の低電位電圧とが入力され、前記映像線駆動回路は、階調電圧生成回路を有し、前記階調電圧生成回路は、隣接する前記２つの階調基準電圧の間に接続される複数の分圧回路と、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗と、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗とを有し、前記階調電圧生成回路は、前記各階調基準電圧の電位間を前記各分圧回路により複数の電位に分圧して前記複数の電位の階調電圧を生成し、前記隣接する２つの階調基準電圧の間に接続される前記各分圧回路の抵抗値、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗の抵抗値、および、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗の抵抗値を、各階調基準電圧間の電位差、前記最大の階調基準電圧と前記高電位電圧との間の電位差、および、前記最小の階調基準電圧と前記低電位電圧との間の電位差にほぼ比例した抵抗値に設定される。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A display panel having a plurality of subpixels, a video line driving circuit for outputting a voltage selected from a plurality of gradation voltages to the plurality of subpixels, and generating a plurality of gradation reference voltages And a gradation reference voltage generation circuit for outputting to the video line driving circuit, wherein the plurality of gradation reference voltages generated by the gradation reference voltage generation circuit are a maximum gradation reference. Voltage, a minimum gradation reference voltage, and a gradation reference voltage other than the maximum and minimum gradation reference voltages, and the video line driving circuit has a high potential higher than the maximum gradation reference voltage. Voltage and a low potential voltage lower than the minimum gradation reference voltage are input, the video line driving circuit has a gradation voltage generation circuit, and the gradation voltage generation circuit is adjacent to the gradation voltage generation circuit. Multiple voltage dividers connected between two gradation reference voltages A first resistor connected between the maximum gradation reference voltage and the high potential voltage, and a second resistor connected between the minimum gradation reference voltage and the low potential voltage. And the gradation voltage generation circuit divides the potentials of the gradation reference voltages into a plurality of potentials by the voltage dividing circuits to generate gradation voltages of the plurality of potentials. A resistance value of each of the voltage dividing circuits connected between two gradation reference voltages, a resistance value of a first resistor connected between the maximum gradation reference voltage and the high potential voltage, and the minimum The resistance value of the second resistor connected between the gray scale reference voltage and the low potential voltage is represented by a potential difference between the gray scale reference voltages and a potential difference between the maximum gray scale reference voltage and the high potential voltage. And a resistance value substantially proportional to the potential difference between the minimum gradation reference voltage and the low potential voltage. It is constant.

（２）複数のサブピクセルを有する表示パネルと、前記複数のサブピクセルに、複数の電位の階調電圧から選択した電圧を出力する少なくとも１個の映像線駆動回路と、複数の電位の階調基準電圧を生成し、前記映像線駆動回路に出力する階調基準電圧生成回路とを備える表示装置であって、前記階調基準電圧生成回路で生成される前記複数の階調基準電圧は、最大の階調基準電圧、最小の階調基準電圧および当該最大と最小の階調基準電圧以外の階調基準電圧を有し、前記最大の階調基準電圧と前記最大の階調基準電圧よりも高電位の高電位電圧との間に接続される第１抵抗と、前記最小の階調基準電圧と前記最小の階調基準電圧よりも低電位の低電位電圧との間に接続される第２抵抗とを有し、前記少なくとも１個の映像線駆動回路は、階調電圧生成回路を有し、前記階調電圧生成回路は、隣接する前記２つの階調基準電圧の間に接続される複数の分圧回路を有し、前記各階調基準電圧の電位間を前記各分圧回路により複数の電位に分圧して前記複数の電位の階調電圧を生成し、前記隣接する２つの階調基準電圧の間に並列に接続される、前記少なくとも１個の映像線駆動回路の前記各分圧回路の合成抵抗値、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗の抵抗値、および、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗の抵抗値を、各階調基準電圧間の電位差、前記最大の階調基準電圧と前記高電位電圧との間の電位差、および、前記最小の階調基準電圧と前記低電位電圧との間の電位差にほぼ比例した抵抗値に設定される。 (2) a display panel having a plurality of subpixels, at least one video line driving circuit for outputting a voltage selected from a plurality of gradation voltages to the plurality of subpixels, and a plurality of gradations of potentials And a gradation reference voltage generation circuit that generates a reference voltage and outputs the reference voltage to the video line driving circuit, wherein the plurality of gradation reference voltages generated by the gradation reference voltage generation circuit is a maximum Gradation reference voltage, minimum gradation reference voltage, and gradation reference voltage other than the maximum and minimum gradation reference voltages, and higher than the maximum gradation reference voltage and the maximum gradation reference voltage. A first resistor connected between the high potential voltage and a second resistor connected between the minimum gradation reference voltage and a low potential voltage lower than the minimum gradation reference voltage. And the at least one video line driving circuit includes: A gradation voltage generation circuit, and the gradation voltage generation circuit has a plurality of voltage dividing circuits connected between the two gradation reference voltages adjacent to each other. The at least one video line driving unit configured to generate gradation voltages of the plurality of potentials by dividing the voltage into a plurality of potentials by each voltage dividing circuit and connected in parallel between the two adjacent gradation reference voltages. A combined resistance value of each of the voltage dividing circuits of the circuit, a resistance value of a first resistor connected between the maximum gradation reference voltage and the high potential voltage, and the minimum gradation reference voltage and the low The resistance value of the second resistor connected to the potential voltage is set to the potential difference between the gradation reference voltages, the potential difference between the maximum gradation reference voltage and the high potential voltage, and the minimum gradation. Set to a resistance value approximately proportional to the potential difference between the reference voltage and the low potential voltage.

（３）（１）または（２）において、前記階調基準電圧は、等間隔でない階調基準電圧を有する。
（４）（１）ないし（３）の何れかにおいて、複数の電位の階調基準電圧は、ｎ（ｎ≧３）個の階調基準電圧であり、前記隣接する２つの階調基準電圧の間の電位差をＶｊ（ｊ＋１）（ｊ＝１,...,ｎ−１）、前記最大の階調基準電圧と前記高電位電圧との間の電位差をＶ０１、前記最小の階調基準電圧と前記低電位電圧との間の電位差をＶｎ（ｎ＋１）、前記隣接する２つの階調基準電圧の間の合成抵抗値Ｒｊ、前記第１抵抗の抵抗値をＲ０、前記第２の抵抗の抵抗値をＲ（ｎ＋１）とするとき、Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が特定の返納の範囲内で一致する。
（５）（４）において、前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が、±２０％の変動の範囲内で一致する。
（６）（４）において、前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が、±１０％の変動の範囲内で一致する。
（７）（４）において、前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が完全に一致する。 (3) In (1) or (2), the gradation reference voltage has gradation reference voltages that are not equally spaced.
(4) In any one of (1) to (3), the plurality of gradation reference voltages are n (n ≧ 3) gradation reference voltages, and the two adjacent gradation reference voltages Vj (j + 1) (j = 1,..., N−1), the potential difference between the maximum gradation reference voltage and the high potential voltage is V01, and the minimum gradation reference voltage The potential difference from the low potential voltage is Vn (n + 1), the combined resistance value Rj between the two adjacent gradation reference voltages, the resistance value of the first resistor is R0, and the resistance value of the second resistor. Is R (n + 1), the values of Vk (k + 1) / Rk (k = 0,..., N) match within a specific return range.
(5) In (4), the values of Vk (k + 1) / Rk (k = 0,..., N) match within a variation range of ± 20%.
(6) In (4), the values of Vk (k + 1) / Rk (k = 0,..., N) match within a fluctuation range of ± 10%.
(7) In (4), the values of Vk (k + 1) / Rk (k = 0,..., N) completely match.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記の通りである。
本発明の表示装置によれば、最大の階調基準電圧と最小の階調基準電圧のバラツキを低減することが可能となる。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the display device of the present invention, it is possible to reduce the variation between the maximum gradation reference voltage and the minimum gradation reference voltage.

以下、図面を参照して本発明の実施例を詳細に説明する。
なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
図１は、本発明の実施例の液晶表示モジュールの概略構成を示すブロック図である。本実施例の液晶表示モジュールは、液晶表示パネル１と、映像線駆動回路２と、走査線駆動回路３と、表示制御回路４と、電源回路５と、階調基準電圧生成回路６とで構成される。
映像線駆動回路２は、液晶表示パネル１の一辺に配置された半導体チップで構成され、また、走査線駆動回路３は、液晶表示パネル１の他の辺に配置された半導体チップで構成される。
表示制御回路４は、テレビ受信回路等の表示信号源（ホスト側）から入力される表示データ（Ｒ［７：０］、Ｇ［７：０］、Ｂ［７：０］）と、ドットクロック（ＤＣＬＫ）、ディスプレイタイミング信号（ＤＴＭＧ）、水平同期信号（ＨＳＹＮＣ）、および垂直同期信号（ＶＳＹＮＣ）に基づき、表示データの交流化等、液晶表示パネル１の表示に適したタイミング調整を行い、同期信号（クロック信号）と共に映像線駆動回路２と、走査線駆動回路３に入力する。
表示制御回路４の制御の基に、走査線駆動回路３は、走査線（ＧＬ；ゲート線ともいう）に走査電圧を供給し、また、映像線駆動回路２は、映像線（ＤＬ；ドレイン線、ソース線ともいう）に階調電圧を供給して映像を表示する。電源回路５は液晶表示装置に要する各種の電圧を生成し、階調基準電圧生成回路６は、Ｖ１〜Ｖ１２の階調基準電圧を生成する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display module according to an embodiment of the present invention. The liquid crystal display module of the present embodiment includes a liquid crystal display panel 1, a video line driving circuit 2, a scanning line driving circuit 3, a display control circuit 4, a power supply circuit 5, and a gradation reference voltage generating circuit 6. Is done.
The video line driving circuit 2 is composed of a semiconductor chip disposed on one side of the liquid crystal display panel 1, and the scanning line driving circuit 3 is composed of a semiconductor chip disposed on the other side of the liquid crystal display panel 1. .
The display control circuit 4 includes display data (R [7: 0], G [7: 0], B [7: 0]) input from a display signal source (host side) such as a television receiver circuit, and a dot clock. Based on (DCLK), display timing signal (DTMG), horizontal synchronization signal (HSYNC), and vertical synchronization signal (VSYNC), the timing adjustment suitable for the display of the liquid crystal display panel 1, such as AC conversion of display data, is performed to synchronize. The signal (clock signal) is input to the video line driving circuit 2 and the scanning line driving circuit 3.
Under the control of the display control circuit 4, the scanning line driving circuit 3 supplies a scanning voltage to the scanning line (GL; also referred to as a gate line), and the video line driving circuit 2 has a video line (DL; drain line). The gray scale voltage is supplied to the source line) to display an image. The power supply circuit 5 generates various voltages required for the liquid crystal display device, and the gradation reference voltage generation circuit 6 generates gradation reference voltages V1 to V12.

図１において、ＴＦＴは薄膜トランジスタ、ＰＸは画素電極であり、ＣＴは対向電極（コモン電極）、ＣＬは液晶層を等価的に示す液晶容量、Ｃａｄｄは、画素電極（ＰＸ）と対向電極（ＣＴ）との間に形成された保持容量である。
図１に示す液晶表示パネル１において、列方向に配置された各サブピクセルの薄膜トランジスタ（ＴＦＴ）の第１の電極（ドレイン電極またはソース電極）は、映像線（ＤＬ）に接続され、各映像線（ＤＬ）は列方向に配置されたサブピクセルに、表示データに対応する階調電圧を供給する映像線駆動回路２に接続される。
また、行方向に配置された各サブピクセルの薄膜トランジスタ（ＴＦＴ）のゲート電極は、それぞれ走査線（ＧＬ）に接続され、各走査線（ＧＬ）は、１水平走査時間、薄膜トランジスタ（ＴＦＴ）のゲートに走査電圧（正または負のバイアス電圧）を供給する走査線駆動回路３に接続される。
液晶表示パネル１に画像を表示する際、走査線駆動回路３は、走査線（ＧＬ）を上から下（あるいは、下から上）に向かって順次選択し、一方で、ある走査線の選択期間中に、映像線駆動回路２は、表示データに対応する階調電圧を、映像線（ＤＬ）に供給する。
映像線（ＤＬ）に供給された電圧は、薄膜トランジスタ（ＴＦＴ）を経由して、画素電極（ＰＸ）に印加され、最終的に、保持容量（Ｃａｄｄ）と、液晶容量（ＣＬ）に電荷がチャージされ、液晶分子をコントロールすることにより画像が表示される。 In FIG. 1, TFT is a thin film transistor, PX is a pixel electrode, CT is a counter electrode (common electrode), CL is a liquid crystal capacitor equivalently showing a liquid crystal layer, and Cadd is a pixel electrode (PX) and a counter electrode (CT). Is a storage capacitor formed between the two.
In the liquid crystal display panel 1 shown in FIG. 1, the first electrode (drain electrode or source electrode) of the thin film transistor (TFT) of each subpixel arranged in the column direction is connected to the video line (DL), and each video line (DL) is connected to a video line driving circuit 2 that supplies gradation voltages corresponding to display data to sub-pixels arranged in the column direction.
Further, the gate electrodes of the thin film transistors (TFTs) of the sub-pixels arranged in the row direction are connected to the scanning lines (GL), respectively, and each scanning line (GL) is a gate of the thin film transistor (TFT) for one horizontal scanning time. Are connected to a scanning line driving circuit 3 for supplying a scanning voltage (positive or negative bias voltage) to the scanning line.
When displaying an image on the liquid crystal display panel 1, the scanning line driving circuit 3 sequentially selects the scanning lines (GL) from the top to the bottom (or from the bottom to the top), and on the other hand, a selection period of a certain scanning line The video line driving circuit 2 supplies a gradation voltage corresponding to the display data to the video line (DL).
The voltage supplied to the video line (DL) is applied to the pixel electrode (PX) via the thin film transistor (TFT), and finally the charge is charged to the storage capacitor (Cadd) and the liquid crystal capacitor (CL). Then, an image is displayed by controlling the liquid crystal molecules.

ここでは、各サブピクセルに供給される階調電圧が、大きくなるほど高い輝度を示す、所謂、ノーマリ黒表示モード（Normally Black-displaying Mode）で動作することを前提とする。
液晶表示パネル１は、画素電極（ＰＸ）、薄膜トランジスタ（ＴＦＴ）、映像線（ＤＬ）、走査線（ＧＬ）などが設けられた第１の基板（ＴＦＴ基板、アクティブマトリクス基板ともいう）と、カラーフィルタ等が形成される第２の基板（対向基板ともいう）とを、所定の間隙を隔てて重ね合わせ、該両基板間の周縁部近傍に枠状に設けたシール材により、両基板を貼り合わせると共に、シール材の一部に設けた液晶封入口から両基板間のシール材の内側に液晶を封入、封止し、さらに、両基板の外側に偏光板を貼り付けて構成される。
また、対向電極（ＣＴ）は、ＴＮ方式やＶＡ方式の液晶表示パネルであれば第２の基板側に設けられる。ＩＰＳ方式の場合は、第１の基板側に設けられる。
なお、本発明は、液晶パネルの内部構造とは関係がないので、液晶パネルの内部構造の詳細な説明は省略する。また、本発明は、どのような構造の液晶パネルであっても適用可能である。
さらに、実際の製品では、液晶表示パネル１の後ろ側にバックライトが配置されるが、本発明は、バックライトの構造とは関係がないので、バックライトの詳細な説明も省略する。 Here, it is assumed that the gradation voltage supplied to each sub-pixel operates in a so-called normally black-displaying mode in which luminance increases as the voltage increases.
The liquid crystal display panel 1 includes a first substrate (also referred to as a TFT substrate or an active matrix substrate) provided with a pixel electrode (PX), a thin film transistor (TFT), a video line (DL), a scanning line (GL), and the like, A second substrate (also referred to as a counter substrate) on which a filter or the like is formed is overlapped with a predetermined gap, and the two substrates are pasted with a sealing material provided in a frame shape in the vicinity of the peripheral edge between the two substrates. In addition, liquid crystal is sealed and sealed inside a sealing material between both substrates from a liquid crystal sealing port provided in a part of the sealing material, and a polarizing plate is attached to the outside of both substrates.
The counter electrode (CT) is provided on the second substrate side in the case of a TN liquid crystal display panel or a VA liquid crystal display panel. In the case of the IPS system, it is provided on the first substrate side.
Since the present invention is not related to the internal structure of the liquid crystal panel, a detailed description of the internal structure of the liquid crystal panel is omitted. Further, the present invention can be applied to a liquid crystal panel having any structure.
Further, in an actual product, a backlight is disposed on the back side of the liquid crystal display panel 1, but since the present invention is not related to the structure of the backlight, a detailed description of the backlight is also omitted.

図２は、図１に示す映像線駆動回路２の概略回路構成を示すブロック図である。
図２において、２１はクロック制御部、２２はラッチアドレスセレクタ、２３はラッチ回路、２４はＤ／Ａコンバータ回路、２５は出力アンプ回路である。
ラッチ回路２３は、ラッチアドレスセレクタ２２の制御の元に、表示制御回路４から出力される表示データラッチ用クロック（ＣＬ２）に同期して、外部から入力される表示データ（Ｒ［７：０］、Ｇ［７：０］、Ｂ［７：０］）を順次ラッチする。
ラッチ回路２３にラッチされた表示データは、表示制御回路４から出力される、出力タイミング制御用クロック信号（ＣＬ１）に基づき、Ｄ／Ａコンバータ回路２４に出力される。
Ｄ／Ａコンバータ回路２４の階調電圧生成回路は、階調基準電圧生成回路６から入力される、正極性のＶ１〜Ｖ６の階調基準電圧と、負極性のＶ７〜Ｖ１２の階調基準電圧に基づき、正極性および負極性の０〜２５５階調の階調電圧を生成する階調電圧生成回路（２４−１）を有する。
Ｄ／Ａコンバータ回路２４は、階調電圧生成回路（２４−１）で生成された、正極性および負極性の０〜２５５階調の階調電圧の中から、ラッチ回路２３から入力された表示データに対応した階調電圧を選択して、出力アンプ回路２５に入力する。
出力アンプ回路２５は、Ｄ／Ａコンバータ回路２４から入力された階調電圧を、アンプ回路で電流増幅し、対応する映像線（ＤＬ）に出力する。 FIG. 2 is a block diagram showing a schematic circuit configuration of the video line driving circuit 2 shown in FIG.
In FIG. 2, 21 is a clock control unit, 22 is a latch address selector, 23 is a latch circuit, 24 is a D / A converter circuit, and 25 is an output amplifier circuit.
The latch circuit 23 synchronizes with the display data latch clock (CL2) output from the display control circuit 4 under the control of the latch address selector 22 to display data (R [7: 0]) input from the outside. , G [7: 0], B [7: 0]) are sequentially latched.
The display data latched by the latch circuit 23 is output to the D / A converter circuit 24 based on the output timing control clock signal (CL1) output from the display control circuit 4.
The gradation voltage generation circuit of the D / A converter circuit 24 includes positive gradation reference voltages V1 to V6 and negative gradation reference voltages V7 to V12 input from the gradation reference voltage generation circuit 6. And a grayscale voltage generation circuit (24-1) for generating grayscale voltages of 0 to 255 grayscales having positive polarity and negative polarity.
The D / A converter circuit 24 displays the display inputted from the latch circuit 23 from the gradation voltages of positive and negative 0 to 255 gradations generated by the gradation voltage generation circuit (24-1). A gradation voltage corresponding to the data is selected and input to the output amplifier circuit 25.
The output amplifier circuit 25 amplifies the gradation voltage input from the D / A converter circuit 24 with an amplifier circuit and outputs the amplified voltage to the corresponding video line (DL).

図６は、図２に示す階調電圧生成回路（２４−１）の従来の回路構成を示す図であり、図６（ａ）は全体の回路構成を、図６（ｂ）は、図６（ａ）の（イ）で示す部分を拡大して示す図である。
図６（ａ)に示すように、従来の階調電圧生成回路（２４−１）は、階調基準電圧生成回路６から入力される６値の階調基準電圧（Ｖ１−Ｖ６）の各階調基準電圧間を、直列抵抗分圧回路（２４−２）により分圧して、正極性の０〜２５５階調分の階調電圧を生成する部分と、階調基準電圧生成回路６から入力される６値の階調基準電圧（Ｖ７−Ｖ１２）の各階調基準電圧間を、直列抵抗分圧回路（２４−３）により分圧して、負極性の０〜２５５階調分の階調電圧を生成する部分とで構成される。
ここで、１２値の階調基準電圧（Ｖ１−Ｖ１２）の階調基準電圧Ｖｊと階調基準電圧Ｖｊ＋１（ｊ＝１,...,１１）の電位差をＶｊ（ｊ＋１）と表記し、直列抵抗分圧回路（２４−２，２４−３）の階調基準電圧Ｖｊと階調基準電圧Ｖｊ＋１（ｊ＝１,...,５，７,...,１１）とが供給される供給端子間の合成抵抗の抵抗値をＲｊと表記すると、図６に示す階調電圧生成回路では、下記（１）式をほぼ満たすように抵抗値が設定されている。 FIG. 6 is a diagram showing a conventional circuit configuration of the gradation voltage generation circuit (24-1) shown in FIG. 2. FIG. 6 (a) shows the overall circuit configuration, and FIG. 6 (b) shows FIG. It is a figure which expands and shows the part shown by (a) of (a).
As shown in FIG. 6A, the conventional gradation voltage generation circuit (24-1) has each gradation of the 6-value gradation reference voltage (V 1 -V 6) input from the gradation reference voltage generation circuit 6. The reference voltage is divided by the series resistance voltage dividing circuit (24-2) to generate a gradation voltage corresponding to 0 to 255 gradations having a positive polarity, and the gradation reference voltage generation circuit 6 inputs the reference voltage. The gradation reference voltages of the 6-value gradation reference voltages (V7 to V12) are divided by the series resistance voltage dividing circuit (24-3) to generate gradation voltages of 0 to 255 gradations having a negative polarity. It consists of a part to do.
Here, the potential difference between the gradation reference voltage Vj of the 12-value gradation reference voltage (V1−V12) and the gradation reference voltage Vj + 1 (j = 1,..., 11) is expressed as Vj (j + 1), and is connected in series. Supply to which the gradation reference voltage Vj and the gradation reference voltage Vj + 1 (j = 1,..., 5, 7,..., 11) of the resistance voltage dividing circuit (24-2, 24-3) are supplied. When the resistance value of the combined resistance between the terminals is expressed as Rj, the resistance value is set so as to substantially satisfy the following expression (1) in the gradation voltage generating circuit shown in FIG.

［式１］
Ｖ１（２）／Ｒ１
＝Ｖ２（３）／Ｒ２
＝Ｖ３（４）／Ｒ３
＝Ｖ４（５）／Ｒ４
＝Ｖ５（６）／Ｒ５

Ｖ７（８）／Ｒ７
＝Ｖ８（９）／Ｒ８
＝Ｖ９（１０）／Ｒ９
＝Ｖ１０（１１）／Ｒ１０
＝Ｖ１１（１２）／Ｒ１１
・・・・・・・・・・・・・・・・・・・・（１）
したがって、直列抵抗分圧回路（２４−２，２４−３）を流れる電流は、一定の電流値（Ｖｊ（ｊ+１）／Ｒｊ＝一定の電流値）となり、図６に示す階調電圧生成回路では、最大の階調基準電圧（Ｖ１，Ｖ１２）と最小の階調基準電圧（Ｖ６，Ｖ７）の供給端子以外からの電流の流入、流出がほとんど「０」（Ｉ２＝Ｉ３＝Ｉ４＝Ｉ５＝Ｉ８＝Ｉ９＝Ｉ１０＝Ｉ１１＝０）となり、映像線駆動回路２の消費電力を低減することが可能となり、それにより、液晶表示モジュールの消費電力を低減することが可能となる。 [Formula 1]
V1 (2) / R1
= V2 (3) / R2
= V3 (4) / R3
= V4 (5) / R4
= V5 (6) / R5

V7 (8) / R7
= V8 (9) / R8
= V9 (10) / R9
= V10 (11) / R10
= V11 (12) / R11
(1)
Therefore, the current flowing through the series resistance voltage dividing circuit (24-2, 24-3) has a constant current value (Vj (j + 1) / Rj = constant current value), and the gradation voltage generation shown in FIG. In the circuit, inflow and outflow of current from other than the supply terminals of the maximum gradation reference voltage (V1, V12) and the minimum gradation reference voltage (V6, V7) are almost “0” (I2 = I3 = I4 = I5). = I8 = I9 = I10 = I11 = 0), so that the power consumption of the video line driving circuit 2 can be reduced, and thereby the power consumption of the liquid crystal display module can be reduced.

図３は、図２に示す階調電圧生成回路（２４−１）の回路構成を示す図であり、図３（ａ）は全体の回路構成を、図３（ｂ）は、図３（ａ）の（イ）で示す部分を拡大して示す図である。なお、図３において、ＡＶＤＤは、最大の階調基準電圧（Ｖ１）よりも高電位の高電位電圧である。
図３と、図６と比較して直ぐに理解できるように、図３に示す回路構成では、Ｖ１の階調基準電圧とＡＶＤＤの高電位電圧との間に、Ｒ０の抵抗が、また、Ｖ６の階調基準電圧とＶ７の階調基準電圧との間に、Ｒ６の抵抗が、さらに、Ｖ１２の階調基準電圧と接地電圧（ＧＮＤ）との間に、Ｒ１２の抵抗が接続されている点で、図６に示す回路構成と相異する。
ここで、Ｖ１の階調基準電圧とＡＶＤＤの高電位電圧との間の電位差を、Ｖ０（１）、Ｖ１２の階調基準電圧と接地電圧（ＧＮＤ）との間の電位差を、Ｖ１２（１３）、直列抵抗分圧回路の階調基準電圧Ｖｊと階調基準電圧Ｖｊ＋１（ｊ＝１,...,１１）の供給端子間の合成抵抗の抵抗値をＲｊと表記すると、図３に示す階調電圧生成回路では、下記（２）式を満たすように各抵抗の抵抗値が設定される。 3 is a diagram showing a circuit configuration of the gradation voltage generation circuit (24-1) shown in FIG. 2, FIG. 3 (a) shows the entire circuit configuration, and FIG. 3 (b) shows a circuit configuration of FIG. It is a figure which expands and shows the part shown by (A) of (). In FIG. 3, AVDD is a high potential voltage that is higher than the maximum gradation reference voltage (V1).
As can be readily understood by comparing FIG. 3 with FIG. 6, in the circuit configuration shown in FIG. 3, the resistance of R 0 between the gradation reference voltage of V 1 and the high potential voltage of AVDD is The resistor R6 is connected between the gradation reference voltage and the gradation reference voltage V7, and further the resistor R12 is connected between the gradation reference voltage V12 and the ground voltage (GND). This is different from the circuit configuration shown in FIG.
Here, the potential difference between the gradation reference voltage of V1 and the high potential voltage of AVDD is defined as V0 (1), and the potential difference between the gradation reference voltage of V12 and the ground voltage (GND) is defined as V12 (13). When the resistance value of the combined resistance between the supply terminals of the gradation reference voltage Vj and the gradation reference voltage Vj + 1 (j = 1,..., 11) of the series resistance voltage dividing circuit is expressed as Rj, the level shown in FIG. In the regulated voltage generation circuit, the resistance value of each resistor is set so as to satisfy the following equation (2).

［式２］
Ｖ０（１）／Ｒ０
＝Ｖ１（２）／Ｒ１
＝Ｖ２（３）／Ｒ２
＝Ｖ３（４）／Ｒ３
＝Ｖ４（５）／Ｒ４
＝Ｖ５（６）／Ｒ５
＝Ｖ６（７）／Ｒ６
＝Ｖ７（８）／Ｒ７
＝Ｖ８（９）／Ｒ８
＝Ｖ９（１０）／Ｒ９
＝Ｖ１０（１１）／Ｒ１０
＝Ｖ１１（１２）／Ｒ１１
＝Ｖ１２（１３）／Ｒ１２
・・・・・・・・・・・・・・・・・・・・（２）
したがって、図３に示す回路構成では、直列抵抗分圧回路（２４−４）を流れる電流は、一定の電流値（Ｖｋ（ｋ＋１）／Ｒｋ＝一定の電流値；ｋ＝０,...,１２）となり、直列抵抗分圧回路（２４−４）を流れる電流は、高電位電圧（ＡＶＤＤ）から供給されることになる。
そのため、図３に示す回路構成では、Ｖ１〜Ｖ１２の階調基準電圧が供給される供給端子からの電流の流入、流出がほとんど「０」（Ｉ１＝Ｉ２＝Ｉ３＝Ｉ４＝Ｉ５＝Ｉ８＝Ｉ９＝Ｉ１０＝Ｉ１１＝Ｉ１２＝０）となるので、従来のように、最大の階調基準電圧と最小の階調基準電圧の出力電圧精度が他の階調基準電圧の出力電圧精度よりも悪くなるのを低減することが可能となる。 [Formula 2]
V0 (1) / R0
= V1 (2) / R1
= V2 (3) / R2
= V3 (4) / R3
= V4 (5) / R4
= V5 (6) / R5
= V6 (7) / R6
= V7 (8) / R7
= V8 (9) / R8
= V9 (10) / R9
= V10 (11) / R10
= V11 (12) / R11
= V12 (13) / R12
(2)
Therefore, in the circuit configuration shown in FIG. 3, the current flowing through the series resistance voltage dividing circuit (24-4) has a constant current value (Vk (k + 1) / Rk = constant current value; k = 0,..., 12), and the current flowing through the series resistance voltage dividing circuit (24-4) is supplied from the high potential voltage (AVDD).
Therefore, in the circuit configuration shown in FIG. 3, inflow and outflow of current from the supply terminal to which the gradation reference voltages V1 to V12 are supplied are almost “0” (I1 = I2 = I3 = I4 = I5 = I8 = I9). = I10 = I11 = I12 = 0), so that the output voltage accuracy of the maximum gradation reference voltage and the minimum gradation reference voltage is worse than the output voltage accuracy of the other gradation reference voltages as in the prior art. Can be reduced.

図４は、図１に示す階調基準電圧生成回路６で生成される階調基準電圧の一例を示す図である。なお、図４において、Ｖ−Ｖｎ−１は、隣接する階調基準電圧の間の電位差を示す。
図４に示す例では、Ｖ１の階調基準電圧（正極性の２５５階調の階調基準電圧）は１１．８Ｖ、Ｖ２の階調基準電圧（正極性の２２４階調の階調基準電圧）は１０．４Ｖ、Ｖ３の階調基準電圧（正極性の１２８階調の階調基準電圧）は９．１Ｖ、Ｖ４の階調基準電圧（正極性の６４階調の階調基準電圧）は８．３Ｖ、Ｖ５の階調基準電圧（正極性の３２階調の階調基準電圧）は７．７Ｖ、Ｖ６の階調基準電圧（正極性の０階調の階調基準電圧）は６．０Ｖ、Ｖ７の階調基準電圧（負極性の０階調の階調基準電圧）は６．０Ｖ、Ｖ８の階調基準電圧（負極性の３２階調の階調基準電圧）は４．３Ｖ、Ｖ９の階調基準電圧（負極性の６４階調の階調基準電圧）は３．７Ｖ、Ｖ１０の階調基準電圧（負極性の１２８階調の階調基準電圧）は２．９Ｖ、Ｖ１１の階調基準電圧（負極性の２２４階調の階調基準電圧）は１．６Ｖ、Ｖ１２の階調基準電圧（負極性の２５５階調の階調基準電圧）は０．２Ｖである。 FIG. 4 is a diagram showing an example of the gradation reference voltage generated by the gradation reference voltage generation circuit 6 shown in FIG. In FIG. 4, V-Vn-1 indicates a potential difference between adjacent gradation reference voltages.
In the example shown in FIG. 4, the gradation reference voltage of V1 (positive gradation reference voltage of 255 gradations) is 11.8 V, and the gradation reference voltage of V2 (positive gradation reference voltage of 224 gradations). Is 10.4V, the gradation reference voltage of V3 (positive gradation reference voltage of 128 gradations) is 9.1V, and the gradation reference voltage of V4 (positive gradation reference voltage of 64 gradations) is 8. .3V, V5 gradation reference voltage (positive gradation reference voltage of 32 gradations) is 7.7V, V6 gradation reference voltage (positive gradation 0 gradation reference voltage) is 6.0V , V7 gradation reference voltage (negative gradation 0 gradation reference voltage) is 6.0V, and V8 gradation reference voltage (negative gradation 32 gradation reference voltage) is 4.3V, V9. The gradation reference voltage (negative gradation gradation reference voltage of 64 gradations) is 3.7V, and the gradation reference voltage V10 (negative gradation gradation reference voltage of 128 gradations) is 2.9V. Gradation reference voltage V11 (gradation reference voltage of the negative polarity 224 gradations) is 1.6V, the gradation reference voltage V12 (gradation reference voltage of the negative polarity 255 gradations) is 0.2V.

また、Ｖ１の階調基準電圧とＶ２の階調基準電圧との間の電位差は１．４Ｖ、Ｖ２の階調基準電圧とＶ３の階調基準電圧との間の電位差は１．３Ｖ、Ｖ３の階調基準電圧とＶ４の階調基準電圧との間の電位差は０．８Ｖ、Ｖ４の階調基準電圧とＶ５の階調基準電圧との間の電位差は０．６Ｖ、Ｖ５の階調基準電圧とＶ６の階調基準電圧との間の電位差は１．７Ｖ、Ｖ７の階調基準電圧とＶ８の階調基準電圧との間の電位差は１．７Ｖ、Ｖ８の階調基準電圧とＶ９の階調基準電圧との間の電位差は０．６Ｖ、Ｖ８の階調基準電圧とＶ９の階調基準電圧との間の電位差は０．８Ｖ、Ｖ９の階調基準電圧とＶ１０の階調基準電圧との間の電位差は１．３Ｖ、Ｖ１１の階調基準電圧とＶ１２の階調基準電圧との間の電位差は１．４Ｖである。
図４に示すように、階調基準電圧値は、等間隔ではなく、中間調付近（Ｖ２〜Ｖ６）で隣接する階調基準電圧間の電位差が小さく、それ以外（Ｖ０〜Ｖ２，Ｖ６〜Ｖ８）で隣接する階調基準電圧間の電位差が大きくなっている。 Further, the potential difference between the gradation reference voltage of V1 and the gradation reference voltage of V2 is 1.4V, and the potential difference between the gradation reference voltage of V2 and the gradation reference voltage of V3 is 1.3V, V3. The potential difference between the gradation reference voltage and the gradation reference voltage of V4 is 0.8V, the potential difference between the gradation reference voltage of V4 and the gradation reference voltage of V5 is 0.6V, and the gradation reference voltage of V5. The difference in potential between the gradation reference voltage of V6 and V6 is 1.7V, the difference between the gradation reference voltage of V7 and the gradation reference voltage of V8 is 1.7V, the gradation reference voltage of V8 and the level of V9. The potential difference between the tone reference voltage is 0.6V, the potential difference between the tone reference voltage of V8 and the tone reference voltage of V9 is 0.8V, the tone reference voltage of V9 and the tone reference voltage of V10. Is 1.3V, and the potential difference between the V11 gradation reference voltage and the V12 gradation reference voltage is 1.4V.
As shown in FIG. 4, the gradation reference voltage values are not equally spaced, but the potential difference between the gradation reference voltages adjacent to each other in the vicinity of the halftone (V2 to V6) is small, and the others (V0 to V2, V6 to V8). ), The potential difference between adjacent gradation reference voltages is large.

図５は、図１に示す階調基準電圧生成回路６の変形例を示す図である。
図３に示す回路構成では、映像線駆動回路２内に、Ｒ０と、Ｒ６と、Ｒ１２の抵抗を設けるようにしたが、図５では、表示制御回路４と電源回路５と階調基準電圧生成回路６とが実装される基板上に、Ｒ０と、Ｒ６と、Ｒ１２の抵抗を設けるようにしたものである。この図５に示す場合でも、下記（３）式を満足するように、各抵抗の抵抗値が設定される。
［式３］
Ｖ０（１）／Ｒ０
＝Ｖ１（２）／Ｒ’１
＝Ｖ２（３）／Ｒ’２
＝Ｖ３（４）／Ｒ’３
＝Ｖ４（５）／Ｒ’４
＝Ｖ５（６）／Ｒ’５
＝Ｖ６（７）／Ｒ６
＝Ｖ７（８）／Ｒ’７
＝Ｖ８（９）／Ｒ’８
＝Ｖ９（１０）／Ｒ’９
＝Ｖ１０（１１）／Ｒ’１０
＝Ｖ１１（１２）／Ｒ’１１
＝Ｖ１２（１３）／Ｒ６
・・・・・・・・・・・・・・・・・・・・（３） FIG. 5 is a diagram showing a modification of the gradation reference voltage generation circuit 6 shown in FIG.
In the circuit configuration shown in FIG. 3, resistors R0, R6, and R12 are provided in the video line driving circuit 2, but in FIG. 5, the display control circuit 4, the power supply circuit 5, and the gradation reference voltage generation are generated. R0, R6, and R12 resistors are provided on a substrate on which the circuit 6 is mounted. Even in the case shown in FIG. 5, the resistance value of each resistor is set so as to satisfy the following expression (3).
[Formula 3]
V0 (1) / R0
= V1 (2) / R'1
= V2 (3) / R'2
= V3 (4) / R'3
= V4 (5) / R'4
= V5 (6) / R'5
= V6 (7) / R6
= V7 (8) / R'7
= V8 (9) / R'8
= V9 (10) / R'9
= V10 (11) / R'10
= V11 (12) / R'11
= V12 (13) / R6
(3)

ここで、Ｒ’２〜Ｒ’５、Ｒ’７〜Ｒ’１１の抵抗は、各階調基準電圧間に並列に接続される、複数の映像線駆動回路２内の直列抵抗分圧回路（図６の２４−２，２４−３に相当する直列抵抗分圧回路）の合成抵抗である。
図５に示す回路構成でも、直列抵抗分圧回路（２４−４）を流れる電流は、一定の電流値となり、直列抵抗分圧回路（２４−４）を流れる電流は、高電位電圧（ＡＶＤＤ）から供給されることになる。
そのため、図５に示す回路構成では、Ｖ１〜Ｖ１２の階調基準電圧が供給される供給端子からの電流の流入、流出がほとんど「０」（Ｉ１＝Ｉ２＝Ｉ３＝Ｉ４＝Ｉ５＝Ｉ８＝Ｉ９＝Ｉ１０＝Ｉ１１＝Ｉ１２＝０）となるので、従来のように、最大の階調基準電圧と最小の階調基準電圧の出力電圧精度が他の階調基準電圧の出力電圧精度よりも悪くなるのを低減することが可能となる。
なお、図３、図５において、Ｖ６の階調基準電圧と、Ｖ７の階調基準電圧とが、図４に示すように同じ電圧である場合は、Ｒ６の抵抗は必要ない。 Here, the resistors R′2 to R′5 and R′7 to R′11 are connected in parallel between the grayscale reference voltages, and are connected in series to the resistance dividing circuit in the plurality of video line driving circuits 2 (see FIG. 6 is a combined resistance of a series resistance voltage dividing circuit corresponding to 24-2 and 24-3.
Even in the circuit configuration shown in FIG. 5, the current flowing through the series resistance voltage dividing circuit (24-4) has a constant current value, and the current flowing through the series resistance voltage dividing circuit (24-4) is a high potential voltage (AVDD). Will be supplied from.
Therefore, in the circuit configuration shown in FIG. 5, current inflow and outflow from the supply terminal to which the gradation reference voltages V1 to V12 are supplied are almost “0” (I1 = I2 = I3 = I4 = I5 = I8 = I9). = I10 = I11 = I12 = 0), so that the output voltage accuracy of the maximum gradation reference voltage and the minimum gradation reference voltage is worse than the output voltage accuracy of the other gradation reference voltages as in the prior art. Can be reduced.
In FIGS. 3 and 5, when the gray scale reference voltage of V6 and the gray scale reference voltage of V7 are the same voltage as shown in FIG. 4, the resistance of R6 is not necessary.

また、本実施例の階調基準電圧生成回路では、直列抵抗分圧回路（２４−２〜２４−４）の各階調基準電圧印加端子間の抵抗値を、各階調基準電圧間の電位差に完全に比例した抵抗値としているが、完全に比例していなくても、同様な効果を有する。即ち、Ｖｋ（ｋ＋１）／Ｒｋ＝一定の電流値（ｋ＝０,...,１２）の値が完全に一致していなくとも、その値のばらつきが特定の範囲内にあれば、特定の範囲外のものに比べ、余分な消費電力の発生を抑えることが出来る。
直列抵抗分圧回路は半導体集積回路の内部に作られる。一般に、半導体集積回路内に作られる抵抗にはばらつきがあり、抵抗に半導体の拡散抵抗を用いた場合、抵抗値は±２０％のばらつきを生じる。なお出来上がった半導体集積回路を選別して抵抗値を±１０％のばらつきにすることも可能であるが、半導体集積回路の歩留が下がるので映像線駆動回路２のコストが高くなる。したがって、図３に示した直列抵抗分圧回路を用いる液晶表示装置で、Ｖｋ（ｋ＋１）／Ｒｋの値を完全に一致させるのは理想的であるが実用的ではない。
例えば、一定の電流値をＩｏ（Ｉｏ＝（Ｖｋ（ｋ＋１）／Ｒｋ）とするとき、Ｒｋの抵抗の抵抗値が、±２０％のばらつきを生じた場合、Ｒｋは、（１±０．２）Ｒｋとなるので、Ｉｏは、８３％から１２５％までばらつくことになる。
同様に、Ｒｋの抵抗の抵抗値が、±１０％のばらつきを生じた場合、Ｒｋは、（１±０．１）Ｒｋとなるので、Ｉｏは、９０％から１１１％までばらつくことになる。
したがって、本実施例において、直列抵抗分圧回路（２４−２〜２４−４）を流れる電流のばらつきが、±１５％以内、より好ましくは、±１０％以内であれば、コストが高くなく実用的な映像線駆動回路２を実現することが可能となる。
なお、前述の説明では、本発明を液晶表示装置に適用した実施例について説明したが、本発明はこれに限定されるものではなく、本発明は、有機ＥＬなどの大型高精細パネルを備える表示装置全てに適用可能である。
以上、本発明者によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。 In the gradation reference voltage generation circuit of this embodiment, the resistance value between the gradation reference voltage application terminals of the series resistance voltage dividing circuit (24-2 to 24-4) is completely set to the potential difference between the gradation reference voltages. Although the resistance value is proportional to, the same effect is obtained even if the resistance value is not completely proportional. That is, even if the value of Vk (k + 1) / Rk = constant current value (k = 0,..., 12) does not completely match, if the variation of the value is within a specific range, The generation of excess power consumption can be suppressed compared to those outside the range.
The series resistance voltage dividing circuit is formed inside the semiconductor integrated circuit. In general, there are variations in resistances produced in a semiconductor integrated circuit. When a semiconductor diffused resistor is used as the resistance, the resistance value varies by ± 20%. Although it is possible to select the completed semiconductor integrated circuit and make the resistance value vary by ± 10%, the yield of the semiconductor integrated circuit is lowered, so that the cost of the video line driving circuit 2 is increased. Therefore, in the liquid crystal display device using the series resistance voltage dividing circuit shown in FIG. 3, it is ideal but not practical to make the values of Vk (k + 1) / Rk completely coincide.
For example, when the constant current value is Io (Io = (Vk (k + 1) / Rk)), when the resistance value of the resistance of Rk varies ± 20%, Rk is (1 ± 0.2 ) Since Rk, Io varies from 83% to 125%.
Similarly, when the resistance value of the Rk resistor varies ± 10%, Rk becomes (1 ± 0.1) Rk, and therefore Io varies from 90% to 111%.
Therefore, in this embodiment, if the variation of the current flowing through the series resistance voltage dividing circuit (24-2 to 24-4) is within ± 15%, more preferably within ± 10%, the cost is not high and practical. A typical video line driving circuit 2 can be realized.
In the above description, the embodiment in which the present invention is applied to the liquid crystal display device has been described. However, the present invention is not limited to this, and the present invention is a display including a large-sized high-definition panel such as an organic EL. Applicable to all devices.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の実施例の液晶表示モジュールの概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the liquid crystal display module of the Example of this invention. 図１に示す映像線駆動回路の概略回路構成を示すブロック図である。FIG. 2 is a block diagram illustrating a schematic circuit configuration of a video line driving circuit illustrated in FIG. 1. 図２に示す階調電圧生成回路の回路構成を示す図である。FIG. 3 is a diagram showing a circuit configuration of a gradation voltage generation circuit shown in FIG. 2. 図１に示す階調基準電圧生成回路で生成される階調基準電圧の一例を示す図である。It is a figure which shows an example of the gradation reference voltage produced | generated by the gradation reference voltage generation circuit shown in FIG. 図１に示す階調基準電圧生成回路の変形例を示す図である。FIG. 6 is a diagram illustrating a modification of the gradation reference voltage generation circuit illustrated in FIG. 1. 図２に示す階調電圧生成回路の従来の回路構成を示す図である。It is a figure which shows the conventional circuit structure of the gradation voltage generation circuit shown in FIG.

符号の説明Explanation of symbols

１液晶表示パネル
２映像線駆動回路
３走査線駆動回路
４表示制御回路
５電源回路
６階調基準電圧生成回路
２１クロック制御部
２２ラッチアドレスセレクタ
２３ラッチ回路
２４Ｄ／Ａコンバータ回路
２４−１階調電圧生成回路
２４−２，２４−３，２４−４直列抵抗分圧回路
２５出力アンプ回路
ＧＬ走査線
ＤＬ映像線
ＴＦＴ薄膜トランジスタ
ＰＸ画素電極
ＣＴ対向電極（コモン電極
ＣＬ液晶容量
Ｃａｄｄ保持容量
Ｒ０〜Ｒ１２抵抗 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Video line drive circuit 3 Scan line drive circuit 4 Display control circuit 5 Power supply circuit 6 Gradation reference voltage generation circuit 21 Clock control part 22 Latch address selector 23 Latch circuit 24 D / A converter circuit 24-1 Gradation Voltage generation circuit 24-2, 24-3, 24-4 Series resistance voltage dividing circuit 25 Output amplifier circuit GL Scan line DL Video line TFT Thin film transistor PX Pixel electrode CT Counter electrode (Common electrode CL Liquid crystal capacitance Cadd Holding capacitance R0 to R12 Resistance

Claims

複数のサブピクセルを有する表示パネルと、
前記複数のサブピクセルに、複数の電位の階調電圧から選択した電圧を出力する映像線駆動回路と、
複数の電位の階調基準電圧を生成し、前記映像線駆動回路に出力する階調基準電圧生成回路とを備える表示装置であって、
前記階調基準電圧生成回路で生成される前記複数の階調基準電圧は、最大の階調基準電圧、最小の階調基準電圧および当該最大と最小の階調基準電圧以外の階調基準電圧を有し、
前記映像線駆動回路には、前記最大の階調基準電圧よりも高電位の高電位電圧と、前記最小の階調基準電圧よりも低電位の低電位電圧とが入力され、
前記映像線駆動回路は、階調電圧生成回路を有し、
前記階調電圧生成回路は、隣接する前記２つの階調基準電圧の間に接続される複数の分圧回路と、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗と、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗とを有し、
前記階調電圧生成回路は、前記各階調基準電圧の電位間を前記各分圧回路により複数の電位に分圧して前記複数の電位の階調電圧を生成し、
前記隣接する２つの階調基準電圧の間に接続される前記各分圧回路の抵抗値、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗の抵抗値、および、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗の抵抗値を、各階調基準電圧間の電位差、前記最大の階調基準電圧と前記高電位電圧との間の電位差、および、前記最小の階調基準電圧と前記低電位電圧との間の電位差にほぼ比例した抵抗値に設定したことを特徴とする表示装置。 A display panel having a plurality of subpixels;
A video line driving circuit for outputting a voltage selected from a plurality of gradation voltages to the plurality of sub-pixels;
A display device including a gradation reference voltage generation circuit that generates gradation reference voltages of a plurality of potentials and outputs the gradation reference voltages to the video line driving circuit;
The plurality of gradation reference voltages generated by the gradation reference voltage generation circuit include a maximum gradation reference voltage, a minimum gradation reference voltage, and a gradation reference voltage other than the maximum and minimum gradation reference voltages. Have
The video line driving circuit receives a high potential voltage higher than the maximum gradation reference voltage and a low potential voltage lower than the minimum gradation reference voltage.
The video line driving circuit has a gradation voltage generation circuit,
The gradation voltage generation circuit includes a plurality of voltage dividing circuits connected between the two adjacent gradation reference voltages, and a first voltage connected between the maximum gradation reference voltage and the high potential voltage. 1 resistor, and a second resistor connected between the minimum gradation reference voltage and the low potential voltage,
The gradation voltage generation circuit divides a potential between the gradation reference voltages into a plurality of potentials by the voltage dividing circuits to generate gradation voltages of the plurality of potentials,
A resistance value of each of the voltage dividing circuits connected between the two adjacent gradation reference voltages, a resistance value of a first resistor connected between the maximum gradation reference voltage and the high potential voltage; And a resistance value of a second resistor connected between the minimum gradation reference voltage and the low potential voltage, a potential difference between the gradation reference voltages, the maximum gradation reference voltage, and the high potential voltage. And a resistance value substantially proportional to the potential difference between the minimum gradation reference voltage and the low potential voltage.

複数のサブピクセルを有する表示パネルと、
前記複数のサブピクセルに、複数の電位の階調電圧から選択した電圧を出力する少なくとも１個の映像線駆動回路と、
複数の電位の階調基準電圧を生成し、前記映像線駆動回路に出力する階調基準電圧生成回路とを備える表示装置であって、
前記階調基準電圧生成回路で生成される前記複数の階調基準電圧は、最大の階調基準電圧、最小の階調基準電圧および当該最大と最小の階調基準電圧以外の階調基準電圧を有し、
前記最大の階調基準電圧と前記最大の階調基準電圧よりも高電位の高電位電圧との間に接続される第１抵抗と、
前記最小の階調基準電圧と前記最小の階調基準電圧よりも低電位の低電位電圧との間に接続される第２抵抗とを有し、
前記少なくとも１個の映像線駆動回路は、階調電圧生成回路を有し、
前記階調電圧生成回路は、隣接する前記２つの階調基準電圧の間に接続される複数の分圧回路を有し、前記各階調基準電圧の電位間を前記各分圧回路により複数の電位に分圧して前記複数の電位の階調電圧を生成し、
前記隣接する２つの階調基準電圧の間に並列に接続される、前記少なくとも１個の映像線駆動回路の前記各分圧回路の合成抵抗値、前記最大の階調基準電圧と前記高電位電圧との間に接続される第１抵抗の抵抗値、および、前記最小の階調基準電圧と前記低電位電圧との間に接続される第２抵抗の抵抗値を、各階調基準電圧間の電位差、前記最大の階調基準電圧と前記高電位電圧との間の電位差、および、前記最小の階調基準電圧と前記低電位電圧との間の電位差にほぼ比例した抵抗値に設定したことを特徴とする表示装置。 A display panel having a plurality of subpixels;
At least one video line driving circuit for outputting a voltage selected from a plurality of gradation voltages of a plurality of potentials to the plurality of sub-pixels;
A display device including a gradation reference voltage generation circuit that generates gradation reference voltages of a plurality of potentials and outputs the gradation reference voltages to the video line driving circuit;
The plurality of gradation reference voltages generated by the gradation reference voltage generation circuit include a maximum gradation reference voltage, a minimum gradation reference voltage, and a gradation reference voltage other than the maximum and minimum gradation reference voltages. Have
A first resistor connected between the maximum gradation reference voltage and a high potential voltage higher than the maximum gradation reference voltage;
A second resistor connected between the minimum gradation reference voltage and a low potential voltage lower than the minimum gradation reference voltage;
The at least one video line driving circuit includes a gradation voltage generating circuit;
The gradation voltage generation circuit includes a plurality of voltage dividing circuits connected between the two adjacent gradation reference voltages, and a plurality of potentials are generated between the potentials of the gradation reference voltages by the voltage dividing circuits. To generate gradation voltages of the plurality of potentials,
The combined resistance value of each of the voltage dividing circuits of the at least one video line driving circuit connected in parallel between the two adjacent gradation reference voltages, the maximum gradation reference voltage, and the high potential voltage The resistance value of the first resistor connected between the second reference voltage and the resistance value of the second resistance connected between the minimum gray level reference voltage and the low potential voltage is a potential difference between the gray level reference voltages. The resistance value is approximately proportional to the potential difference between the maximum gradation reference voltage and the high potential voltage and the potential difference between the minimum gradation reference voltage and the low potential voltage. Display device.

前記階調基準電圧は、等間隔でない階調基準電圧を有することを特徴とする請求項１または請求項２に記載の表示装置。 The display device according to claim 1, wherein the gradation reference voltages have gradation reference voltages that are not equally spaced.

複数の電位の階調基準電圧は、ｎ（ｎ≧３）個の階調基準電圧であり、
前記隣接する２つの階調基準電圧の間の電位差をＶｊ（ｊ＋１）（ｊ＝１,...,ｎ−１）、前記最大の階調基準電圧と前記高電位電圧との間の電位差をＶ０１、前記最小の階調基準電圧と前記低電位電圧との間の電位差をＶｎ（ｎ＋１）、前記隣接する２つの階調基準電圧の間の合成抵抗値Ｒｊ、前記第１抵抗の抵抗値をＲ０、前記第２の抵抗の抵抗値をＲ（ｎ＋１）とするとき、Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が特定の返納の範囲内で一致することを特徴とする請求項１ないし請求項３の何れか１項に記載の表示装置。 The gradation reference voltages of a plurality of potentials are n (n ≧ 3) gradation reference voltages,
The potential difference between the two adjacent gradation reference voltages is Vj (j + 1) (j = 1,..., N−1), and the potential difference between the maximum gradation reference voltage and the high potential voltage is V01 is a potential difference between the minimum gradation reference voltage and the low potential voltage, Vn (n + 1), a combined resistance value Rj between the two adjacent gradation reference voltages, and a resistance value of the first resistor. R0, when the resistance value of the second resistor is R (n + 1), the value of Vk (k + 1) / Rk (k = 0,..., N) matches within a specific return range. The display device according to any one of claims 1 to 3, wherein the display device is characterized.

前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が、±２０％の変動の範囲内で一致することを特徴とする請求項４に記載の表示装置。 The display device according to claim 4, wherein the values of Vk (k + 1) / Rk (k = 0,..., N) match within a variation range of ± 20%.

前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が、±１０％の変動の範囲内で一致することを特徴とする請求項４に記載の表示装置。 The display device according to claim 4, wherein the values of Vk (k + 1) / Rk (k = 0,..., N) match within a range of fluctuation of ± 10%.

前記Ｖｋ（ｋ＋１）／Ｒｋ（ｋ＝０,...,ｎ）の値が完全に一致することを特徴とする請求項４に記載の表示装置。 The display device according to claim 4, wherein the values of Vk (k + 1) / Rk (k = 0,..., N) completely coincide with each other.