JP2008159948A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008159948A JP2008159948A JP2006348570A JP2006348570A JP2008159948A JP 2008159948 A JP2008159948 A JP 2008159948A JP 2006348570 A JP2006348570 A JP 2006348570A JP 2006348570 A JP2006348570 A JP 2006348570A JP 2008159948 A JP2008159948 A JP 2008159948A
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Abstract
【解決手段】この半導体装置は、半導体チップ1と、半導体チップ1の機能面1Aを被覆する表面保護膜3と、表面保護膜3の上に形成され、貫通孔10を有する応力緩和層4と、貫通孔10に埋設された埋設部13および、埋設部13と一体的に形成され、応力緩和層4上に突出する突出部14を有する接続パッド5とを備えている。接続パッド5の突出部14は、半田濡れ性を有する金属(たとえば、銅)からなる外周銅膜24の周縁部21に囲まれている。そして、外部との電気接続のための半田パッド6は、突出部14の全表面(先端面14Aおよび側面14B)および外周銅膜24の周縁部21の表面21Aを覆うように形成されている。
【選択図】図2
Description
そこで、この発明の目的は、半田端子に生じる応力を緩和することができるとともに、半導体チップに対する接着強度を向上させ、半田端子の剥離を防止することができる半導体装置を提供することにある。
図1は、この発明の一実施形態に係る半導体装置の図解的な底面図(実装基板への接合面を示す図)である。図2は、図1に示すA−Aの切断面で切断したときの断面図である。なお、図2では、半導体装置を破断線で破断することにより、その一部を省略して示している。
電極パッド2は、たとえば、平面視略矩形状のアルミニウムパッドであり、半導体チップ1の機能面1Aに作り込まれた機能素子と電気的に接続されている。また、電極パッド2は、半導体チップ1の外周縁に沿って、平面視矩形環状に2列に並べて配置されており、互いに隣り合う電極パッド2の間には、それぞれ適当な間隔が空けられている(図1参照)。
応力緩和層4は、たとえば、ポリイミドからなる。応力緩和層4は、表面保護膜3の表面全域を被覆するように形成されて、この半導体装置に加わる応力を吸収して緩和する機能を有している。また、応力緩和層4には、各電極パッド2と対向する位置に貫通孔10(開口部)が貫通して形成されており、パッド開口9から露出する電極パッド2は、貫通孔10を通して外部に臨んでいる。そして、電極パッド2の表面、貫通孔10の内面および応力緩和層4の表面における貫通孔10の周縁部11を覆うように、たとえば、チタン、クロム、チタンタングステンなどからなるバンプ下地層12が形成されている。
そして、外周銅膜24上に、接続パッド5が形成されている。この接続パッド5は、半田濡れ性を有する金属、たとえば、銅を用いて形成されている。この接続パッド5は、貫通孔10に埋設された埋設部13と、この埋設部13と一体的に形成され、応力緩和層4上に突出した突出部14とを備えている。
突出部14は、たとえば、外周銅膜24の表面からの高さが10〜50μmの円柱状に形成されている。また、突出部14は、半導体チップ1と応力緩和層4との積層方向(以下、単に「積層方向」という。)と直交する方向における幅(径)が、貫通孔10の同方向における開口幅(径)よりも大きく(幅広に)形成されている。これにより、突出部14の周縁部15は、積層方向と直交する方向に張り出し、バンプ下地層12および外周銅膜24を介して、応力緩和層4の表面と積層方向に対向している。さらに、突出部14は、積層方向と直交する方向における幅(径)が、外周銅膜24の同方向における幅(径)よりも小さく形成されている。これにより、外周銅膜24の周縁部21は、突出部14の側方に張り出しており、突出部14の周囲を取り囲み、突出部14の応力緩和層4上への突出量よりも小さな厚さに形成された金属鍔部をなしている。
図3A〜図3Gは、図1に示す半導体装置の製造方法を示す図解的な断面図である。
この半導体装置を製造するに際しては、図3Aに示すように、まず、複数の半導体チップ1が作り込まれ、その表面全域が表面保護膜3で覆われた半導体ウエハWが用意される。なお、表面保護膜3には、電極パッド2を露出させるパッド開口9が形成されている。この半導体ウエハWの状態で、表面保護膜3上に、応力緩和層4が形成される。
貫通孔10が形成された後は、図3Cに示すように、半導体ウエハW上に、バンプ下地層12および銅膜25が、たとえば、スパッタリング法などにより、この順に形成される。
次に、図3Dに示すように、銅膜25の上に、フォトレジスト16および金属層17が形成される。より具体的には、まず、公知のフォトリソグラフィ技術により、銅膜25の上に、接続パッド5の突出部14を形成すべき領域に開口部18を有するフォトレジスト16が形成される。フォトレジスト16が形成された後は、半導体ウエハW上の全領域に、接続パッド5の材料として用いられる銅からなる金属層17が、スパッタリング法などにより形成される。その後は、フォトレジスト16が除去されることにより、金属層17の不要部分(接続パッド5以外の部分)がフォトレジスト16とともにリフトオフされる。これにより、接続パッド5が形成される。
続いて、図3Fに示すように、接続パッド5の突出部14の全表面(先端面14Aおよび側面14B)および外周銅膜24の周縁部21の表面21Aに半田を接着させることにより、突出部14の全表面(先端面14Aおよび側面14B)および外周銅膜24の周縁部21の表面21Aを覆う半田パッド6が形成される。そして、図3Gに示すように、半導体ウエハW内の各半導体チップ1間に設定されたダイシングラインLに沿って、半導体ウエハWが切断されて(ダイシング)される。これにより、図1に示す構成の半導体装置が得られる。
なお、上述の実施形態では、接続パッド5に接着される半田端子を略半球状の半田パッド6としたが、実装基板7上のパッド8と接続可能な半田端子であれば、その形状は略半球状に限られない。たとえば、図4に示すように、略球状に形成される半田ボール20としてもよい。
たとえば、上述の実施形態では、接続パッド5が銅を用いて形成されるとしたが、半田濡れ性を有する金属であれば、銅に限られない。たとえば、接続パッド5は、金を用いて形成されてもよい。その場合には、たとえば、図5に示すように、接続パッド5の突出部14と半田パッド6との界面に、金の拡散を防止するためのニッケルからなる拡散防止層19を形成することが好ましい。
また、上述の実施形態では、半導体チップ1における電極パッド2の配置形態について、電極パッド2は、半導体チップ1の外周縁に沿って、平面視矩形環状に2列に並べて配置されているとしたが、半導体チップ1の機能面1Aに規則的に配置される形態であれば矩形環状に限られず、たとえば、マトリックス状などで配置されていてもよい。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。
2 電極パッド
4 応力緩和層
5 接続パッド
6 半田パッド
10 貫通孔
14 突出部
14A 先端面
14B 側面
20 半田ボール
21 周縁部
26 突出部
27 上側突出部
28 下側突出部
29 金属パッド
Claims (1)
- 半導体チップと、
前記半導体チップの表面に形成された電気接続用の内部パッドと、
前記半導体チップ上に形成され、前記内部パッドを露出させる開口部を有する応力緩和層と、
半田濡れ性を有する金属からなり、前記内部パッドにおける前記開口部に臨む部分上に形成され、前記応力緩和層上に突出する突出部を備える接続パッドと、
半田濡れ性を有する金属からなり、前記突出部の周囲を取り囲み、前記突出部の前記応力緩和層上への突出量より小さい厚さに形成された金属鍔部と、
前記突出部および前記金属鍔部上に形成され、外部との電気接続のための半田端子と、を含むことを特徴とする、半導体装置。
Priority Applications (5)
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JP2006348570A JP2008159948A (ja) | 2006-12-25 | 2006-12-25 | 半導体装置 |
CN2007101611233A CN101211876B (zh) | 2006-12-25 | 2007-12-18 | 半导体装置 |
KR1020070136626A KR20080059525A (ko) | 2006-12-25 | 2007-12-24 | 반도체 장치 |
TW096149978A TW200843060A (en) | 2006-12-25 | 2007-12-25 | Semiconductor device |
US12/003,422 US9343416B2 (en) | 2006-12-25 | 2007-12-26 | Semiconductor device employing wafer level chip size package technology |
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JP2006348570A JP2008159948A (ja) | 2006-12-25 | 2006-12-25 | 半導体装置 |
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US (1) | US9343416B2 (ja) |
JP (1) | JP2008159948A (ja) |
KR (1) | KR20080059525A (ja) |
CN (1) | CN101211876B (ja) |
TW (1) | TW200843060A (ja) |
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JPWO2017098809A1 (ja) * | 2015-12-11 | 2018-08-30 | 株式会社村田製作所 | 弾性波装置 |
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US8446008B2 (en) * | 2006-12-25 | 2013-05-21 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
US8604356B1 (en) | 2010-11-12 | 2013-12-10 | Amkor Technology, Inc. | Electronic assembly having increased standoff height |
FR2977383A1 (fr) * | 2011-06-30 | 2013-01-04 | St Microelectronics Grenoble 2 | Plot de reception d'un fil de cuivre |
US9786634B2 (en) * | 2015-07-17 | 2017-10-10 | National Taiwan University | Interconnection structures and methods for making the same |
US10699948B2 (en) * | 2017-11-13 | 2020-06-30 | Analog Devices Global Unlimited Company | Plated metallization structures |
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- 2007-12-24 KR KR1020070136626A patent/KR20080059525A/ko not_active Application Discontinuation
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TW200843060A (en) | 2008-11-01 |
KR20080059525A (ko) | 2008-06-30 |
CN101211876A (zh) | 2008-07-02 |
CN101211876B (zh) | 2011-11-09 |
US20090160049A1 (en) | 2009-06-25 |
US9343416B2 (en) | 2016-05-17 |
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