JP2008153682A - Electronic parts mounter and its manufacturing method - Google Patents

Electronic parts mounter and its manufacturing method Download PDF

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Publication number
JP2008153682A
JP2008153682A JP2008014206A JP2008014206A JP2008153682A JP 2008153682 A JP2008153682 A JP 2008153682A JP 2008014206 A JP2008014206 A JP 2008014206A JP 2008014206 A JP2008014206 A JP 2008014206A JP 2008153682 A JP2008153682 A JP 2008153682A
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Prior art keywords
electronic component
wiring
bump
component mounting
resin layer
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Tadatomo Suga
唯知 須賀
Hiroshi Ohira
洋 大平
Kenji Osawa
健治 大澤
Asao Iijima
朝雄 飯島
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Invensas Corp
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Tessera Interconnect Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic parts mounter and its manufacturing method, that enhance the properties in high-frequency, quick response or the like and with high reliability, by enhancing the mounting density of electronic parts and reducing the length of wirings. <P>SOLUTION: The mounter is provided with a first wiring portion 5a in which bumps 4 are formed upward in a portion of wiring films 2a, an electronic part 6 whose electrodes are connected to the bumps 4, a second wiring portion 5b in which the bumps 4 are formed downward in a portion of wiring films 2a, an electronic part 6 whose electrodes are connected to the downward-looking bumps 4, an electronic part 6 whose electrodes are connected to the first wiring portion 5a and the wiring films 2a so that the wiring films of the first wiring portion 5a exposes downward, and the wiring films of the second wiring portion exposes upward, and an interlayer insulating resin layer 10 sealing the second wiring portion 5b and the electronic part 6 whose electrodes are connected to the wiring films 2a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子部品実装装置とその製造方法に関する。   The present invention relates to an electronic component mounting apparatus and a manufacturing method thereof.

各種電子部品、例えば抵抗素子、誘導素子或いは容量素子、整流素子（ダイオード）等の受動素子、或いは増幅素子（トランジスタ等）、半導体集積回路素子（ＩＣ）は、従来、プリント配線基板の一方又は両方の主面の配線膜に電極を半田付け等でボンディングするというような方法により搭載され、そのプリント配線基板が各種電子機器その他の機器類等に取り付けられるのが普通であった（特許第３６５３４５２号公報参照）。   Various electronic components such as resistive elements, inductive elements or capacitive elements, passive elements such as rectifier elements (diodes), amplifying elements (transistors etc.), and semiconductor integrated circuit elements (ICs) are conventionally one or both of printed wiring boards. In general, the printed circuit board is mounted on various electronic devices and other devices by mounting the electrodes on the wiring film of the main surface by soldering or the like (Japanese Patent No. 36553452). See the official gazette).

しかし、各種電子機器その他の機器類は小型化、多機能化の要求が強くなる一方であり、そのような要求に応えるには、電子部品の搭載密度を高める必要があるが、単にプリント配線基板の一方又は両方の主面の配線膜に電子部品の電極を半田付け等をボンディングするというような電子部品の搭載方法では、電子部品の搭載密度を高めることには大きな制約があり、電子部品の搭載密度を高める要求に充分に応えることが難しいのが実情である。   However, various electronic devices and other devices are becoming increasingly demanded for miniaturization and multi-functionality. In order to meet such demands, it is necessary to increase the mounting density of electronic components. In the mounting method of an electronic component such as soldering the electrode of the electronic component to the wiring film on one or both of the main surfaces, there is a great restriction on increasing the mounting density of the electronic component. The reality is that it is difficult to fully meet the demand for higher mounting density.

そして、電子部品の搭載密度を高めるという要求に応えることができないことは、単に、それを用いる電子機器等の機器類の小型化、高機能化に寄与できないと言う問題をもたらすのみならず、電子部品及びプリント配線基板の配線からなる電子回路の電気的特性、例えば高周波特性、高速性の向上という要求にも応えることが難しいという問題ももたらす。   And the failure to meet the demand to increase the mounting density of electronic components not only brings about the problem that it cannot contribute to the downsizing and higher functionality of electronic devices and the like that use the electronic components. There is also the problem that it is difficult to meet the demands for improving the electrical characteristics of electronic circuits composed of components and wiring of printed circuit boards, such as high frequency characteristics and high speed.

即ち、電子部品、特にＩＣは種々の技術開発により極めて高周波数特性、高速性の向上が進んでいるが、それをプリント配線基板に高密度の搭載できないが故に、配線長が長くなり、寄生抵抗、寄生容量、寄生誘導が大きくなり、折角のＩＣの優れた電気的特性がプリント配線基板への搭載によって大きく損なわれてしまうという問題があったのである。   In other words, electronic components, especially ICs, have improved extremely high frequency characteristics and high speed due to various technological developments, but they cannot be mounted on a printed wiring board at a high density, resulting in a long wiring length and parasitic resistance. There is a problem that parasitic capacitance and parasitic induction increase, and the excellent electrical characteristics of the IC at the corner are greatly impaired by mounting on the printed wiring board.

そのため、電子部品の高密度搭載のための各種試みが行われた。図１４はそのような試みの一例を工程順に示す断面図である。
（Ａ）図１４（Ａ）に示すように、ＩＣサポート板ａを用意し、その上に所定の位置関係で複数の電子部品、例えばＩＣｂ、ｂ、・・・を配置する。 Therefore, various attempts for high-density mounting of electronic components have been made. FIG. 14 is a cross-sectional view showing an example of such an attempt in the order of steps.
(A) As shown in FIG. 14A, an IC support plate a is prepared, and a plurality of electronic components, for example, ICb, b,.

（Ｂ）次に、図１４（Ｂ）に示すように、絶縁性樹脂ｃを、上記ＩＣサポート板ａ上に上記ＩＣｂ、ｂ、・・・を覆うように圧着する。これにより、ＩＣｂ、ｂ、・・・を絶縁性樹脂ｃで封止した状態にする。
（Ｃ）次に、図１４（Ｃ）に示すように、上記ＩＣサポート板ａを取り外す。 (B) Next, as shown in FIG. 14B, an insulating resin c is pressure-bonded onto the IC support plate a so as to cover the ICb, b,. Thereby, ICb, b,... Are sealed with the insulating resin c.
(C) Next, as shown in FIG. 14C, the IC support plate a is removed.

（Ｄ）次に、図１４（Ｄ）に示すように、上記絶縁性樹脂ｃ及びＩＣｂ、ｂ、・・・のＩＣサポート板ａを取り外すことにより露出した表面に銅箔ｄをスパッタリング或いはメッキ等により形成する。
（Ｅ）次に、上記銅箔ｄをパターニング（選択的エッチング）することにより、図１４（Ｅ）に示すように、配線膜ｅ、ｅ、・・・を形成する。 (D) Next, as shown in FIG. 14 (D), the copper foil d is sputtered or plated on the surface exposed by removing the insulating resin c and the IC support plate a of ICb, b,... To form.
(E) Next, by patterning (selective etching) the copper foil d, wiring films e, e,... Are formed as shown in FIG.

このような技術によれば、プリント配線基板の本体を成す絶縁層に相当する絶縁樹脂層ｃ内にＩＣｂ、ｂ、・・・を埋め込むことができ、その分、小型化、高集積化を図ることができる。また、高密度実装ができるが故に、ＩＣｂ、ｂ、・・・相互間、或いは外部と各ＩＣｂ、ｂ・・・間を結ぶ配線の長さを比較的短くできるので、実装した状態におけるＩＣｂ、ｂ、・・・及び配線からなる回路の各種電気的特性、例えば高周波特性、高速性を改善することができるという利点があった。
特許第３６５３４５２号公報 According to such a technique, ICb, b,... Can be embedded in the insulating resin layer c corresponding to the insulating layer constituting the main body of the printed wiring board, and accordingly, miniaturization and high integration are achieved. be able to. Further, since high-density mounting is possible, the length of the wiring connecting ICb, b,... Or between the outside and each ICb, b. There is an advantage that various electrical characteristics of the circuit composed of b,... and wiring, for example, high frequency characteristics and high speed can be improved.
Japanese Patent No. 3655352

しかしながら、図１４に示す従来技術には下記の問題があった。
第１の問題は、配線膜ｅ、ｅ、・・・が、ＩＣｂと絶縁樹脂層ｃとの境界の近傍にあたる部分［図１４（Ｅ）のｆ参照］にて断線が生じ易いという問題である。これは、ＩＣｂと絶縁樹脂層ｃとの熱膨張係数が異なることから製造過程における、或いは使用時における温度変化により熱応力が配線膜ｅ、ｅ、・・・の上記ｆの部分に生じることに起因すると考えられる。 However, the prior art shown in FIG. 14 has the following problems.
The first problem is that the wiring films e, e,... Are likely to be disconnected at a portion near the boundary between the ICb and the insulating resin layer c (see f in FIG. 14E). . This is because the thermal expansion coefficient is different between the ICb and the insulating resin layer c, so that thermal stress is generated in the portion f of the wiring films e, e,. It is thought to be caused.

第２の問題は、ＩＣサポート板ａ上に置いたＩＣｂ、ｂ、・・・が位置ずれし易く、各ＩＣｂ、ｂ、・・・を、その間の位置関係が精確に設定通りになるように位置決めして樹脂ｃにより封止することが難しく、不良品が生じ易いという問題である。
即ち、ＩＣサポート板ａ上に各ＩＣｂ、ｂ、・・・を所定の位置関係に精確に置くことは現在の技術では可能ではあるが、しかし、その位置決めされたＩＣｂ、ｂ、・・・を絶縁樹脂層ｃで樹脂封止するまで各ＩＣｂ、ｂ、・・・の位置をＩＣサポート板ａ上にて動かないように保つ有効な手段がなく、また、絶縁樹脂層ｃで樹脂封止する過程でもＩＣｂ、ｂ、・・・の位置がずれる可能性がある。従って、各ＩＣｂ、ｂ、・・・を、その間の位置関係が精確に設定通りになるように位置決めして樹脂ｃにより封止することが難しいという問題が生じるのである。 The second problem is that the ICb, b,... Placed on the IC support plate a are easily displaced, and the positional relationship between the ICb, b,. This is a problem that it is difficult to position and seal with resin c, and defective products are likely to occur.
In other words, it is possible with the current technology to accurately place each ICb, b,... On the IC support plate a, but the positioned ICb, b,. There is no effective means for keeping the position of each ICb, b,... On the IC support plate a until the resin sealing is performed with the insulating resin layer c, and the resin sealing is performed with the insulating resin layer c. There is a possibility that the positions of ICb, b,. Therefore, there is a problem that it is difficult to position each ICb, b,... So that the positional relationship therebetween is exactly as set and to be sealed with the resin c.

第３の問題は、配線膜ｅ、ｅ、・・・を形成すべく、銅箔ｄを選択的にエッチングするときに、エッチング液がＩＣｂと絶縁樹脂層ｃとの境界に染み込み易く、染みこんだ場合、封止効果が低下し信頼性が低くなるおそれがあるという問題である。
これは、電子部品実装装置としての信頼性を低くする大きな要因となるので、看過できない問題である。 The third problem is that when the copper foil d is selectively etched to form the wiring films e, e,..., The etchant easily permeates the boundary between the ICb and the insulating resin layer c. In this case, there is a problem that the sealing effect is lowered and the reliability may be lowered.
This is a problem that cannot be overlooked because it is a major factor in reducing the reliability of the electronic component mounting apparatus.

第４の問題は、より一層の多層配線化が難しいという問題である。電子部品実装装置にはより一層の高集積化、高密度化が要求され、それに応えるには電子部品実装装置の多層配線化が有効と思われるが、上記従来技術によれば、多層配線化が難しく、より一層の高集積化、高密度化の要求に応える可能性が低いのである。   The fourth problem is that it is difficult to form a multilayer wiring. Electronic component mounting devices are required to have higher integration and higher density. To meet this demand, it is considered effective to make multilayer wiring of electronic component mounting devices. It is difficult, and the possibility of meeting the demand for higher integration and higher density is low.

本発明はこのような問題点を解決すべく為されたものであり、電子部品の実装密度を高くし、配線長を短くして高周波特性、高速性等の特性を高くし、且つ信頼度を高くした電子部品実装装置とその製造方法を提供することを目的とする。   The present invention has been made to solve such problems. The mounting density of electronic components is increased, the wiring length is shortened, the characteristics such as high frequency characteristics and high speed are increased, and the reliability is improved. An object of the present invention is to provide an electronic component mounting apparatus and a method for manufacturing the same.

請求項１の電子部品実装装置は、金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが上向きに形成された第１の配線部分と、この第１の配線部分の上記上向きのバンプに電極が接続された電子部品と、金属箔により形成された複数の配線膜の少なくとも一部の配線膜の一部分に金属からなる略コニーデ状のバンプが下向きに形成された第２の配線部分と、この第２の配線部分の上記下向きのバンプに電極が接続された電子部品と、上記第１の配線部分の上記配線膜が下面に露出し、上記第２の配線部分の上記配線膜が上面に露出するように、上記第１の配線部分及びその配線膜に電極が接続された電子部品、並びに上記第２の配線部分及びその配線膜に電極が接続された電子部品を封止する層間絶縁樹脂層と、を少なくとも有することを特徴とする。   The electronic component mounting apparatus according to claim 1 includes a first wiring portion in which a substantially conical bump made of metal is formed upward on at least a part of a plurality of wiring films formed of a metal foil, An electronic component in which an electrode is connected to the upward bump of the first wiring portion, and a substantially conical bump made of metal downward on at least a part of the wiring film of a plurality of wiring films formed of metal foil A second wiring portion formed on the second wiring portion; an electronic component having an electrode connected to the downward bump of the second wiring portion; and the wiring film of the first wiring portion exposed on a lower surface. The first wiring portion and the electronic component having an electrode connected to the wiring film, and the electrode connected to the second wiring portion and the wiring film so that the wiring film of the second wiring portion is exposed on the upper surface. Sealed electronic components And having an interlayer insulating resin layer, at least.

請求項２の電子部品実装装置は、金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分と、この配線部分の上記バンプに電極が接続された電子部品と、上記配線部分の上記配線膜が露出するように上記電子部品を、その配線膜との間の接続部分及び反電極側の部分を含め囲繞する層間絶縁樹脂層と、この層間絶縁用絶縁樹脂層の上記配線部分と反対側の主面に金属箔により形成された配線膜と、上記層間絶縁用絶縁樹脂層の上記配線部分と反対側の主面に金属箔により形成された配線膜に、そこから該樹脂層自身を貫通して上記配線部分の配線膜と接続されるように形成された金属からなるバンプと、を少なくとも有することを特徴とする。   The electronic component mounting apparatus according to claim 2 is a wiring portion in which a substantially conical bump made of metal is formed on at least a part of a plurality of wiring films formed of metal foil, and the bump of the wiring portion An interlayer insulating resin layer that surrounds the electronic component including the connection portion between the electronic component having the electrode connected to the wiring film and the wiring film so that the wiring film of the wiring portion is exposed and the portion on the side opposite to the electrode. A wiring film formed of a metal foil on the main surface opposite to the wiring portion of the insulating resin layer for interlayer insulation, and a metal foil on the main surface opposite to the wiring portion of the insulating resin layer for interlayer insulation. And a bump made of a metal formed so as to penetrate the resin layer itself and to be connected to the wiring film of the wiring portion.

請求項３の電子部品実装装置の製造方法は、金属箔の一方の主面に金属からなる略コニーデ状のバンプを選択的に形成した金属部材の該各バンプに電子部品の各電極を接続した電子部品搭載金属部材を２つ用意し、上記電子部品搭載金属部材のうちの一方に、その搭載電子部品をその上面を含め囲繞するように層間絶縁樹脂層を塗布し、その後、上記電子部品搭載金属部材のうちの他方の電子部品の搭載面を上記一方の電子部品搭載金属部材の搭載面に臨ませ、上記層間絶縁樹脂層によって該他方の電子部品により封止され、両電子部品搭載金属部材の金属箔間が層間絶縁されるように、上記二つの電子部品搭載金属部材を、上記層間絶縁樹脂層を介して積層一体化し、しかる後、上記二つの電子部品搭載金属部材の金属箔を順次又は同時にパターニングすることを特徴とする。   According to a third aspect of the present invention, there is provided a method of manufacturing an electronic component mounting apparatus in which each electrode of an electronic component is connected to each bump of a metal member in which a substantially conical bump made of metal is selectively formed on one main surface of the metal foil. Two electronic component mounting metal members are prepared, and an interlayer insulating resin layer is applied to one of the electronic component mounting metal members so as to surround the mounting electronic component including its upper surface, and then the electronic component mounting is performed. The mounting surface of the other electronic component among the metal members faces the mounting surface of the one electronic component mounting metal member, and is sealed by the other electronic component by the interlayer insulating resin layer. The two electronic component mounting metal members are laminated and integrated via the interlayer insulating resin layer so that the metal foils are interlayer-insulated, and then the metal foils of the two electronic component mounting metal members are sequentially formed. Or at the same time Characterized in that it turning.

請求項４の電子部品実装装置の製造方法は、金属箔の一方の主面に金属からなるコニーデ状の複数のバンプを形成した第１の金属部材と、金属箔の一方の主面に金属からなり上記バンプより高さの高いコニーデ状のバンプを形成した第２の金属部材を用意し、上記第１の金属部材には、そのバンプに電子部品の電極を接続することによって電子部品を搭載し、上記第２の金属部材には、その金属箔のバンプ形成面に層間絶縁樹脂層を塗布し、上記第２の金属部材のバンプ形成側に、上記第１の金属部材のバンプ形成側を臨ませて、上記電子部品が上記層間絶縁樹脂層内に入り且つ第２の金属部材のバンプが第１の金属部材の配線膜に接続されるように上記第１及び第２の金属部材を層間絶縁樹脂層を介して積層一体化することを特徴とする。   According to a fourth aspect of the present invention, there is provided a method for manufacturing the electronic component mounting apparatus, comprising: a first metal member having a plurality of conical-shaped bumps formed of metal on one main surface of the metal foil; and a metal on one main surface of the metal foil. A second metal member formed with a conical-shaped bump higher than the bump is prepared, and the electronic component is mounted on the first metal member by connecting an electrode of the electronic component to the bump. The second metal member is coated with an interlayer insulating resin layer on the bump forming surface of the metal foil, and the bump forming side of the first metal member is exposed to the bump forming side of the second metal member. Further, the first and second metal members are interlayer-insulated so that the electronic component enters the interlayer insulating resin layer and the bumps of the second metal member are connected to the wiring film of the first metal member. It is characterized by being laminated and integrated through a resin layer.

請求項５の電子部品実装装置は、ベアの半導体集積回路素子と、金属箔により形成された複数の配線膜の内の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分と、この配線部分の上記バンプの形成された側の面に該各バンプによって貫通された状態で形成された層間絶縁樹脂層と、からなり、上記各バンプが上記ベアの半導体集積回路素子の電極に接続されて、上記配線部分が上記層間絶縁樹脂層を介して上記ベアの半導体集積回路素子に一体化されてなることを特徴とする。   In the electronic component mounting apparatus according to claim 5, a bare semiconductor integrated circuit element and a substantially conical bump made of metal are formed on at least a part of a plurality of wiring films formed of a metal foil. A wiring portion; and an interlayer insulating resin layer formed on the surface of the wiring portion on the side where the bump is formed, and being penetrated by the bump. The bump is a bare semiconductor integrated circuit element. And the wiring portion is integrated with the bare semiconductor integrated circuit element through the interlayer insulating resin layer.

請求項６の電子部品実装装置の製造方法は、金属箔の一部に金属からなる略コニーデ状のバンプが形成された電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものと、電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハとを用意し、上記各バンプ端部を、上記半導体ウェハの対応する電極に接続することにより上記電子部品実装装置複数個分の配線部分を上記層間絶縁樹脂層を介して上記半導体ウェハと一体化し、その後、上記金属箔をパターニングすることにより配線膜を形成し、しかる後、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離することにより請求項５の電子部品実装装置を得ることを特徴とする。   According to a sixth aspect of the present invention, there is provided a method for manufacturing an electronic component mounting apparatus, comprising: a plurality of electronic component mounting apparatuses each having a substantially conical-shaped bump formed on a part of a metal foil; A semiconductor wafer in which a semiconductor integrated circuit element for a plurality of electronic component mounting apparatuses is integrally formed is prepared by forming an interlayer insulating resin layer in a state of being penetrated by bumps, By connecting to the corresponding electrode of the semiconductor wafer, the wiring parts for the plurality of electronic component mounting apparatuses are integrated with the semiconductor wafer via the interlayer insulating resin layer, and then the metal foil is patterned to form a wiring film Thereafter, the semiconductor wafer, the interlayer insulating resin layer, and the upper wiring portion are cut into individual electronic component mounting apparatuses by cutting. Wherein the of obtaining an electronic component mounting apparatus.

請求項７の電子部品実装装置は、ベアの半導体集積回路素子と、金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分の該バンプの形成された側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものを、各バンプと配線膜とを接続することにより複数段積層したものと、からなり、
上記複数段積層したもののバンプが露出する側のその各バンプを上記半導体集積回路素子の各電極に接続してなることを特徴とする。 The electronic component mounting apparatus according to claim 7 is a wiring part in which a bare semiconductor integrated circuit element and a substantially conical bump made of metal are formed on at least a part of a plurality of wiring films formed of a metal foil. A layer in which an interlayer insulating resin layer is formed in a state of being penetrated by each bump on the surface on which the bump is formed, and a plurality of layers are laminated by connecting each bump and a wiring film. ,
The bumps on the side where the bumps of the multi-layered laminate are exposed are connected to the electrodes of the semiconductor integrated circuit element.

請求項８の電子部品実装装置の製造方法は、電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハと、金属からなる配線膜の少なくとも一部に金属からなる略コニーデ状のバンプが形成された電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したもの又はそれを複数段積層したものとを、各バンプを上記半導体ウェハの各電極に接続することにより一体化し、その後、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離することにより請求項７の電子部品実装装置を得ることを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing an electronic component mounting apparatus, comprising: a semiconductor wafer in which a plurality of semiconductor integrated circuit elements for a plurality of electronic component mounting apparatuses are integrally formed; Electronic component mounting apparatus with a plurality of bumps formed on the surface of the bump forming side of a plurality of wiring portions corresponding to a plurality of wiring portions formed with an interlayer insulating resin layer being penetrated by each bump, or by stacking multiple layers thereof Are integrated by connecting each bump to each electrode of the semiconductor wafer, and then separated into individual electronic component mounting apparatuses by cutting the semiconductor wafer, the interlayer insulating resin layer, and the upper wiring portion. An electronic component mounting apparatus according to claim 7 is obtained.

請求項９の電子部品実装装置は、ベアの半導体集積回路素子と、金属箔からなる配線膜の一部に第１のバンプを形成した第１の配線部分と、この第１のバンプに電極が接続されて上記第１の配線部分の該第１のバンプ形成側に設けられた１又は複数の電子部品と、金属箔からなる配線膜の一部に上記第１のバンプよりも高い高さを有する第２のバンプを形成した第２の配線部分と、上記第１と第２の配線部分間に設けられた上記電子部品を封止する層間絶縁樹脂層と、
からなり、上記第２の配線部分を、それの上記第２のバンプを上記第１の配線部分の配線膜に接続することにより、上記第１の配線部分の上側にその間に上記電子部品が存在するように位置させ、該第２の配線部分の配線膜と上記ベアの半導体集積回路素子の電極とを接続してなる
ことを特徴とする。 The electronic component mounting apparatus according to claim 9 includes a bare semiconductor integrated circuit element, a first wiring portion in which a first bump is formed on a part of a wiring film made of a metal foil, and an electrode on the first bump. One or more electronic components that are connected and provided on the first bump forming side of the first wiring portion, and a part of the wiring film made of metal foil has a height higher than that of the first bump. A second wiring portion having a second bump formed thereon, an interlayer insulating resin layer for sealing the electronic component provided between the first and second wiring portions,
By connecting the second wiring portion of the second wiring portion to the wiring film of the first wiring portion, the electronic component exists above the first wiring portion. The wiring film of the second wiring portion and the electrode of the bare semiconductor integrated circuit element are connected to each other.

請求項１０の電子部品実装装置の製造方法は、金属箔からなる配線膜の一部に第１のバンプを形成した第１の配線部分の上記第１のバンプが形成された側に第１の層間絶縁樹脂層を設け、該第１のバンプと１又は複数の電子部品の電極とを接続し、金属箔の一部に上記第１のバンプよりも高い高さを有する第２のバンプを形成した第２の配線部分の第２のバンプ形成側の面を、第２の層間絶縁樹脂層を介して上記第１の配線部分の電子部品搭載側の面に臨ませ、上記第２のバンプを上記第２の層間絶縁樹脂層を貫通させて上記第１の配線部分の金属箔の一部に接続することにより上記第１と第２の配線部分同士を一体化し、上記第２の配線部分の第２の金属箔をパターニングすることにより配線膜を形成し、電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハの各電極と、上記第２の配線部分の上記配線膜を接続することにより、該半導体ウェハ及び上記第１及び第２の配線部分を一体化し、第１の配線部分の金属箔をパターニングすることにより配線膜を形成し、上記半導体ウェハ、上記第１、第２の配線部分及び上記第１、第２の層間絶縁樹脂層をカッティングすることにより個々の電子部品実装装置に分離することにより請求項９の電子部品実装装置を得ることを特徴とする。   According to a tenth aspect of the present invention, there is provided a method for manufacturing an electronic component mounting apparatus, comprising: a first wiring portion having a first bump formed on a part of a wiring film made of a metal foil; An interlayer insulating resin layer is provided, the first bump and one or a plurality of electronic component electrodes are connected, and a second bump having a height higher than the first bump is formed on a part of the metal foil. The surface of the second wiring portion on the second bump forming side faces the surface of the first wiring portion on the electronic component mounting side through the second interlayer insulating resin layer, and the second bump is The first and second wiring portions are integrated by passing through the second interlayer insulating resin layer and connecting to a part of the metal foil of the first wiring portion. A wiring film is formed by patterning the second metal foil, and a semiconductor for a plurality of electronic component mounting apparatuses is formed. By connecting each electrode of the semiconductor wafer integrally formed with the integrated circuit element and the wiring film of the second wiring portion, the semiconductor wafer and the first and second wiring portions are integrated, A wiring film is formed by patterning the metal foil of one wiring portion, and the semiconductor wafer, the first and second wiring portions, and the first and second interlayer insulating resin layers are cut to form individual wiring films. The electronic component mounting apparatus according to claim 9 is obtained by separating the electronic component mounting apparatus.

請求項１の電子部品実装装置によれば、両面に配線部分を有する層間絶縁樹脂層内に電子部品が、その電極と一方の主面の配線膜と一体のバンプとが電気的に接続された状態で埋込状に形成されているので、回路集積度を高めることができ、また、配線長も短くすることができ、寄生抵抗、寄生容量、寄生誘導を低減することができ、延いては高周波特性、高速性等、電気的特性、性能の向上を図りやすくすることができる。
また、電子部品の電極と配線を直接接続するのではなく、バンプを介して接続するので、層間絶縁樹脂層と電子部品との熱膨張係数に違いがあってもその違いによる熱応力が配線に生じるおそれがなく、延いては配線の断線のおそれをなくすことができる。 According to the electronic component mounting apparatus of the first aspect, the electronic component is electrically connected in the interlayer insulating resin layer having the wiring portions on both surfaces, and the electrode and the wiring film on one main surface are electrically connected to the bump. Since it is formed in an embedded state, the degree of circuit integration can be increased, the wiring length can be shortened, and parasitic resistance, parasitic capacitance, and parasitic induction can be reduced. It is possible to easily improve electrical characteristics and performance such as high frequency characteristics and high speed.
In addition, since the electrodes of the electronic component and the wiring are connected directly via bumps, even if there is a difference in the thermal expansion coefficient between the interlayer insulating resin layer and the electronic component, the thermal stress due to the difference is applied to the wiring. There is no possibility that it will occur, and as a result, the possibility of disconnection of the wiring can be eliminated.

更には、電子部品の電極と配線を直接接続する構造ではなく、バンプを介して接続するので、配線形成の際に、電子部品と層間絶縁樹脂層との境界が外部に露出していない。従って、配線形成の際に電子部品と層間絶縁樹脂層との境界を通じてエッチング液が該樹脂層内部に侵入して封止効果が低下するおそれがなく、信頼度、耐久性が損なわれるおそれがない。   Furthermore, since the electrodes of the electronic component and the wiring are not directly connected but connected via bumps, the boundary between the electronic component and the interlayer insulating resin layer is not exposed to the outside when the wiring is formed. Therefore, there is no possibility that the etching solution may enter the resin layer through the boundary between the electronic component and the interlayer insulating resin layer during wiring formation, and the sealing effect may not be reduced, and the reliability and durability may not be impaired. .

そして、層間絶縁樹脂層の一方の主面の配線膜とバンプを介して接続された電子部品と、他方の主面の配線膜とバンプを介して接続された電子部品を一つの層間絶縁樹脂層内に埋込状に封止したので、上記各電子部品を同一領域内にて上下に重ねて配置した場合には回路集積度を顕著に高める（倍増する）ことができるし、重ねるのではなく、ずらして配置した場合であっても、上側の配線と接続する電子部品と、下側の接続する電子部品を同一の層間絶縁樹脂層内に収納することができ、徒に電子部品間配線長を長くすることなく、層間絶縁樹脂層内の電子部品間の電気的接続ができ、高周波特性、高速性を高めることができる。   An electronic component connected to the wiring film on one main surface of the interlayer insulating resin layer via bumps and an electronic component connected to the wiring film on the other main surface via bumps into one interlayer insulating resin layer Since the electronic parts are sealed in an embedded manner, the circuit integration degree can be remarkably increased (doubled) when the electronic components are arranged one above the other in the same region. Even if they are arranged in a staggered manner, the electronic component connected to the upper wiring and the electronic component connected to the lower wiring can be accommodated in the same interlayer insulating resin layer. Without increasing the length, electrical connection between the electronic components in the interlayer insulating resin layer can be achieved, and the high frequency characteristics and high speed can be improved.

請求項２の電子部品実装装置によれば、層間絶縁樹脂層の両主面の配線間を接続する手段として、一方の主面の配線膜と接続されたバンプを用いるので、スルーホールによる層間接続をする場合のように、貫通孔の形成、無電解メッキ、電解メッキという面倒な方法を用いることなく、ＩＣを搭載した金属部材と、層間接続用のバンプを形成した金属部材を用意し、層間絶縁樹脂層を介して積層することにより簡単に電子部品実装装置をつくることができる。   According to the electronic component mounting apparatus of claim 2, since the bumps connected to the wiring film on one main surface are used as means for connecting the wirings on both main surfaces of the interlayer insulating resin layer, the interlayer connection by the through hole Without using the troublesome methods of forming through-holes, electroless plating, and electrolytic plating as in the case of performing the process, a metal member with an IC and a metal member with bumps for interlayer connection are prepared. By laminating through the insulating resin layer, an electronic component mounting apparatus can be easily manufactured.

請求項３の電子部品実装装置の製造方法によれば、金属箔にバンプを形成した金属部材の該各バンプに電子部品の各電極を接続した電子部品搭載金属部材を２つ用意し、そのうちの一方に、その搭載電子部品をその上面を含め囲繞するように層間絶縁樹脂層を塗布し、他方の上記電子部品搭載金属部材の他方の電子部品搭載面を上記一方の電子部品搭載金属部材の搭載面に臨ませて上記層間絶縁樹脂層によって上記二つの電子部品搭載金属部材を、封止して積層一体化し、上記二つの電子部品搭載金属部材の金属箔を順次又は同時にパターニングするので、請求項１の電子部品実装装置を得ることができる。   According to the method for manufacturing an electronic component mounting apparatus according to claim 3, two electronic component mounting metal members are prepared in which each electrode of the electronic component is connected to each bump of the metal member in which the bump is formed on the metal foil, of which On one side, an interlayer insulating resin layer is applied so as to surround the mounted electronic component including its upper surface, and the other electronic component mounting surface of the other electronic component mounting metal member is mounted on the one electronic component mounting metal member. The two electronic component mounting metal members are sealed and laminated and integrated with the interlayer insulating resin layer facing the surface, and the metal foils of the two electronic component mounting metal members are sequentially or simultaneously patterned. 1 electronic component mounting apparatus can be obtained.

請求項４の電子部品実装装置の製造方法によれば、金属箔にバンプを形成した第１の金属部材と、金属箔に上記バンプより高いバンプを形成した第２の金属部材を用意し、第１の金属部材には、そのバンプを介して電子部品を搭載し、第２の金属部材には、その金属箔のバンプ形成面に層間絶縁樹脂層を塗布し、該第２の金属部材のバンプ形成側に、上記第１の金属部材のバンプ形成側を臨ませて、上記電子部品が上記層間絶縁樹脂層内に入り且つ第２の金属部材のバンプが第１の金属部材の配線膜に接続されるように上記第１及び第２の金属部材を層間絶縁樹脂層を介して積層一体化するので、バンプを層間絶縁樹脂層両主面の配線膜間を接続する層間接続手段として用いる請求項２の電子部品実装装置を得ることができる。   According to the method for manufacturing an electronic component mounting apparatus of claim 4, a first metal member in which bumps are formed on a metal foil and a second metal member in which bumps higher than the bumps are formed on the metal foil are prepared. An electronic component is mounted on the first metal member via the bump, and an interlayer insulating resin layer is applied to the bump forming surface of the metal foil on the second metal member, and the bump of the second metal member is applied. The formation side faces the bump formation side of the first metal member, the electronic component enters the interlayer insulating resin layer, and the bump of the second metal member is connected to the wiring film of the first metal member As described above, the first and second metal members are laminated and integrated through an interlayer insulating resin layer, so that the bump is used as an interlayer connecting means for connecting the wiring films on both main surfaces of the interlayer insulating resin layer. 2 electronic component mounting apparatuses can be obtained.

請求項５の電子部品実装装置によれば、ベアのＩＣと、バンプが形成された配線部分と、該各バンプによって貫通された層間絶縁樹脂層からなり、上記各バンプが上記ベアのＩＣの電極に接続されて、上記配線部分が上記層間絶縁樹脂層を介して上記ベアのＩＣに一体化されてなり、配線部分の外側にベアのＩＣがあるので、ＩＣが複数個分一体に形成された半導体ウェハと配線部分を組み付け、その状態で電子部品実装装置の組立を進め、最終的段階でその半導体ウェハと配線部分等をカッティングするという方法で製造することができる。
従って、電子部品実装装置の製造効率を高めることが可能となり、延いては、電子部品実装装置の低価格化を図ることができる。 According to the electronic component mounting apparatus of claim 5, the device includes a bare IC, a wiring portion on which a bump is formed, and an interlayer insulating resin layer penetrated by each bump, and each bump is an electrode of the bare IC. The wiring portion is integrated with the bare IC via the interlayer insulating resin layer, and there is a bare IC outside the wiring portion, so that a plurality of ICs are integrally formed. The semiconductor wafer and the wiring portion can be assembled, the electronic component mounting apparatus can be assembled in that state, and the semiconductor wafer and the wiring portion can be cut at the final stage.
Therefore, it is possible to increase the manufacturing efficiency of the electronic component mounting apparatus, and it is possible to reduce the price of the electronic component mounting apparatus.

請求項６の電子部品実装装置の製造方法によれば、電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものと、電子部品実装装置複数個分のＩＣが一体に形成された半導体ウェハとを用意し、上記各バンプ端部を、上記半導体ウェハの対応する電極に接続することにより上記電子部品実装装置複数個分の配線部分を上記層間絶縁樹脂層を介して上記半導体ウェハと一体化し、その後、上記金属箔をパターニングすることにより配線膜を形成し、しかる後、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離することにより請求項５の電子部品実装装置を得るので、電子部品実装装置の製造効率を高め、電子部品実装装置の低価格化を図ることができる。   According to the method for manufacturing an electronic component mounting apparatus of claim 6, an interlayer insulating resin layer is formed in a state of being pierced by each bump on the bump forming side surface of a wiring portion for a plurality of electronic component mounting apparatuses. A plurality of electronic component mounting apparatuses are prepared, and a plurality of electronic component mounting apparatuses are prepared by connecting each bump end to a corresponding electrode of the semiconductor wafer. The wiring portion is integrated with the semiconductor wafer through the interlayer insulating resin layer, and then a wiring film is formed by patterning the metal foil, and then the semiconductor wafer, the interlayer insulating resin layer and the upper wiring are formed. Since the electronic component mounting apparatus according to claim 5 is obtained by separating the individual electronic component mounting apparatuses by cutting a part, the manufacturing efficiency of the electronic component mounting apparatus is increased, It is possible to reduce the cost of electronic component mounting apparatus.

請求項７の電子部品実装装置は、ベアのＩＣと、複数の配線膜の少なくとも一部の配線膜にバンプが形成された配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものを、複数段積層したものからなり、複数段積層したもののバンプが露出する側のその各バンプを上記ＩＣの各電極に接続してなり、配線部分の積層体の外側にベアのＩＣがあるので、ＩＣが複数個分一体に形成された半導体ウェハと配線部分を組み付け、その状態で電子部品実装装置の組立を進め、最終的段階でその半導体ウェハと配線部分等をカッティングする言う方法で製造することができる。
従って、電子部品実装装置の製造効率を高めることが可能となり、延いては、電子部品実装装置の低価格化を図ることができる。 The electronic component mounting apparatus according to claim 7 is a state in which the bump IC is penetrated by a bump forming side surface of a bare IC and a wiring portion where a bump is formed on at least a part of the plurality of wiring films. It is composed of a multi-layered structure in which an interlayer insulating resin layer is formed. Each of the bumps on the side where the bumps are exposed is connected to each electrode of the IC. Since there is a bare IC on the outside, the semiconductor wafer and the wiring part in which a plurality of ICs are integrally formed are assembled and the assembly of the electronic component mounting apparatus is proceeded in that state, and the semiconductor wafer and the wiring part etc. in the final stage It can be manufactured by the method of cutting.
Therefore, it is possible to increase the manufacturing efficiency of the electronic component mounting apparatus, and it is possible to reduce the price of the electronic component mounting apparatus.

請求項８の電子部品実装装置の製造方法は、半導体ウェハと、電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したもの又はそれを複数段積層したものとを、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離することにより請求項７の電子部品実装装置を得るので、電子部品実装装置の製造効率を高め、電子部品実装装置の低価格化を図ることができる。   According to the method for manufacturing an electronic component mounting apparatus of claim 8, an interlayer insulating resin layer is formed in a state of being pierced by each bump on the surface of the bump forming side of the wiring portion of the semiconductor wafer and a plurality of electronic component mounting apparatuses. The electronic component mounting apparatus according to claim 7, wherein the electronic component mounting apparatus is separated into individual electronic component mounting apparatuses by cutting the semiconductor wafer, the interlayer insulating resin layer, and the upper wiring portion. Therefore, the manufacturing efficiency of the electronic component mounting apparatus can be increased, and the price of the electronic component mounting apparatus can be reduced.

請求項９の電子部品実装装置によれば、ベアのＩＣと、配線膜の一部に第１のバンプを形成した第１の配線部分と、上記第１のバンプに電極が接続されて上記第１の配線部分の該第１のバンプ形成側に設けられた１又は複数の電子部品と、配線膜の一部に上記第１のバンプよりも高い高さを有する第２のバンプを形成した第２の配線部分と、上記ベアのＩＣ及び第１の配線部分の配線膜と、第２の配線部分の配線膜との間を層間絶縁する層間絶縁樹脂層と、からなり、上記第２の配線部分を、それの上記第２のバンプを上記第１の配線部分の配線膜に接続することにより、上記第１の配線部分の上側にその間に上記電子部品が存在するように位置させ、該第２の配線部分の配線膜と上記ベアのＩＣの電極とを接続してなり、第１、第２の配線部分の外側にベアのＩＣがあるので、ＩＣが複数個分一体に形成された半導体ウェハと配線部分を組み付け、その状態で電子部品実装装置の組立を進め、最終的段階でその半導体ウェハと配線部分等をカッティングする言う方法で製造することができる。
従って、電子部品実装装置の製造効率を高めることが可能となり、延いては、電子部品実装装置の低価格化を図ることができる。 According to the electronic component mounting apparatus of the ninth aspect, the bare IC, the first wiring portion in which the first bump is formed on a part of the wiring film, and the electrode is connected to the first bump so that the first One or a plurality of electronic components provided on the first bump forming side of one wiring portion and a second bump having a height higher than the first bump formed on a part of the wiring film 2 wiring portions, a wiring film of the bare IC and the first wiring portion, and an interlayer insulating resin layer that insulates between the wiring films of the second wiring portion, and the second wiring By connecting the second bump of the second bump to the wiring film of the first wiring portion, the portion is positioned on the upper side of the first wiring portion so that the electronic component exists therebetween, The first and second wirings are formed by connecting the wiring film of the second wiring part and the bare IC electrode. Since there is a bare IC on the outside, the semiconductor wafer on which a plurality of ICs are integrally formed and the wiring part are assembled, the assembly of the electronic component mounting apparatus is proceeded in that state, and the semiconductor wafer and the wiring are finalized. It can be manufactured by a method of cutting a part or the like.
Therefore, it is possible to increase the manufacturing efficiency of the electronic component mounting apparatus, and it is possible to reduce the price of the electronic component mounting apparatus.

請求項１０の電子部品実装装置の製造方法によれば、第１の配線部分の第１のバンプが形成された側に第１の層間絶縁樹脂層を設け、該第１のバンプと１又は複数の電子部品の電極とを接続し、上記第１のバンプよりも高い第２のバンプを形成した第２の配線部分の第２のバンプ形成側の面を、第２の層間絶縁樹脂層を介して上記第１の配線部分の電子部品搭載側の面に臨ませ、上記第２のバンプを上記第２の層間絶縁樹脂層を貫通させて上記第１の配線部分の金属箔の一部に接続することにより上記第１と第２の配線部分同士を一体化し、上記第２の配線部分の第２の金属箔をパターニングすることにより配線膜を形成し、電子部品実装装置複数個分のＩＣが一体に形成された半導体ウェハの各電極と、上記第２の配線部分の上記配線膜を接続することにより、該半導体ウェハ及び上記第１及び第２の配線部分を一体化し、第１の配線部分の金属箔をパターニングすることにより配線膜を形成し、上記半導体ウェハ、上記第１、第２の配線部分及び上記第１、第２の層間絶縁樹脂層をカッティングすることにより個々の電子部品実装装置に分離することにより請求項９の電子部品実装装置を得るので、電子部品実装装置の製造効率を高め、電子部品実装装置の低価格化を図ることができる。   According to the method for manufacturing an electronic component mounting apparatus of claim 10, the first interlayer insulating resin layer is provided on the side of the first wiring portion where the first bump is formed, and one or a plurality of the first bumps are provided. The surface on the second bump forming side of the second wiring portion that is connected to the electrodes of the electronic component and has formed the second bump higher than the first bump is interposed through the second interlayer insulating resin layer. Then, the first bump portion faces the surface on which the electronic component is mounted, and the second bump penetrates the second interlayer insulating resin layer and is connected to a part of the metal foil of the first wire portion. Then, the first and second wiring parts are integrated with each other, and a wiring film is formed by patterning the second metal foil of the second wiring part. Each electrode of the integrally formed semiconductor wafer and the wiring film of the second wiring portion By continuing, the semiconductor wafer and the first and second wiring portions are integrated, and a metal film of the first wiring portion is patterned to form a wiring film, and the semiconductor wafer, the first and second wiring portions are formed. 10. The electronic component mounting apparatus according to claim 9 is obtained by separating the two wiring portions and the first and second interlayer insulating resin layers into individual electronic component mounting apparatuses by cutting. The efficiency can be increased and the price of the electronic component mounting apparatus can be reduced.

本発明において重要な要素となる、層間接続用のバンプを有する金属部材は、配線膜となる薄い銅層と、エッチングバリアとなる更に薄いニッケル層と、バンプとなる比較的厚い銅層を積層した三層構造の金属板が最適である。
そして、バンプの形成は上記金属部材の薄い銅層を選択的にエッチングすることにより行うと良い。 The metal member having bumps for interlayer connection, which is an important element in the present invention, is formed by laminating a thin copper layer serving as a wiring film, a thinner nickel layer serving as an etching barrier, and a relatively thick copper layer serving as a bump. A three-layer metal plate is most suitable.
The bumps are preferably formed by selectively etching the thin copper layer of the metal member.

以下、本発明を図示実施例に従って詳細に説明する。
図１（Ａ）〜（Ｇ）は本発明に係る電子部品実装装置の第１の実施例（：実施例１）の製造方法を工程順に示す断面図である。以下にこの製造方法について説明する。
（Ａ）図１（Ａ）に示すように、配線膜となる銅箔２の一方の主面に略コニーデ状の層間接続用のバンプ４、４、・・・を形成した金属部材５を用意する。 Hereinafter, the present invention will be described in detail according to illustrated embodiments.
1A to 1G are cross-sectional views showing a manufacturing method of a first embodiment (Example 1) of an electronic component mounting apparatus according to the present invention in the order of steps. This manufacturing method will be described below.
(A) As shown in FIG. 1 (A), a metal member 5 is prepared in which bumps 4, 4,... For substantially interlayer connection are formed on one main surface of a copper foil 2 to be a wiring film. To do.

該部材５は例えば配線膜となる薄い銅層と、エッチングバリアとなる更に薄い例えばニッケル層と、バンプとなる比較的厚い銅層を積層した三層構造の金属板を用意し、そのバンプとなる比較的厚い銅層を選択的にエッチングすることによりバンプを形成し、その後、該バンプをマスクとしてニッケル膜をエッチングすることにより形成することができる。尚、このニッケル膜はバンプを形成するエッチングの際にエッチングバリアとして配線膜となる銅膜のエッチングを阻んだものであるが、もうその役割を終え、しかも今はバンプ間を相互にショートする存在なのでここで除去するのである。
また、該部材５は、単層構造の銅板を一方の主面側から選択的にハーフエッチング（銅板の板厚より適宜薄い深さのエッチング）をすること等によっても形成することができ、その形成方法には種々のものが考えられ得る。 The member 5 is, for example, a three-layer metal plate in which a thin copper layer to be a wiring film, a further thin nickel layer to be an etching barrier, for example, and a relatively thick copper layer to be a bump are laminated. A bump can be formed by selectively etching a relatively thick copper layer, and then the nickel film can be etched using the bump as a mask. This nickel film prevents the etching of the copper film that becomes the wiring film as an etching barrier during the etching to form bumps, but it has already finished its role and now it is a short circuit between the bumps. So it is removed here.
The member 5 can also be formed by selectively half-etching a copper plate having a single layer structure from one main surface side (etching with a depth appropriately thinner than the thickness of the copper plate). Various formation methods can be considered.

（Ｂ）次に、図１（Ｂ）に示すように、ベアのＩＣ（半導体集積回路素子）６を、その各電極８、８、・・・がそれに対応するバンプ４、４、・・・の頂部上に位置するように位置決めし、その各電極８、８、・・・とバンプ４、４、・・・とを接合する。そのベアのＩＣ６の金属部材５への位置決めは例えばチップマウンタにより極めて精確に行うことができる。
（Ｃ）次に、図１（Ｃ）に示すように、上記金属部材５のバンプ４、４、・・・側の面に層間絶縁樹脂層１０を上記ベアＩＣ６を完全に封止するように圧着形成する。 (B) Next, as shown in FIG. 1 (B), a bare IC (semiconductor integrated circuit element) 6 has bumps 4, 4,... Corresponding to the electrodes 8, 8,. Are positioned so as to be located on the top of each of the electrodes, and the electrodes 8, 8,... And the bumps 4, 4,. The positioning of the bare IC 6 on the metal member 5 can be performed very accurately by, for example, a chip mounter.
(C) Next, as shown in FIG. 1C, an interlayer insulating resin layer 10 is completely sealed on the bump 4, 4,... Side of the metal member 5 so that the bare IC 6 is completely sealed. Crimp formation.

（Ｄ）次に、図１（Ｄ）に示すように、上記層間絶縁樹脂層１０の主面上に配線膜となる銅箔１２を接着する。
（Ｅ）次に、図１（Ｅ）に示すように、上記銅箔２、１２を含め上記層間絶縁樹脂層１０を貫通する貫通孔１４を形成する。該貫通孔１４は層間接続用のスルーホールとなるものである。
（Ｆ）次に、図１（Ｆ）に示すように、上記貫通孔１４内面に金属からなる層間接続用導電層１６を形成する。この形成は、例えば無電解メッキ処理と電解メッキ処理を施すことにより容易に為すことができる。 (D) Next, as shown in FIG. 1 (D), a copper foil 12 to be a wiring film is bonded onto the main surface of the interlayer insulating resin layer 10.
(E) Next, as shown in FIG. 1 (E), a through-hole 14 that penetrates the interlayer insulating resin layer 10 including the copper foils 2 and 12 is formed. The through hole 14 becomes a through hole for interlayer connection.
(F) Next, as shown in FIG. 1 (F), an interlayer connection conductive layer 16 made of metal is formed on the inner surface of the through hole 14. This formation can be easily performed by performing, for example, an electroless plating process and an electrolytic plating process.

（Ｇ）次に、銅箔２、１２に対する選択的エッチング処理を同時又は所定の順序で施すことにより配線膜２ａ、２ａ、・・・、１２ａ、１２ａ、・・・を形成し、その後、配線膜２ａ、２ａ、・・・、１２ａ、１２ａ、・・・に電子部品１８、１８、・・・の電極を接続することにより電子部品１８、１８、・・・を搭載する。図１（Ｇ）は電子部品の搭載後の状態を示す。この図１（Ｇ）における、２０が本発明に係る電子部品実装装置の第１の実施例（：実施例１）を示す。尚、本実施例では、両面に電子部品１８が搭載されていたが、片面のみに電子部品１８を搭載するようにしても良い。 (G) Next, the selective etching process for the copper foils 2 and 12 is performed simultaneously or in a predetermined order to form the wiring films 2a, 2a,..., 12a, 12a,. Are mounted on the membranes 2a, 2a,..., 12a, 12a,. FIG. 1G shows a state after the electronic component is mounted. In FIG. 1G, reference numeral 20 denotes a first embodiment (Example 1) of the electronic component mounting apparatus according to the present invention. In this embodiment, the electronic components 18 are mounted on both sides, but the electronic components 18 may be mounted only on one side.

このような電子部品実装装置２０は、基板本体を構成する層間絶縁樹脂層１０内にＩＣ６を封止することができるので、回路の集積密度を顕著に高めることができる。従って、従来のプリント配線基板の一方乃至双方の両主面に部材を取り付けるタイプのものに比較して顕著に回路の集積密度を高めることができる。
そして、集積密度を高めることができることから、電子部品間の間隔をより短くすることが可能となり、延いては、電子部品間を互いに接続する配線膜の長さ（配線長）を短くすることが可能となり、延いては、高周波数特性、高速性を高め、性能の向上を図ることができる。 In such an electronic component mounting apparatus 20, the IC 6 can be sealed in the interlayer insulating resin layer 10 constituting the substrate body, so that the circuit integration density can be remarkably increased. Therefore, the circuit integration density can be remarkably increased as compared with the conventional type in which members are attached to one or both main surfaces of a printed wiring board.
Since the integration density can be increased, the distance between the electronic components can be further shortened, and the length of the wiring film (wiring length) for connecting the electronic components to each other can be shortened. As a result, high frequency characteristics and high speed can be improved and performance can be improved.

そして、ベアのＩＣ６を例えばベアマウンタ等により精確に位置決めしたら直ぐにその電極８と金属部材５のバンプ４、４、・・・とを接続して位置関係を強固に固定し、その後、その位置関係を強固に固定した状態で層間絶縁樹脂層１０を形成してそのＩＣ６を封止するので、図１４に示す従来例におけるような、ＩＣｂ、ｂ、・・・が、サポート板ａ上に位置決めされた後、樹脂ｃが形成されそれにより封止されるまでの間に位置ずれを生じるというおそれは、ない。   Then, as soon as the bear IC 6 is accurately positioned by, for example, a bear mounter, the electrode 8 and the bumps 4, 4,... Of the metal member 5 are connected to firmly fix the positional relationship. Since the interlayer insulating resin layer 10 is formed in a firmly fixed state and the IC 6 is sealed, ICb, b,... As in the conventional example shown in FIG. 14 are positioned on the support plate a. There is no fear that a positional shift will occur between the time when the resin c is formed and sealed after that.

また、図１４に示す従来例によれば、樹脂ｃとＩＣｂとの熱膨張係数の違いにより、配線膜ｅ、ｅ、・・・の樹脂ｃとＩＣｂとの境界部分ｆ、ｆ、・・・に熱応力による断線等が生じ易いという問題があるが、本実施例２０によれば、ＩＣ６が樹脂１０中に深く埋もれており、配線膜１２ａ、１２ａ、・・・に樹脂１０とＩＣ６との熱膨張係数の違いによる熱応力が加わるおそれがなく、そのような問題は生じ得ない。
また、図１４に示す従来例によれば、銅箔ｄを選択的にエッチングすることにより配線膜ｅ、ｅ、・・・を形成する際に、樹脂ｃとＩＣｂとの境界に沿ってエッチング液が浸透してしまい、封止効果が低減するおそれがあるが、本実施例２０によれば、樹脂１０とＩＣ６との境界が樹脂１０外部に露出していないので、銅箔２、１２を選択的にエッチングするときにエッチング液が樹脂１０とＩＣ６との境界に沿って樹脂１０内に深く浸透するおそれもない。 Further, according to the conventional example shown in FIG. 14, the boundary portions f, f,... Between the resin c and the ICb of the wiring films e, e,. However, according to the 20th embodiment, the IC 6 is deeply buried in the resin 10, and the wiring films 12a, 12a,. There is no fear of applying thermal stress due to the difference in thermal expansion coefficient, and such a problem cannot occur.
Further, according to the conventional example shown in FIG. 14, when the wiring films e, e,... Are formed by selectively etching the copper foil d, an etching solution is formed along the boundary between the resin c and the ICb. However, according to the present example 20, the boundary between the resin 10 and the IC 6 is not exposed to the outside of the resin 10, so the copper foils 2 and 12 are selected. Therefore, there is no possibility that the etching solution penetrates deeply into the resin 10 along the boundary between the resin 10 and the IC 6 when etching is performed.

（第１の変形例）
図２（Ａ）、（Ｂ）は図１に示した製造方法の第１の変形例の要部を工程順に示す断面図である。
（Ａ）銅箔２の一方の主面にバンプ４、４、・・・を形成した金属部材５のバンプ形成側の面に、図２（Ａ）に示すように、バンプ４の高さよりも薄いバンプ保護絶縁樹脂層１０ａを形成する。
（Ｂ）その後、図２（Ｂ）に示すように、各バンプ４、４、・・・の露出した頂部にベアのＩＣ６の各電極８、８、・・・を接続する。 (First modification)
2A and 2B are cross-sectional views showing the main part of the first modification of the manufacturing method shown in FIG. 1 in the order of steps.
(A) As shown in FIG. 2 (A), the height of the bumps 4 on the surface on the bump forming side of the metal member 5 having the bumps 4, 4,. A thin bump protection insulating resin layer 10a is formed.
(B) Then, as shown in FIG. 2B, the electrodes 8, 8,... Of the bare IC 6 are connected to the exposed top portions of the bumps 4, 4,.

その後は、図１に示した製造方法と同じ工程を行う。
この第１の変形例によれば、微細なるが故に折れたり曲がったりし易いバンプ４、４、・・・がＩＣ６搭載前に或いは搭載の際に折れたり、曲がったりすることを層間絶縁樹脂層１０ａにより防止することができ、延いては、不良率の低減、信頼性の向上を図ることができる。 After that, the same process as the manufacturing method shown in FIG. 1 is performed.
According to the first modified example, the bumps 4, 4,... That are easy to bend or bend because of being fine are bent or bent before or after the IC 6 is mounted. This can be prevented by 10a, and consequently the defect rate can be reduced and the reliability can be improved.

（第２の変形例）
図３（Ａ）〜（Ｃ）は図１に示した製造方法の第２の変形例の要部を工程順に示す断面図である。
（Ａ）金属部材５にＩＣ６を搭載した後、図３（Ａ）に示すように、層間絶縁樹脂層として、ＩＣ６を逃げる逃げ孔１０ｈを有するフィルム状の樹脂１０を用意し、その逃げ孔１０ｈがＩＣ６と位置整合するようにその樹脂１０を金属部材５上に臨ませる。尚、金属部材５はバンプ４の高さより薄いバンプ保護絶縁樹脂層１０ａが形成されていてもいなくても良い。 (Second modification)
3A to 3C are cross-sectional views showing the main part of the second modification of the manufacturing method shown in FIG. 1 in the order of steps.
(A) After mounting the IC 6 on the metal member 5, as shown in FIG. 3A, as the interlayer insulating resin layer, a film-like resin 10 having an escape hole 10h for escaping the IC 6 is prepared, and the escape hole 10h The resin 10 is made to face the metal member 5 so as to be aligned with the IC 6. The metal member 5 may or may not have the bump protection insulating resin layer 10 a thinner than the bump 4.

（Ｂ）次に、図３（Ｂ）に示すように、層間絶縁樹脂層１０を金属部材５のバンプ形成面上に位置させる。
（Ｃ）その後、圧着処理すると、圧着処理により生じた層間絶縁樹脂層１０の流動性により、図３（Ｃ）に示すように、ＩＣ６を覆った状態になり、硬化すると封止した状態になる。 (B) Next, as shown in FIG. 3B, the interlayer insulating resin layer 10 is positioned on the bump forming surface of the metal member 5.
(C) After that, when the crimping process is performed, the fluidity of the interlayer insulating resin layer 10 generated by the crimping process results in a state of covering the IC 6 as shown in FIG. .

その後は、図１に示した製造方法と同じ工程を経て電子部品実装装置２０を得る。
このような変形例によれば、層間絶縁樹脂層１０を形成するために、フィルム状の樹脂をあてがうときに、その樹脂によりベアのＩＣ６が損傷を受けるおそれをなくすことができる。 Thereafter, the electronic component mounting apparatus 20 is obtained through the same steps as the manufacturing method shown in FIG.
According to such a modification, when the film-like resin is applied to form the interlayer insulating resin layer 10, there is no possibility that the bare IC 6 is damaged by the resin.

図４は本発明に係る電子部品実装装置の第２の実施例（：実施例２）２０ａを示す断面図である。本実施例２０ａは、同じ領域内に２個のベアＩＣ６、６が背中合わせの向きで上下に離間して重なるように層間絶縁樹脂層１０内に封止されるように集積度を高めた点で図１（Ｇ）に示す電子部品実装装置２０と異なっている。これにより電子部品実装装置の単位専有面積当たりの回路の集積度を略倍増することができる。   FIG. 4 is a sectional view showing a second embodiment (embodiment 2) 20a of the electronic component mounting apparatus according to the present invention. Example 20a is that the degree of integration is enhanced so that the two bare ICs 6 and 6 are sealed in the interlayer insulating resin layer 10 so as to be separated from each other in the same region in the back-to-back direction. This is different from the electronic component mounting apparatus 20 shown in FIG. As a result, the degree of circuit integration per unit-occupied area of the electronic component mounting apparatus can be substantially doubled.

図５（Ａ）〜（Ｃ）は図４に示した電子部品実装装置２０ａの製造方法の要部を工程順に示す断面図である。
（Ａ）バンプ４、４、・・・にて電極８、８、・・・を介してベアのＩＣ６、６、・・・が搭載された金属部材５を一対５ａ、５ｂを用意し、その一方５ａのバンプ形成側の面に層間絶縁樹脂層１０を圧着処理により該ＩＣ６、６、・・・を封止するように形成し、他方の金属部材５ｂをＩＣ６、６、・・・の搭載側を一方の金属部材５ａに向けて、所定の位置関係に位置合わせして臨ませる。図５（Ａ）はその状態を示す。 5A to 5C are cross-sectional views showing the main part of the manufacturing method of the electronic component mounting apparatus 20a shown in FIG. 4 in the order of steps.
(A) A pair of metal members 5 on which bare ICs 6, 6,... Are mounted via electrodes 8, 8,. On the other hand, the interlayer insulating resin layer 10 is formed on the surface of the bump forming side of 5a by pressure bonding so as to seal the ICs 6, 6,... The side is faced to one metal member 5a so as to be aligned in a predetermined positional relationship. FIG. 5A shows this state.

（Ｂ）次に、層間絶縁樹脂層１０に対して加熱処理を施して軟化させながら上記他方の金属部材５ｂを金属部材５ａに近接させ、その金属部材５ｂのＩＣ６、６、・・・を該層間絶縁樹脂層１０内に埋もれ、該樹脂層１０によって封止された状態にする。図５（Ｂ）はその封止された状態を示す。 (B) Next, while heat-treating the interlayer insulating resin layer 10 to soften it, the other metal member 5b is brought close to the metal member 5a, and the ICs 6, 6,. The resin is buried in the interlayer insulating resin layer 10 and sealed with the resin layer 10. FIG. 5B shows the sealed state.

（Ｃ）次に、図５（Ｃ）に示すように、樹脂層１０に貫通孔１４を形成し、更に、導電膜１６を形成する。その後は、例えば図１に示す製造方法と同じ工程を行う。すると、図４に示す電子部品実装装置２０ａが出来上がる。 (C) Next, as shown in FIG. 5C, a through hole 14 is formed in the resin layer 10, and a conductive film 16 is further formed. Thereafter, for example, the same steps as the manufacturing method shown in FIG. 1 are performed. Then, the electronic component mounting apparatus 20a shown in FIG. 4 is completed.

（第１の変形例）
図６は図４に示した電子部品実装装置の第１の変形例２０ｂを示す断面図である。本変形例２０ａは、図４に示した電子部品実装装置２０ｂとは、一つの領域内に存するＩＣ６は一個であり、上面（反電極側の面）が上向きに搭載されたＩＣ６ａと下面（電極側の面）が上向きに搭載されたＩＣ６ｂを有するように層間絶縁樹脂層１０に封止してなる点で異なる。このようにすれば、電子部品実装装置の単位専有面積当たりの回路の集積度を高めることは必ずしもできないが、ＩＣ６ａの電極が下側の配線膜と多く接続され、ＩＣ６ｂの電極が上側の配線膜と多く接続される場合には比較的配線長を短くしつつ多くのＩＣ６を搭載することができ、配線長が全体的に長くならないようにすることが容易に為し得る。 (First modification)
6 is a cross-sectional view showing a first modification 20b of the electronic component mounting apparatus shown in FIG. This modification 20a is different from the electronic component mounting apparatus 20b shown in FIG. 4 in that there is one IC 6 in one area, and the upper surface (surface on the opposite electrode side) is mounted upward and the lower surface (electrode) This is different in that it is sealed in the interlayer insulating resin layer 10 so that the IC 6b mounted on the side surface) faces upward. In this way, it is not always possible to increase the degree of circuit integration per unit-occupied area of the electronic component mounting apparatus, but many of the electrodes of the IC 6a are connected to the lower wiring film, and the electrodes of the IC 6b are connected to the upper wiring film. When a large number of ICs are connected, a large number of ICs 6 can be mounted while the wiring length is relatively short, and it is easy to prevent the wiring length from being increased as a whole.

図７（Ａ）〜（Ｃ）は図６に示した電子部品実装装置２０ｂの製造方法の要部を工程順に示す断面図である。
（Ａ）バンプ４、４、・・・にて電極８、８、・・・を介してベアのＩＣ６、６、・・・が搭載された金属部材５を一対５ａ、５ｂを用意し、その一方５ａのバンプ形成側の面に層間絶縁樹脂層１０を圧着処理により該ＩＣ６、６、・・・を封止するように形成し、他方の金属部材５ｂをＩＣ６、６、・・・の搭載側を一方の金属部材５ａに向けて、所定の位置関係に位置合わせして臨ませる。図７（Ａ）はその状態を示す。 7A to 7C are cross-sectional views showing the main part of the manufacturing method of the electronic component mounting apparatus 20b shown in FIG. 6 in the order of steps.
(A) A pair of metal members 5 on which bare ICs 6, 6,... Are mounted via electrodes 8, 8,. On the other hand, the interlayer insulating resin layer 10 is formed on the surface of the bump forming side of 5a by pressure bonding so that the ICs 6, 6,... Are sealed, and the other metal member 5b is mounted on the ICs 6, 6,. The side is faced to one metal member 5a so as to be aligned in a predetermined positional relationship. FIG. 7A shows this state.

（Ｂ）次に、層間絶縁樹脂層１０に対して加熱処理を施して軟化させながら上記他方の金属部材５ｂを金属部材５ａに近接させ、その金属部材５ｂのＩＣ６、６、・・・を該層間絶縁樹脂層１０内に埋もれ、該樹脂層１０によって封止された状態にする。図７（Ｂ）はその封止された状態を示す。 (B) Next, while heat-treating the interlayer insulating resin layer 10 to soften it, the other metal member 5b is brought close to the metal member 5a, and the ICs 6, 6,. The resin is buried in the interlayer insulating resin layer 10 and sealed with the resin layer 10. FIG. 7B shows the sealed state.

（Ｃ）次に、図７（Ｃ）に示すように、樹脂層１０に貫通孔１４を形成し、更に、導電膜１６を形成する。その後は、例えば図１に示す製造方法と同じ工程を行う。すると、図６に示す電子部品実装装置２０ｂが出来上がる。 (C) Next, as shown in FIG. 7C, a through hole 14 is formed in the resin layer 10, and a conductive film 16 is further formed. Thereafter, for example, the same steps as the manufacturing method shown in FIG. 1 are performed. Then, the electronic component mounting apparatus 20b shown in FIG. 6 is completed.

図８は本発明に係る電子部品実装装置の第３の実施例（：実施例３）を示す断面図である。本実施例２０ｃは層間絶縁樹脂層１０の両面の配線膜間をスルーホールによってではなく、バンプ２４、２４・・・によって電気的に接続するようにしたものであり、貫通孔を形成し、無電解メッキ、電解メッキを形成するという面倒な工程を経ることなく層間接続するようにすることができるという利点を有する。１８は一方の主面に搭載された電子部品である。本実施例２０ｃにおいては一方の主面のみに形成されているが、双方の主面に搭載するようにしても良いことは言うまでもない。   FIG. 8 is a cross-sectional view showing a third embodiment (embodiment 3) of the electronic component mounting apparatus according to the present invention. In this example 20c, the wiring films on both surfaces of the interlayer insulating resin layer 10 are electrically connected not by the through holes but by the bumps 24, 24... There is an advantage that interlayer connection can be made without going through a troublesome process of forming electrolytic plating and electrolytic plating. Reference numeral 18 denotes an electronic component mounted on one main surface. In this embodiment 20c, it is formed only on one main surface, but it goes without saying that it may be mounted on both main surfaces.

図９（Ａ）、（Ｂ）は図８に示す電子部品実装装置２０ｃの製造方法の要部を工程順に示す断面図である。
（Ａ）図９（Ａ）に示すように、バンプ４、４、・・・にて電極８、８、・・・を介してベアのＩＣ６、６、・・・が搭載された金属部材５ａと、層間絶縁樹脂層１０の厚さと同じ高さの層間接続用バンプ２４、２４、・・・を銅箔２の一方の主面に形成し、そのバンプ２４形成面に層間絶縁樹脂層１０を形成した金属部材５ｃを用意し、該金属部材５ｃを、そのバンプ２４形成面が金属部材５ａのバンプ４形成面に所定の位置関係になるように位置決めして臨ませる。図９（Ａ）はその位置決めして臨ませた状態を示す。 9A and 9B are cross-sectional views showing the main part of the manufacturing method of the electronic component mounting apparatus 20c shown in FIG. 8 in the order of steps.
(A) As shown in FIG. 9A, a metal member 5a on which bare ICs 6, 6,... Are mounted via bumps 4, 4,. Are formed on one main surface of the copper foil 2 and the interlayer insulating resin layer 10 is formed on the bump 24 forming surface. The formed metal member 5c is prepared, and the metal member 5c is positioned so as to face the bump 4 formation surface of the metal member 5a with a predetermined positional relationship. FIG. 9 (A) shows a state of being positioned and faced.

（Ｂ）次に、図９（Ｂ）に示すように、層間絶縁樹脂層１０に対する加熱処理を施して軟化させながら金属部材５ａを金属部材５ｃに近接させ、バンプ２４、２４、・・・が金属部材５ａの銅箔２に接続され、その層間絶縁樹脂層１０によってベアのＩＣ６、６、・・が封止され、金属部材５ａ及び５ｃの銅箔２・２間が絶縁された状態にする。
その後は、上下両面の銅箔２、２をパターニングして配線膜を形成し、更に、必要な電子部品１８の搭載を行う。すると、図８に示す電子部品実装装置２０ｃが出来上がる。 (B) Next, as shown in FIG. 9B, the metal member 5a is brought close to the metal member 5c while being softened by applying heat treatment to the interlayer insulating resin layer 10, and the bumps 24, 24,. .. Are connected to the copper foil 2 of the metal member 5a , and the bare ICs 6, 6,... Are sealed by the interlayer insulating resin layer 10 so that the copper foils 2 and 2 of the metal members 5a and 5c are insulated. .
After that, the upper and lower copper foils 2 and 2 are patterned to form a wiring film, and necessary electronic components 18 are mounted. Then, the electronic component mounting apparatus 20c shown in FIG. 8 is completed.

（他の各種変形例）
尚、上記本発明に係る電子部品実装装置の第１乃至第３各実施例２０、２０ａ〜２０ｃにおいて、バンプ４、４、・・・とベアのＩＣ６、６、・・・の電極８、８、・・・との接続が不可欠であるが、その接続において、そのバンプ４、４、・・・と電極８、８、・・・との間にＡＣＦ等の異方性導電膜を介在させるようにしても良い。
また、バンプ４、４、・・・と電極８、８、・・・との接続は、ベアのＩＣ６をチップマウンタにより位置決めし、その状態で適宜加圧することにより行うことができるが、その際に、超音波振動を加えるようにすると、接続性をより良好にすることができる。 (Other variations)
In the first to third embodiments 20, 20a to 20c of the electronic component mounting apparatus according to the present invention, bumps 4, 4,... And bare ICs 6, 6,. Are indispensable, but an anisotropic conductive film such as ACF is interposed between the bumps 4, 4,... And the electrodes 8, 8,. You may do it.
In addition, the connection between the bumps 4, 4,... And the electrodes 8, 8,... Can be performed by positioning the bare IC 6 with a chip mounter and appropriately pressing in that state. Further, when ultrasonic vibration is applied, the connectivity can be improved.

更に、接続工程の直前に例えばチャンバー内にてバンプ４、４、・・・及び電極８、８、・・・の表面をクリーンにする処理をし、その後、上記接続をするようにすると、低い加圧力で良好な接続ができる。
更にまた、上記各種実施例において、層間絶縁樹脂層１０の一方の主面或いは双方の主面上に、厚膜或いは薄膜による抵抗素子、容量素子或いは誘導素子を形成するようにしても良いことは言うまでもない。抵抗素子は、例えば銅箔として若干比抵抗の大きなものを用い、パターニングにより細くて長い（例えばジグザグ状にパターニングすることにより配線膜を長くする。）配線膜部分を形成することにより得ることができる。 Further, the surface of the bumps 4, 4,... And the electrodes 8, 8,. A good connection can be made with pressure.
Furthermore, in the various embodiments described above, a thick film or thin film resistance element, capacitive element or induction element may be formed on one main surface or both main surfaces of the interlayer insulating resin layer 10. Needless to say. The resistance element can be obtained, for example, by using a copper foil having a relatively large specific resistance and forming a wiring film portion that is thin and long by patterning (for example, the wiring film is lengthened by patterning in a zigzag pattern). .

また、容量素子は、薄膜或いは厚膜により例えば銅箔による下側電極を形成し、その下側電極を比較的誘電率の高い絶縁層により覆い、該絶縁層上に該下側電極とと対向する上側電極を形成することにより得ることができる。また、誘導素子は、厚膜又は薄膜により例えば渦巻き状のパターンを形成し、更に、絶縁膜として例えばセラミック粒子を含有した比較的透磁率の高い膜をその渦巻き状の膜間に介在するように形成することによっても得ることができる。   Further, the capacitive element is formed by forming a lower electrode made of, for example, copper foil with a thin film or a thick film, covering the lower electrode with an insulating layer having a relatively high dielectric constant, and facing the lower electrode on the insulating layer. Can be obtained by forming the upper electrode. In addition, the inductive element forms, for example, a spiral pattern by a thick film or a thin film, and further, a relatively high permeability film containing, for example, ceramic particles as an insulating film is interposed between the spiral films. It can also be obtained by forming.

図１０（Ａ）〜（Ｄ）は本発明に係る第４の実施例（：実施例４）である、電子部品実装装置の製造方法を工程順に示す断面図である。本実施例は、後述する第５、第６の実施例と同様に、半導体ウェハの状態で配線部分等との組付けを進めるという点で、上述した第１乃至第３の実施例とは異なり、製造効率を高めることができるという利点を有し、また、第１乃至第３の実施例が図１４に示した従来例と比較して優れた各利点も有する。 FIGS. 10A to 10D are cross-sectional views illustrating a method of manufacturing an electronic component mounting apparatus according to the fourth embodiment (Example 4) of the present invention in the order of steps. This embodiment, the fifth will be described later, similarly to the sixth embodiment, in that proceeding Mel the assembly of the wiring portion such as a state of the semiconductor wafer, and the first to third embodiments described above Unlike the conventional example shown in FIG. 14, the first to third embodiments also have advantages that the manufacturing efficiency can be increased.

（Ａ）図１０（Ａ）に示すように、銅箔５２の一方の主表面に銅からなるバンプ５４を形成した配線部分５６の該バンプ５４側の面に層間絶縁樹脂層５８を該バンプ５４、５４、・・・に貫通されるようにして形成したものと、半導体ウェハ６０を用意する。配線部分５６は、複数の電子部品実装装置分の配線部分を一体に形成したものであり、また、半導体ウェハ６０も複数の電子部品実装装置分のＩＣを一体に形成したものである。 (A) As shown in FIG. 10A, an interlayer insulating resin layer 58 is provided on the bump 54 side surface of a wiring portion 56 in which a bump 54 made of copper is formed on one main surface of a copper foil 52. , 54,..., And a semiconductor wafer 60 are prepared. The wiring portion 56 is formed by integrally forming wiring portions for a plurality of electronic component mounting apparatuses, and the semiconductor wafer 60 is also formed by integrally forming ICs for a plurality of electronic component mounting apparatuses.

（Ｂ）次に、図１０（Ｂ）に示すように、上記配線部分５６の各バンプ５４、５４、・・・を、上記半導体ウェハ６０の各電極に接続する。
（Ｃ）次に、図１０（Ｃ）に示すように、上記銅箔５２を選択的にエッチングすることにより配線膜５２ａ、５２、・・・を形成する。 (B) Next, as shown in FIG. 10B, the bumps 54, 54,... Of the wiring portion 56 are connected to the electrodes of the semiconductor wafer 60.
(C) Next, as shown in FIG. 10C, the copper foil 52 is selectively etched to form wiring films 52a, 52,.

（Ｄ）次に、上記半導体ウェハ６０と、層間絶縁樹脂層５８及び配線部分５６をカットすることにより、個々の電子部品実装装置６２、６２、・・・に分離する。
この電子部品実装装置６２が本発明電子部品実装装置の実施例の一つである。
このような実施例によれば、電子部品であるＩＣ６０の電極と配線を直接接続するのではなく、バンプ５８を介して接続するので、層間絶縁樹脂層５８とＩＣ６０との熱膨張係数に違いがあってもその違いによる熱応力が配線に生じるおそれがなく、延いては配線の断線のおそれをなくすことができる。 (D) Next, the semiconductor wafer 60, the interlayer insulating resin layer 58, and the wiring portion 56 are cut to be separated into individual electronic component mounting apparatuses 62, 62,.
This electronic component mounting apparatus 62 is one embodiment of the electronic component mounting apparatus of the present invention.
According to such an embodiment, the electrodes and wiring of the IC 60 which is an electronic component are not directly connected but connected via the bumps 58, so that there is a difference in the thermal expansion coefficient between the interlayer insulating resin layer 58 and the IC 60. Even if it exists, there is no possibility that the thermal stress due to the difference is generated in the wiring, and the possibility of disconnection of the wiring can be eliminated.

更には、ＩＣ６０の電極と配線を直接接続する構造ではなく、バンプ５８を介して接続するので、配線形成の際に、ＩＣ６０と層間絶縁樹脂層５８との境界が外部に露出していない。従って、配線形成の際にＩＣ６０と層間絶縁樹脂層５８との境界を通じてエッチング液が該樹脂層５８内部に侵入して封止効果が低下するおそれがなく、信頼度、耐久性が損なわれるおそれがない。
また、半導体ウェハ６０単位で電子部品実装装置の製造を進め、最終的段階でカッティングにより個々の電子部品実装装置に分離することにより電子部品実装装置を得ることができ、半導体ウェハをカッティングしてチップに分離したものに配線部分を組み付ける場合に比較して、高い効率で電子部品実装装置の製造ができ、電子部品実装装置の低価格化を図ることができる。 Further, since the electrodes of the IC 60 and the wiring are not directly connected but via the bumps 58, the boundary between the IC 60 and the interlayer insulating resin layer 58 is not exposed to the outside when the wiring is formed. Therefore, there is no risk that the etching solution may enter the resin layer 58 through the boundary between the IC 60 and the interlayer insulating resin layer 58 during wiring formation, and the sealing effect may be reduced, and the reliability and durability may be impaired. Absent.
In addition, it is possible to obtain an electronic component mounting apparatus by proceeding with the manufacture of an electronic component mounting apparatus in units of 60 semiconductor wafers, and separating the individual electronic component mounting apparatuses by cutting at the final stage. Compared with the case where the wiring part is assembled into the separated parts, the electronic component mounting apparatus can be manufactured with higher efficiency, and the price of the electronic component mounting apparatus can be reduced.

図１１（Ａ）〜（Ｄ）は本発明に係る第５の実施例（：実施例５）である、電子部品実装装置の製造方法を工程順に示す断面図である。
（Ａ）図１０（Ａ）、（Ｂ）に示したと同様の工程で、銅箔５２のバンプ５４、５４、・・・を半導体ウェハ６０の各電極に接続した状態を形成する。図１１（Ａ）はその状態を示す。 FIGS. 11A to 11D are cross-sectional views showing a manufacturing method of an electronic component mounting apparatus according to the fifth embodiment (Example 5) of the present invention in the order of steps.
(A) A state in which the bumps 54, 54,... Of the copper foil 52 are connected to the respective electrodes of the semiconductor wafer 60 is formed by the same process as shown in FIGS. FIG. 11A shows this state.

（Ｂ）次に、上記銅箔５２を選択的にエッチングすることにより、図１１（Ｂ）に示すように、配線膜５２ａ、５２ａ、・・・を形成し、それに、図１０（Ａ）に示す配線部分と同様の構造の別の部材である配線部分５６を用意し、図１１（Ｂ）に示すように、その各バンプ５４、５４、・・・が対応する上記配線膜５２ａ、５２ａ、・・・と対向するように、半導体ウェハ６０と接続された配線部分５６に、別途用意した上記配線部分５６を、これのバンプ５４、５４、・・・に貫通された状態の層間絶縁樹脂層５８を介して臨ませる。 (B) Next, the copper foil 52 is selectively etched to form wiring films 52a, 52a,... As shown in FIG. A wiring portion 56, which is another member having the same structure as the wiring portion shown, is prepared. As shown in FIG. 11B, the bumps 54, 54,... Correspond to the wiring films 52a, 52a,. The inter-layer insulating resin layer in a state in which the wiring portion 56 prepared separately is passed through the bumps 54, 54,... In the wiring portion 56 connected to the semiconductor wafer 60 so as to face the semiconductor wafer 60. Through 58.

（Ｃ）次に、図１１（Ｃ）に示すように、半導体ウェハ６０と接続された配線部分５６に、別途用意した上記配線部分５６のバンプ５４、５４、・・・を接続し、その後、その配線部分５６の銅箔５２を選択的にエッチングすることにより配線膜５２ａを形成する。
（Ｄ）次に、上記半導体ウェハ６０と、層間絶縁樹脂層５８、５８及び配線部分５６、５６をカットすることにより、個々の電子部品実装装置６２ａ、６２ａ、・・・に分離する。
この分離された各電子部品実装装置６２ａも本発明に係る電子部品実装装置の実施の別の形態例である。 (C) Next, as shown in FIG. 11C, the bumps 54, 54,... Of the wiring part 56 prepared separately are connected to the wiring part 56 connected to the semiconductor wafer 60, and then A wiring film 52 a is formed by selectively etching the copper foil 52 of the wiring portion 56.
(D) Next, the semiconductor wafer 60, the interlayer insulating resin layers 58, 58, and the wiring portions 56, 56 are cut to be separated into individual electronic component mounting apparatuses 62a, 62a,.
Each separated electronic component mounting apparatus 62a is another embodiment of the electronic component mounting apparatus according to the present invention.

このような実施例によれば、半導体ウェハ単位で電子部品実装装置の製造を進め、最終的段階でカッティングにより個々の電子部品実装装置に分離することにより電子部品実装装置を得ることができ、半導体ウェハをカッティングしてチップに分離したものに配線部分を組み付ける場合に比較して、高い効率で電子部品実装装置の製造ができ、電子部品実装装置の低価格化を図ることができるのみならず、配線部分５６の銅箔５２から形成された配線膜５２ａを複数層に形成することができ、例えば、第２層目の配線膜５２ａ、５２ａ、・・・によって一つのＩＣ６０ａの電極相互の電気的接続を成すことが可能であり、ＩＣ６０ａ内の一部の配線を配線部分５６の配線膜５２ａに委ねることができ、ＩＣ６０ａの、或いは電子部品実装装置６２ａの設計の自由度を高めることができる。   According to such an embodiment, it is possible to obtain an electronic component mounting apparatus by proceeding with the manufacture of an electronic component mounting apparatus in units of semiconductor wafers, and separating into individual electronic component mounting apparatuses by cutting at the final stage. Compared to the case where the wafer is cut and separated into chips and the wiring part is assembled, the electronic component mounting apparatus can be manufactured with high efficiency, and the price of the electronic component mounting apparatus can be reduced. The wiring film 52a formed from the copper foil 52 of the wiring portion 56 can be formed in a plurality of layers. For example, the second layer wiring films 52a, 52a,. It is possible to make a connection, and a part of the wiring in the IC 60a can be entrusted to the wiring film 52a of the wiring part 56. 2a degree of freedom in the design of the can be increased.

図１２（Ａ）〜（Ｅ）及び図１３（Ｆ）、（Ｇ）は本発明に係る第６の実施例（：実施例６）である、電子部品実装装置の製造方法の工程（Ａ）〜（Ｇ）を順に示す断面図である。
（Ａ）銅箔５２の一方の主面にバンプ（第１のバンプ）５４、５４、・・・を形成した配線部分（第１の配線部分）５６を用意し、そのバンプ５４形成面に、層間絶縁樹脂層５８を各バンプ５４、５４、・・・に貫通された状態で形成する。図１２（Ａ）はその層間絶縁樹脂層５４形成後の状態を示す 12 (A) to 12 (E) and FIGS. 13 (F) and 13 (G) are steps (A) of the manufacturing method of the electronic component mounting apparatus according to the sixth embodiment (Example 6) of the present invention. It is sectional drawing which shows ~ (G) in order.
(A) A wiring portion (first wiring portion) 56 in which bumps (first bumps) 54, 54,... Are formed on one main surface of the copper foil 52 is prepared. An interlayer insulating resin layer 58 is formed so as to penetrate through the bumps 54, 54,. FIG. 12A shows a state after the interlayer insulating resin layer 54 is formed.

（Ｂ）次に、上記バンプ（第１のバンプ）５４、５４、・・・に電子部品６４、６４、・・・の電極を接続することにより、図１２（Ｂ）に示すように、配線部分（第１の配線部分）５６に電子部品実装装置複数個分の電子部品６４、６４、・・・を搭載する。
（Ｃ）次に、図１２（Ｃ）に示すように、上記電子部品６４、６４、・・・を搭載した配線部分５６の電子部品６４搭載側に、層間絶縁樹脂層７２を介して、別の配線部分（第２の配線部分）６６を臨ませる。 (B) Next, by connecting the electrodes of the electronic components 64, 64,... To the bumps (first bumps) 54, 54,..., As shown in FIG. The electronic components 64, 64,... For a plurality of electronic component mounting apparatuses are mounted on the portion (first wiring portion) 56.
(C) Next, as shown in FIG. 12 (C), the wiring part 56 on which the electronic parts 64, 64,... Are mounted on the electronic component 64 mounting side through an interlayer insulating resin layer 72. The wiring part (second wiring part) 66 is exposed.

該配線部分６６は銅箔６８の一方の主面にバンプ（第２のバンプ）７０、７０、・・・を形成したもので、該バンプ７０、７０、・・・は上記第１の配線部分５６のバンプ（第１のバンプ）５４よりも長さ（高さ）が電子部品６４の厚さ以上長い（高い）。バンプ７０、７０、・・・は、配線部分５６のバンプ５４、５４、・・・及びそれに電極が接続されて搭載された上記電子部品６４と位置が逸れるように位置設定されている。そして、各バンプ７０、７０、・・・が配線部分５６の電子部品６４搭載側の面を向き、配線部分５６・６６間に層間絶縁樹脂層７２が介在し、該配線部分５６・６６を位置合わせした状態で、配線部分５６に配線部分６６を臨ませるのである。   The wiring portion 66 is formed by forming bumps (second bumps) 70, 70,... On one main surface of the copper foil 68. The bumps 70, 70,. The length (height) of the 56 bumps (first bumps) 54 is longer (higher) than the thickness of the electronic component 64. The bumps 70, 70,... Are positioned so as to deviate from the positions of the bumps 54, 54,... Of the wiring portion 56 and the electronic component 64 mounted with electrodes connected thereto. The bumps 70, 70,... Face the electronic component 64 mounting surface of the wiring portion 56, the interlayer insulating resin layer 72 is interposed between the wiring portions 56 and 66, and the wiring portions 56 and 66 are positioned. In the combined state, the wiring portion 66 faces the wiring portion 56.

（Ｄ）次に、図１２（Ｄ）に示すように、層間絶縁樹脂層７２を上記各第２のバンプ７０、７０、・・・で貫通しつつ、該バンプ７０、７０、・・・の先端が配線部分５６の銅箔５２のバンプ（第１のバンプ）形成面に接続させることにより、二つの配線部分５６・６６を一体化する。７２はその二つの配線部分５６・６６の銅箔５２・６８間の層間絶縁樹脂層７２・５８が互いに溶融してできた層間絶縁樹脂層で、銅箔５２・６８間において、バンプ７０・５４及び電子部品６４相互間を絶縁分離し、更には、銅箔５２・６８を層間絶縁する。 (D) Next, as shown in FIG. 12D, while passing through the interlayer insulating resin layer 72 with the second bumps 70, 70,..., The bumps 70, 70,. The two wiring parts 56 and 66 are integrated by connecting the tip to the bump (first bump) forming surface of the copper foil 52 of the wiring part 56. Reference numeral 72 denotes an interlayer insulating resin layer formed by melting the interlayer insulating resin layers 72 and 58 between the copper foils 52 and 68 of the two wiring portions 56 and 66. Between the copper foils 52 and 68, bumps 70 and 54 are formed. And the electronic parts 64 are insulated from each other, and the copper foils 52 and 68 are further insulated from each other.

（Ｅ）次に、第２の配線部分６６の銅箔６８を選択的にエッチングすることにより配線膜６８ａ、６８ａ、・・・を形成すると共に、該各配線膜６８ａ、６８ａ、・・・形成側の面に、半導体ウェハ６０を、自身の電極と各配線膜６８ａ、６８ａ、・・・が対応するように臨ませる。図１１（Ｅ）はその半導体ウェハ６０を第１、第２の配線部分５６・６６を一体化したものに臨ませた状態を示す。
（Ｆ）次に、銅箔５２を選択的にエッチングすることにより配線膜５２ａ、５２ａ、・・・を形成し、その後、図１３（Ｇ）に示すように、半導体ウェハ６０及び第１、第２の配線部分５６・６６を一体化したものをカッティングすることにより個々の電子部品実装装置６２ｂ、６２ｂ、・・・に分離する。 (E) Next, by selectively etching the copper foil 68 of the second wiring portion 66, wiring films 68a, 68a,... Are formed, and the wiring films 68a, 68a,. The semiconductor wafer 60 faces the side surface so that its own electrode and each wiring film 68a, 68a,. FIG. 11E shows a state in which the semiconductor wafer 60 is made to face the integrated first and second wiring portions 56 and 66.
(F) Next, by selectively etching the copper foil 52, wiring films 52a, 52a,... Are formed, and then, as shown in FIG. .. Are separated into individual electronic component mounting apparatuses 62b, 62b,...

このような実施例によれば、半導体ウェハ単位で電子部品実装装置の製造を進め、最終的段階でカッティングにより個々の電子部品実装装置に分離することにより電子部品実装装置を得ることができ、半導体ウェハをカッティングしてチップに分離したものに配線部分を組み付ける場合に比較して、高い効率で電子部品実装装置の製造ができ、電子部品実装装置の低価格化を図ることができるのみならず、層間絶縁樹脂層７２内に電子部品６４を封止して内蔵することができ、ＩＣ６０ａとは別個に電子部品６４を設けることができる。
このように、本発明は種々の形態で実施することができ、種々の変形例があり得る。 According to such an embodiment, it is possible to obtain an electronic component mounting apparatus by proceeding with the manufacture of an electronic component mounting apparatus in units of semiconductor wafers, and separating into individual electronic component mounting apparatuses by cutting at the final stage. Compared to the case where the wafer is cut and separated into chips and the wiring part is assembled, the electronic component mounting apparatus can be manufactured with high efficiency, and the price of the electronic component mounting apparatus can be reduced. The electronic component 64 can be sealed and incorporated in the interlayer insulating resin layer 72, and the electronic component 64 can be provided separately from the IC 60a.
Thus, the present invention can be implemented in various forms, and there can be various modifications.

本発明は、電子部品実装装置とその製造方法に利用可能性がある。   The present invention is applicable to an electronic component mounting apparatus and a manufacturing method thereof.

（Ａ）〜（Ｇ）は本発明に係る電子部品実装装置の第１の実施例（：実施例１）の製造方法を工程順に示す断面図であり、（Ｇ）がその第１の実施例を示している。(A)-(G) is sectional drawing which shows the manufacturing method of 1st Example (: Example 1) of the electronic component mounting apparatus based on this invention in order of a process, (G) is the 1st Example. Is shown. （Ａ）、（Ｂ）は図１に示した製造方法の第１の変形例の要部を工程順に示す断面図である。(A), (B) is sectional drawing which shows the principal part of the 1st modification of the manufacturing method shown in FIG. 1 in order of a process. （Ａ）〜（Ｃ）は図１に示した製造方法の第２の変形例の要部を工程順に示す断面図である。(A)-(C) are sectional drawings which show the principal part of the 2nd modification of the manufacturing method shown in FIG. 1 in order of a process. 本発明に係る電子部品実装装置の第２の実施例（：実施例２）を示す断面図である。It is sectional drawing which shows the 2nd Example (: Example 2) of the electronic component mounting apparatus which concerns on this invention. （Ａ）〜（Ｃ）は図４に示した第２の実施例の製造方法の要部を工程順に示す断面図である。(A)-(C) are sectional drawings which show the principal part of the manufacturing method of the 2nd Example shown in FIG. 4 in order of a process. 本発明に係る電子部品実装装置の第３の実施例（：実施例３）を示す断面図である。It is sectional drawing which shows the 3rd Example (: Example 3) of the electronic component mounting apparatus which concerns on this invention. （Ａ）〜（Ｃ）は図６に示した第３の実施例の製造方法の要部を工程順に示す断面図である。(A)-(C) are sectional drawings which show the principal part of the manufacturing method of the 3rd Example shown in FIG. 6 in order of a process. 本発明に係る電子部品実装装置の第４の実施例（：実施例４）を示す断面図である。It is sectional drawing which shows the 4th Example (: Example 4) of the electronic component mounting apparatus which concerns on this invention. （Ａ）、（Ｂ）は図８に示した第３の実施例の製造方法の要部を工程順に示す断面図である。(A), (B) is sectional drawing which shows the principal part of the manufacturing method of the 3rd Example shown in FIG. 8 in order of a process. （Ａ）〜（Ｄ）は本発明に係る第４の実施例である、電子部品実装装置の製造方法を工程順に示す断面図である。(A)-(D) are sectional drawings which show the manufacturing method of the electronic component mounting apparatus which is the 4th Example which concerns on this invention in order of a process. （Ａ）〜（Ｄ）は本発明に係る第５の実施例（：実施例５）である、電子部品実装装置の製造方法を工程順に示す断面図である。(A)-(D) is sectional drawing which shows the manufacturing method of the electronic component mounting apparatus which is a 5th Example (: Example 5) based on this invention in order of a process. （Ａ）〜（Ｅ）は本発明に係る第６の実施例（：実施例６）である、電子部品実装装置の製造方法の工程（Ａ）〜（Ｇ）の内の（Ａ）〜（Ｅ）を順に示す断面図である。(A)-(E) are the 6th Example (: Example 6) which concerns on this invention, (A)-(G) of process (A)-(G) of the manufacturing method of an electronic component mounting apparatus. It is sectional drawing which shows E) in order. （Ｆ）、（Ｇ）は本発明に係る第６の実施例である、電子部品実装装置の製造方法の工程（Ａ）〜（Ｇ）の内の（Ｆ）、（Ｇ）を順に示す断面図である。(F), (G) is a sixth embodiment according to the present invention, and is a cross-sectional view sequentially showing (F), (G) among steps (A)-(G) of the method for manufacturing an electronic component mounting apparatus. FIG. （Ａ）〜（Ｅ）は電子部品実装装置の従来例の一つの製造方法を工程順に示す断面図である。(A)-(E) is sectional drawing which shows one manufacturing method of the prior art example of an electronic component mounting apparatus in order of a process.

符号の説明Explanation of symbols

２・・・金属箔（銅箔）、２ａ・・・配線膜、
４・・・バンプ（電子部品の電極と接続されるバンプ）、２ａ・・・配線部分、
５・・・金属部材、６・・・電子部品（層間絶縁樹脂層中に封止される電子部品）、
８・・・電極、１０・・・層間絶縁樹脂層、１０ａ・・・バンプ保護絶縁樹脂層、
１０ｈ・・・逃げ孔、１２・・・金属箔（銅箔）、１２ａ・・・配線膜、
１２ａ・・・配線部分、１４・・・貫通孔、１６・・・導電膜。 2 ... metal foil (copper foil), 2a ... wiring film,
4 ... Bump (bump connected to the electrode of the electronic component), 2a ... wiring part,
5 ... Metal member, 6 ... Electronic component (electronic component sealed in an interlayer insulating resin layer),
8 ... Electrode, 10 ... Interlayer insulating resin layer, 10a ... Bump protection insulating resin layer,
10h ... escape hole, 12 ... metal foil (copper foil), 12a ... wiring film,
12a ... wiring portion, 14 ... through hole, 16 ... conductive film.

Claims (10)

金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが上向きに形成された第１の配線部分と、
上記第１の配線部分の上記上向きのバンプに電極が接続された電子部品と、
金属箔により形成された複数の配線膜の少なくとも一部の配線膜の一部分に金属からなる略コニーデ状のバンプが下向きに形成された第２の配線部分と、
上記第２の配線部分の上記下向きのバンプに電極が接続された電子部品と、
上記第１の配線部分の上記配線膜が下面に露出し、上記第２の配線部分の上記配線膜が上面に露出するように、上記第１の配線部分及びその配線膜に電極が接続された電子部品、並びに上記第２の配線部分及びその配線膜に電極が接続された電子部品を封止する層間絶縁樹脂層と、
を少なくとも有することを特徴とする電子部品実装装置 A first wiring portion in which a substantially conical bump made of metal is formed upward on at least a part of a plurality of wiring films formed of a metal foil;
An electronic component having an electrode connected to the upward bump of the first wiring portion;
A second wiring portion in which a substantially conical bump made of metal is formed downward on a part of at least a part of the plurality of wiring films formed of metal foil;
An electronic component having an electrode connected to the downward bump of the second wiring portion;
An electrode is connected to the first wiring portion and the wiring film so that the wiring film of the first wiring portion is exposed on the lower surface and the wiring film of the second wiring portion is exposed on the upper surface. An interlayer insulating resin layer for sealing the electronic component, and the second wiring portion and the electronic component having an electrode connected to the wiring film;
Electronic component mounting apparatus characterized by comprising at least 金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分と、
上記配線部分の上記バンプに電極が接続された電子部品と、
上記配線部分の上記配線膜が露出するように上記電子部品を、その配線膜との間の接続部分及び反電極側の部分を含め囲繞する層間絶縁樹脂層と、
上記層間絶縁用絶縁樹脂層の上記配線部分と反対側の主面に金属箔により形成された配線膜と、
上記層間絶縁用絶縁樹脂層の上記配線部分と反対側の主面に金属箔により形成された配線膜に、そこから該樹脂層自身を貫通して上記配線部分の配線膜と接続されるように形成された金属からなるバンプと、
を少なくとも有することを特徴とする電子部品実装装置。 A wiring portion in which a substantially conical bump made of metal is formed on at least a part of a plurality of wiring films formed of a metal foil; and
An electronic component having electrodes connected to the bumps of the wiring portion;
An interlayer insulating resin layer surrounding the electronic component including the connection part between the wiring film and the part on the opposite electrode side so that the wiring film of the wiring part is exposed;
A wiring film formed of a metal foil on the main surface opposite to the wiring portion of the insulating resin layer for interlayer insulation;
A wiring film formed of a metal foil on the main surface opposite to the wiring portion of the insulating resin layer for interlayer insulation, and from there, penetrates through the resin layer itself and is connected to the wiring film of the wiring portion. Bumps made of formed metal,
An electronic component mounting apparatus characterized by comprising: 金属箔の一方の主面に金属からなる略コニーデ状のバンプを選択的に形成した金属部材の該各バンプに電子部品の各電極を接続した電子部品搭載金属部材を２つ用意し、
上記電子部品搭載金属部材のうちの一方に、その搭載電子部品をその上面を含め囲繞するように層間絶縁樹脂層を塗布し、
その後、上記電子部品搭載金属部材のうちの他方の電子部品の搭載面を上記一方の電子部品搭載金属部材の搭載面に臨ませ、上記層間絶縁樹脂層によって該他方の電子部品により封止され、両電子部品搭載金属部材の金属箔間が層間絶縁されるように、上記二つの電子部品搭載金属部材を、上記層間絶縁樹脂層を介して積層一体化し、
しかる後、上記二つの電子部品搭載金属部材の金属箔を順次又は同時にパターニングする
ことを特徴とする電子部品実装装置の製造方法。 Prepare two electronic component mounting metal members in which each electrode of the electronic component is connected to each bump of the metal member in which the substantially conical bump made of metal is selectively formed on one main surface of the metal foil,
Applying an interlayer insulating resin layer to one of the electronic component mounting metal members so as to surround the mounted electronic component including its upper surface,
Then, the mounting surface of the other electronic component of the electronic component mounting metal member faces the mounting surface of the electronic component mounting metal member, and is sealed by the other electronic component by the interlayer insulating resin layer, The two electronic component mounting metal members are laminated and integrated via the interlayer insulating resin layer so that the metal foils of both electronic component mounting metal members are interlayer-insulated,
Thereafter, the metal foils of the two electronic component mounting metal members are patterned sequentially or simultaneously. 金属箔の一方の主面に金属からなるコニーデ状の複数のバンプを形成した第１の金属部材と、金属箔の一方の主面に金属からなり上記バンプより高さの高いコニーデ状のバンプを形成した第２の金属部材を用意し、
上記第１の金属部材には、そのバンプに電子部品の電極を接続することによって電子部品を搭載し、上記第２の金属部材には、その金属箔のバンプ形成面に層間絶縁樹脂層を塗布し、
上記第２の金属部材のバンプ形成側に、上記第１の金属部材のバンプ形成側を臨ませて、上記電子部品が上記層間絶縁樹脂層内に入り且つ第２の金属部材のバンプが第１の金属部材の配線膜に接続されるように上記第１及び第２の金属部材を層間絶縁樹脂層を介して積層一体化する
ことを特徴とする電子部品実装装置の製造方法。 A first metal member formed with a plurality of conical-shaped bumps made of metal on one main surface of the metal foil, and a conical-shaped bump made of metal on one main surface of the metal foil and having a height higher than the bumps. Prepare the formed second metal member,
An electronic component is mounted on the first metal member by connecting an electrode of the electronic component to the bump, and an interlayer insulating resin layer is applied to the bump forming surface of the metal foil on the second metal member. And
The bump formation side of the first metal member faces the bump formation side of the second metal member, the electronic component enters the interlayer insulating resin layer, and the bump of the second metal member is the first. A method of manufacturing an electronic component mounting apparatus, wherein the first and second metal members are laminated and integrated via an interlayer insulating resin layer so as to be connected to a wiring film of the metal member. ベアの半導体集積回路素子と、
金属箔により形成された複数の配線膜の内の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分と、
上記配線部分の上記バンプの形成された側の面に該各バンプによって貫通された状態で形成された層間絶縁樹脂層と、
からなり、
上記各バンプが上記ベアの半導体集積回路素子の電極に接続されて、上記配線部分が上記層間絶縁樹脂層を介して上記ベアの半導体集積回路素子に一体化されてなる
ことを特徴とする電子部品実装装置。 A bare semiconductor integrated circuit element; and
A wiring portion in which a substantially conical bump made of metal is formed on at least a part of a plurality of wiring films formed of a metal foil; and
An interlayer insulating resin layer formed in a state of being penetrated by each bump on the surface of the wiring portion on which the bump is formed;
Consists of
Each of the bumps is connected to an electrode of the bare semiconductor integrated circuit element, and the wiring portion is integrated with the bare semiconductor integrated circuit element through the interlayer insulating resin layer. Mounting device. 金属箔の一部に金属からなる略コニーデ状のバンプが形成された電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものと、電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハとを用意し、
上記各バンプ端部を、上記半導体ウェハの対応する電極に接続することにより上記電子部品実装装置複数個分の配線部分を上記層間絶縁樹脂層を介して上記半導体ウェハと一体化し、
その後、上記金属箔をパターニングすることにより配線膜を形成し、
しかる後、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離する
ことにより請求項５の電子部品実装装置を得ることを特徴とする電子部品実装装置の製造方法。 An electronic component mounting device having a metal foil formed on a part of a metal foil. An inter-layer insulating resin layer is formed on the surface of the bump forming side of a wiring portion for a plurality of wiring parts in a state of being penetrated by each bump. And a semiconductor wafer in which semiconductor integrated circuit elements for a plurality of electronic component mounting apparatuses are integrally formed,
By connecting the bump ends to the corresponding electrodes of the semiconductor wafer, the wiring parts for the plurality of electronic component mounting apparatuses are integrated with the semiconductor wafer via the interlayer insulating resin layer,
Then, the wiring film is formed by patterning the metal foil,
Thereafter, the semiconductor wafer, the interlayer insulating resin layer, and the upper wiring portion are cut to be separated into individual electronic component mounting apparatuses, whereby the electronic component mounting apparatus according to claim 5 is obtained. Device manufacturing method. ベアの半導体集積回路素子と、
金属箔により形成された複数の配線膜の少なくとも一部の配線膜に金属からなる略コニーデ状のバンプが形成された配線部分の該バンプの形成された側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したものを、各バンプと配線膜とを接続することにより複数段積層したものと、
からなり、
上記複数段積層したもののバンプが露出する側のその各バンプを上記半導体集積回路素子の各電極に接続してなる
ことを特徴とする電子部品実装装置。 A bare semiconductor integrated circuit element; and
At least a part of the plurality of wiring films formed of the metal foil is penetrated by the bumps on the surface on the side where the bumps are formed in the wiring portion in which the substantially conical bumps made of metal are formed. What formed the interlayer insulation resin layer in the state, laminated multiple stages by connecting each bump and the wiring film,
Consists of
An electronic component mounting apparatus, wherein the bumps on the side where the bumps of the multi-layered laminate are exposed are connected to the electrodes of the semiconductor integrated circuit element. 電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハと、金属からなる配線膜の少なくとも一部に金属からなる略コニーデ状のバンプが形成された電子部品実装装置複数個分の配線部分のバンプ形成側の面に該各バンプによって貫通された状態で層間絶縁樹脂層を形成したもの又はそれを複数段積層したものとを、各バンプを上記半導体ウェハの各電極に接続することにより一体化し、
その後、上記半導体ウェハ、上記層間絶縁樹脂層及び上配線部分をカッティングすることにより個々の電子部品実装装置に分離する
ことにより請求項７の電子部品実装装置を得ることを特徴とする電子部品実装装置の製造方法。 A plurality of electronic component mounting apparatuses in which semiconductor integrated circuit elements corresponding to a plurality of electronic component mounting apparatuses are integrally formed, and a substantially conical bump made of metal is formed on at least a part of a wiring film made of metal Connect each bump to each electrode of the semiconductor wafer by forming an interlayer insulating resin layer in a state of being penetrated by each bump on the surface on the bump forming side of the wiring portion or by laminating a plurality of layers thereof To be integrated,
Then, the electronic component mounting apparatus according to claim 7 is obtained by separating the semiconductor wafer, the interlayer insulating resin layer, and the upper wiring portion into individual electronic component mounting apparatuses by cutting. Manufacturing method. ベアの半導体集積回路素子と、
金属箔からなる配線膜の一部に第１のバンプを形成した第１の配線部分と、
上記第１のバンプに電極が接続されて上記第１の配線部分の該第１のバンプ形成側に設けられた１又は複数の電子部品と、
金属箔からなる配線膜の一部に上記第１のバンプよりも高い高さを有する第２のバンプを形成した第２の配線部分と、
上記第１と第２の配線部分間に設けられた上記電子部品を封止する層間絶縁樹脂層と、
からなり、
上記第２の配線部分を、それの上記第２のバンプを上記第１の配線部分の配線膜に接続することにより、上記第１の配線部分の上側にその間に上記電子部品が存在するように位置させ、
該第２の配線部分の配線膜と上記ベアの半導体集積回路素子の電極とを接続してなる
ことを特徴とする電子部品実装装置。 A bare semiconductor integrated circuit element; and
A first wiring portion in which a first bump is formed on a part of a wiring film made of metal foil;
One or a plurality of electronic components provided on the first bump forming side of the first wiring portion with electrodes connected to the first bump;
A second wiring portion in which a second bump having a height higher than that of the first bump is formed on a part of the wiring film made of metal foil;
An interlayer insulating resin layer for sealing the electronic component provided between the first and second wiring portions;
Consists of
By connecting the second bump of the second wiring portion to the wiring film of the first wiring portion so that the electronic component exists above the first wiring portion. Position
An electronic component mounting apparatus comprising: a wiring film of the second wiring portion connected to an electrode of the bare semiconductor integrated circuit element. 金属箔からなる配線膜の一部に第１のバンプを形成した第１の配線部分の上記第１のバンプが形成された側に第１の層間絶縁樹脂層を設け、該第１のバンプと１又は複数の電子部品の電極とを接続し、
金属箔の一部に上記第１のバンプよりも高い高さを有する第２のバンプを形成した第２の配線部分の第２のバンプ形成側の面を、第２の層間絶縁樹脂層を介して上記第１の配線部分の電子部品搭載側の面に臨ませ、上記第２のバンプを上記第２の層間絶縁樹脂層を貫通させて上記第１の配線部分の金属箔の一部に接続することにより上記第１と第２の配線部分同士を一体化し、
上記第２の配線部分の第２の金属箔をパターニングすることにより配線膜を形成し、
電子部品実装装置複数個分の半導体集積回路素子が一体に形成された半導体ウェハの各電極と、上記第２の配線部分の上記配線膜を接続することにより、該半導体ウェハ及び上記第１及び第２の配線部分を一体化し、
第１の配線部分の金属箔をパターニングすることにより配線膜を形成し、
上記半導体ウェハ、上記第１、第２の配線部分及び上記第１、第２の層間絶縁樹脂層をカッティングすることにより個々の電子部品実装装置に分離する
ことにより請求項９の電子部品実装装置を得ることを特徴とする電子部品実装装置の製造方法。 A first interlayer insulating resin layer is provided on a side of the first wiring portion where the first bump is formed on a part of the wiring film made of metal foil on the side where the first bump is formed. Connecting electrodes of one or more electronic components,
A surface on the second bump forming side of the second wiring portion in which the second bump having a height higher than the first bump is formed on a part of the metal foil, with the second interlayer insulating resin layer interposed therebetween. Then, the first bump portion faces the surface on which the electronic component is mounted, and the second bump penetrates the second interlayer insulating resin layer and is connected to a part of the metal foil of the first wire portion. By integrating the first and second wiring parts,
Forming a wiring film by patterning the second metal foil of the second wiring portion;
By connecting each electrode of a semiconductor wafer integrally formed with a plurality of semiconductor integrated circuit elements for a plurality of electronic component mounting apparatuses to the wiring film of the second wiring portion, the semiconductor wafer and the first and first 2 wiring parts are integrated,
A wiring film is formed by patterning the metal foil of the first wiring portion,
10. The electronic component mounting apparatus according to claim 9, wherein the semiconductor wafer, the first and second wiring portions, and the first and second interlayer insulating resin layers are separated into individual electronic component mounting apparatuses by cutting. A method of manufacturing an electronic component mounting apparatus, wherein:
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