JP2008135574A - Wiring board, semiconductor device using the same and probe card - Google Patents

Wiring board, semiconductor device using the same and probe card Download PDF

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Publication number
JP2008135574A
JP2008135574A JP2006320779A JP2006320779A JP2008135574A JP 2008135574 A JP2008135574 A JP 2008135574A JP 2006320779 A JP2006320779 A JP 2006320779A JP 2006320779 A JP2006320779 A JP 2006320779A JP 2008135574 A JP2008135574 A JP 2008135574A
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wiring board
substrate
thermal expansion
insulating layer
expansion coefficient
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Hitoshi Tega
仁 手賀
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board superior in electric reliability. <P>SOLUTION: The multilayer wiring board is provided with a substrate 2 having a first face 2a and a second face 2b and having a wiring conductor 5 inside, a first electrode pad 21 formed on the first face 2a, a second electrode pad 22 which is electrically connected to the first electrode pad 21 through the wiring conductor 5 and is formed on the second face 2b, a first insulating layer 4 which has a first thermal expansion coefficient α and is bonded to the first face 2a of the substrate 2 and a second insulating layer 5 which has a second thermal expansion coefficient β larger than the first thermal expansion coefficient α and is bonded to the second face 2b of the substrate 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、配線基板およびそれを用いた半導体装置とプローブカード。   The present invention relates to a wiring board, a semiconductor device using the wiring board, and a probe card.

従来の配線基板は、複数の絶縁層からなり、上面と下面とに電極を有する基板と、基板内部に形成されており、上面および下面の電極を電気的に接続する配線導体とからなる。このような従来の配線基板において、配線導体は、複数の絶縁層間に配置された配線パターンと、この配線パターンに接続された貫通導体とからなる。   A conventional wiring board includes a plurality of insulating layers, and includes a substrate having electrodes on the upper surface and the lower surface, and a wiring conductor that is formed inside the substrate and electrically connects the electrodes on the upper surface and the lower surface. In such a conventional wiring board, the wiring conductor is composed of a wiring pattern arranged between a plurality of insulating layers and a through conductor connected to the wiring pattern.

このような配線基板は、上面の電極に半導体素子の電極が電気的に接続されるとともに、下面がプリント配線基板に二次実装されることで、半導体装置やプローブカードなどとして用いられる。
特開２００４−１３４７２４号公報 Such a wiring board is used as a semiconductor device, a probe card, or the like by electrically connecting the electrode of the semiconductor element to the electrode on the upper surface and secondary mounting the lower surface on the printed wiring board.
JP 2004-134724 A

このような配線基板においては、配線基板の上面に接続される部材と、配線基板の下面に接続される部材とが異なるため、その熱膨張係数差に起因して、配線基板に応力が生じ、配線基板の電気的特性が劣化するという問題があった。   In such a wiring board, since the member connected to the upper surface of the wiring board is different from the member connected to the lower surface of the wiring board, stress is generated in the wiring board due to the difference in thermal expansion coefficient. There was a problem that the electrical characteristics of the wiring board deteriorated.

本発明は上記課題に鑑みて案出されたものであり、その目的は、電気的特性に優れた配線基板をおよびそれを用いた半導体装置、プローブカードを提供することにある。   The present invention has been devised in view of the above problems, and an object of the present invention is to provide a wiring board having excellent electrical characteristics, a semiconductor device using the wiring board, and a probe card.

本発明の多層配線基板は、基板の第１の面に形成されており、第１の熱膨張係数を有する第１の絶縁層と、基板の第２の面に形成されており、第２の熱膨張係数を有する第２の絶縁層とを有することを特徴とするものである。   The multilayer wiring board of the present invention is formed on the first surface of the substrate, formed on the first insulating layer having the first thermal expansion coefficient, and on the second surface of the substrate, And a second insulating layer having a thermal expansion coefficient.

本発明の配線基板は、内部に配線導体を有する基板の第１の面に形成されており、第１の熱膨張係数を有する第１の絶縁層と、内部に配線導体を有する基板の第２の面に形成されており、第２の熱膨張係数を有する第２の絶縁層とを備えていることにより、配線基板と接合される部材と配線基板との間に生じる応力を低減して、基板の変形を低減することができる。このように、本発明の配線基板において、第１の絶縁層と第２の絶縁層との熱膨張係数を異ならせ、第１の熱膨張係数と第２の熱膨張係数との関係に工夫を施したことにより、配線基板の電気的特性を向上させることができる。   The wiring board of the present invention is formed on a first surface of a substrate having a wiring conductor therein, and includes a first insulating layer having a first thermal expansion coefficient and a second of the substrate having a wiring conductor inside. By forming the second insulating layer having the second thermal expansion coefficient, the stress generated between the member bonded to the wiring board and the wiring board is reduced, The deformation of the substrate can be reduced. As described above, in the wiring board of the present invention, the first insulating layer and the second insulating layer have different thermal expansion coefficients, and the device is devised for the relationship between the first thermal expansion coefficient and the second thermal expansion coefficient. By applying, the electrical characteristics of the wiring board can be improved.

本発明の半導体装置は、配線基板の第１の電極に電気的に接続された半導体素子と、配線基板の第２の電極に電気的に接続されたプリント配線基板とを備えることにより、半導体素子の動作時の発熱などにより、配線基板に生じる変形を低減でき、半導体装置の電気的信頼性を向上できる。ここで、一般的にプリント配線基板の熱膨張係数は、半導体素子の熱膨張係数よりも大きい。本発明において、半導体素子側に配置される第１の絶縁層の第１の熱膨張係数を、第２の絶縁層の第２の熱膨張係数よりも小さくすることにより、配線基板の半導体素子に接合される側を拘束し、半導体素子と配線基板との電気的接続を向上することができるとともに、配線基板のプリント配線基板側とプリント基板との接続信頼性を向上することができる。   A semiconductor device according to the present invention includes a semiconductor element electrically connected to a first electrode of a wiring board and a printed wiring board electrically connected to a second electrode of the wiring board. Due to the heat generated during the operation, deformation generated in the wiring board can be reduced, and the electrical reliability of the semiconductor device can be improved. Here, generally, the thermal expansion coefficient of the printed wiring board is larger than the thermal expansion coefficient of the semiconductor element. In the present invention, the first thermal expansion coefficient of the first insulating layer disposed on the semiconductor element side is made smaller than the second thermal expansion coefficient of the second insulating layer, whereby the semiconductor element of the wiring board is formed. The bonding side can be restrained, and the electrical connection between the semiconductor element and the wiring board can be improved, and the connection reliability between the printed wiring board side of the wiring board and the printed board can be improved.

また、配線基板の複数の第１の電極に電気的に接続されており、被検査対象に設けられた複数の電極に接触する複数の端子と、上面に半導体素子が搭載された配線基板とを備えるプローブカードとして配線基板が用いられる場合、プローブカードのバーンインテスト時などに配線基板に生じる変形が抑制されるため、プローブカードの電気的特性を向上させることができる。   In addition, a plurality of terminals that are electrically connected to the plurality of first electrodes of the wiring board and are in contact with the plurality of electrodes provided on the object to be inspected, and a wiring board on which the semiconductor element is mounted on the upper surface When a wiring board is used as the probe card provided, deformation that occurs in the wiring board during a burn-in test of the probe card is suppressed, so that the electrical characteristics of the probe card can be improved.

以下、本発明の実施の形態に係る配線基板について図面を参照して詳細に説明する。   Hereinafter, a wiring board according to an embodiment of the present invention will be described in detail with reference to the drawings.

（第１実施形態）本発明の第１の実施の形態について図１を用いて説明する。図１（ａ）は、本発明における第１の実施の形態に係る配線基板１の構造を示す平面図である。図１（ｂ）は、図１（ａ）に示した配線基板１のＸ−Ｘ’線における断面図である。   (First Embodiment) A first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view showing the structure of the wiring board 1 according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line X-X ′ of the wiring board 1 shown in FIG.

本実施形態の配線基板１は、基板２と、基板２の第１の面２ａ上に形成された第１の絶縁層３と、基板２の第２の面２ｂ上に形成された第２の絶縁層４とを備えている。   The wiring substrate 1 according to the present embodiment includes a substrate 2, a first insulating layer 3 formed on the first surface 2a of the substrate 2, and a second layer formed on the second surface 2b of the substrate 2. And an insulating layer 4.

本実施形態における基板２は、複数の層２ｓからなり、複数の第１の電極パッド２１が形成された第１の面（図１（ｂ）における上面）２ａと、複数の第２の電極パッド２２が形成された第２の面（図１（ｂ）における下面）２ｂとを有している。複数の第１の電極パッド２１と複数の第２の電極パッド２２とは、基板２の内部に形成された配線導体５を介して電気的に接続されている。   The substrate 2 in the present embodiment includes a plurality of layers 2s, a first surface (upper surface in FIG. 1B) 2a on which a plurality of first electrode pads 21 are formed, and a plurality of second electrode pads. And a second surface (lower surface in FIG. 1B) 2b on which 22 is formed. The plurality of first electrode pads 21 and the plurality of second electrode pads 22 are electrically connected via wiring conductors 5 formed inside the substrate 2.

また、本実施形態において基板２は、第１の絶縁層３と第２の絶縁層４とを固定（支持）している。このような基板２を構成する複数の絶縁層２ｓは、例えば、ポリイミド，ＢＣＢ（ベンゾシクロブテン），エポキシ樹脂，フッ素系樹脂などからなり、このような樹脂で形成することにより、微細で高密度な配線を行うことができる。図１において、複数の層２ｓは、エポキシ樹脂からなり、配線導体５は、複数の絶縁層２ｓの各々の表面に形成された配線パターンと、複数の絶縁層２ｓの各々を貫通する貫通導体とからなる。   In the present embodiment, the substrate 2 fixes (supports) the first insulating layer 3 and the second insulating layer 4. The plurality of insulating layers 2s constituting such a substrate 2 are made of, for example, polyimide, BCB (benzocyclobutene), epoxy resin, fluorine-based resin, and the like. Wiring can be performed. In FIG. 1, the plurality of layers 2s are made of epoxy resin, and the wiring conductor 5 includes a wiring pattern formed on each surface of the plurality of insulating layers 2s, and a through conductor penetrating each of the plurality of insulating layers 2s. Consists of.

第１の絶縁層３は、基板２の第１の面２ａ上に形成されており、第１の熱膨張係数αを有する。図１において、第１の絶縁層３は、表面（図１（ｂ）における上面）３ａに複数の電極３１を有している。第１の絶縁層３の上面３ａに形成された複数の電極３１は、第１の絶縁層３を貫通するビア導体を介して、基板２の上面２ａに形成された複数の電極２１と電気的に接続されている。このような第１の絶縁層３の上面３ａには、例えば、半導体素子などが搭載され、半導体素子が有する複数の電極と、第１の絶縁層３の複数の電極３１とが電気的に接続される。   The first insulating layer 3 is formed on the first surface 2a of the substrate 2 and has a first thermal expansion coefficient α. In FIG. 1, the first insulating layer 3 has a plurality of electrodes 31 on the surface (upper surface in FIG. 1B) 3a. The plurality of electrodes 31 formed on the upper surface 3 a of the first insulating layer 3 are electrically connected to the plurality of electrodes 21 formed on the upper surface 2 a of the substrate 2 through via conductors that penetrate the first insulating layer 3. It is connected to the. For example, a semiconductor element or the like is mounted on the upper surface 3a of the first insulating layer 3, and a plurality of electrodes included in the semiconductor element and a plurality of electrodes 31 of the first insulating layer 3 are electrically connected. Is done.

第２の絶縁層４は、基板２の第２の面２ｂ上に形成されており、第２の熱膨張係数βを有する。図１（ｂ）において、第２の絶縁層４は、表面（図１（ｂ）における下面）４ａに複数の電極４２を有している。第２の絶縁層４の下面４ａに形成された複数の電極４２は、第２の絶縁層４を貫通するビア導体を介して、基板２の下面２ｂに形成された複数の電極２２と電気的に接続されている。このような第２の絶縁層４の下面４ａは、半田等を介して、例えば、プリント配線基板（マザーボード）に実装される。   The second insulating layer 4 is formed on the second surface 2b of the substrate 2 and has a second thermal expansion coefficient β. In FIG.1 (b), the 2nd insulating layer 4 has the some electrode 42 on the surface (lower surface in FIG.1 (b)) 4a. The plurality of electrodes 42 formed on the lower surface 4 a of the second insulating layer 4 are electrically connected to the plurality of electrodes 22 formed on the lower surface 2 b of the substrate 2 through via conductors that penetrate the second insulating layer 4. It is connected to the. Such a lower surface 4a of the second insulating layer 4 is mounted on, for example, a printed wiring board (motherboard) via solder or the like.

このような第１の絶縁層３と第２の絶縁層４とは、内部に配線導体５を有する基板２を介して接合されていることにより、第１の絶縁層３と第２の絶縁層４とが接着剤を介して直接接合されている場合と比べて、それぞれの歪みにより第１の絶縁層３および第２の絶縁層４間に互いに及ぼしあう応力を低減することができる。   The first insulating layer 3 and the second insulating layer 4 are joined to each other through the substrate 2 having the wiring conductor 5 therein, so that the first insulating layer 3 and the second insulating layer are joined. As compared with the case where the first and second insulating layers 4 and 4 are directly bonded to each other through an adhesive, the stress exerted between the first insulating layer 3 and the second insulating layer 4 due to the respective strains can be reduced.

本実施の形態における第２の絶縁層４は、第１の絶縁層３の第１の熱膨張係数αよりも大きい第２の熱膨張係数βを有する。本実施の形態の配線基板１は、このような構成により、配線基板１の電気的信頼性を向上することができる。   The second insulating layer 4 in the present embodiment has a second thermal expansion coefficient β that is larger than the first thermal expansion coefficient α of the first insulating layer 3. The wiring board 1 of the present embodiment can improve the electrical reliability of the wiring board 1 with such a configuration.

このような第１の絶縁層３として、例えばシリコンに熱膨張係数が近いムライト、チッ化アルミなどのセラミックスを用い、第２の絶縁層４として、例えばプリント配線基板に熱膨張係数が近いガラスセラミックスを用いることができる。このように絶縁性に優れたガラスセラミックスを用い、その熱膨張率を第１の絶縁層３と第２の絶縁層４において異ならせることで、電気的特性に優れた配線基板１とすることができる。   For example, a ceramic such as mullite or aluminum nitride having a thermal expansion coefficient close to that of silicon is used as the first insulating layer 3, and a glass ceramic having a thermal expansion coefficient close to that of a printed wiring board is used as the second insulating layer 4. Can be used. As described above, by using glass ceramics having excellent insulating properties, and having different thermal expansion coefficients between the first insulating layer 3 and the second insulating layer 4, the wiring substrate 1 having excellent electrical characteristics can be obtained. it can.

ここで、このように構成される配線基板１を用いる例を図８（ａ）（ｂ）を参照し説明する。図８（ａ）は、本発明の配線基板１を用いた半導体装置１０を示す断面図、図８（ｂ）は、本発明の配線基板１を用いたプローブカードを示す断面図である。   Here, an example using the wiring board 1 configured as described above will be described with reference to FIGS. 8A is a cross-sectional view showing a semiconductor device 10 using the wiring board 1 of the present invention, and FIG. 8B is a cross-sectional view showing a probe card using the wiring board 1 of the present invention.

図８（ａ）に示す半導体装置１０において、配線基板１は、半導体素子６０をプリント配線基板７０上に支持する機能を有している。半導体素子６０の電極６１は、配線基板１の第１の絶縁層３上の複数の第１の電極３１と、半田３５を介して、電気的に接続されており、プリント配線基板７０の電極７１は、配線基板１の第２の絶縁層４上（図８ａにおいては、第２の絶縁層４の下面側）の第２の電極４２と、半田７５を介して、電気的に接続されている。   In the semiconductor device 10 shown in FIG. 8A, the wiring board 1 has a function of supporting the semiconductor element 60 on the printed wiring board 70. The electrode 61 of the semiconductor element 60 is electrically connected to the plurality of first electrodes 31 on the first insulating layer 3 of the wiring board 1 through the solder 35, and the electrode 71 of the printed wiring board 70. Is electrically connected to the second electrode 42 on the second insulating layer 4 of the wiring board 1 (on the lower surface side of the second insulating layer 4 in FIG. 8 a) via the solder 75. .

ここで、半導体素子６０を配線基板１の第１の絶縁層３上に搭載し、このような配線基板１をプリント配線基板７０上に二次実装する場合、一般的に、半導体素子６０の熱膨張率は、プリント配線基板７０よりも小さいため、配線基板１全体に配線基板１が下に凸となるような反り変形が生じようとする。本実施の形態においては、このような反りが生じようとしても、配線基板１の半導体素子６０側に位置する第１の絶縁層３の熱膨張係数αを、プリント配線基板７０側に位置する第２の絶縁層４の熱膨張係数βより小さく設定しておくことで、配線基板１と半導体素子６０とを接合する半田３５や、配線基板１とプリント配線基板７０とを接合する半田７５にクラックが発生し、破断する不具合を低減することができ、半導体装置１０の電気的特性を向上できる。   Here, when the semiconductor element 60 is mounted on the first insulating layer 3 of the wiring board 1 and such a wiring board 1 is secondarily mounted on the printed wiring board 70, the heat of the semiconductor element 60 is generally provided. Since the expansion coefficient is smaller than that of the printed wiring board 70, the entire wiring board 1 tends to be warped and deformed so that the wiring board 1 protrudes downward. In the present embodiment, even if such warpage is likely to occur, the thermal expansion coefficient α of the first insulating layer 3 located on the semiconductor element 60 side of the wiring board 1 is set to the first coefficient located on the printed wiring board 70 side. 2 is set to be smaller than the thermal expansion coefficient β of the insulating layer 4, cracks occur in the solder 35 that joins the wiring board 1 and the semiconductor element 60 and the solder 75 that joins the wiring board 1 and the printed wiring board 70. This can reduce the failure to break and improve the electrical characteristics of the semiconductor device 10.

また、図８（ｂ）において、配線基板１は、インターポーザー（中継基板）として機能している。配線基板１の第２の絶縁層４の複数の電極４２は、プリント配線基板７０の電極７１と電気的に接続されており、このプリント配線基板７０の電極７２が、外部のテスターと電気的に接続される。   In FIG. 8B, the wiring board 1 functions as an interposer (relay board). The plurality of electrodes 42 of the second insulating layer 4 of the wiring board 1 are electrically connected to the electrodes 71 of the printed wiring board 70, and the electrodes 72 of the printed wiring board 70 are electrically connected to an external tester. Connected.

検査作業を行う場合には、検査を行う必要のある被検査対象の半導体素子６０の電極６１に、接触端子８０を介して、配線基板１の第１の絶縁層３の複数の電極３１を電気的に接続することで、被検査対象６０がテスターに接続されて、そのテスターの作動による検査を行うことができる。図８（ｂ）に示すプローブカードにおいて、本実施形態の配線基板１が用いられるため、半田３５を介する配線基板１とプローブピン８０との接続および半田７５を介する配線基板１とプリント配線基板７０との接続が強固となり、プローブカードの電気的信頼性が向上する。   When performing the inspection work, the plurality of electrodes 31 of the first insulating layer 3 of the wiring board 1 are electrically connected to the electrodes 61 of the semiconductor element 60 to be inspected that need to be inspected via the contact terminals 80. Therefore, the inspection target 60 can be connected to the tester and the test can be performed by operating the tester. In the probe card shown in FIG. 8B, since the wiring board 1 of the present embodiment is used, the connection between the wiring board 1 and the probe pin 80 via the solder 35 and the wiring board 1 and the printed wiring board 70 via the solder 75 are used. And the electrical reliability of the probe card is improved.

このように、本実施形態の配線基板１を用いられた半導体装置１０とプローブカードにおいては、クラックなどにより電気的特性に不具合が生じにくく、信頼性の高い半導体装置およびプローブカードとすることができる。   As described above, in the semiconductor device 10 and the probe card using the wiring substrate 1 of the present embodiment, the electrical characteristics are hardly caused by a crack or the like, and a highly reliable semiconductor device and probe card can be obtained. .

また、基板２が、第１の熱膨張係数αより大きく、第２の熱膨張係数βより小さい第３の熱膨張係数γを有することで、配線基板２の電気的特性をさらに向上することができる。すなわち、複数の絶縁層２ｓからなる基板２の第３の熱膨張係数γを、第１の熱膨張係数αと第２の熱膨張係数βとの間の値とすることで、基板２の第１の面２ａ側から第２の面２ｂ側に向かって徐々に熱膨張係数を大きくすることができる。このため、配線導体５を有する基板２の内部における熱膨張による応力も低減することができ、基板２の全体に生じる応力を低減することができ、配線基板１の電気的特性が向上する。   Further, since the substrate 2 has the third thermal expansion coefficient γ that is larger than the first thermal expansion coefficient α and smaller than the second thermal expansion coefficient β, the electrical characteristics of the wiring board 2 can be further improved. it can. That is, by setting the third thermal expansion coefficient γ of the substrate 2 made of the plurality of insulating layers 2s to a value between the first thermal expansion coefficient α and the second thermal expansion coefficient β, The thermal expansion coefficient can be gradually increased from the first surface 2a side toward the second surface 2b side. For this reason, the stress due to thermal expansion inside the substrate 2 having the wiring conductor 5 can also be reduced, the stress generated in the entire substrate 2 can be reduced, and the electrical characteristics of the wiring substrate 1 are improved.

このような第１の膨張係数α、第２の熱膨張係数β、第３の熱膨張係数γは、ＴＭＡ（ＴｈｅｒｍｏｍｅｃｈａｎｉｃａｌＡｎａｌｙｓｉｓ）装置を用いて求めることができる。   Such first expansion coefficient α, second thermal expansion coefficient β, and third thermal expansion coefficient γ can be obtained using a TMA (Thermal Mechanical Analysis) apparatus.

（第２の実施の形態）図２、３を用いて本発明の第２の実施の形態に係る配線基板について説明する。図２は、本発明の第２の実施の形態に係る配線基板の構成を示す断面図である。図３は、本発明の第２の実施の形態に係る配線基板の製造方法の一例を示す工程図である。   (Second Embodiment) A wiring board according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing the configuration of the wiring board according to the second embodiment of the present invention. FIG. 3 is a process diagram showing an example of a method of manufacturing a wiring board according to the second embodiment of the present invention.

本実施の形態の配線基板１において、図１に示した第１の実施の形態の配線基板と異なる構成は、基板２０が単層構造からなる点である。図２において、基板２０は樹脂からなり、基板２０の第１の面２０ａに形成された複数の第１の電極パッド２１と、第２の面２０ｂに形成された複数の第２の電極パッド２２とは、基板２０を貫通する配線導体５０を介して電気的に接続されている。このような配線導体５０は、第１の電極２１と第２の電極２２とを短い距離で接続することができるため、配線基板１の電気的特性を向上することができる。   The wiring substrate 1 of the present embodiment is different from the wiring substrate of the first embodiment shown in FIG. 1 in that the substrate 20 has a single layer structure. In FIG. 2, the substrate 20 is made of resin, and a plurality of first electrode pads 21 formed on the first surface 20a of the substrate 20 and a plurality of second electrode pads 22 formed on the second surface 20b. Is electrically connected through a wiring conductor 50 penetrating the substrate 20. Since such a wiring conductor 50 can connect the first electrode 21 and the second electrode 22 at a short distance, the electrical characteristics of the wiring board 1 can be improved.

すなわち、本実施の形態の配線基板１は、基板２０の内部に形成された配線導体５０が、基板２０の内部を引き回される距離を短くすることができるため、配線導体５０の抵抗を低減することができる。   That is, the wiring substrate 1 of the present embodiment can reduce the distance that the wiring conductor 50 formed inside the substrate 20 is routed around the inside of the substrate 20, thereby reducing the resistance of the wiring conductor 50. can do.

図２において、拡大図で示すように、複数の配線導体５０は、ワイヤ５０ａと、ワイヤ５０ａを被覆する絶縁材料５０ｂとからなる。このような構造により、配線基板１の電気的特性を向上することができる。例えば、第１の絶縁層３上に搭載される半導体素子のファインピッチ化に対応して、配線基板１に形成された第１および第２の複数の電極２１，２２が多数形成される場合に、仮に、基板２０の内部において複数の配線導体５０同士が接触したとしても、ショートなどの不具合が生じ難い。   In FIG. 2, as shown in an enlarged view, the plurality of wiring conductors 50 include a wire 50a and an insulating material 50b that covers the wire 50a. With such a structure, the electrical characteristics of the wiring board 1 can be improved. For example, when a large number of first and second electrodes 21 and 22 formed on the wiring board 1 are formed corresponding to the fine pitch of the semiconductor element mounted on the first insulating layer 3. Even if a plurality of wiring conductors 50 are in contact with each other inside the substrate 20, problems such as a short circuit hardly occur.

このような本実施の形態に係る配線基板の製造方法について図３を用いて説明する。   A method for manufacturing the wiring board according to the present embodiment will be described with reference to FIG.

（イ）複数の第１の電極３１を有する第１の絶縁層３と、複数の第２の電極４２を有する第２の絶縁層４と、ホルダーＨに固定された配線導体５０とを準備する。（図３ａ）
（ロ）第１の絶縁層３の複数の第１の電極３１を、複数の配線導体５０の一端に接続し、第２の絶縁層４の複数の第２の電極４２を、複数の配線導体５０の他端に接続する。（図３ｂ〜図３ｅ）
（ハ）第１の絶縁層および第２の絶縁層と接続された配線導体５０を、型Ｍで固定し、型Ｍの中に、基板２０となる部材を注入する。（図３ｆ）
（ニ）型Ｍを取り除く。（図３ｇ）
以上（イ）〜（ニ）の工程を経ることにより、本実施形態の配線基板とすることができる。 (A) preparing a first insulating layer 3 having a plurality of first electrodes 31, a second insulating layer 4 having a plurality of second electrodes 42, and a wiring conductor 50 fixed to the holder H; . (Fig. 3a)
(B) The plurality of first electrodes 31 of the first insulating layer 3 are connected to one end of the plurality of wiring conductors 50, and the plurality of second electrodes 42 of the second insulating layer 4 are connected to the plurality of wiring conductors. 50 is connected to the other end. (FIGS. 3b to 3e)
(C) The wiring conductor 50 connected to the first insulating layer and the second insulating layer is fixed with the mold M, and a member to be the substrate 20 is injected into the mold M. (Fig. 3f)
(D) Remove the mold M. (Fig. 3g)
The wiring board of this embodiment can be obtained through the steps (a) to (d).

ここで、工程（ロ）において、複数の電極３１と複数の配線導体５０の一端とが接続される際、および複数の第２の電極４２と複数の配線導体５０の他端とが接続される際、複数の配線導体５０の各々のホルダーＨから突出した部分は、切断、研磨されることによりその接合端を接合に適した形とされる。（図３ｂ）また、このような切断、研磨の際に配線導体５０とホルダーＨとの位置ずれを低減するため、配線導体５０をホルダーＨに接着剤を介して固定しておくとよい。   Here, in the step (b), when the plurality of electrodes 31 and one end of the plurality of wiring conductors 50 are connected, and the plurality of second electrodes 42 and the other end of the plurality of wiring conductors 50 are connected. At this time, portions protruding from the respective holders H of the plurality of wiring conductors 50 are cut and polished, so that the joining ends thereof have a shape suitable for joining. (FIG. 3b) Further, in order to reduce misalignment between the wiring conductor 50 and the holder H during such cutting and polishing, the wiring conductor 50 may be fixed to the holder H with an adhesive.

また、図３に示す工程（ロ）において、複数の第１の電極３１および複数の配線導体５０の一端の接続と、複数の第２の電極４２および複数の配線導体５０の他端の接続とは、半田３５、４５を介して行われる。（図３ｃ、図３ｅ）
工程（ハ）において、基板２０となる部材の注入は、図３（ｆ）に矢印で示すように、型Ｍの開口側から行う。このような部材として、樹脂を用いることにより、弾性に優れた配線基板１とすることができる。 Further, in the step (b) shown in FIG. 3, the connection of one end of the plurality of first electrodes 31 and the plurality of wiring conductors 50 and the connection of the other ends of the plurality of second electrodes 42 and the plurality of wiring conductors 50 Is performed via the solders 35 and 45. (Fig. 3c, Fig. 3e)
In the step (c), the member to be the substrate 20 is injected from the opening side of the mold M as shown by an arrow in FIG. By using a resin as such a member, the wiring board 1 having excellent elasticity can be obtained.

（第３の実施の形態）図４を用いて本発明の第３の実施の形態に係る配線基板について説明する。図４（ａ）は、本発明の第３の実施の形態に係る配線基板１の構成を示す断面図である。図４（ｂ）は、図４（ａ）の配線基板１の第１の絶縁層３を取り除いた斜視図である。   (Third Embodiment) A wiring board according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4A is a cross-sectional view showing the configuration of the wiring board 1 according to the third embodiment of the present invention. FIG. 4B is a perspective view in which the first insulating layer 3 of the wiring board 1 of FIG.

本実施の形態の配線基板１は、第１の面２００ａおよび第２の面２００ｂを有し、貫通孔Ｓを有する基板２００と、第１の熱膨張係数αを有するとともに、基板２００の第１の面２００ａに接合された第１の絶縁層３と、第１の熱膨張係数αより大きい第２の熱膨張係数βを有するとともに、基板２００の第２の面２００ｂに接合された第２の絶縁層４とを有する。   Wiring substrate 1 of the present embodiment has first surface 200a and second surface 200b, substrate 200 having through-hole S, first thermal expansion coefficient α, and first substrate 200. A first insulating layer 3 bonded to the second surface 200a, a second thermal expansion coefficient β greater than the first thermal expansion coefficient α, and a second bonded to the second surface 200b of the substrate 200. And an insulating layer 4.

本実施の形態において、第１の絶縁層３は、複数の第１の電極パッド２１が形成された下面（図４ａにおいて、基板２００の上面２００ａと接合される面）を有している。また、第２の絶縁層４は、複数の第２の電極パッド２２が形成された上面を有している。本実施の形態において、複数の第１の電極パッド２１と複数の第２の電極パッド２２とは、基板２００の貫通孔Ｓ内に配置された複数の配線導体５０を介して、電気的に接続されている。本実施形態の配線基板１において、複数の配線導体５０が第１の電極２１と第２の電極２２との間を短い距離で接続することができるため、配線基板１の電気的特性を向上することができる。   In the present embodiment, the first insulating layer 3 has a lower surface (a surface bonded to the upper surface 200a of the substrate 200 in FIG. 4A) on which the plurality of first electrode pads 21 are formed. The second insulating layer 4 has an upper surface on which a plurality of second electrode pads 22 are formed. In the present embodiment, the plurality of first electrode pads 21 and the plurality of second electrode pads 22 are electrically connected via the plurality of wiring conductors 50 disposed in the through holes S of the substrate 200. Has been. In the wiring board 1 of the present embodiment, the plurality of wiring conductors 50 can connect the first electrode 21 and the second electrode 22 with a short distance, so that the electrical characteristics of the wiring board 1 are improved. be able to.

また、本実施の形態において、貫通孔Ｓ内を真空とすることで、第１の絶縁層３、基板２００および第２の絶縁層４との接合信頼性を向上することができる。   Moreover, in this Embodiment, the inside of the through-hole S is made into a vacuum, and the joining reliability with the 1st insulating layer 3, the board | substrate 200, and the 2nd insulating layer 4 can be improved.

（第４の実施の形態）図５を用いて本発明の第４の実施の形態に係る配線基板について説明する。図５は、本発明の第４の実施の形態に係る配線基板１の構成を示す断面図である。 (Fourth Embodiment) A wiring board according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of the wiring board 1 according to the fourth embodiment of the present invention.

本実施の形態の配線基板１は、複数の絶縁層からなる基板５００を有している。図５において、複数の絶縁層は、基板５００の第１の面５００ａ側から第２の面５００ｂ側に向かって第１の絶縁層５００ｌ、第２の絶縁層５００ｍ、第３の絶縁層５００ｎと順に配置されており、第１の絶縁層３は、第１の絶縁層５００ｌ上に接合される。また、第２の絶縁層４は、第３の絶縁層５００ｎ上に接合される。   The wiring board 1 of the present embodiment has a substrate 500 made of a plurality of insulating layers. In FIG. 5, the plurality of insulating layers include a first insulating layer 500l, a second insulating layer 500m, and a third insulating layer 500n from the first surface 500a side to the second surface 500b side of the substrate 500. Arranged sequentially, the first insulating layer 3 is bonded onto the first insulating layer 500l. The second insulating layer 4 is bonded onto the third insulating layer 500n.

本実施の形態の基板５００は、第１の面５００ａから第２の面５００ｂに向かうに伴って、熱膨張係数が漸次大きく形成されている。すなわち、図５において、第１の絶縁層５００ｌから第３の絶縁層５００ｎに向かって熱膨張係数を漸次大きくされている。このような構成により、配線基板１に熱が負荷された場合においても、配線基板１の全体において熱による歪みが低減されるため、配線基板１の電気的特性が向上される。   The substrate 500 of this embodiment has a coefficient of thermal expansion that gradually increases from the first surface 500a toward the second surface 500b. That is, in FIG. 5, the thermal expansion coefficient is gradually increased from the first insulating layer 500l to the third insulating layer 500n. With such a configuration, even when heat is applied to the wiring board 1, distortion due to heat is reduced in the entire wiring board 1, so that the electrical characteristics of the wiring board 1 are improved.

本実施形態の配線基板１の他の例としては、基板５００として、図２に示した単層構造の基板を用いる。このような単層構造の基板５００において、第１の面５００ａから第２の面５００ｂに向かうに従って、徐々に熱膨張率を大きく形成することにより、電気抵抗が低減され、信頼性が向上した配線基板１とすることができる。   As another example of the wiring substrate 1 of the present embodiment, the substrate 500 having the single-layer structure shown in FIG. In such a single-layer structure substrate 500, the wiring having improved electrical reliability and reliability by gradually increasing the coefficient of thermal expansion from the first surface 500a toward the second surface 500b. The substrate 1 can be obtained.

（第５の実施の形態）図６を用いて本発明の第５の実施の形態に係る配線基板について説明する。図６は、本発明の第５の実施の形態に係る配線基板１の構成を示す断面図である。   (Fifth Embodiment) A wiring board according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a configuration of a wiring board 1 according to the fifth embodiment of the present invention.

本実施の形態の配線基板１において、第１の絶縁層３は二つ部分３０Ａ、３０Ｂからなる。第１の部分３０Ａは、第１の絶縁層３の複数の第１の電極３１に接合される第１の領域Ａに配置されており、第４の熱膨張係数ζを有する。第２の部分３０Ｂは、第１の部分３０Ａを囲む第２の領域Ｂに形成されており、第４の熱膨張係数ζより小さい第５の熱膨張係数θを有する。このように、基板２の半導体素子などが搭載される第１の領域Ａに配置された第１の部分３０Ａの第４の熱膨張率ζを、その周囲に位置する第２の領域Ｂに配置された第２の部分３０Ｂの第５の熱膨張率θよりも大きくすることにより、第１の部分３０Ａと第２の部分３０Ｂとの間に生じるクラックを低減することができる。すなわち、第１の部分３０Ａの熱膨張を第２の部分３０Ｂで拘束することで、第１の絶縁層３における破断を低減することができる。   In the wiring board 1 of the present embodiment, the first insulating layer 3 is composed of two portions 30A and 30B. The first portion 30A is disposed in the first region A joined to the plurality of first electrodes 31 of the first insulating layer 3, and has a fourth thermal expansion coefficient ζ. The second portion 30B is formed in the second region B surrounding the first portion 30A, and has a fifth thermal expansion coefficient θ smaller than the fourth thermal expansion coefficient ζ. As described above, the fourth coefficient of thermal expansion ζ of the first portion 30A disposed in the first region A on which the semiconductor element or the like of the substrate 2 is mounted is disposed in the second region B positioned around the first portion 30A. By making it larger than the fifth coefficient of thermal expansion θ of the second part 30B, the cracks generated between the first part 30A and the second part 30B can be reduced. That is, by constraining the thermal expansion of the first portion 30A with the second portion 30B, it is possible to reduce breakage in the first insulating layer 3.

なお、第４の熱膨張係数ζ、第５の熱膨張係数θは、ＴＭＡ（ＴｈｅｒｍｏｍｅｃｈａｎｉｃａｌＡｎａｌｙｓｉｓ）装置を用いて求めることができる。   Note that the fourth thermal expansion coefficient ζ and the fifth thermal expansion coefficient θ can be obtained using a TMA (Thermal Mechanical Analysis) apparatus.

本実施の形態において、第２の部分３０Ｂをチッ化アルミにより形成することで、例えば、配線基板１に搭載された半導体素子の動作時の熱などを良好に放散することができる。   In the present embodiment, by forming the second portion 30B with aluminum nitride, for example, heat during operation of the semiconductor element mounted on the wiring substrate 1 can be dissipated well.

このような第１の絶縁層３を二つの部分３０Ａ、３０Ｂとから構成する構造の他の例を図７に示す。図７において、基板２０を単層構造とし、第１の面２０ａと第２の面２０ｂとを貫通する配線導体５０を介して、複数の第１の電極２１と複数の第２の電極２２とを電気的に接続する。このように図７に示す構造の場合、電気抵抗が低減され、信頼性が向上した配線基板１とすることができる。   FIG. 7 shows another example of a structure in which the first insulating layer 3 is composed of two portions 30A and 30B. In FIG. 7, the substrate 20 has a single-layer structure, and a plurality of first electrodes 21 and a plurality of second electrodes 22 are arranged via wiring conductors 50 penetrating the first surface 20 a and the second surface 20 b. Are electrically connected. As described above, in the case of the structure shown in FIG. 7, it is possible to obtain the wiring board 1 with reduced electrical resistance and improved reliability.

（ａ）は、本発明の第１実施形態による多層配線基板の平面図である。（ｂ）は、（ａ）のＸ−Ｘ’線における断面図である。(A) is a top view of the multilayer wiring board by 1st Embodiment of this invention. (B) is sectional drawing in the X-X 'line | wire of (a). 本発明の第２実施形態による配線基板の断面図と、配線導体５０の拡大図とを示している。Sectional drawing of the wiring board by 2nd Embodiment of this invention and the enlarged view of the wiring conductor 50 are shown. （ａ）〜（ｇ）本発明の第２実施形態による配線基板の製造工程の一例を示す図である。(A)-(g) It is a figure which shows an example of the manufacturing process of the wiring board by 2nd Embodiment of this invention. 本発明の第３実施形態による配線基板の断面図である。It is sectional drawing of the wiring board by 3rd Embodiment of this invention. 本発明の第４実施形態による配線基板の断面図である。It is sectional drawing of the wiring board by 4th Embodiment of this invention. （ａ）は、本発明の第５実施形態による多層配線基板の一例を示す平面図である。（ｂ）は、（ａ）のＹ−Ｙ’線における断面図である。(A) is a top view which shows an example of the multilayer wiring board by 5th Embodiment of this invention. (B) is sectional drawing in the Y-Y 'line | wire of (a). 本発明の第５実施形態による多層配線基板の他の例を示す平面図である。（ｂ）は、（ａ）のＺ−Ｚ’線における断面図である。It is a top view which shows the other example of the multilayer wiring board by 5th Embodiment of this invention. (B) is sectional drawing in the Z-Z 'line | wire of (a). （ａ）本発明の配線基板を用いた半導体装置の概略断面図である。（ｂ）本発明の配線基板を用いたプローブカード示す概略断面図である。(A) It is a schematic sectional drawing of the semiconductor device using the wiring board of this invention. (B) It is a schematic sectional drawing which shows the probe card using the wiring board of this invention.

符号の説明Explanation of symbols

１：配線基板
２：基板
３：第１の絶縁層
４：第２の絶縁層
５：配線導体 1: Wiring substrate 2: Substrate 3: First insulating layer 4: Second insulating layer 5: Wiring conductor

Claims (12)

第１の面および第２の面を有するとともに、内部に配線導体を有しており、樹脂からなる基板と、
該基板の前記第１の面に形成された第１の電極パッドと、
前記配線導体を介して、前記第１の電極パッドに電気的に接続されており、前記基板の前記第２の面に形成された第２の電極パッドと、
第１の熱膨張係数を有し、前記基板の前記第１の面に接合された第１の絶縁層と、
前記第１の熱膨張係数より大きい第２の熱膨張係数を有し、前記基板の前記第２の面に接合された第２の絶縁層と、を備えた配線基板。 A substrate having a first surface and a second surface and having a wiring conductor therein; and a resin substrate;
A first electrode pad formed on the first surface of the substrate;
A second electrode pad formed on the second surface of the substrate, electrically connected to the first electrode pad via the wiring conductor;
A first insulating layer having a first coefficient of thermal expansion and bonded to the first surface of the substrate;
And a second insulating layer having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion and bonded to the second surface of the substrate. 前記基板は、前記第１の熱膨張係数より大きく、前記第２の熱膨張係数より小さい第３の熱膨張係数を有することを特徴とする請求項１に記載の配線基板。 The wiring board according to claim 1, wherein the board has a third thermal expansion coefficient that is larger than the first thermal expansion coefficient and smaller than the second thermal expansion coefficient. 前記配線導体が前記第１の面および第２の面間を貫通する金属線からなることを特徴とする請求項１または２に記載の配線基板。 The wiring board according to claim 1, wherein the wiring conductor is made of a metal wire penetrating between the first surface and the second surface. 前記金属線が絶縁材料に被覆されていることを特徴とする請求項３に記載の配線基板。 The wiring board according to claim 3, wherein the metal wire is covered with an insulating material. 前記第１の絶縁層において、前記第１の電極パッドに接合された第１の領域の熱膨張係数が、前記第１の領域を囲む第２の領域の熱膨張係数よりも大きいことを特徴とする請求項１〜４のいずれかに記載の配線基板。 In the first insulating layer, a thermal expansion coefficient of a first region bonded to the first electrode pad is larger than a thermal expansion coefficient of a second region surrounding the first region. The wiring board according to claim 1. 請求項１〜５のいずれかに記載の配線基板と、
該配線基板の前記基板に形成された前記第１の電極パッドに電気的に接続されており、被検査対象に設けられた電極に接触する端子と、を備えたことを特徴とするプローブカード。 The wiring board according to any one of claims 1 to 5,
A probe card comprising: a terminal that is electrically connected to the first electrode pad formed on the substrate of the wiring substrate and contacts an electrode provided on an object to be inspected. 請求項１〜５のいずれかに記載の配線基板と、
該配線基板の前記基板に形成された前記第１の電極パッドに電気的に接続された半導体素子と、
前記配線基板の前記第２の層に形成された前記第２の電極に電気的に接続されたプリント配線基板と、を備えたことを特徴とする半導体装置。 The wiring board according to any one of claims 1 to 5,
A semiconductor element electrically connected to the first electrode pad formed on the substrate of the wiring substrate;
And a printed wiring board electrically connected to the second electrode formed in the second layer of the wiring board. 第１の面および第２の面を有し、貫通孔を有する基板と、
複数の第１の電極パッドが形成された下面を有しており、第１の熱膨張係数を有するとともに、前記基板の前記第１の面に接合された第１の絶縁層と、
複数の第２の電極パッドが形成された上面を有しており、前記第１の熱膨張係数より大きい第２の熱膨張係数を有するとともに、前記基板の前記第２の面に接合された第２の絶縁層と、
前記複数の第１の電極パッドと前記複数の第２の電極パッドとを電気的に接続しており、前記基板の前記貫通孔内に配置された複数の配線導体とを備えた配線基板。 A substrate having a first surface and a second surface and having a through hole;
A first insulating layer having a lower surface on which a plurality of first electrode pads are formed, having a first thermal expansion coefficient, and bonded to the first surface of the substrate;
A plurality of second electrode pads formed thereon, having a second thermal expansion coefficient greater than the first thermal expansion coefficient, and being bonded to the second surface of the substrate; Two insulating layers;
A wiring board comprising a plurality of wiring conductors that are electrically connected to the plurality of first electrode pads and the plurality of second electrode pads and are disposed in the through holes of the board. 前記基板の前記貫通孔内が真空とされていることを特徴とする請求項８に記載の配線基板。 The wiring substrate according to claim 8, wherein the inside of the through hole of the substrate is evacuated. 前記第１の絶縁層において、前記第１の電極パッドが形成された第１の領域の熱膨張係数が、前記第１の領域を囲む第２の領域の熱膨張係数よりも大きいことを特徴とする請求項８または９に記載の配線基板。 In the first insulating layer, a thermal expansion coefficient of a first region where the first electrode pad is formed is larger than a thermal expansion coefficient of a second region surrounding the first region. The wiring board according to claim 8 or 9. 請求項８〜１０のいずれかに記載の配線基板と、
該配線基板の前記第１の層に形成された前記第１の電極パッドに電気的に接続されており、被検査対象に設けられた電極に接触する端子と、を備えたことを特徴とするプローブカード。 A wiring board according to any one of claims 8 to 10,
And a terminal that is electrically connected to the first electrode pad formed on the first layer of the wiring board and contacts an electrode provided on the object to be inspected. Probe card. 請求項８〜１０のいずれかに記載の配線基板と、
該配線基板の前記第１の層に形成された前記第１の電極パッドに電気的に接続された半導体素子と、
前記配線基板の前記第２の層が有する前記第２の電極に電気的に接続されたプリント配線基板と、を備えたことを特徴とする半導体装置。 A wiring board according to any one of claims 8 to 10,
A semiconductor element electrically connected to the first electrode pad formed in the first layer of the wiring board;
And a printed wiring board electrically connected to the second electrode of the second layer of the wiring board.
JP2006320779A 2006-11-28 2006-11-28 Wiring board, semiconductor device using the same and probe card Pending JP2008135574A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010098315A1 (en) * 2009-02-25 2010-09-02 京セラ株式会社 Probe card substrate, probe card laminated body, and probe card equipped with said probe card laminated body and probe
WO2010150659A1 (en) * 2009-06-25 2010-12-29 京セラ株式会社 Probe card, probe card laminated body, and probe card using the probe card laminated body
CN113196879A (en) * 2018-12-26 2021-07-30 京瓷株式会社 Wiring substrate, light-emitting device using the same, and display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010098315A1 (en) * 2009-02-25 2010-09-02 京セラ株式会社 Probe card substrate, probe card laminated body, and probe card equipped with said probe card laminated body and probe
JP2010197193A (en) * 2009-02-25 2010-09-09 Kyocera Corp Substrate for probe card, laminate for probe card, and probe card using the laminate for probe card
WO2010150659A1 (en) * 2009-06-25 2010-12-29 京セラ株式会社 Probe card, probe card laminated body, and probe card using the probe card laminated body
JP2011007597A (en) * 2009-06-25 2011-01-13 Kyocera Corp Board for probe card constituting probe card, laminate for probe card, and probe card using laminate for probe card
CN113196879A (en) * 2018-12-26 2021-07-30 京瓷株式会社 Wiring substrate, light-emitting device using the same, and display device
CN113196879B (en) * 2018-12-26 2024-04-23 京瓷株式会社 Wiring substrate, light emitting device using the same, and display device

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