JP2008124422A - ウエハレベルパッケージ - Google Patents
ウエハレベルパッケージ Download PDFInfo
- Publication number
- JP2008124422A JP2008124422A JP2007127311A JP2007127311A JP2008124422A JP 2008124422 A JP2008124422 A JP 2008124422A JP 2007127311 A JP2007127311 A JP 2007127311A JP 2007127311 A JP2007127311 A JP 2007127311A JP 2008124422 A JP2008124422 A JP 2008124422A
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- cap
- wafer level
- level package
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Micromachines (AREA)
Abstract
【解決手段】ウエハレベルパッケージ100は、前面に複数のボンディングパッド112を備えた半導体チップ110と、半導体チップ110の上にボンディングパッド112を露出させるように形成された下部絶縁層120と、下部絶縁層120の上に一端がボンディングパッド112と連結されるように形成された再配線126と、再配線126を含んだ下部絶縁層120の上に再配線126の一部分を露出させるように形成された上部絶縁層128と、露出した再配線126部分に取り付けられたソルダボール130と、半導体チップ126の後面を覆いかぶせるキャップ140とを含む。
【選択図】図1
Description
キャップと半導体チップは、熱伝導性物質からなる接着剤により相互結合される。
110 半導体チップ
112 ボンディングパッド
114 保護膜
120 下部絶縁層
122 シード金属膜
124 配線用金属膜
126 再配線
128 上部絶縁層
130 ソルダボール
140、440 キャップ
150 接着剤
H 溝
Claims (10)
- 前面に複数のボンディングパッドを備えた半導体チップと、
前記半導体チップの上にボンディングパッドを露出させるように形成された下部絶縁層と、
前記下部絶縁層の上に一端がボンディングパッドと連結されるように形成された再配線と、
前記再配線を含んだ下部絶縁層の上に前記再配線の一部分を露出させるように形成された上部絶縁層と、
前記露出した再配線部分に取り付けられたソルダボールと、
前記半導体チップの後面を覆いかぶせるキャップと
を含むことを特徴とするウエハレベルパッケージ。 - 前記キャップは、半導体チップと接触する面に前記半導体チップが挿入固定される溝が備えられることを特徴とする請求項1記載のウエハレベルパッケージ。
- 前記キャップの溝は、半導体チップと類似な大きさを有することを特徴とする請求項1記載のウエハレベルパッケージ。
- 前記キャップは、熱伝導性物質からなることを特徴とする請求項1記載のウエハレベルパッケージ。
- 前記キャップは、金属からなることを特徴とする請求項4記載のウエハレベルパッケージ。
- 前記キャップと半導体チップは、接着剤により相互結合されることを特徴とする請求項1記載のウエハレベルパッケージ。
- 前記接着剤は、熱伝導性物質からなることを特徴とする請求項5記載のウエハレベルパッケージ。
- 前記キャップと半導体チップは、機械的結合方式により相互結合されることを特徴とする請求項1記載のウエハレベルパッケージ。
- 前記キャップと半導体チップは、スライド方式により相互結合されることを特徴とする請求項8記載のウエハレベルパッケージ。
- 前記キャップは、一面に半導体チップの大きさに対応する大きさを有し、かつ一側面が開放された溝を具備し、前記半導体チップは、前記キャップの開放された一側面からスライディングされて前記キャップの溝内に固定配置されることを特徴とする請求項9記載のウエハレベルパッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2006-0110145 | 2006-11-08 | ||
KR1020060110145A KR100818101B1 (ko) | 2006-11-08 | 2006-11-08 | 웨이퍼 레벨 칩 사이즈 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008124422A true JP2008124422A (ja) | 2008-05-29 |
JP5140314B2 JP5140314B2 (ja) | 2013-02-06 |
Family
ID=39405234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007127311A Expired - Fee Related JP5140314B2 (ja) | 2006-11-08 | 2007-05-11 | ウエハレベルパッケージ |
Country Status (5)
Country | Link |
---|---|
US (1) | US7629682B2 (ja) |
JP (1) | JP5140314B2 (ja) |
KR (1) | KR100818101B1 (ja) |
CN (1) | CN100546020C (ja) |
TW (1) | TWI329353B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101099583B1 (ko) | 2010-04-16 | 2011-12-28 | 앰코 테크놀로지 코리아 주식회사 | 웨이퍼 레벨의 칩 적층형 패키지 및 그 제조 방법 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164179B2 (en) * | 2008-12-16 | 2012-04-24 | STMicroelectronics Asia Pacific PTE Ltd-Singapore | Chip scale package structure with can attachment |
CN104347542A (zh) * | 2014-09-26 | 2015-02-11 | 上海朕芯微电子科技有限公司 | 五面包封的csp结构及制造工艺 |
DE102018204764A1 (de) * | 2018-03-28 | 2019-10-02 | Infineon Technologies Ag | Halbleiter- packagesystem |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110862A (ja) * | 2000-09-29 | 2002-04-12 | Oki Electric Ind Co Ltd | 半導体装置とその製造方法 |
JP2004266175A (ja) * | 2003-03-04 | 2004-09-24 | Life:Kk | 複数電極接着用の電子部品とその実装方法 |
JP2004281897A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3972062A (en) * | 1973-10-04 | 1976-07-27 | Motorola, Inc. | Mounting assemblies for a plurality of transistor integrated circuit chips |
US4323914A (en) * | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
CA2089435C (en) * | 1992-02-14 | 1997-12-09 | Kenzi Kobayashi | Semiconductor device |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
KR100269540B1 (ko) | 1998-08-28 | 2000-10-16 | 윤종용 | 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법 |
US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US6154366A (en) * | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US7242088B2 (en) | 2000-12-29 | 2007-07-10 | Intel Corporation | IC package pressure release apparatus and method |
KR100632476B1 (ko) * | 2004-01-13 | 2006-10-09 | 삼성전자주식회사 | 멀티칩 패키지 및 이에 사용되는 반도체칩 |
TWI256095B (en) * | 2004-03-11 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Wafer level semiconductor package with build-up layer and process for fabricating the same |
KR100630698B1 (ko) * | 2004-08-17 | 2006-10-02 | 삼성전자주식회사 | 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법 |
KR20060058954A (ko) * | 2004-11-26 | 2006-06-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
US7476980B2 (en) * | 2006-06-27 | 2009-01-13 | Infineon Technologies Ag | Die configurations and methods of manufacture |
-
2006
- 2006-11-08 KR KR1020060110145A patent/KR100818101B1/ko not_active IP Right Cessation
- 2006-12-29 US US11/647,622 patent/US7629682B2/en not_active Expired - Fee Related
-
2007
- 2007-02-26 TW TW096106561A patent/TWI329353B/zh not_active IP Right Cessation
- 2007-04-13 CN CNB2007100961013A patent/CN100546020C/zh not_active Expired - Fee Related
- 2007-05-11 JP JP2007127311A patent/JP5140314B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110862A (ja) * | 2000-09-29 | 2002-04-12 | Oki Electric Ind Co Ltd | 半導体装置とその製造方法 |
JP2004266175A (ja) * | 2003-03-04 | 2004-09-24 | Life:Kk | 複数電極接着用の電子部品とその実装方法 |
JP2004281897A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101099583B1 (ko) | 2010-04-16 | 2011-12-28 | 앰코 테크놀로지 코리아 주식회사 | 웨이퍼 레벨의 칩 적층형 패키지 및 그 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR100818101B1 (ko) | 2008-03-31 |
US20080122062A1 (en) | 2008-05-29 |
TW200822309A (en) | 2008-05-16 |
US7629682B2 (en) | 2009-12-08 |
TWI329353B (en) | 2010-08-21 |
CN100546020C (zh) | 2009-09-30 |
CN101179056A (zh) | 2008-05-14 |
JP5140314B2 (ja) | 2013-02-06 |
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