JP2008118049A - GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - Google Patents
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本発明は、量子井戸構造の活性層（発光層）にＩｎを含むＧａＮ系半導体発光素子に関する。 The present invention relates to a GaN-based semiconductor light-emitting device containing In in an active layer (light-emitting layer) having a quantum well structure.
半導体レーザやＬＥＤ等の半導体発光素子の材料には、様々なものが使用されているが、その中で、活性層（発光層）に、Ｉｎ（インジウム）を用いた半導体発光素子が開発されている。特に、ＧａＮ系半導体による青色発光素子では、活性層にＩｎＧａＮが使用される。 Various materials are used for semiconductor light emitting devices such as semiconductor lasers and LEDs. Among them, semiconductor light emitting devices using In (indium) as an active layer (light emitting layer) have been developed. Yes. In particular, in a blue light emitting element using a GaN-based semiconductor, InGaN is used for the active layer.
上記、半導体発光素子の結晶成長方法としては、ハイドライド気相成長方法（ＨＶＰＥ）や有機金属化学気相成長方法（ＭＯＣＶＤ）が用いられる。これらの方法を用いて結晶成長を行う場合には、通常、成長用基板上にｎ型コンタクト層やｎ型クラッド層等を積層した後、発光層となる活性層を成長させ、その後ｐ型クラッド層やｐ型コンタクト層等のｐ型層を積層し、最後に電極を形成している。 As the crystal growth method of the semiconductor light emitting device, a hydride vapor phase growth method (HVPE) or a metal organic chemical vapor deposition method (MOCVD) is used. When crystal growth is performed using these methods, an n-type contact layer, an n-type cladding layer, and the like are usually stacked on a growth substrate, and then an active layer to be a light-emitting layer is grown, and then a p-type cladding. A p-type layer such as a p-type contact layer or a p-type contact layer is laminated, and finally an electrode is formed.
ＧａＮ系半導体発光素子では、例えば、クラッド層にＡｌＧａＮやＧａＮ等が、コンタクト層にはＧａＮ等が用いられる。ＧａＮ系半導体発光素子を作製する場合は、成長用基板上にｎ型ＧａＮ系半導体層を積層し、次に活性層を結晶成長させるのであるが、活性層にはＩｎＧａＮが含まれており、この中のＩｎの蒸気圧が高いために、活性層の成長温度は、６５０〜８００℃程度に下げる必要がある。 In the GaN-based semiconductor light emitting device, for example, AlGaN or GaN is used for the cladding layer, and GaN or the like is used for the contact layer. When manufacturing a GaN-based semiconductor light-emitting device, an n-type GaN-based semiconductor layer is stacked on a growth substrate, and then an active layer is crystal-grown, but the active layer contains InGaN. Since the vapor pressure of In is high, the growth temperature of the active layer needs to be lowered to about 650 to 800 ° C.
活性層成長後に、ｐ型ＧａＮ系半導体層を成膜するのであるが、ｐ型ＧａＮやｐ型ＡｌＧａＮの結晶品質を高めるために、活性層の成長温度よりも２００〜３００℃高い温度となる１０００℃付近の成長温度でエピタキシャル成長させており、成長時間は通常１５〜６０分程かかる。
しかし、上記従来のように、活性層を成長した後、その上にｐ型層を成膜する場合、ｐ型層の成長温度が高いために、既に成膜されている活性層が熱のダメージを受け、発光特性が著しく悪化することが問題となっていた。 However, when the p-type layer is formed on the active layer after the active layer is grown as in the conventional case, the active layer already formed is damaged by heat because the growth temperature of the p-type layer is high. As a result, there has been a problem that the light emission characteristics are remarkably deteriorated.
特に、４５０ｎｍ以上の長波長のＧａＮ系半導体発光素子を作製する場合、活性層における井戸層のＩｎ組成比率が１０％を越える程高くなるが、Ｉｎ組成比率が高くなるほど、高温状態に置かれた場合Ｉｎが昇華して壊れやすくなり、発光効率が極端に落ちる。熱のダメージを受け続けると、Ｉｎが分離してウエハが黒色化する場合も発生する。このように、井戸層のＩｎ組成比率が大きい場合には、ｐ型層の成長温度が高いことにより、活性層が劣化して発光特性が著しく悪くなる。 In particular, when a GaN-based semiconductor light-emitting device having a long wavelength of 450 nm or more is manufactured, the In composition ratio of the well layer in the active layer increases as it exceeds 10%, but the higher the In composition ratio, the higher the temperature of the well layer. In the case of In sublimation, it becomes fragile and the luminous efficiency is extremely lowered. If the thermal damage continues, the In may be separated and the wafer may be blackened. As described above, when the In composition ratio of the well layer is large, the growth temperature of the p-type layer is high, so that the active layer is deteriorated and the light emission characteristics are remarkably deteriorated.
また、長波長化のためには活性層のＩｎ組成比率を高くしなければならないが、活性層へのＩｎの取り込みを多くするためには、成長温度をより下げていくことが必要となる。しかし、成長温度を下げて、活性層を一定の温度で作製すると、順方向電圧の増大や低電流域（μＡ以下）でのリークの増大、逆方向電流の増大等、電気特性が悪化するという問題が発生する。したがって、Ｉｎの取り込みを高くしつつ、電気特性が良好なＧａＮ系半導体素子を得ることができなかった。 Further, in order to increase the wavelength, the In composition ratio of the active layer must be increased. However, in order to increase the incorporation of In into the active layer, it is necessary to lower the growth temperature. However, when the growth temperature is lowered and the active layer is manufactured at a constant temperature, the electrical characteristics deteriorate, such as an increase in forward voltage, an increase in leakage in a low current region (μA or less), and an increase in reverse current. A problem occurs. Therefore, it has not been possible to obtain a GaN-based semiconductor element with good electrical characteristics while increasing In incorporation.
ところで、特許文献１には、発光効率に優れたＧａＮ系半導体素子の構成について記載されているが、波長３８０ｎｍ以下の発光素子に関するものであり、活性層のＩｎ組成が非常に小さくなった場合に、Ｉｎ組成揺らぎが減ることによる発光効率を改善しようとするものであって、Ｉｎ組成を大きくして長波長の発光を得る場合に、エピタキシャル成長過程で発生する熱による活性層の劣化を防ぐとともに、Ｉｎの取り込みを高くしつつ、電気特性を向上させるものではなく、上記問題を解決する手段は従来提案されていなかった。 By the way, Patent Document 1 describes a configuration of a GaN-based semiconductor element having excellent luminous efficiency, but relates to a light-emitting element having a wavelength of 380 nm or less, and when the In composition of the active layer becomes very small. In order to improve the light emission efficiency by reducing the fluctuation of the In composition, when obtaining a long wavelength light emission by increasing the In composition, the deterioration of the active layer due to the heat generated during the epitaxial growth process is prevented. It has not been proposed in the past to improve the electrical characteristics while increasing the incorporation of In and to solve the above problems.
本発明は、上述した課題を解決するために創案されたものであり、Ｉｎを含む量子井戸構造の活性層を有し、活性層よりも後に成長させる半導体層の成長温度による熱のダメージを抑制することができるとともに、Ｉｎの取り込みを高くしつつ、発光特性や電気特性を向上させたＧａＮ系半導体発光素子を提供することを目的としている。 The present invention was devised to solve the above-mentioned problems, and has an active layer having a quantum well structure containing In, and suppresses thermal damage due to the growth temperature of a semiconductor layer grown after the active layer. An object of the present invention is to provide a GaN-based semiconductor light-emitting device that can improve the light emission characteristics and electrical characteristics while increasing the incorporation of In.
上記目的を達成するために、請求項１記載の発明は、量子井戸構造を有する活性層を備えたＧａＮ系半導体発光素子であって、前記活性層はＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）井戸層とＡｌＸ２ＩｎＹ２ＧａＺ２Ｎバリア層（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１、Ｙ１＞Ｙ２）とで構成されており、前記井戸層の成長温度とバリア層の成長温度とは異なることを特徴とするＧａＮ系半導体発光素子である。 In order to achieve the above object, the invention described in claim 1 is a GaN-based semiconductor light-emitting device including an active layer having a quantum well structure, wherein the active layer is Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1). , 0 <X1 <1, 0 <Y1 <1) well layer and Al X2 In Y2 Ga Z2 N barrier layer (X2 + Y2 + Z2 = 1, 0 ≦ X2 <1, 0 ≦ Y2 <1, Y1> Y2) In the GaN-based semiconductor light emitting device, the growth temperature of the well layer and the growth temperature of the barrier layer are different.
また、請求項２記載の発明は、前記井戸層のＩｎ組成が、１０％よりも大きいことを特徴とする請求項１記載のＧａＮ系半導体発光素子である。 The invention according to claim 2 is the GaN-based semiconductor light-emitting element according to claim 1, wherein the In composition of the well layer is larger than 10%.
また、請求項３記載の発明は、前記井戸層のＡｌ組成が、５％以下であることを特徴とする請求項１又は請求項２のいずれか１項に記載のＧａＮ系半導体発光素子である。 The invention according to claim 3 is the GaN-based semiconductor light-emitting element according to claim 1, wherein the Al composition of the well layer is 5% or less. .
また、請求項４記載の発明は、前記井戸層のＡｌ組成が、１％以下であることを特徴とする請求項１又は請求項２のいずれか１項に記載のＧａＮ系半導体発光素子である。 The invention according to claim 4 is the GaN-based semiconductor light-emitting device according to claim 1, wherein the Al composition of the well layer is 1% or less. .
また、請求項５記載の発明は、少なくとも前記活性層の結晶成長表面がノンポーラ面又はセミポーラ面により形成されていることを特徴とする請求項１〜請求項４のいずれか１項に記載のＧａＮ系半導体発光素子である。 The invention according to claim 5 is characterized in that at least the crystal growth surface of the active layer is formed by a nonpolar surface or a semipolar surface, and the GaN according to any one of claims 1 to 4 This is a semiconductor light emitting device.
本発明によれば、少なくとも井戸層には、Ａｌを添加したＡｌＩｎＧａＮを用いているので耐熱性が向上し、井戸層の成長温度とバリア層の成長温度とを異なるように変化させているので、バリア層の最適温度で成長させることができ、結晶品質の優れたバリア層を形成できるため順方向電圧等の電気特性の悪化を防ぐことができる。 According to the present invention, since AlInGaN doped with Al is used for at least the well layer, the heat resistance is improved, and the growth temperature of the well layer and the growth temperature of the barrier layer are changed differently. Since the barrier layer can be grown at the optimum temperature and a barrier layer having excellent crystal quality can be formed, deterioration of electrical characteristics such as forward voltage can be prevented.
また、ｎ型ＧａＮ系半導体層からｐ型ＧａＮ系半導体層まで、成長表面がノンポーラ面又はセミポーラ面により形成されているので、ＧａＮのＧａ極性面やＮ（窒素）極性面で形成されている場合と比較して、ピエゾ電場により発生する電界の影響を小さくすることができる。 In addition, since the growth surface is formed by a nonpolar surface or a semipolar surface from the n-type GaN-based semiconductor layer to the p-type GaN-based semiconductor layer, the GaN Ga polar surface or N (nitrogen) polar surface is formed. As compared with the above, the influence of the electric field generated by the piezoelectric field can be reduced.
以下、図面を参照して本発明の一実施形態を説明する。図１は本発明のＧａＮ系半導体発光素子の断面図の一例を示す。ここで、ＧａＮ系半導体とは、窒素を含む六方晶化合物半導体の中でも良く知られたIII−Ｖ族窒化物半導体であり、４元混晶系のＡｌｘＧａｙＩｎｚＮ（ｘ＋ｙ＋ｚ＝１、０≦ｘ≦１、０≦ｙ≦１、０≦ｚ≦１）で表される。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of a cross-sectional view of a GaN-based semiconductor light emitting device of the present invention. Here, the GaN-based semiconductor is a group III-V nitride semiconductor well known among hexagonal compound semiconductors containing nitrogen, and is a quaternary mixed crystal Al x Ga y In z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1).
サファイア基板１の上に、ｎ型ＧａＮコンタクト層２、ｎ型のＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３、活性層４、ｐ型ＡｌＧａＮブロック層８、ｐ型ＧａＮコンタクト層５が順次積層されており、ｐ型ＧａＮコンタクト層５から一部領域がメサエッチングされて、ｎ型ＧａＮコンタクト層２が露出した面にｎ電極７が形成されている。また、ｐ型ＧａＮコンタクト層５の上にはｐ電極６が形成されている。 On the sapphire substrate 1, an n-type GaN contact layer 2, an n-type AlInGaN / AlGaN superlattice layer 3, an active layer 4, a p-type AlGaN block layer 8, and a p-type GaN contact layer 5 are sequentially stacked. A partial region is mesa-etched from the n-type GaN contact layer 5 to form an n-electrode 7 on the surface where the n-type GaN contact layer 2 is exposed. A p-electrode 6 is formed on the p-type GaN contact layer 5.
活性層４は、量子井戸構造（Quantum Well）を有する活性層であり、井戸層（ウェル層）を、井戸層よりもバンドギャップの大きな障壁層（バリア層）でサンドイッチ状に挟んだ構造となっている。この量子井戸構造は、１つではなく、多重化しても良く、この場合は、ＭＱＷ（Multi Quantum Well）、すなわち多重量子井戸構造となる。 The active layer 4 is an active layer having a quantum well structure, and has a structure in which a well layer (well layer) is sandwiched between barrier layers (barrier layers) having a larger band gap than the well layer. ing. The quantum well structure may be multiplexed instead of one. In this case, an MQW (Multi Quantum Well), that is, a multiple quantum well structure is formed.
ところで、ＧａＮ系半導体の中でＡｌＧａＮは熱に対する耐性が非常に優れていることは良く知られている。そこで、本発明では、活性層４全体にＡｌを添加して４元混晶系のＡｌＩｎＧａＮとし、井戸層をＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）、バリア層をＡｌＸ２ＩｎＹ２ＧａＺ２Ｎ（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１、Ｙ１＞Ｙ２）の多重量子井戸構造とした。 By the way, it is well known that AlGaN is extremely excellent in heat resistance among GaN-based semiconductors. Therefore, in the present invention, Al is added to the entire active layer 4 to form a quaternary mixed crystal AlInGaN, and the well layer is made of Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1, 0 <X1 <1, 0 <Y1 < 1) The barrier layer has a multiple quantum well structure of Al X2 In Y2 Ga Z2 N (X2 + Y2 + Z2 = 1, 0 ≦ X2 <1, 0 ≦ Y2 <1, Y1> Y2).
なお、井戸層のみにＡｌを添加する（上記Ｘ２＝０）ＡｌＩｎＧａＮ／ＩｎＧａＮ多重量子井戸構造や、バリア層をＧａＮで構成する（上記Ｘ２＝０、Ｙ２＝０）ＡｌＩｎＧａＮ／ＧａＮ多重量子井戸構造でも良い。活性層４では、上記Ｙ１を０＜Ｙ１＜１の範囲で変化させることにより、発光波長を紫色から赤色まで変化させることができるが、特に、発光波長が４５０ｎｍ以上の長波長のＧａＮ系半導体発光素子を対象とする場合、井戸層のＩｎ組成比率が１０％を越える活性層で構成する。 It should be noted that Al is added only to the well layer (X2 = 0) AlInGaN / InGaN multiple quantum well structure or the barrier layer is composed of GaN (X2 = 0, Y2 = 0) AlInGaN / GaN multiple quantum well structure. good. In the active layer 4, the emission wavelength can be changed from purple to red by changing the Y1 in the range of 0 <Y1 <1. In particular, the GaN-based semiconductor light emission having a long emission wavelength of 450 nm or more is possible. When an element is intended, it is composed of an active layer in which the In composition ratio of the well layer exceeds 10%.
活性層４の構造を詳細に示すのが、図２である。活性層４がＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３と接する側にバリア層４ａが配置され、その上に井戸層４ｂが積層されており、このバリア層４ａと井戸層４ｂとが交互に何周期か積層された後、最後のバリア層４ａが形成されており、この最後のバリア層４ａの上にｐ型ＧａＮコンタクト層５が積層される。 FIG. 2 shows the structure of the active layer 4 in detail. A barrier layer 4a is disposed on the side where the active layer 4 is in contact with the AlInGaN / AlGaN superlattice layer 3, and a well layer 4b is stacked thereon. The barrier layer 4a and the well layer 4b are alternately stacked for several cycles. After that, the last barrier layer 4a is formed, and the p-type GaN contact layer 5 is laminated on the last barrier layer 4a.
ここで、一例を示すと、バリア層４ａは、ノンドープ又はＳｉドーピング濃度が５×１０１６ｃｍ−３〜５×１０１８ｃｍ−３で、膜厚７０〜１６０ÅのＡｌ０．００５ＧａＮで構成される。一方、井戸層４ｂは、例えば、膜厚３０ÅのノンドープＡｌ０．００５ＩｎＧａＮで構成し、井戸層とバリア層とを交互に５周期程度積層する。また、井戸層のみにＡｌを添加してＡｌ０．００５ＩｎＧａＮ／ＧａＮとすることもできる。上記のように活性層４の井戸層、バリア層ともにＡｌを添加することで、熱のダメージに強い活性層を構成することができる。 Here, as an example, the barrier layer 4a is made of Al 0.005 GaN having a non-doped or Si doping concentration of 5 × 10 16 cm −3 to 5 × 10 18 cm −3 and a film thickness of 70 to 160 mm. The On the other hand, the well layer 4b is made of, for example, non-doped Al 0.005 InGaN with a thickness of 30 mm, and the well layers and the barrier layers are alternately stacked for about five periods. Alternatively, Al may be added only to the well layer to obtain Al 0.005 InGaN / GaN. By adding Al to both the well layer and the barrier layer of the active layer 4 as described above, an active layer resistant to heat damage can be formed.
また、バリア層４ａは、上記のようにＡｌＧａＮ又はＧａＮで形成するようにしても良いが、発光効率の向上のためには、ＡｌＩｎＧａＮ（上記Ｙ２≠０）とする方が望ましく、その場合は、バリア層４ａは井戸層４ｂよりも高いバンドギャップエネルギーを有する必要があり、通常、Ｙ１＞Ｙ２になるように、バリア層４ａのＩｎ組成比率は井戸層４ｂよりも小さくする。 In addition, the barrier layer 4a may be formed of AlGaN or GaN as described above. However, in order to improve the light emission efficiency, it is preferable to use AlInGaN (the above Y2 ≠ 0). The barrier layer 4a needs to have a higher band gap energy than the well layer 4b, and the In composition ratio of the barrier layer 4a is usually smaller than that of the well layer 4b so that Y1> Y2.
ＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３は、格子定数差の大きいＡｌＩｎＧａＮとＡｌＧａＮの応力を緩和し、活性層４のＡｌＩｎＧａＮを成長させやすくするものであり、例えば、Ｓｉドーピング濃度が１〜５×１０１８ｃｍ−３で膜厚１０ÅのＡｌ０．０１Ｉｎ０．０５ＧａＮと、同様のＳｉドーピング濃度で膜厚２０ÅのＧａＮとを交互に１０周期程度積層した構成が用いられる。 The AlInGaN / AlGaN superlattice layer 3 relieves stress of AlInGaN and AlGaN having a large difference in lattice constant and facilitates the growth of AlInGaN in the active layer 4. For example, the Si doping concentration is 1 to 5 × 10 18 cm. -3 and a structure in which Al 0.01 In 0.05 GaN with a thickness of 10 と and GaN with a thickness of 20 で with the same Si doping concentration are alternately stacked for about 10 cycles.
まず、図４を用いて、井戸層４ｂをＡｌＩｎＧａＮ、バリア層４ａをＡｌＧａＮとした場合の活性層４の具体的形成方法を示す。キャリアガスの窒素（Ｎ２）を流し、Ｇａ原子の原料ガスであるトリエチルガリウム（ＴＥＧ）又はトリメチルガリウム（ＴＭＧ）、窒素原子の原料ガスであるアンモニア（ＮＨ３）、Ａｌ原子の材料ガスとしてトリメチルアルミニウム（ＴＭＡ）を供給する。なお、ｎ型にする場合にはドーパントガスとしてのシラン（ＳｉＨ４）も供給する。 First, a specific method of forming the active layer 4 when the well layer 4b is made of AlInGaN and the barrier layer 4a is made of AlGaN will be described with reference to FIG. Nitrogen (N 2 ) as a carrier gas is flown, triethyl gallium (TEG) or trimethyl gallium (TMG) as a source gas for Ga atoms, ammonia (NH 3 ) as a source gas for nitrogen atoms, and trimethyl as a source gas for Al atoms Supply aluminum (TMA). In the case of n-type, silane (SiH 4 ) as a dopant gas is also supplied.
図４からもわかるように、ＴＥＧ、ＴＭＡ、及び図示はしていないがＮＨ３については活性層４の作製中は、連続して流すようにし、井戸層４ｂを作製するときのみ、Ｉｎ原子の原料ガスであるトリメチルインジウム（ＴＭＩ）を図のように時間Ｌの間だけ流すようにする。そして、ＴＭＩを供給する期間と供給を停止する期間を交互に設定する。このようにして、時間Ｌに対応する期間では井戸層４ｂが、それ以外のＴＭＩの供給が停止されている期間ではバリア層４ａが作製され、バリア層４ａと井戸層４ｂとが交互に形成される。また、バリア層４ａにＡｌを添加せずに、ＧａＮとする場合には、図４のＴＭＡを連続して供給せずに、ＴＭＩの供給のオン−オフに同期させて、断続的（間欠的）に流すようにすれば良い。 As can be seen from FIG. 4, although TEG, TMA, and NH 3 are not shown, NH 3 is allowed to flow continuously during the production of the active layer 4 and only when the well layer 4b is produced. The source gas, trimethylindium (TMI), is allowed to flow for a time L as shown. Then, the period for supplying the TMI and the period for stopping the supply are alternately set. In this manner, the well layer 4b is produced in the period corresponding to the time L, and the barrier layer 4a is produced in the other periods in which the supply of TMI is stopped. The barrier layers 4a and the well layers 4b are alternately formed. The Further, in the case of using GaN without adding Al to the barrier layer 4a, the TMA of FIG. 4 is not continuously supplied, but is intermittently (intermittently) synchronized with the on / off of the TMI supply. ).
図４の方法で、井戸層４ｂとバリア層４ａとを同じ温度（例えば７３０℃）で成長させた場合の活性層の耐熱性の向上を示すデータが図５である。図５は、図１のＧａＮ系半導体発光素子において、サファイア基板１上にＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３を形成した後、以上のようにして、活性層４としてＡｌＩｎＧａＮ井戸層とＡｌＧａＮバリア層とを５周期形成した後、アニール処理を行い、そのアニール温度（熱処理温度）とＡｌの組成比率によって活性層４の表面が黒色化しているかどうかを検査した。Ａｌの組成比率は、ＡｌＩｎＧａＮ井戸層とＡｌＧａＮバリア層とで共通である。 FIG. 5 shows data showing an improvement in heat resistance of the active layer when the well layer 4b and the barrier layer 4a are grown at the same temperature (for example, 730 ° C.) by the method of FIG. FIG. 5 shows the GaN-based semiconductor light emitting device of FIG. 1, after the AlInGaN / AlGaN superlattice layer 3 is formed on the sapphire substrate 1, the AlInGaN well layer and the AlGaN barrier layer are formed as the active layer 4 as described above. After forming 5 cycles, annealing treatment was performed, and it was inspected whether the surface of the active layer 4 was blackened by the annealing temperature (heat treatment temperature) and the Al composition ratio. The Al composition ratio is common to the AlInGaN well layer and the AlGaN barrier layer.
また、図５は、実験データの一部を示すもので、活性層４表面の画像データを縦軸Ａｌ組成（Ａｌ／Ｇａ供給比）、横軸熱処理温度（アニール温度）の座標上に並べたものである。活性層４には、バリア層（障壁層）としてアンドープＧａＮを交互に積層したものを用い、ＡｌＩｎＧａＮ井戸層のＩｎ組成比率は２０％程度とし、各温度毎の熱処理は窒素雰囲気中で行い、熱処理時間は３０分とした。 FIG. 5 shows a part of the experimental data. The image data on the surface of the active layer 4 is arranged on the coordinates of the vertical axis Al composition (Al / Ga supply ratio) and the horizontal axis heat treatment temperature (annealing temperature). Is. The active layer 4 is formed by alternately laminating undoped GaN as barrier layers (barrier layers), the In composition ratio of the AlInGaN well layer is about 20%, and heat treatment at each temperature is performed in a nitrogen atmosphere. The time was 30 minutes.
また、活性層にＡｌを添加したものと比較するために、活性層４を従来のＩｎＧａＮ／ＧａＮ活性層とし、ＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３をＩｎＧａＮ／ＧａＮ超格子層とした構成で同様の条件で熱処理を行った。なお、ＩｎＧａＮ井戸層のＩｎ組成比率は上記同様２０％程度とした。図５中の破線は、ウエハの黒色化が始まる境界線を示す。 Further, in order to compare with the case where Al is added to the active layer, the active layer 4 is a conventional InGaN / GaN active layer, and the AlInGaN / AlGaN superlattice layer 3 is an InGaN / GaN superlattice layer. A heat treatment was performed. The In composition ratio of the InGaN well layer was set to about 20% as described above. A broken line in FIG. 5 indicates a boundary line where the blackening of the wafer starts.
図５からもわかるように、従来のＩｎＧａＮ／ＧａＮ活性層では、９５０℃でウエハの黒色化が見られる。しかし、ＡｌＩｎＧａＮ／ＡｌＧａＮ活性層で、Ａｌ組成が０．５％の場合、１０００℃の熱処理で黒色化が始まっている。さらに、Ａｌ組成を増加させてＡｌ組成が１．０％の場合には１０５０℃の熱処理温度にならないと、黒色化せず、１０００℃でも活性層に問題は発生しない。Ａｌ組成を２．０％まで増加させた場合は、Ａｌ組成１．０％の場合と状態は変わらず、耐熱性はたいして向上しない。 As can be seen from FIG. 5, in the conventional InGaN / GaN active layer, the wafer is blackened at 950.degree. However, when the AlInGaN / AlGaN active layer has an Al composition of 0.5%, blackening has started by heat treatment at 1000 ° C. Further, when the Al composition is increased and the Al composition is 1.0%, the heat treatment temperature of 1050 ° C. is not reached, and blackening does not occur, and no problem occurs in the active layer even at 1000 ° C. When the Al composition is increased to 2.0%, the state remains the same as when the Al composition is 1.0%, and the heat resistance is not significantly improved.
次に、図６は、ＰＬ（フォトルミネセンス）測定の結果を示す。縦軸はＰＬ強度（任意単位）、横軸は熱処理温度を表す。まず、図５の場合と同様に、図１の構成でサファイア基板１上に、活性層４としてＡｌＩｎＧａＮ井戸層とＡｌＧａＮバリア層又は、ＡｌＩｎＧａＮ井戸層とＧａＮバリア層とを５周期程度形成した後、アニール温度を変化させて窒素雰囲気中で熱処理（時間３０分）を行い、その後室温で発光スペクトル（ＰＬ強度分布）を測定し、各温度毎のＰＬ強度分布の積分値を求めた。 Next, FIG. 6 shows the results of PL (photoluminescence) measurement. The vertical axis represents the PL intensity (arbitrary unit), and the horizontal axis represents the heat treatment temperature. First, as in the case of FIG. 5, after the AlInGaN well layer and the AlGaN barrier layer or the AlInGaN well layer and the GaN barrier layer are formed as the active layer 4 on the sapphire substrate 1 in the configuration of FIG. The annealing temperature was changed and heat treatment was performed in a nitrogen atmosphere (time 30 minutes), and then the emission spectrum (PL intensity distribution) was measured at room temperature to obtain the integrated value of the PL intensity distribution at each temperature.
曲線Ａ１は、活性層がＡｌＩｎＧａＮ井戸層／ＡｌＧａＮバリア層のＭＱＷ構造でＡｌの組成比率が０．２５％を示す。曲線Ａ２は、従来構造の活性層を用いたもので、ＩｎＧａＮ井戸層／ＧａＮバリア層のＭＱＷ構造の場合を示す。曲線Ａ３は、活性層がＡｌＩｎＧａＮ井戸層／ＧａＮバリア層のＭＱＷ構造でＡｌの組成比率が１％を示す。曲線Ａ４は、活性層がＡｌＩｎＧａＮ井戸層／ＡｌＧａＮバリア層のＭＱＷ構造でＡｌの組成比率が１％を示す。 Curve A1 shows an MQW structure in which the active layer is an AlInGaN well layer / AlGaN barrier layer and the Al composition ratio is 0.25%. A curve A2 uses an active layer having a conventional structure, and shows an MQW structure of an InGaN well layer / GaN barrier layer. A curve A3 shows an MQW structure in which the active layer is an AlInGaN well layer / GaN barrier layer and the Al composition ratio is 1%. A curve A4 indicates that the active layer is an AlInGaN well layer / AlGaN barrier layer MQW structure and the Al composition ratio is 1%.
従来構造の活性層を用いたＡ２では、９５０℃の熱処理を行うと、ＰＬ強度が激減し、活性層の劣化が見られる。これは、図５の結果とも一致している。一方、Ａｌの組成比率が０．２５％では、９５０℃付近で良好なＰＬ強度を示し、１０００℃の熱処理でＰＬ強度が低下している。したがって、Ａｌを添加したＡ１の方が、従来構造の活性層を用いたＡ２よりもＴ℃（図では５０℃）耐熱性が向上した。また、Ａ３では井戸層にのみＡｌが１％添加されているが、１０００℃になると発光強度が低下しており、耐熱性はＡ１とほとんど変わらないが、Ａｌ組成比率の増加にともない発光強度も低下している。一方、井戸層とバリア層の両方にＡｌを１％添加したＡ４は、図５も参照すればわかるように耐熱性は、Ａ１やＡ３よりも向上するが、発光強度はＡ３よりも低下する。 In A2 using an active layer having a conventional structure, when heat treatment at 950 ° C. is performed, the PL strength is drastically reduced and the active layer is deteriorated. This is consistent with the result of FIG. On the other hand, when the Al composition ratio is 0.25%, good PL strength is exhibited at around 950 ° C., and the PL strength is lowered by heat treatment at 1000 ° C. Therefore, A1 to which Al was added improved T.degree. C. (50.degree. C. in the drawing) heat resistance over A2 using an active layer having a conventional structure. In A3, 1% Al is added only to the well layer, but the emission intensity decreases at 1000 ° C., and the heat resistance is almost the same as A1, but the emission intensity increases as the Al composition ratio increases. It is falling. On the other hand, A4 with 1% Al added to both the well layer and the barrier layer improves the heat resistance as compared with A1 and A3 as shown in FIG. 5, but the emission intensity decreases as compared with A3.
以上のように、図５、６に示された測定結果からは活性層にＡｌが少しでも添加されていれば、耐熱性の向上がみられると考えられる。一方、ＡｌＩｎＧａＮ井戸層のＡｌ組成比率を増加させていくと、バンドギャップは次第に大きくなり、発光はより短波長化するが、その波長シフト量が大きくならないように、少なくとも井戸層のＡｌ組成は５％以下とするのが望ましい。また、図６を参照すれば、より好ましいＡｌ組成は１％以下である。 As described above, from the measurement results shown in FIGS. 5 and 6, it is considered that if Al is added to the active layer, heat resistance can be improved. On the other hand, when the Al composition ratio of the AlInGaN well layer is increased, the band gap gradually increases and the emission becomes shorter, but at least the Al composition of the well layer is 5 so that the wavelength shift amount does not increase. % Or less is desirable. Referring to FIG. 6, the more preferable Al composition is 1% or less.
なお、実際にＬＥＤ構造の作製も行ったが、従来のＩｎＧａＮ／ＧａＮ活性層では９００℃以上でｐ型層を成膜すると黒色化し、ＬＥＤ発光が得られないのに対し、今回作製したＡｌＩｎＧａＮを用いた活性層では９５０℃でｐ型ＧａＮ層を成膜しても熱のダメージを受けず、特性の良好なＬＥＤが得られた。 Although the LED structure was actually fabricated, the conventional InGaN / GaN active layer turned black when the p-type layer was deposited at 900 ° C. or higher, and LED emission was not obtained. The active layer used was not damaged by heat even when a p-type GaN layer was formed at 950 ° C., and an LED having good characteristics was obtained.
次に、図３に示すように井戸層４ｂとバリア層４ａで、成長温度を異なるようにして温度変調によって活性層４を作製する場合を以下に説明する。ガスフローパターンは図４と同じである。まず、温度Ｔ２まで基板温度を下げた後、一定時間さらに結晶成長が行われ、その後井戸層４ｂを成膜するために温度Ｔ２まで下降させる過程でもバリア層４ａの結晶成長が行われる。温度Ｔ２に達すると温度Ｔ２で図４の時間Ｌの間、井戸層４ｂの結晶成長を行った後、再び上記のように次のバリア層４ａの結晶成長が行われる。井戸層４ａは、一定の温度Ｔ２で成長が行われるが、バリア層４ａはＴ２からＴ１まで温度が上昇する過程と、一定温度Ｔ１の期間と、Ｔ１からＴ２まで温度が下降する過程とで行われる。このようにして、バリア層４ａと井戸層４ｂが交互に成膜される。 Next, the case where the active layer 4 is formed by temperature modulation with different growth temperatures in the well layer 4b and the barrier layer 4a as shown in FIG. 3 will be described below. The gas flow pattern is the same as in FIG. First, after the substrate temperature is lowered to the temperature T2, crystal growth is further performed for a certain time, and then the barrier layer 4a is also grown in the process of lowering to the temperature T2 in order to form the well layer 4b. When the temperature T2 is reached, after the crystal growth of the well layer 4b is performed at the temperature T2 for the time L in FIG. 4, the crystal growth of the next barrier layer 4a is performed again as described above. The well layer 4a is grown at a constant temperature T2. The barrier layer 4a is grown in a process in which the temperature increases from T2 to T1, a period of the constant temperature T1, and a process in which the temperature decreases from T1 to T2. Is called. In this way, barrier layers 4a and well layers 4b are alternately formed.
ここで、Ｔ１は８５０℃〜９５０℃、Ｔ２は６５０℃〜８００℃に設定される。また、Ｔ２からＴ１までの昇温時間とＴ１からＴ２までの降温時間は、いずれも５分以内程度で行った。また、井戸層４ｂとバリア層４ａともに、成長レートは１５Å／分程度、井戸層４ｂの成長時間（期間Ｌに相当）は０．８６分、バリア層４ａの成長時間７分、ＴＥＧ流量７４ｓｃｃｍ、ＴＭＩ流量１１５ｓｃｃｍ、ＴＭＡ流量１０〜２００ｓｃｃｍ等とした。 Here, T1 is set to 850 ° C to 950 ° C, and T2 is set to 650 ° C to 800 ° C. Further, the temperature raising time from T2 to T1 and the temperature lowering time from T1 to T2 were both within about 5 minutes. Further, the growth rate of both the well layer 4b and the barrier layer 4a is about 15 Å / min, the growth time of the well layer 4b (corresponding to the period L) is 0.86 minutes, the growth time of the barrier layer 4a is 7 minutes, the TEG flow rate is 74 sccm, The TMI flow rate was 115 sccm, the TMA flow rate was 10 to 200 sccm, and the like.
図１の構成のＬＥＤ構造で、ＡｌＩｎＧａＮ／ＡｌＧａＮのＭＱＷ構造を井戸層、バリア層の成長を異なる温度で作製したところ、一定温度で成膜したサンプルよりも高い内部量子効率が得られた。バリア層成長温度の高温化によりバリア層の品質が向上したこと、及び、Ａｌ添加により井戸層の耐熱性が向上したため、バリア層の成長温度を高温化しても井戸層に熱ダメージが入らなくなったためであると考えられる。 When the AlInGaN / AlGaN MQW structure was fabricated at different temperatures in the LED structure having the configuration shown in FIG. 1, the internal quantum efficiency was higher than that of the sample formed at a constant temperature. Because the barrier layer quality has been improved by increasing the barrier layer growth temperature, and the heat resistance of the well layer has been improved by adding Al, the thermal damage to the well layer has been prevented even if the growth temperature of the barrier layer is increased. It is thought that.
図７は、活性層４を温度変調により成長させた場合と、一定温度により成長させた場合とで順方向電圧（Ｖｆ）−順方向電流（Ｉｆ）特性を比較したものである。Ｚ１は井戸層４ｂとバリア層４ａともに同じ温度で成長させた場合のＶｆ−Ｉｆ特性曲線を示し、Ｚ２は図３のように温度変調を行って井戸層４ｂとバリア層４ａを成長させた場合のＶｆ−Ｉｆ特性曲線を示す。井戸層４ｂとバリア層４ａの構成は、前述したものを用いており、発光波長が５２０ｎｍ程度の緑色域の発光を有する。図７からわかるように、温度変調により作製した活性層（曲線Ｚ２）の方が、駆動電圧が非常に低くなり好ましい。例えば、一定温度で作製した活性層の場合（Ｚ１）ではＶｆ（２０ｍＡ）が４Ｖ以上であったのに対し、温度変調により作製した場合（Ｚ２）では、Ｖｆ（２０ｍＡ）３．２〜３．４Ｖが得られた。 FIG. 7 compares the forward voltage (Vf) -forward current (If) characteristics when the active layer 4 is grown by temperature modulation and when grown at a constant temperature. Z1 shows a Vf-If characteristic curve when both the well layer 4b and the barrier layer 4a are grown at the same temperature, and Z2 is a case where the well layer 4b and the barrier layer 4a are grown by performing temperature modulation as shown in FIG. The Vf-If characteristic curve of is shown. The structure of the well layer 4b and the barrier layer 4a uses what was mentioned above, and has light emission of the green region whose light emission wavelength is about 520 nm. As can be seen from FIG. 7, the active layer (curve Z2) produced by temperature modulation is preferable because the driving voltage is very low. For example, in the case of the active layer manufactured at a constant temperature (Z1), Vf (20 mA) was 4 V or more, whereas in the case of manufacturing by temperature modulation (Z2), Vf (20 mA) 3.2-3. 4V was obtained.
図８は、活性層４を温度変調により成長させた場合と、一定温度により成長させた場合とで輝度−順方向電流（Ｉｆ）特性を比較したものである。Ｚ３は井戸層４ｂとバリア層４ａともに同じ温度で成長させた場合の輝度−Ｉｆ特性曲線を示し、Ｚ４は図３のように温度変調を行って井戸層４ｂとバリア層４ａを成長させた場合の輝度−Ｉｆ特性曲線を示す。井戸層４ｂとバリア層４ａの構成は、前述したものを用いており、発光波長が５２０ｎｍ程度の緑色域の発光を有する。図８からわかるように、温度変調により作製した活性層（曲線Ｚ４）の方が、すべての電流域で輝度が強くなっており、発光特性Ｇ大きく改善されている。 FIG. 8 compares the luminance-forward current (If) characteristics when the active layer 4 is grown by temperature modulation and when grown at a constant temperature. Z3 represents a luminance-If characteristic curve when both the well layer 4b and the barrier layer 4a are grown at the same temperature, and Z4 represents a case where the well layer 4b and the barrier layer 4a are grown by performing temperature modulation as shown in FIG. The luminance-If characteristic curve is shown. The structure of the well layer 4b and the barrier layer 4a uses what was mentioned above, and has light emission of the green region whose light emission wavelength is about 520 nm. As can be seen from FIG. 8, the brightness of the active layer (curve Z4) produced by temperature modulation is stronger in all current regions, and the emission characteristics G are greatly improved.
以上のように、活性層にＡｌ添加をしただけでは耐熱性の向上が図れるもののＧａＮ系半導体発光素子の特性としては不十分である。一方、Ａｌ添加せずに、温度変調をしただけでは短波長側（青より短波側）では効果が得られず、また長波長側（青より長波側）では井戸層の膜が黒色化してしまい、発光素子の作製が不可能である。Ａｌ添加と、温度変調を組み合わせることではじめて発光特性、電気特性の優れた発光素子が作製できる。 As described above, the heat resistance can be improved only by adding Al to the active layer, but the characteristics of the GaN-based semiconductor light emitting device are insufficient. On the other hand, if only temperature modulation is performed without adding Al, no effect is obtained on the short wavelength side (short wave side from blue), and the well layer film becomes black on the long wavelength side (long wave side from blue). It is impossible to manufacture a light emitting element. Only by combining Al addition and temperature modulation can a light emitting device with excellent light emission characteristics and electrical characteristics be produced.
本発明の手法は緑色域等の長波長の領域で有効あるが、長波長域の発光素子は注入電流増加に伴いピーク波長が短波長側にシフトするという現象が見られる。サファイア基板のｃ面又は−ｃ面にＧａＮ系半導体を成長させると、ＧａＮ系半導体層の成長表面がｃ面又は−ｃ面に揃い、ｃ軸方向に対称性がなく、ｃ面成長のエピタキシャル膜には表裏が生じるというウルツ鉱構造のため活性層の歪みによる電場（ピエゾ電場）が発生し、その影響によって発光波長が長波長化するためであり、井戸層のＩｎ組成が高くなればなるほど顕著に現れる。 Although the method of the present invention is effective in a long wavelength region such as a green region, a phenomenon that a peak wavelength shifts to a short wavelength side with an increase in injection current is observed in a light emitting element in a long wavelength region. When a GaN-based semiconductor is grown on the c-plane or the −c-plane of the sapphire substrate, the growth surface of the GaN-based semiconductor layer is aligned with the c-plane or the −c-plane, and there is no symmetry in the c-axis direction. This is because the electric field (piezo electric field) due to the distortion of the active layer is generated due to the wurtzite structure where the front and back sides are generated, and the emission wavelength becomes longer due to the effect. The higher the In composition of the well layer, the more remarkable Appear in
そこでピエゾ電場の発生しないノンポーラ面（非極性面）を成長表面としてＧａＮ系半導体発光素子を形成すると、波長シフトのほとんどない発光素子が作製できる。また、ピエゾ電場の発生を極力抑えることができるセミポーラ面（半極性面）を成長表面とするようにＧａＮ系半導体発光素子を作製するようにしても良い。 Therefore, when a GaN-based semiconductor light-emitting device is formed using a nonpolar surface (nonpolar surface) that does not generate a piezoelectric field as a growth surface, a light-emitting device having almost no wavelength shift can be manufactured. Further, the GaN-based semiconductor light-emitting element may be fabricated so that a growth surface is a semipolar surface (semipolar surface) that can suppress the generation of a piezoelectric field as much as possible.
ところで、ＧａＮ系半導体、サファイア基板、６Ｈ−ＳｉＣ基板等の六方晶系の結晶構造は、ウルツ鉱型の結晶構造とも言われ、結晶の面や方位はいわゆるミラー指数で表され、例えば、ｃ面は（０００１）、ａ面は（１１−２０）と表される。上記ノンポーラ面とは、ｃ面又は−ｃ面と直交している面に相当し、ａ面（１１−２０）、結晶の柱面でもあるｍ面（１０−１０）が該当する。一方、セミポーラ面とは、（１０−１−１）面、（１０−１−３）面、（１１−２２）面のいずれかの面である。そして、サファイア基板、ＳｉＣ基板、ＧａＮ基板等の成長用基板のノンポーラ面又はセミポーラ面をＧａＮ系半導体層の結晶成長表面に用いると、形成されたすべてのＧａＮ系半導体層の成長表面は、ノンポーラ面又はセミポーラ面となる。 By the way, a hexagonal crystal structure such as a GaN-based semiconductor, a sapphire substrate, or a 6H-SiC substrate is also called a wurtzite type crystal structure, and the plane and orientation of the crystal are expressed by a so-called Miller index. Is represented as (0001), and the a-plane is represented as (11-20). The nonpolar plane corresponds to a plane orthogonal to the c-plane or the -c-plane, and corresponds to the a-plane (11-20) and the m-plane (10-10) which is also a crystal column face. On the other hand, the semipolar plane is any one of the (10-1-1) plane, the (10-1-3) plane, and the (11-22) plane. When the nonpolar or semipolar surface of a growth substrate such as a sapphire substrate, SiC substrate, or GaN substrate is used as the crystal growth surface of the GaN-based semiconductor layer, the growth surfaces of all formed GaN-based semiconductor layers are nonpolar surfaces. Or it becomes a semipolar surface.
例えば、図１の構造のＬＥＤを作製する場合には、成長用基板としてのサファイア基板１のｒ面上にＧａＮ系半導体を結晶成長させれば、その成長表面はａ面となり、ノンポーラ面を成長表面とする図１のＬＥＤを形成することができる。また、サファイア基板１のセミポーラ面上にＧａＮ系半導体を結晶成長させると、この面が引き継がれてＧａＮ系半導体の成長表面もセミポーラ面となる。 For example, in the case of manufacturing an LED having the structure shown in FIG. 1, if a GaN-based semiconductor is crystal-grown on the r-plane of a sapphire substrate 1 as a growth substrate, the growth surface becomes an a-plane and a nonpolar plane is grown. The LED of FIG. 1 as the surface can be formed. Further, when a GaN-based semiconductor is crystal-grown on the semipolar surface of the sapphire substrate 1, this surface is taken over and the growth surface of the GaN-based semiconductor also becomes a semipolar surface.
製造方法としては、良く知られたＭＯＣＶＤ法等で成長させる。例えば、サファイア基板１をサーマルクリーニングした後、基板温度を１０００℃程度に上げて、サファイア基板１のｒ面上に、Ｓｉドープのｎ型ＧａＮコンタクト層２を１〜５μｍ程度積層し、次に基板温度を７００℃〜８００℃に下げて、ＳｉドープのＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層３、ＭＱＷ構造の活性層４を形成する。その後、基板温度を９５０℃〜１０００℃程度まで上げて、電子ブロック層として機能するＭｇドープのｐ型ＡｌＧａＮブロック層８を形成し、次にＭｇドープのｐ型ＧａＮコンタクト層５を０．２〜１μｍ程度積層する。活性層４は、上述したように、井戸層ＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）、バリア層ＡｌＸ２ＩｎＹ２ＧａＺ２Ｎ（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１）を交互に積層する。 As a manufacturing method, growth is performed by a well-known MOCVD method or the like. For example, after the sapphire substrate 1 is thermally cleaned, the substrate temperature is raised to about 1000 ° C., the Si-doped n-type GaN contact layer 2 is laminated on the r-plane of the sapphire substrate 1 by about 1 to 5 μm, and then the substrate The temperature is lowered to 700 ° C. to 800 ° C. to form an Si-doped AlInGaN / AlGaN superlattice layer 3 and an active layer 4 having an MQW structure. Thereafter, the substrate temperature is raised to about 950 ° C. to 1000 ° C. to form an Mg-doped p-type AlGaN block layer 8 functioning as an electron block layer, and then the Mg-doped p-type GaN contact layer 5 is formed to 0.2 to Laminate about 1 μm. As described above, the active layer 4 includes the well layer Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1, 0 <X1 <1, 0 <Y1 <1), the barrier layer Al X2 In Y2 Ga Z2 N (X2 + Y2 + Z2 = 1) , 0 ≦ X2 <1, 0 ≦ Y2 <1) are alternately stacked.
ｐ型ＧａＮコンタクト層５を形成した後、ｐ型ＧａＮコンタクト層５〜ｎ型ＧａＮコンタクト層２の途中までを反応性イオンエッチング等によりメサエッチングして除去し、ｎ型ＧａＮコンタクト層２表面を露出させる。その後、露出したｎ型ＧａＮコンタクト層２表面にｎ電極７を蒸着により形成し、ｐ型ＧａＮコンタクト層５の上にｐ電極６を蒸着により形成する。 After the p-type GaN contact layer 5 is formed, the p-type GaN contact layer 5 to the n-type GaN contact layer 2 are removed by mesa etching by reactive ion etching or the like to expose the surface of the n-type GaN contact layer 2 Let Thereafter, an n-electrode 7 is formed on the exposed n-type GaN contact layer 2 surface by vapor deposition, and a p-electrode 6 is formed on the p-type GaN contact layer 5 by vapor deposition.
ところで、ｐ型ＧａＮコンタクト層５上にｐ電極６を形成するのではなく、ｐ型ＧａＮコンタクト層５上に透明のＺｎＯ電極を積層した後、ｐ電極６を形成するようにしても良い。この場合、ＧａドープＺｎＯ電極をたとえばＭＢＥ（Molecular beam epitaxy）やＰＬＤ（Pulsed Laser Deposition）によってｐ型ＧａＮコンタクト層５上に形成する。 By the way, instead of forming the p-electrode 6 on the p-type GaN contact layer 5, the p-electrode 6 may be formed after a transparent ZnO electrode is laminated on the p-type GaN contact layer 5. In this case, a Ga-doped ZnO electrode is formed on the p-type GaN contact layer 5 by, for example, MBE (Molecular Beam Epitaxy) or PLD (Pulsed Laser Deposition).
図６は、導電性のｎ型６Ｈ−ＳｉＣ基板１２を用いて、ＧａＮ系半導体を結晶成長させ、ｐ電極とｎ電極を対向するようにしたＬＥＤの一例を示す。図１の構成では、サファイア基板１の熱伝導が約０．５Ｗ／（ｃｍ・Ｋ）と悪く、ボンディングワイヤーもｐ電極側とｎ電極側の両方必要となるが、ＳｉＣ基板を用いた場合は、熱伝導はサファイア基板の１０倍（約４．９Ｗ／（ｃｍ・Ｋ））と放熱性が良いのと、ｎ電極側を金属配線に直接ボンディングできるため、ｐ電極側のボンディングワイヤーが１本で良くなるという利点がある。 FIG. 6 shows an example of an LED in which a GaN-based semiconductor is crystal-grown using a conductive n-type 6H—SiC substrate 12 so that a p-electrode and an n-electrode face each other. In the configuration of FIG. 1, the heat conduction of the sapphire substrate 1 is poor at about 0.5 W / (cm · K), and bonding wires are required on both the p-electrode side and the n-electrode side. However, when a SiC substrate is used, The heat conduction is 10 times that of the sapphire substrate (approx. 4.9 W / (cm · K)) and the heat dissipation is good, and since the n electrode side can be directly bonded to the metal wiring, there is one bonding wire on the p electrode side There is an advantage of getting better.
さて、ｎ型６Ｈ−ＳｉＣ基板１２のｍ面上にＧａＮ系半導体を結晶成長させることで、ＧａＮ系半導体の成長表面もノンポーラのｍ面となる。また、セミポーラ面である（１０−１−１）面上にＧａＮ系半導体を結晶成長させると、この面が引き継がれてＧａＮ系半導体の成長表面も（１０−１−１）面となる。 By growing a GaN-based semiconductor on the m-plane of the n-type 6H—SiC substrate 12, the growth surface of the GaN-based semiconductor also becomes a non-polar m-plane. Further, when a GaN-based semiconductor is crystal-grown on the (10-1-1) plane which is a semipolar plane, this plane is taken over and the growth surface of the GaN-based semiconductor also becomes the (10-1-1) plane.
製造方法を簡単に説明すると、ＭＯＣＶＤ法で、基板温度を１０００℃程度に上げて、ｎ型６Ｈ−ＳｉＣ基板１２のノンポーラ面又はセミポーラ面上に、Ｓｉドープのｎ型ＧａＮコンタクト層１３を積層し、次に基板温度を７００℃〜８００℃に下げて、ＳｉドープのＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層１４、ＭＱＷ構造の活性層４１を形成する。その後、基板温度を９５０℃〜１０００℃程度まで上げて、電子ブロック層として機能するＭｇドープのｐ型ＡｌＧａＮブロック層１７を形成し、次にＭｇドープのｐ型ＧａＮコンタクト層１５を積層する。最後にｐ電極１６、ｎ電極１１を蒸着又はスパッタにより形成する。ＭＱＷ構造の活性層４１は、上述したように、井戸層ＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）、バリア層ＡｌＸ２ＩｎＹ２ＧａＺ２Ｎ（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１）を交互に積層する。 The manufacturing method will be briefly described. The substrate temperature is raised to about 1000 ° C. by MOCVD, and the Si-doped n-type GaN contact layer 13 is laminated on the non-polar or semipolar surface of the n-type 6H—SiC substrate 12. Then, the substrate temperature is lowered to 700 ° C. to 800 ° C., and the Si-doped AlInGaN / AlGaN superlattice layer 14 and the active layer 41 having the MQW structure are formed. Thereafter, the substrate temperature is raised to about 950 ° C. to 1000 ° C. to form an Mg-doped p-type AlGaN blocking layer 17 functioning as an electron blocking layer, and then an Mg-doped p-type GaN contact layer 15 is laminated. Finally, the p electrode 16 and the n electrode 11 are formed by vapor deposition or sputtering. As described above, the active layer 41 having the MQW structure includes the well layer Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1, 0 <X1 <1, 0 <Y1 <1), the barrier layer Al X2 In Y2 Ga Z2 N ( X2 + Y2 + Z2 = 1, 0 ≦ X2 <1, 0 ≦ Y2 <1) are alternately stacked.
図７は、リッジ構造を有するＬＤ（レーザダイオード）の一例を示す。ｎ型ＧａＮ基板２１上にｎ型クラッド層２２、ｎ型ＧａＮ導波路層２３、ｎ型のＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層２４、ＭＱＷ活性層４２、ｐ型ＡｌＧａＮブロック層２５、ｐ型ＧａＮ導波路層２６、ｐ型ＳＬＳクラッド層２７、ｐ型ＧａＮコンタクト層２８を積層した後、メサエッチングにより、ｐ型ＧａＮコンタクト層２８〜ｐ型ＧａＮ導波路層２６途中までを除去して、リッジ構造を形成し、リッジ部の側面からｐ型ＧａＮ導波路層２６の露出した表面を覆うように絶縁層２９を形成し、ｐ型ＧａＮコンタクト層２８上面に接触するようにコンタクト電極３０を絶縁層２９上面に渡って形成した後、パッド電極３１をコンタクト電極３０上に設けた構造となっている。 FIG. 7 shows an example of an LD (laser diode) having a ridge structure. An n-type cladding layer 22, an n-type GaN waveguide layer 23, an n-type AlInGaN / AlGaN superlattice layer 24, an MQW active layer 42, a p-type AlGaN block layer 25, a p-type GaN waveguide layer on the n-type GaN substrate 21. 26, after laminating the p-type SLS cladding layer 27 and the p-type GaN contact layer 28, the p-type GaN contact layer 28 to the middle of the p-type GaN waveguide layer 26 are removed by mesa etching to form a ridge structure. Then, an insulating layer 29 is formed so as to cover the exposed surface of the p-type GaN waveguide layer 26 from the side surface of the ridge portion, and the contact electrode 30 is extended over the upper surface of the insulating layer 29 so as to contact the upper surface of the p-type GaN contact layer 28. After the formation, the pad electrode 31 is provided on the contact electrode 30.
この場合、ｎ型ＧａＮ基板２１の表面はノンポーラ面又はセミポーラが用いられ、ＭＱＷ活性層４２は、上述したように、井戸層ＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）、バリア層ＡｌＸ２ＩｎＹ２ＧａＺ２Ｎ（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１）を交互に積層する。また、ｎ型クラッド層２２は、ｎ型ＡｌＧａＮ層又はｎ型ＡｌＧａＮとｎ型ＧａＮ層を交互に積層した超格子層で構成され、ｐ型ＳＬＳクラッド層２７は、歪超格子構造を有する層であり、ｐ型ＡｌＧａＮとｐ型ＧａＮを交互に積層した構造となっている。なお、ＭＱＷ活性層４２より上に積層するｐ型ＡｌＧａＮブロック層２５〜ｐ型ＧａＮコンタクト層２８までは、基板温度９５０℃〜１０００℃程度で成長させる。 In this case, the surface of the n-type GaN substrate 21 is a nonpolar surface or a semipolar surface, and the MQW active layer 42 is formed of the well layer Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1, 0 <X1 <1, 0 <Y1 <1) and barrier layers Al X2 In Y2 Ga Z2 N (X2 + Y2 + Z2 = 1, 0 ≦ X2 <1, 0 ≦ Y2 <1) are alternately stacked. The n-type cladding layer 22 is composed of an n-type AlGaN layer or a superlattice layer in which n-type AlGaN and n-type GaN layers are alternately stacked, and the p-type SLS cladding layer 27 is a layer having a strained superlattice structure. There is a structure in which p-type AlGaN and p-type GaN are alternately stacked. The p-type AlGaN block layer 25 to the p-type GaN contact layer 28 stacked above the MQW active layer 42 are grown at a substrate temperature of about 950 ° C. to 1000 ° C.
なお、上述した各半導体層の製造については、キャリアガスの水素／窒素とともに、トリエチルガリウム（ＴＥＧａ）、トリメチルガリウム（ＴＭＧ）、アンモニア（ＮＨ３）、トリメチルアルミニウム（ＴＭＡ）、トリメチルインジウム（ＴＭＩｎ）などの各半導体層の成分に対応する反応ガス、ｎ型にする場合のドーパントガスとしてのシラン（ＳｉＨ４）、ｐ型にする場合のドーパントガスとしてのＣＰ２Ｍｇ（シクロペンタジエチルマグネシウム）等の必要なガスを供給して、６５０℃〜１０００℃程度の範囲で順次成長させることにより、所望の組成で、所望の導電型の半導体層を、必要な厚さに形成することができる。
Note that the manufacturing of the semiconductor layers described above, with hydrogen / nitrogen carrier gas triethylgallium (TEGa), trimethyl gallium (TMG), ammonia (NH 3), trimethyl aluminum (TMA), trimethyl indium (TMIn), etc. Reaction gas corresponding to the components of each semiconductor layer, silane (SiH 4 ) as a dopant gas for n-type, CP 2 Mg (cyclopentadiethylmagnesium) as a dopant gas for p-type, etc. By supplying a suitable gas and sequentially growing it in the range of about 650 ° C. to 1000 ° C., a semiconductor layer of a desired conductivity type can be formed with a desired composition and a required thickness.
１ サファイア基板
２ ｎ型ＧａＮコンタクト層
３ ＡｌＩｎＧａＮ／ＡｌＧａＮ超格子層
４ 活性層
５ ｐ型ＧａＮコンタクト層
６ ｐ電極
７ ｎ電極
８ ｐ型ＡｌＧａＮブロック層
1 Sapphire substrate 2 n-type GaN contact layer 3 AlInGaN / AlGaN superlattice layer 4 active layer 5 p-type GaN contact layer 6 p-electrode 7 n-electrode 8 p-type AlGaN block layer
Claims (5)
前記活性層はＡｌＸ１ＩｎＹ１ＧａＺ１Ｎ（Ｘ１＋Ｙ１＋Ｚ１＝１、０＜Ｘ１＜１、０＜Ｙ１＜１）井戸層とＡｌＸ２ＩｎＹ２ＧａＺ２Ｎバリア層（Ｘ２＋Ｙ２＋Ｚ２＝１、０≦Ｘ２＜１、０≦Ｙ２＜１、Ｙ１＞Ｙ２）とで構成されており、前記井戸層の成長温度とバリア層の成長温度とは異なることを特徴とするＧａＮ系半導体発光素子。 A GaN-based semiconductor light emitting device including an active layer having a quantum well structure,
The active layer includes an Al X1 In Y1 Ga Z1 N (X1 + Y1 + Z1 = 1, 0 <X1 <1, 0 <Y1 <1) well layer and an Al X2 In Y2 Ga Z2 N barrier layer (X2 + Y2 + Z2 = 1, 0 ≦ X2 <1). , 0 ≦ Y2 <1, Y1> Y2), and the growth temperature of the well layer and the growth temperature of the barrier layer are different from each other.
5. The GaN-based semiconductor light-emitting element according to claim 1, wherein at least a crystal growth surface of the active layer is formed by a nonpolar plane or a semipolar plane.
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| JP2011014746A (en) * | 2009-07-02 | 2011-01-20 | Sharp Corp | Nitride semiconductor element, method of fabricating the same, and semiconductor device |
| JP2011029237A (en) * | 2009-07-21 | 2011-02-10 | Sharp Corp | Nitride semiconductor chip, method of fabrication thereof, and semiconductor device |
| JP2011159771A (en) * | 2010-01-29 | 2011-08-18 | Nec Corp | Nitride semiconductor light-emitting element, and manufacturing method of the nitride semiconductor light-emitting element, and electronic device |
| US8344413B2 (en) | 2009-05-29 | 2013-01-01 | Sharp Kabushiki Kaisha | Nitride semiconductor wafer, nitride semiconductor chip, and method of manufacture of nitride semiconductor chip |
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| US8664688B2 (en) | 2009-03-27 | 2014-03-04 | Sharp Kabushiki Kaisha | Nitride semiconductor light-emitting chip, method of manufacture thereof, and semiconductor optical device |
| US8344413B2 (en) | 2009-05-29 | 2013-01-01 | Sharp Kabushiki Kaisha | Nitride semiconductor wafer, nitride semiconductor chip, and method of manufacture of nitride semiconductor chip |
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