JP2008117397A - プロセシング・コアの独立電力制御 - Google Patents
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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Abstract
【解決手段】第二のプロセシング・コアとは独立に第一のプロセシング・コアの電力消費を制御する電力制御論理を設ける。
【選択図】図4
Description
105 プロセシング・コア
110 プロセシング・コア
200 プロセッサ・コア
207 出力回路
208 電力回路
209 クロック修正回路
215 電力制御論理
300 電力制御論理
301 入力
310 出力
401 あるコアについて電力条件が検出される
405 第一の条件?
407 コア/アンコアが第一の状態に置かれる
410 第二の条件?
413 コア/アンコアが第二の状態に置かれる
505 プロセッサ
510 キャッシュ・メモリ
515 メイン・メモリ
520 ハード・ディスク・ドライブ
530 インターフェース
62 メモリ
64 メモリ
614 I/Oデバイス
618 バス・ブリッジ
624 オーディオI/O
622 キーボード/マウス
626 通信デバイス
628 データ記憶装置
630 コード
638 高パフォーマンス・グラフィクス回路
639 高パフォーマンス・グラフィクス・インターフェース
650 ポイント・ツー・ポイント(PtP)インターフェース
652 個別のPtPインターフェース
654 個別のPtPインターフェース
670 プロセッサ
672 メモリ・コントローラ・ハブ(MCH)
674 プロセシング・コア
676 PtPインターフェース回路
678 PtPインターフェース回路
680 プロセッサ
682 メモリ・コントローラ・ハブ(MCH)
684 プロセシング・コア
686 PtPインターフェース回路
688 PtPインターフェース回路
694 PtPインターフェース回路
698 PtPインターフェース回路
690 チップセット
Claims (30)
- 第一のプロセシング・コアと;
第一のプロセシング・コアに結合された第二のプロセシング・コアと;
第二のプロセシング・コアとは独立に第一のプロセシング・コアの電力消費を制御する電力制御論理とを有する装置。 - 前記電力制御論理が第一のプロセシング・コアを複数の電力状態のうちの任意の状態に置く、請求項1記載の装置。
- 前記複数の電力状態のうちある第一のものが、第一のプロセシング・コアをデータ保持電力状態にするものである、請求項2記載の装置。
- 前記複数の電力状態のうちある第二のものが、第一のプロセシング・コアおよび出力を無効にするものである、請求項3記載の装置。
- 前記第一のコアによっても前記第二のコアによっても実行されない機能を実行する少なくとも一つのアンコア論理をさらに有する、請求項1記載の装置。
- 前記電力制御論理が、前記少なくとも一つのアンコア論理を複数の電力状態のうちの任意の状態に置く、請求項5記載の装置。
- 前記複数の電力状態のうちある第一のものが、少なくとも一つのアンコア論理をデータ保持電力状態にするものである、請求項6記載の装置。
- 前記複数の電力状態のうちある第二のものが、前記少なくとも一つのアンコア論理を無効にするものである、請求項7記載の装置。
- 複数のプロセシング・コアを有するシステムであって:各プロセシング・コアは前記複数のプロセシング・コアのうち残りのもののいずれの電力状態にも関わりなく複数の電力状態に置かれることができ、該複数の電力状態は前記複数のプロセシング・コアのうち少なくとも一つをプロセシング・コアのうち前記少なくとも一つ以外の残りとは異なるある第一の電力状態に置くことを含む、システム。
- 前記複数の電力状態が、前記複数のプロセシング・コアのうち少なくとも一つを無効状態に置くことを含む、請求項9記載のシステム。
- 前記複数のプロセシング・コアのうちの前記少なくとも一つが、該複数のプロセシング・コアのうち前記少なくとも一つの、少なくとも一つの機能ブロック(FUB)が受ける電圧の変化を引き起こす助けとなるパワー・トランジスタを含む、請求項10記載のシステム。
- 前記複数のプロセシング・コアのうち前記少なくとも一つが、前記少なくとも一つのFUBが受けるクロック信号の変化を引き起こす位相ロック・ループ(PLL)を含む、請求項11記載のシステム。
- 前記複数の電力状態が、前記電圧を変化させることによって達成される、請求項12記載のシステム。
- 前記複数の電力状態が、前記クロック信号を変化させることによって達成される、請求項12記載のシステム。
- 前記複数の電力状態が、前記電圧および前記クロック信号を変化させることによって達成される、請求項12記載のシステム。
- 前記複数のコアのうち少なくとも二つを含む少なくとも一つのマルチコア・プロセッサをさらに含んでいる、請求項9記載のシステム。
- 前記複数のコアのうち一つを含む少なくとも一つの単一コア・プロセッサをさらに含んでいる、請求項9記載のシステム。
- 電力に関係したある条件を示す第一の信号を受領する段階と;
前記第一の信号を受領するのに反応して、複数のプロセシング・コアのうちの一つを複数の電力状態のうちの一つに置く段階とを有する方法であって、複数の電力状態のうちの前記一つは前記複数のプロセシング・コアのうちの他のものの他の電力状態とは独立である、方法。 - 前記第一の信号がある第一の電力状態に対応する場合、前記複数の電力状態のうちの前記一つが、前記複数のプロセシング・コアのうちの前記一つがデータ保持状態にあり、前記複数のプロセシング・コアのうちの前記一つ以外の残りが通常の動作状態にあるという出力を含む、請求項18記載の方法。
- 前記第一の信号がある第二の電力状態に対応する場合、前記複数の電力状態のうちの前記一つが、前記複数のプロセシング・コアのうちの前記一つを無効にすることを含む、請求項19記載の方法。
- 前記複数のプロセシング・コアのうちの前記一つが受ける電圧を調整することをさらに含む、請求項20記載の方法。
- 前記複数のプロセシング・コアのうちの前記一つが受けるクロック信号を調整することをさらに含む、請求項20記載の方法。
- 前記複数のプロセシング・コアのうちの前記一つが受けるクロック信号および電圧を調整することをさらに含む、請求項20記載の方法。
- 前記複数のプロセシング・コアがACPI規格に従って定義されたものである、請求項18記載の方法。
- それぞれが対応する出力を有する少なくとも二つのプロセシング・コアと;
前記少なくとも二つのプロセシング・コアのうちのある第一のプロセシング・コアの電力状態を、前記少なくとも二つのプロセシング・コアのうちのある第二のプロセシング・コアの電力状態とは独立に変更する電力制御論理とを有するプロセッサであって、前記第一のプロセシング・コアが、該第一のプロセシング・コアへの電圧を調整する少なくとも一つのパワー・トランジスタと、該第一のプロセシング・コアが受けるクロック信号を調整する少なくとも一つの位相ロック・ループ(PLL)を含んでいる、プロセッサ。 - 前記少なくとも二つのプロセシング・コアのうち前記第二のプロセシング・コアが、前記少なくとも二つのプロセシング・コアのうち前記第一のプロセシング・コアと共有されていない少なくとも一つのパワー・トランジスタおよび少なくとも一つのPLLを有する、請求項25記載のプロセッサ。
- 前記少なくとも二つのプロセシング・コアのうち前記第二のプロセシング・コアが、前記少なくとも二つのプロセシング・コアのうち前記第一のプロセシング・コアと共有されていない電力制御論理を含む、請求項26記載のプロセッサ。
- 前記少なくとも二つのプロセシング・コアのうち前記第一のプロセシング・コアが、データ保持電圧を受け取る電力状態に置かれ、前記少なくとも二つのプロセシング・コアのうち前記第一のプロセシング・コア以外の残りが通常の動作電圧を受け取る、請求項25記載のプロセッサ。
- 前記少なくとも二つのプロセシング・コアのうち前記第一のプロセシング・コアおよびその対応する出力が無効にされる、請求項25記載のプロセッサ。
- 他のコアまたは論理に関わりなくある電力状態に置かれるアンコア論理をさらに有する、請求項25記載のプロセッサ。
Applications Claiming Priority (1)
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US11/555,609 US7949887B2 (en) | 2006-11-01 | 2006-11-01 | Independent power control of processing cores |
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US (11) | US7949887B2 (ja) |
JP (1) | JP2008117397A (ja) |
KR (2) | KR100988396B1 (ja) |
CN (2) | CN101403944B (ja) |
DE (1) | DE102007051841B4 (ja) |
GB (1) | GB2444597B (ja) |
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