JP2008109043A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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Abstract
【解決手段】本願発明の半導体装置の製造方法では、半導体基板上に形成された第1の絶縁膜上に、互いに隣接するように複数の配線を形成する工程と、第1の絶縁膜上にプラズマCVD法により第2の絶縁膜を形成して、隣接する配線の配線間にエアーギャップが形成されるように配線を第2の絶縁膜により覆う工程と、第2の絶縁膜上に高密度プラズマCVD法により、第3の絶縁膜を形成する工程と、第3の絶縁膜上に耐湿性の高い第4の絶縁膜を形成する工程とを有する。
【選択図】図4
Description
このような構成は例えば特許文献1で開示されている。
さらに、本実施例の半導体装置は半導体記憶装置に関するものでありメモリセル101とメモリセル101からデータを読み出すビット線とを備える。
本実施例では、メモリセル領域110上に配置される配線300の配線幅wは0.376μmで、配線間隔dは0.264μmであり、周辺領域120上に配置される配線300の配線幅w´は0.80μmで、配線間隔d´は0.80μmである。
次に、図2に示されているように、第1の絶縁膜200上にプラズマCVD(Plasma Chemical Vapor Deposition)法により第2の絶縁膜500を形成して、隣接する配線300の配線間にエアーギャップ510が形成されるように配線300を第2の絶縁膜500により覆う。
さらに、プラズマCVD法による埋め込み性は、配線の間隔に対する配線の高さの比であるアスペクト比に依存し、配線300のうち配線間隔が狭い箇所でありアスペクト比が大きい箇所では、上述したように配線間が十分に第2の絶縁膜500で埋め込まれずに配線間にエアーギャップ510が形成される一方、配線間隔が広い箇所でありアスペクト比が高い箇所では、配線間が十分に第2の絶縁膜500で埋め込まれ、エアーギャップ510は形成されない。
つまり、エアーギャップ510は第2の絶縁膜500に比べて誘電率が低い為、配線間にエアーギャップ510を設けることで、配線間が全て第2の絶縁膜500で埋め込まれている構成と比べて、大幅に配線間容量を低減することが可能となる。これにより、配線300を伝達する信号の速度を大幅に向上させることが可能となる。
高密度プラズマCVD法による成膜では、堆積膜を削りながら成膜が行なわれるため、下地層に段差がある場合でも、平坦性の高い膜を成膜することが可能となる。
次に、第3の絶縁膜600上に、第2の絶縁膜500および第3の絶縁膜600よりも耐湿性の高い第4の絶縁膜700を形成する。
これにより、外部からの水分等の浸入を第4の絶縁膜700で十分に防ぐことが可能となり、半導体装置の耐湿性を向上させることが可能となる。
さらに、本実施例では、第4の絶縁膜700上に、第5の絶縁膜800が形成されている。
101 メモリセル
102 周辺トランジスタ
110 メモリセル領域
120 周辺領域
200,210 第1の絶縁膜
300,310 配線
320 電極パッド
400 多層配線層
500 第2の絶縁膜
510 エアーギャップ
600 第3の絶縁膜
700 第4の絶縁膜
800 第5の絶縁膜
Claims (16)
- 半導体基板上に形成された第1の絶縁膜上に、互いに隣接するように複数の配線を形成する工程と、
前記第1の絶縁膜上にプラズマCVD法により第2の絶縁膜を形成して、前記隣接する配線の配線間にエアーギャップが形成されるように前記配線を前記第2の絶縁膜により覆う工程と、
前記第2の絶縁膜上に高密度プラズマCVD法により、第3の絶縁膜を形成する工程と、
前記第3の絶縁膜上に、前記第2および前記第3の絶縁膜よりも耐湿性の高い第4の絶縁膜を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 前記半導体基板上には多層配線層が形成され、前記配線は、前記多層配線層の一部であり、前記多層配線層の最上層の配線であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2の絶縁膜は、シリコン酸化膜であることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第2の絶縁膜の膜厚は、3000Å以上であることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置の製造方法。
- 前記第3の絶縁膜は、シリコン酸化膜であることを特徴とする請求項1〜4のいずれか1つに記載の半導体装置の製造方法。
- 前記第4の絶縁膜は、シリコン窒化膜であることを特徴とする請求項1〜5のいずれかに記載の半導体装置の製造方法。
- 前記半導体装置は半導体記憶装置であり、前記半導体装置はメモリセルと前記メモリセルからデータを読み出すビット線とを備え、
前記配線は、前記ビット線に対応することを特徴とする請求項1〜6のいずれか1つに記載の半導体装置の製造方法。 - 前記半導体装置は半導体記憶装置であり、前記半導体基板はメモリセルが形成されるメモリセル領域と周辺トランジスタが形成される周辺領域とを備え、
前記メモリセル領域上に配置される前記隣接する配線の配線間に、前記エアーギャップが形成されることを特徴とする請求項1〜6のいずれか1つに記載の半導体装置の製造方法。 - 半導体基板と、
前記半導体基板上に形成された第1の絶縁膜と、
前記第1の絶縁膜上に互いに隣接するように形成された複数の配線と、
前記第1の絶縁膜上にCVD法により形成され、前記隣接する配線の配線間にエアーギャップが形成されるように前記配線を覆う第2の絶縁膜と、
前記第2の絶縁膜上に高密度プラズマCVD法により形成された第3の絶縁膜と、
前記第3の絶縁膜上に形成され、前記第2および前記第3の絶縁膜よりも耐湿性の高い第4の絶縁膜と、
を有することを特徴とする半導体装置。 - 前記半導体基板上には多層配線層が形成され、前記配線は、前記多層配線層の一部であり、前記多層配線層の最上層の配線であることを特徴とする請求項9に記載の半導体装置。
- 前記第2の絶縁膜は、シリコン酸化膜であることを特徴とする請求項9または10に記載の半導体装置。
- 前記第2の絶縁膜の膜厚は、3000Å以上であることを特徴とする請求項9〜11のいずれか1つに記載の半導体装置。
- 前記第3の絶縁膜は、シリコン酸化膜であることを特徴とする請求項9〜12のいずれか1つに記載の半導体装置。
- 前記第4の絶縁膜は、シリコン窒化膜であることを特徴とする請求項9〜13のいずれかに記載の半導体装置。
- 前記半導体装置は半導体記憶装置であり、前記半導体装置はメモリセルと前記メモリセルからデータを読み出すビット線とを備え、
前記配線は、前記ビット線に対応することを特徴とする請求項9〜14のいずれか1つに記載の半導体装置。 - 前記半導体装置は半導体記憶装置であり、前記半導体基板はメモリセルが形成されるメモリセル領域と周辺トランジスタが形成される周辺領域とを備え、
前記メモリセル領域上に配置される前記隣接する配線の配線間に、前記エアーギャップが形成されることを特徴とする請求項9〜14のいずれか1つに記載の半導体装置。
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JP2011181898A (ja) * | 2010-02-04 | 2011-09-15 | Tokyo Ohka Kogyo Co Ltd | エアギャップ形成用シリカ系被膜形成材料及びエアギャップ形成方法 |
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US7867890B2 (en) | 2011-01-11 |
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