JP2008085111A - Wiring board and manufacturing method therefor - Google Patents

Wiring board and manufacturing method therefor Download PDF

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JP2008085111A
JP2008085111A JP2006264043A JP2006264043A JP2008085111A JP 2008085111 A JP2008085111 A JP 2008085111A JP 2006264043 A JP2006264043 A JP 2006264043A JP 2006264043 A JP2006264043 A JP 2006264043A JP 2008085111 A JP2008085111 A JP 2008085111A
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layer
wiring board
core substrate
build
manufacturing
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Sadashi Nakamura
禎志 中村
Fumio Echigo
文雄 越後
Toshio Sugawa
俊夫 須川
Ayako Iwazawa
綾子 岩澤
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of suppressing warpage and swell that occur due to heat history even if the wiring board has a thin core substrate. <P>SOLUTION: The build-up wiring board comprises: a core substrate 24 having a first via 23 that is filled with a conductive paste 22 for making interlayer connection in via holes that are formed on an insulating layer 21; and a build-up layer 26 that is formed on at least one surface of the core substrate 24 and that is formed with a second via 25 for making interlayer connection. The core substrate 24 is constituted of a resin composite insulating material containing a core material made of an organic fiber or an inorganic fiber, and has a thickness of 200 μm or less. The build-up layer 26 has a thickness equal to or larger than a minimum thickness that assures interlayer insulation, and is constituted of a film-shaped resin insulating material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、パソコン、移動体通信用電話機、ビデオカメラ等の各種電子機器に広く用いられる多層配線基板およびその製造方法に関するものである。   The present invention relates to a multilayer wiring board widely used in various electronic devices such as personal computers, mobile communication telephones, and video cameras, and a method for manufacturing the same.

最近、モバイル商品としてパソコン、デジタルカメラ、携帯電話などが普及し、特にその小型、薄型、軽量、高精細、多機能化等の要望が強く、それに対応するため多層プリント配線板の最外層における絶縁層の薄型化、およびビアの小径化が求められている。   Recently, personal computers, digital cameras, mobile phones, etc. have become popular as mobile products, and there is a strong demand for miniaturization, thinness, lightness, high definition, multi-functionality, etc. There is a demand for thinner layers and smaller via diameters.

以下に従来の多層プリント配線板の製造方法について説明する。先ず、回路パターンが形成されたコア基板上の片面又は両面上の少なくとも該パターン加工部分に、接着フィルムの樹脂組成物層を直接覆い重ねた状態で、市販の真空積層機を用いて、真空条件下、加熱、加圧し積層する。上記接着フィルムに保護フィルムが存在している場合には保護フィルムを除去後、真空条件下、樹脂組成物層を支持ベースフィルム側より加圧、加熱しながら貼り合わせる。ラミネート時の樹脂流れが内層回路の導体厚以上である条件でラミネートすることにより、内層回路パターンの被覆が良好に行われる。   A conventional method for manufacturing a multilayer printed wiring board will be described below. First, in a state where the resin composition layer of the adhesive film is directly covered on at least the pattern processed part on one side or both sides on the core substrate on which the circuit pattern is formed, a vacuum condition is used using a commercially available vacuum laminating machine. Then, heat and pressurize and laminate. When the protective film is present on the adhesive film, the protective film is removed, and then the resin composition layer is bonded under pressure and heat from the support base film side under vacuum conditions. By laminating under the condition that the resin flow during lamination is equal to or greater than the conductor thickness of the inner layer circuit, the inner layer circuit pattern is satisfactorily covered.

次に、該樹脂組成物を熱硬化する。その後、レーザ及び／又はドリルにより穴開けを行う。穴開けには、市販の炭酸ガス、ＵＶ−ＹＡＧ、エキシマ等のレーザ穴開け機及び／又はドリル穴開け機を使用して、公知慣用の方法で所定の位置に行える。接着フィルムは支持ベースフィルムに離型層を有していることにより、熱硬化性樹脂組成物の熱硬化後に容易に剥離できる。   Next, the resin composition is thermoset. Thereafter, drilling is performed with a laser and / or a drill. The hole can be formed in a predetermined position by a known and conventional method using a commercially available laser driller such as carbon dioxide, UV-YAG, excimer and / or a drill puncher. Since the adhesive film has a release layer on the support base film, the adhesive film can be easily peeled off after thermosetting of the thermosetting resin composition.

その後、該樹脂組成物表面を粗化処理し、次いでその上層に導体層をめっきにより形成する。このように樹脂組成物表面に凸凹のアンカーを形成した後、無電解、電解めっき等のめっきにより導体層を形成する。その後、公知慣用のサブトラクティブ法やセミアディティブ法に従って、回路を形成する。   Thereafter, the surface of the resin composition is roughened, and then a conductor layer is formed thereon by plating. After forming uneven anchors on the surface of the resin composition in this manner, a conductor layer is formed by plating such as electroless or electrolytic plating. Thereafter, a circuit is formed according to a known and commonly used subtractive method or semi-additive method.

なお、この発明の出願に関連する先行技術文献情報としては、例えば、特許文献１、２が知られている。
特開２００１−１９６７４３号公報 特許第３７８５７４９号公報 For example, Patent Documents 1 and 2 are known as prior art document information related to the application of the present invention.
JP 2001-196743 A Japanese Patent No. 378549

コア基板に厚み、剛性があればコア基板とビルドアップ層に熱膨張係数差があってもコア基板が反りやうねりの発生原因となる内部応力が発生しても抑制することが可能であるが、コア基板が薄いとき、特に２００μｍ以下になると、従来の製造方法では、特にビルドアップ層の半硬化工程において、コア基板とビルドアップ層の熱膨張係数が大幅に異なるためにコア基板が反りやうねりの発生原因となる内部応力を抑えきれなくなり、基板の平坦形状を維持することが困難となっていた。そのため、薄いコア基板を用いてビルドアップ層を形成したビルドアップ多層基板を形成することは困難であった。本発明は、上記課題を鑑みて成されたものであり、ビルドアップ層を半硬化するときに発生する内部応力を抑制することにより、基板の平坦形状を良好に維持するものである。   If the core substrate has thickness and rigidity, even if there is a difference in thermal expansion coefficient between the core substrate and the build-up layer, it is possible to suppress the occurrence of internal stress that causes the warp and undulation of the core substrate. When the core substrate is thin, especially when the thickness is 200 μm or less, the conventional manufacturing method, particularly in the semi-curing process of the build-up layer, causes the core substrate and the build-up layer to greatly warp. It has become difficult to maintain the flat shape of the substrate because the internal stress that causes undulation cannot be suppressed. Therefore, it has been difficult to form a buildup multilayer substrate in which a buildup layer is formed using a thin core substrate. The present invention has been made in view of the above problems, and maintains the flat shape of a substrate satisfactorily by suppressing internal stress generated when the buildup layer is semi-cured.

上記目的を達成するために、本発明は、絶縁層にビアホールが形成されこれらのビアホール内に層間接続するための導電性ペーストが充填された第１のビアを有するコア基板と、このコア基板の少なくとも一方の面に形成され層間接続するための第２のビアが形成されたビルドアップ層とを有するビルドアップ配線板であって、前記コア基板が有機繊維あるいは無機繊維からなる芯材を含む樹脂複合絶縁材料で構成され、かつ厚みが２００μｍ以下であり、前記ビルドアップ層はその厚さが層間絶縁性を確保できる最小の厚さ以上確保され、かつフィルム状の樹脂絶縁材料で構成される配線基板のビルドアップ層を半硬化する工程において、前記ビルドアップ層を加圧加熱しながら硬化させる配線基板の製造方法を用いている。このような構成にすることにより、基板内に発生する内部応力を抑制することができ、反りやうねりが抑制された配線基板を得ることが可能となる。   In order to achieve the above object, the present invention provides a core substrate having a first via in which via holes are formed in an insulating layer and a conductive paste for interlayer connection is filled in these via holes, A build-up wiring board having a build-up layer formed on at least one surface and having a second via for interlayer connection, wherein the core substrate includes a core material made of organic fiber or inorganic fiber Wiring made of a composite insulating material and having a thickness of 200 μm or less, the build-up layer having a minimum thickness that can ensure interlayer insulation, and a film-like resin insulating material In the step of semi-curing the build-up layer of the substrate, a method of manufacturing a wiring board is used in which the build-up layer is cured while being heated under pressure. By adopting such a configuration, it is possible to suppress internal stress generated in the substrate and to obtain a wiring substrate in which warpage and undulation are suppressed.

以上のように本発明は、ビルドアップ層を半硬化する工程において、コア基板の剛性不足によって発生する反りやうねりを加圧加熱しながら硬化させる製造方法を用いることによりコア基板が薄い場合においてもビルドアップ層を半硬化する工程において発生する反りやうねりを抑制することができ、コア基板の厚さが２００μｍ以下の薄型のビルドアップ配線基板を得ることが可能となる。   As described above, even when the core substrate is thin in the process of semi-curing the build-up layer, the present invention uses a manufacturing method in which warpage and undulation caused by insufficient rigidity of the core substrate are cured while being pressurized and heated. Warpage and undulation generated in the process of semi-curing the build-up layer can be suppressed, and a thin build-up wiring board with a core board thickness of 200 μm or less can be obtained.

（実施の形態１）
以下本発明の実施の形態１について、図面を参照しながら説明する。 (Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.

図１，図２は、本発明の実施の形態１における配線基板の断面図である。図１，図２に示すように、本実施の形態の配線基板は、絶縁層２１にビアホールが形成され、これらのビアホール内に層間接続するための導電性ペースト２２が充填された第１のビア２３を有するコア基板２４と、このコア基板２４の少なくとも一方の面に形成され、層間接続するための第２のビア２５が形成されたビルドアップ層２６とを有する構成となっている。さらに、コア基板２４は、有機繊維あるいは無機繊維からなる芯材を含む樹脂複合絶縁材料で構成され、かつ厚みが２００μｍ以下である。また、ビルドアップ層２６は、その厚さが層間絶縁性を確保できる最小の厚さすなわち２０μｍ以上確保され、かつフィルム状の樹脂絶縁材料で構成されている。   1 and 2 are cross-sectional views of a wiring board according to Embodiment 1 of the present invention. As shown in FIGS. 1 and 2, in the wiring substrate of the present embodiment, via holes are formed in the insulating layer 21, and the first vias filled with the conductive paste 22 for interlayer connection are filled in these via holes. 23, and a build-up layer 26 formed on at least one surface of the core substrate 24 and having a second via 25 for interlayer connection. Furthermore, the core substrate 24 is made of a resin composite insulating material including a core material made of organic fibers or inorganic fibers, and has a thickness of 200 μm or less. The build-up layer 26 has a minimum thickness that can ensure interlayer insulation, that is, 20 μm or more, and is made of a film-like resin insulating material.

本実施の形態では、コア基板２４が芯材を含む樹脂複合絶縁材料で構成されているが、厚みが２００μｍ以下であるためビルドアップ層の半硬化工程における熱履歴により発生する反りやうねりをコア基板の剛性のみで抑制することは困難である。   In the present embodiment, the core substrate 24 is made of a resin composite insulating material including a core material. However, since the thickness is 200 μm or less, the warp and undulation generated by the heat history in the semi-curing process of the build-up layer is the core. It is difficult to suppress only by the rigidity of the substrate.

また、本実施の形態において、コア基板２４の熱膨張係数がビルドアップ層２６の熱膨張係数よりも小さく、具体的にはコア基板２４の熱膨張係数が５〜３０ｐｐｍ／℃、ビルドアップ層２６の熱膨張係数が１００〜２００ｐｐｍ／℃であるため、熱膨張係数差も大きく、これに起因する内部応力によって発生する反りやうねりもコア基板の剛性のみで抑制することは困難である。   In the present embodiment, the thermal expansion coefficient of the core substrate 24 is smaller than the thermal expansion coefficient of the buildup layer 26. Specifically, the thermal expansion coefficient of the core substrate 24 is 5 to 30 ppm / ° C. Therefore, it is difficult to suppress warpage and undulation caused by internal stress due to this only by the rigidity of the core substrate.

そこで、図３（ｅ）に示すような、加圧加熱しながらビルドアップ層２６を半硬化させる方法を用いて、ビルドアップ層を半硬化するときに発生する内部応力を抑制することにより、基板の平坦形状を良好に維持している。   Therefore, by using a method of semi-curing the build-up layer 26 while being heated under pressure as shown in FIG. 3 (e), the internal stress generated when the build-up layer is semi-cured is suppressed. The flat shape is maintained well.

なお、本実施の形態において、第２のビア２５の形状は、図１のようなコンフォーマルビアであっても、図２のようなフィルドビアであっても良い。   In the present embodiment, the shape of the second via 25 may be a conformal via as shown in FIG. 1 or a filled via as shown in FIG.

以上のように、コア基板を有機繊維あるいは無機繊維からなる芯材を含む樹脂複合絶縁材料で、かつビルドアップ層をその厚さが層間絶縁性を確保できる最小の厚さ以上確保される構成としているので、コア基板が２００μｍ以下のような薄い場合においても、反りやうねりを抑制することができる配線基板を得ることが可能となる。   As described above, the core substrate is a resin composite insulating material including a core material made of organic fibers or inorganic fibers, and the build-up layer has a thickness that is ensured to be more than the minimum thickness that can ensure interlayer insulation. Therefore, even when the core substrate is as thin as 200 μm or less, it is possible to obtain a wiring substrate capable of suppressing warpage and undulation.

以下本発明の配線基板の製造方法について、図面を参照しながら説明する。   Hereinafter, a method of manufacturing a wiring board according to the present invention will be described with reference to the drawings.

図３，図４は本発明の配線基板の製造方法を示す工程断面図である。   3 and 4 are process cross-sectional views showing a method for manufacturing a wiring board according to the present invention.

まず、絶縁層２１にビアホール２０を形成し（図３，４（ａ））、ビアホール２０に導電性ペースト２２を充填し、第１のビア２３を形成する（図３，４（ｂ））。次に、絶縁層２１の表面に配線パターン２７を形成して、コア基板２４を形成する（図３，４（ｃ））。本実施の形態におけるコア基板は、有機繊維あるいは無機繊維からなる芯材を含む樹脂複合絶縁材料で構成され、かつ厚みが２００μｍ以下である。   First, a via hole 20 is formed in the insulating layer 21 (FIGS. 3 and 4 (a)), and the via hole 20 is filled with a conductive paste 22 to form a first via 23 (FIGS. 3 and 4 (b)). Next, the wiring pattern 27 is formed on the surface of the insulating layer 21 to form the core substrate 24 (FIGS. 3 and 4 (c)). The core substrate in the present embodiment is made of a resin composite insulating material including a core material made of organic fibers or inorganic fibers, and has a thickness of 200 μm or less.

その後、コア基板２４の少なくとも一方の面に、例えばフィルム状のエポキシ樹脂からなる樹脂絶縁材料で構成されたビルドアップ層２６を真空ラミネータを用い、真空条件下で加圧加熱してラミネートし形成する（図３，４（ｄ））。ビルドアップ層２６の厚さは、層間絶縁性が確保される最小の導体間距離である２０μｍ以上必要であり、かつフィルム状の樹脂絶縁材料で構成されている。また、コア基板２４の熱膨張係数はビルドアップ層２６の熱膨張係数より小さいものを用いており、コア基板の熱膨張係数は５〜３０ｐｐｍ／℃、ビルドアップ層の熱膨張係数は１００〜２００ｐｐｍ／℃である。   Thereafter, a buildup layer 26 made of a resin insulating material made of, for example, a film-like epoxy resin is laminated on at least one surface of the core substrate 24 by using a vacuum laminator and pressurizing and heating under vacuum conditions. (FIGS. 3 and 4 (d)). The thickness of the buildup layer 26 is required to be 20 μm or more, which is the minimum distance between conductors that ensures interlayer insulation, and is made of a film-like resin insulating material. Further, the thermal expansion coefficient of the core substrate 24 is smaller than that of the buildup layer 26, the thermal expansion coefficient of the core substrate is 5 to 30 ppm / ° C., and the thermal expansion coefficient of the buildup layer is 100 to 200 ppm. / ° C.

次に、第１の硬化工程として、ビルドアップ層２６を積層した基板の上下を、フッ素樹脂からなる離型性を有するシート３１を挟み、さらにシート３１の上下をステンレス等の金属からなる剛性板２８で挟んで、温度９０〜１７０℃、圧力５．５Ｋｇ以下の条件で加圧加熱しながらビルドアップ層２６を半硬化させる（図３，４（ｅ））。本工程で使用するシート３１の熱膨張係数は、コア基板２４の熱膨張係数と概同等あるいはそれ以上で、かつビルドアップ層２６の熱膨張係数よりも小さい数値であり、本実施の形態において使用したコア基板の熱膨張係数は１２〜１４ｐｐｍ／℃のものを用いた。   Next, as a first curing step, the substrate 31 on which the build-up layer 26 is stacked is sandwiched between sheets 31 having a releasability made of fluororesin, and the sheet 31 is a rigid plate made of metal such as stainless steel. 28, the buildup layer 26 is semi-cured while being heated under pressure under conditions of a temperature of 90 to 170 ° C. and a pressure of 5.5 kg or less (FIGS. 3 and 4 (e)). The thermal expansion coefficient of the sheet 31 used in this step is a numerical value approximately equal to or higher than the thermal expansion coefficient of the core substrate 24 and smaller than the thermal expansion coefficient of the buildup layer 26, and is used in the present embodiment. The core substrate having a thermal expansion coefficient of 12 to 14 ppm / ° C. was used.

本実施の形態では、シート３１を挟むことにより、ビルドアップ層２６と剛性板２８との熱膨張係数の差を緩和することができ、その結果基板内の内部応力を緩和することが可能となる。また、図３，４（ｅ）の工程において、半硬化時の圧力は、配線板の平坦性を維持できる圧力以上であり、かつ次工程以降での粗化工程において粗化形状にムラを生じない圧力である。   In the present embodiment, by sandwiching the sheet 31, the difference in thermal expansion coefficient between the buildup layer 26 and the rigid plate 28 can be reduced, and as a result, the internal stress in the substrate can be reduced. . 3 and 4 (e), the pressure at the time of semi-curing is equal to or higher than the pressure capable of maintaining the flatness of the wiring board, and the roughened shape is uneven in the subsequent roughening steps. There is no pressure.

ここで、「粗化形状のムラ」に関して言及する。この粗化処理は、次工程のレーザビア加工の後に実施される工程で、半硬化した後のビルドアップ層の表面に施すものである。主な目的は２つで、レーザ加工後にビア内に生じる加工後の樹脂残渣や炭化物の除去と、次工程で形成されるめっき膜とビルドアップ層との密着性向上のためである。特にめっき膜との密着性を向上させるための粗化は、粗化処理条件でも形状変化を生じるが、ビルドアップ層のラミネート条件や半硬化条件、特に圧力パラメータによって形状変化を起こしやすい。本実施の形態で用いたビルドアップ層は半硬化状態のとき、硬化状態と未硬化状態の分子がランダムに混在しており、粗化処理工程で未硬化部分を溶解することで粗化形状を形成するものであるが、ラミネート工程や半硬化工程において加熱と同時に圧力が加わる場合、表面近くの樹脂分子が圧力によって潰され、結果として粗化形状に変化を生じるのである。従って、圧力が高ければ高いほど樹脂分子が潰されてしまい「粗化形状のムラ」を生じ易くなる。「粗化形状のムラ」を生じるとめっき膜との密着性にもムラが生じ、基板面内の導体密着力にばらつきを生じることにつながるため、基板の信頼性劣化の一因となる可能性が高くなるのである。ところで、粗化形状の形成のみに限っていえば、圧力が低ければ低いほど均一で細かい粗化形状を形成でき、圧力なしの状態が最も理想的な粗化形状が形成できる。しかしながら、ラミネート工程や、本発明のように基板の平坦形状を維持するためには加圧は不可欠であり、「粗化形状のムラ」を生じない程度の圧力をかけざるを得ないのである。実験的に検証した結果、本実施の形態では５．５Ｋｇ／ｃｍ２以下の圧力であれば「粗化形状のムラ」を生じないことがわかっている。 Here, reference will be made to “roughness unevenness”. This roughening treatment is a step performed after the laser via processing in the next step, and is performed on the surface of the buildup layer after semi-curing. There are two main purposes, which are to remove post-processing resin residues and carbides generated in the via after laser processing and to improve the adhesion between the plating film formed in the next process and the build-up layer. In particular, the roughening for improving the adhesion to the plating film causes a change in shape even under the roughening conditions, but the shape is likely to change depending on the laminating conditions and the semi-curing conditions of the build-up layer, particularly the pressure parameter. When the build-up layer used in the present embodiment is in a semi-cured state, the cured and uncured molecules are mixed at random, and the roughened shape is obtained by dissolving the uncured part in the roughening treatment step. Although it is formed, when pressure is applied simultaneously with heating in the laminating process or semi-curing process, resin molecules near the surface are crushed by the pressure, resulting in a change in the roughened shape. Therefore, the higher the pressure is, the more the resin molecules are crushed and the “roughness of the roughened shape” is likely to occur. If "roughness of the roughened shape" occurs, the adhesion to the plating film also becomes uneven, leading to variations in the conductor adhesion within the substrate surface, which may contribute to deterioration of the reliability of the substrate. Will be higher. By the way, if it is limited only to the formation of the rough shape, the lower the pressure, the more uniform and fine rough shape can be formed, and the most ideal rough shape can be formed without pressure. However, pressurization is indispensable in order to maintain the flat shape of the substrate as in the laminating process or the present invention, and it is necessary to apply a pressure that does not cause “unevenness of the roughened shape”. As a result of experimental verification, it has been found that in this embodiment, if the pressure is 5.5 kg / cm 2 or less, “roughening of the roughened shape” does not occur.

半硬化工程の後、ビルドアップ層２６に、炭酸ガスやＵＶなどのレーザによって層間接続をとるための第２のビア２５を形成し（図３，４（ｆ））、ビルドアップ層２６の表面と第２のビア２５の内壁面を粗化する（図３，４（ｇ））。その後、めっき等によりビルドアップ層２６の表面に金属層２９を形成し（図３，４（ｈ））、さらに配線パターン３０を形成し、その後第２の硬化工程により本硬化させることにより配線基板を完成させる（図３，４（ｉ））。   After the semi-curing process, the build-up layer 26 is formed with a second via 25 for interlayer connection with a laser such as carbon dioxide or UV (FIGS. 3 and 4 (f)), and the surface of the build-up layer 26 is formed. Then, the inner wall surface of the second via 25 is roughened (FIGS. 3 and 4 (g)). Thereafter, a metal layer 29 is formed on the surface of the build-up layer 26 by plating or the like (FIGS. 3 and 4 (h)), a wiring pattern 30 is further formed, and then a main curing is performed in a second curing step. Is completed (FIGS. 3, 4 (i)).

なお、本実施の形態では、第２のビア２５の形状を、図３のようにコンフォーマルビアで形成しても、図４のようにフィルドビアで形成しても良い。   In the present embodiment, the shape of the second via 25 may be formed by a conformal via as shown in FIG. 3 or a filled via as shown in FIG.

以上のように、本実施の形態によれば、第１の硬化工程においてビルドアップ層を加熱加圧しながら硬化させるので、コア基板が２００μｍ以下のような薄い場合においても、熱履歴により発生する反りやうねりを抑制することができる配線基板を得ることが可能となる。   As described above, according to the present embodiment, the build-up layer is cured while being heated and pressurized in the first curing step. Therefore, even when the core substrate is as thin as 200 μm or less, the warp caused by the thermal history is generated. It is possible to obtain a wiring board capable of suppressing waviness and undulation.

本発明にかかるビルドアップ多層プリント配線基板は総厚を薄型に形成でき、また層間接続構造は、高い層間接続信頼性を得ることができるため、微細な配線パターンや半導体実装等のより高い信頼性基準を満足する必要のある半導体パッケージや小型モジュール部品等の実装基板に関する用途に適用できる。   Since the build-up multilayer printed wiring board according to the present invention can be formed with a thin total thickness, and the interlayer connection structure can obtain high interlayer connection reliability, higher reliability such as fine wiring patterns and semiconductor mounting can be obtained. It can be applied to applications related to mounting substrates such as semiconductor packages and small module parts that need to satisfy the standards.

本発明の実施の形態における配線基板を示す断面図Sectional drawing which shows the wiring board in embodiment of this invention 本発明の実施の形態における配線基板を示す断面図Sectional drawing which shows the wiring board in embodiment of this invention 本発明の実施の形態における配線基板の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the wiring board in embodiment of this invention 本発明の実施の形態における配線基板の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the wiring board in embodiment of this invention

符号の説明Explanation of symbols

２０ ビアホール
２１ 絶縁層
２２ 導電性ペースト
２３ 第１のビア
２４ コア基板
２５ 第２のビア
２６ ビルドアップ層
２７，３０ 配線パターン
２８ 剛性板
２９ 金属層
３１ シート 20 Via hole 21 Insulating layer 22 Conductive paste 23 First via 24 Core substrate 25 Second via 26 Build-up layer 27, 30 Wiring pattern 28 Rigid plate 29 Metal layer 31 Sheet

Claims (8)

絶縁層にビアホールが形成されこれらのビアホール内に層間接続するための導電性ペーストが充填された第１のビアを有するコア基板と、このコア基板の少なくとも一方の面に形成され層間接続するための第２のビアが形成されたビルドアップ層とを有するビルドアップ配線板であって、前記コア基板が有機繊維あるいは無機繊維からなる芯材を含む樹脂複合絶縁材料で構成され、かつ厚みが２００μｍ以下であり、前記ビルドアップ層はその厚さが層間絶縁性を確保できる最小の厚さ以上確保され、かつフィルム状の樹脂絶縁材料で構成されていることを特徴とする配線基板。 A core substrate having a first via formed in the insulating layer and filled with a conductive paste for interlayer connection in the via hole, and formed on at least one surface of the core substrate for interlayer connection A build-up wiring board having a build-up layer in which a second via is formed, wherein the core substrate is made of a resin composite insulating material including a core material made of organic fibers or inorganic fibers, and has a thickness of 200 μm or less. The build-up layer has a thickness of at least a minimum thickness that can ensure interlayer insulation, and is made of a film-like resin insulating material. コア基板の熱膨張係数がビルドアップ層の熱膨張係数よりも小さいことを特徴とする請求項１に記載の配線基板。 The wiring board according to claim 1, wherein a thermal expansion coefficient of the core substrate is smaller than a thermal expansion coefficient of the buildup layer. 絶縁層にビアホールを形成する工程と、前記ビアホールに導電性ペーストを充填して第１のビアを形成する工程と、前記絶縁層表面に配線パターンを形成してコア基板を形成する工程と、前記コア基板の少なくとも一面にビルドアップ層をラミネートする工程と、前記ビルドアップ層を第１の硬化工程により半硬化させる工程と、前記ビルドアップ層に第２のビアを形成する工程と、前記ビルドアップ層表面と第２のビア内壁面を粗化する工程と、前記ビルドアップ層表面と第２のビア内に金属層を形成する工程と、前記金属層をパターニングする工程と、前記ビルドアップ層を第２の硬化工程により本硬化させる工程と、を備えた配線基板の製造方法であって、前記第１の硬化工程は前記ビルドアップ層を加圧加熱しながら硬化させる配線基板の製造方法。 Forming a via hole in the insulating layer; filling the via hole with a conductive paste to form a first via; forming a wiring pattern on the surface of the insulating layer to form a core substrate; A step of laminating a buildup layer on at least one surface of the core substrate, a step of semi-curing the buildup layer by a first curing step, a step of forming a second via in the buildup layer, and the buildup A step of roughening a layer surface and an inner wall surface of the second via, a step of forming a metal layer in the surface of the buildup layer and the second via, a step of patterning the metal layer, and the buildup layer A wiring board manufacturing method comprising: a main curing step according to a second curing step, wherein the first curing step cures the build-up layer while being pressurized and heated. Method of manufacturing the plate. 第１の硬化工程は、ビルドアップ層と剛性板との間に離型性を有するシートを介して加圧加熱しながら硬化させることを特徴とする請求項３に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 3, wherein the first curing step is performed while being pressurized and heated through a sheet having releasability between the buildup layer and the rigid plate. 第１の硬化工程における圧力は、配線基板の平坦性を維持できる圧力以上であり、かつ次工程での粗化工程において粗化形状にムラを生じない圧力に抑制されることを特徴とする請求項３に記載の配線基板の製造方法。 The pressure in the first curing step is equal to or higher than a pressure capable of maintaining the flatness of the wiring board, and is suppressed to a pressure that does not cause unevenness in the roughened shape in the roughening step in the next step. Item 4. A method for manufacturing a wiring board according to Item 3. コア基板の熱膨張係数がビルドアップ層の熱膨張係数よりも小さいものを用いて形成する請求項３に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 3, wherein the core board is formed by using a coefficient of thermal expansion smaller than that of the buildup layer. 離型性を有するシートの熱膨張係数は、コア基板の熱膨張係数以上であり、かつビルドアップ層の熱膨張係数よりも小さいことを特徴とする請求項４に記載の配線基板の製造方法。 The method of manufacturing a wiring board according to claim 4, wherein the sheet having releasability has a thermal expansion coefficient equal to or greater than a thermal expansion coefficient of the core substrate and smaller than a thermal expansion coefficient of the buildup layer. 離型性を有するシートは、フッ素樹脂からなる請求項４に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 4, wherein the sheet having releasability is made of a fluororesin.
JP2006264043A 2006-09-28 2006-09-28 Wiring board and manufacturing method therefor Pending JP2008085111A (en)

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