JP2008042184A - Semiconductor device for high frequency - Google Patents

Semiconductor device for high frequency Download PDF

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JP2008042184A
JP2008042184A JP2007181996A JP2007181996A JP2008042184A JP 2008042184 A JP2008042184 A JP 2008042184A JP 2007181996 A JP2007181996 A JP 2007181996A JP 2007181996 A JP2007181996 A JP 2007181996A JP 2008042184 A JP2008042184 A JP 2008042184A
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semiconductor device
air bridge
region
electrode
frequency semiconductor
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Masaki Kobayashi
正樹 小林
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4821—Bridge structure with air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01013—Aluminum [Al]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for high frequencies capable of restraining the occurrence of defects, such as deterioration in the output characteristics, and of obtaining satisfactory reliability. <P>SOLUTION: The semiconductor device for high frequencies comprises an operation region 12 formed on a compound semiconductor substrate 11; a gate electrode 13 formed on the operation region 12; source and drain electrodes 14, 15 alternately formed on the operating region 12, while they sandwich the gate electrode 13; bonding pads 18, 19 connected to external circuit; and an air bridge 20, of which one end is connected to either the source electrode 14 or to the drain electrode 15 above a region outside the operating region 12, and the other end is connected to the bonding pads 18, 19. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、例えば高周波で用いられる電界効果トランジスタなどの高周波用半導体装置に関する。   The present invention relates to a high-frequency semiconductor device such as a field effect transistor used at high frequency.

近年、インバータ回路やスイッチング素子の高機能化に伴い、電界効果トランジスタ（以下Field Effect Transistor：ＦＥＴと記す）において、さらなる高周波特性、信頼性の向上が要求されている。   2. Description of the Related Art In recent years, with higher functionality of inverter circuits and switching elements, field effect transistors (hereinafter referred to as field effect transistors: FETs) are required to further improve high frequency characteristics and reliability.

そのため、例えば、マルチフィンガー型のＦＥＴが用いられる。マルチフィンガー型のＦＥＴにおいて、複数のゲート電極が動作領域を横切るように形成される。複数のゲート電極は、動作領域と平行に形成されるゲート配線と接続される。また、ソース電極／ドレイン電極は、動作領域上にゲート電極を挟んで交互に形成される。そして、それぞれソース／ドレイン配線によりボンディングパッドと接続される。このとき、ゲート配線とソース／ドレイン配線が交差してしまうが、これらを絶縁するために、ゲート配線上にＳｉＮなどのパシベーション膜が形成される。   Therefore, for example, a multi-finger type FET is used. In a multi-finger type FET, a plurality of gate electrodes are formed so as to cross the operation region. The plurality of gate electrodes are connected to a gate wiring formed in parallel with the operation region. The source / drain electrodes are alternately formed on the operation region with the gate electrode interposed therebetween. Each is connected to a bonding pad by source / drain wiring. At this time, the gate wiring and the source / drain wiring cross each other. In order to insulate them, a passivation film such as SiN is formed on the gate wiring.

しかしながら、このように、誘電率の高いＳｉＮなどのパシベーション膜上に、直接配線を形成することにより、浮遊容量が発生する。特に高周波領域において無視できなくなる。そこで、この浮遊容量を低減するために、空隙を介して上層配線を形成するエアブリッジ構造が用いられている（例えば特許文献１、２参照）。   However, the stray capacitance is generated by directly forming the wiring on the passivation film such as SiN having a high dielectric constant. In particular, it cannot be ignored in the high frequency region. Therefore, in order to reduce the stray capacitance, an air bridge structure is used in which an upper layer wiring is formed through a gap (see, for example, Patent Documents 1 and 2).

このようなエアブリッジ構造におけるソース／ドレイン電極は、動作領域上に例えばＰｔ／ＡｕＧｅなどのオーミックコンタクトと、例えばＡｕ／Ｐｔ／Ｔｉなどのメタル層が順次積層されて形成される。そして、これらメタル層上全面とソース／ドレインボンディングパッドが形成される領域、及びこれらを接続する領域に、例えばＡｕの単層メッキ層が形成され、エアブリッジなどが形成される。   The source / drain electrodes in such an air bridge structure are formed by sequentially laminating an ohmic contact such as Pt / AuGe and a metal layer such as Au / Pt / Ti on the operation region. Then, an Au single-layer plating layer, for example, is formed on the entire surface of the metal layer, the region where the source / drain bonding pads are formed, and the region connecting them, and an air bridge is formed.

エアブリッジを構成するＡｕは、ＧａＡｓ基板など化合物半導体基板より熱膨張率が大きい。従って、メッキ形成温度（例えば６０℃）から、通電温度（例えば加速評価条件の２２５℃）や、非通電時の温度（例えば常温２５℃）のように温度が変動することにより、エアブリッジにおいて、熱膨張、熱収縮が生じる。そして、このような熱膨張、熱収縮により、動作領域に圧縮応力、引張り応力といった大きな内部応力が発生する。そのため、出力特性が劣化するなどの不具合が生じ、良好な信頼性を得ることが困難であるという問題がある。
特開平９−８０６４号公報（図１など） 特開２００１−１５５２６号公報（図１、［０００４］など） Au constituting the air bridge has a larger coefficient of thermal expansion than a compound semiconductor substrate such as a GaAs substrate. Therefore, in the air bridge, the temperature fluctuates from the plating formation temperature (for example, 60 ° C.) to the energization temperature (for example, acceleration evaluation condition 225 ° C.) and the temperature at the time of non-energization (for example, normal temperature 25 ° C.) Thermal expansion and contraction occur. Due to such thermal expansion and contraction, large internal stresses such as compressive stress and tensile stress are generated in the operating region. For this reason, problems such as degradation of output characteristics occur, and it is difficult to obtain good reliability.
Japanese Patent Laid-Open No. 9-8064 (FIG. 1 etc.) Japanese Patent Laid-Open No. 2001-15526 (FIG. 1, [0004], etc.)

本発明は、出力特性劣化などの不具合の発生を抑え、良好な信頼性を得ることが可能な高周波用半導体装置を提供することを目的とするものである。   An object of the present invention is to provide a high-frequency semiconductor device capable of suppressing the occurrence of defects such as output characteristic deterioration and obtaining good reliability.

本発明の一態様によれば、化合物半導体基板に形成される動作領域と、動作領域上に形成されるゲート電極と、動作領域上にゲート電極を挟んで交互に形成されるソース電極及びドレイン電極と、外部回路と接続されるためのボンディングパッドと、一方の端部がソース電極又はドレイン電極と動作領域外上で接続され、他方の端部がボンディングパッドと接続されるエアブリッジを備えることを特徴とする高周波用半導体装置が提供される。   According to one embodiment of the present invention, an operation region formed on a compound semiconductor substrate, a gate electrode formed on the operation region, and a source electrode and a drain electrode formed alternately on the operation region with the gate electrode interposed therebetween A bonding pad for connection to an external circuit, and an air bridge having one end connected to the source or drain electrode outside the operating region and the other end connected to the bonding pad. A high-frequency semiconductor device is provided.

本発明の一実施態様によれば、高周波用半導体装置において、出力特性劣化などの不具合の発生を抑え、良好な信頼性を得ることが可能となる。   According to one embodiment of the present invention, in a high-frequency semiconductor device, it is possible to suppress the occurrence of problems such as deterioration of output characteristics and to obtain good reliability.

以下本発明の実施形態について、図を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１に本実施形態の高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の平面図を、図２にそのＡ−Ａ’断面図を示す。図に示すように、化合物半導体基板１１に動作領域１２が形成され、この動作領域１２上に、複数のゲート電極１３が形成されている。そして、動作領域１２上を含む領域に、ゲート電極１３を挟んで交互にそれぞれ複数のソース電極１４、ドレイン電極１５が形成されている。ソース電極１４、ドレイン電極１５は、例えばＰｔ／ＡｕＧｅなどのオーミックコンタクトと、例えばＡｕ／Ｐｔ／Ｔｉなどのメタル層が順次積層されて構成されている。ゲート電極１３は、ゲート配線１６を介して、外部にボンディングされ、信号を入出力するためのゲートパッド１７に接続されている。   FIG. 1 is a plan view of a multi-finger type FET element which is a high-frequency semiconductor device of the present embodiment, and FIG. As shown in the figure, an operation region 12 is formed in the compound semiconductor substrate 11, and a plurality of gate electrodes 13 are formed on the operation region 12. A plurality of source electrodes 14 and drain electrodes 15 are alternately formed in regions including the operation region 12 with the gate electrode 13 interposed therebetween. The source electrode 14 and the drain electrode 15 are configured by sequentially stacking an ohmic contact such as Pt / AuGe and a metal layer such as Au / Pt / Ti. The gate electrode 13 is bonded to the outside via a gate wiring 16 and connected to a gate pad 17 for inputting and outputting signals.

そして、各ゲートパッド１７を挟むように、ソースパッド１８が形成され、ゲートパッド１７、ソースパッド１８と、動作領域を挟んで反対側にドレインパッド１９が形成されている。さらに、ゲート配線１６或いはＳｉＮ層などのパシベーション膜（図示せず）と接することなく、ソース電極１４とソースパッド１８、ドレイン電極１５とドレインパッド１９を接続するエアブリッジ２０が形成されている。エアブリッジ２０は、例えば単層金メッキ層より形成されている。このエアブリッジ２０の終端２０ａは、動作領域１２の端部１２ａ上に近接するように設けられる。エアブリッジ２０において、ソース電極１４及び／又はドレイン電極１５との接続部２０ｂは、動作領域１２上外に配置されている。   A source pad 18 is formed so as to sandwich each gate pad 17, and a drain pad 19 is formed on the opposite side of the gate pad 17 and source pad 18 across the operation region. Further, an air bridge 20 that connects the source electrode 14 and the source pad 18 and the drain electrode 15 and the drain pad 19 is formed without being in contact with a passivation film (not shown) such as the gate wiring 16 or the SiN layer. The air bridge 20 is formed of, for example, a single-layer gold plating layer. The end 20 a of the air bridge 20 is provided so as to be close to the end 12 a of the operation region 12. In the air bridge 20, the connection portion 20 b with the source electrode 14 and / or the drain electrode 15 is disposed on the outside of the operation region 12.

このような構造により、エアブリッジ２０において、温度の変動により基板との熱膨張率の差による熱膨張、熱収縮が生じた場合でも、動作領域１２における圧縮応力、引張り応力といった大きな内部応力の発生が抑えられる。従って、出力特性が劣化するなどの不具合を抑えることができ、良好な信頼性を得ることが可能となる。   With such a structure, in the air bridge 20, even when thermal expansion or thermal contraction occurs due to a difference in thermal expansion coefficient with the substrate due to temperature fluctuation, large internal stress such as compressive stress or tensile stress is generated in the operation region 12. Is suppressed. Therefore, problems such as deterioration of output characteristics can be suppressed, and good reliability can be obtained.

本実施形態において、エアブリッジ２０の終端２０ａは、動作領域１２の端部１２ａ上に近接するように形成されているが、必ずしも一致する必要はない。図３に断面図を示すように、距離ｄ離間していてもよい。これは、エアブリッジ２０と、動作領域１２が重ならないように、位置合せ精度を考慮するためであり、ｄ≦０．２μｍ程度であればよい。合せずれにより動作領域１２と重なることによる不具合を抑えることができる。しかしながら、チップサイズの増大につながることから、できるだけ近接していることが好ましい。   In the present embodiment, the end 20a of the air bridge 20 is formed so as to be close to the end 12a of the operation region 12, but it is not always necessary to match. As shown in the sectional view of FIG. 3, the distance d may be separated. This is because the alignment accuracy is taken into consideration so that the air bridge 20 and the operation region 12 do not overlap, and d ≦ 0.2 μm is sufficient. Problems caused by overlapping with the operation region 12 due to misalignment can be suppressed. However, it is preferable to be as close as possible because it leads to an increase in chip size.

また、図４に部分断面図を示すように、ソース電極１４（ドレイン電極１５）の端部と、エアブリッジ２０の下面の端部２０ｃとは、同一平面上に形成されていなくてもよい。さらに、エアブリッジ２０と、ソース電極１４との接続部の面積が、エアブリッジの幅方向における断面（Ｂ−Ｂ’断面）の面積より大きいことが好ましい。ドレイン電極１５との接続部分においても同様である。接続抵抗と電界集中を抑え、過電流による配線の溶断を防ぐためである。   Further, as shown in the partial cross-sectional view in FIG. 4, the end portion of the source electrode 14 (drain electrode 15) and the end portion 20 c of the lower surface of the air bridge 20 may not be formed on the same plane. Furthermore, it is preferable that the area of the connection portion between the air bridge 20 and the source electrode 14 is larger than the area of the cross section (B-B ′ cross section) in the width direction of the air bridge. The same applies to the connection portion with the drain electrode 15. This is to suppress the connection resistance and electric field concentration and prevent the wiring from fusing due to overcurrent.

また、エアブリッジは一体で金メッキにより形成されることが好ましい。しかしながら、図５に断面図を示すように、ソース電極１４との接続部分がスペーサとなる第１層２０ｄと、空中部分を構成する第２層２０ｅから構成されてもよい。ドレイン電極１５、ソースパッド１８、ドレインパッド１９との接続部分においても同様である。また、ソースパッド１８、ドレインパッド１９全面が、エアブリッジと一体で形成されてもよい。   The air bridge is preferably formed integrally by gold plating. However, as shown in a cross-sectional view in FIG. 5, the connection portion with the source electrode 14 may be composed of a first layer 20 d that serves as a spacer and a second layer 20 e that constitutes the aerial portion. The same applies to the connection portion between the drain electrode 15, the source pad 18, and the drain pad 19. Further, the entire surface of the source pad 18 and the drain pad 19 may be formed integrally with the air bridge.

また、本実施形態において、ソース電極１４、ドレイン電極１５は、夫々動作領域１２の形成されていない領域上まで突出するように形成されているが、必ずしも、両端が突出してなくてもよい。動作領域１２外に接続領域を設けるために、図６に平面図を示すように、少なくとも夫々ソース電極、ドレイン電極と接続されるソースパッド１８、ドレインパッド１９側に突出していればよい。   Further, in the present embodiment, the source electrode 14 and the drain electrode 15 are formed so as to protrude to the region where the operation region 12 is not formed, but both ends may not necessarily protrude. In order to provide the connection region outside the operation region 12, it is sufficient that the connection region protrudes toward the source pad 18 and the drain pad 19 connected to the source electrode and the drain electrode, respectively, as shown in the plan view of FIG.

また、化合物半導体基板としては、ＧａＡｓを用いたが、これに限定されるものではなく、ＧａＮ、ＳｉＣなどの化合物半導体基板を用いることができる。エピタキシャルウェハを用いてもよい。また、各電極のオーミックコンタクトの下層に、イオン注入、高濃度エピタキシャル層の形成などにより、高濃度層を設けてもよい。   Further, although GaAs is used as the compound semiconductor substrate, the present invention is not limited to this, and a compound semiconductor substrate such as GaN or SiC can be used. An epitaxial wafer may be used. Further, a high concentration layer may be provided under the ohmic contact of each electrode by ion implantation, formation of a high concentration epitaxial layer, or the like.

このような構成は、ＨＥＭＴ（High Electron Mobility Transistor）の他、ＭＥＳＦＥＴ（Metal Semiconductor Field Effect Transistor）や、ＭＯＳＦＥＴ（Metal oxide、semiconductor field effect transistor）などのＦＥＴなどにおいて適用することが可能である。   Such a configuration can be applied to FETs such as HEMT (High Electron Mobility Transistor), MESFET (Metal Semiconductor Field Effect Transistor), and MOSFET (Metal oxide, semiconductor field effect transistor).

尚、本発明は、上述した実施形態に限定されるものではない。その他要旨を逸脱しない範囲で種々変形して実施することができる。   In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

本発明の一態様による高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の平面図。1 is a plan view of a multi-finger type FET element which is a high-frequency semiconductor device according to one embodiment of the present invention. 図１のＡ−Ａ’断面図A-A 'sectional view of FIG. 本発明の一態様による高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の断面図。1 is a cross-sectional view of a multi-finger FET element which is a high-frequency semiconductor device according to one embodiment of the present invention. 本発明の一態様による高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の断面図。1 is a cross-sectional view of a multi-finger FET element which is a high-frequency semiconductor device according to one embodiment of the present invention. 本発明の一態様による高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の部分断面図。1 is a partial cross-sectional view of a multi-finger FET element which is a high-frequency semiconductor device according to one embodiment of the present invention. 本発明の一態様による高周波用半導体装置であるマルチフィンガー型のＦＥＴ素子の平面図。1 is a plan view of a multi-finger type FET element which is a high-frequency semiconductor device according to one embodiment of the present invention.

符号の説明Explanation of symbols

１１…化合物半導体基板、１２…動作領域、１３…ゲート電極、１４…ソース電極、１５…ドレイン電極、１６…ゲート配線、１７…ゲートパッド、１８…ソースパッド、１９…ドレインパッド、２０…エアブリッジ。   DESCRIPTION OF SYMBOLS 11 ... Compound semiconductor substrate, 12 ... Operating region, 13 ... Gate electrode, 14 ... Source electrode, 15 ... Drain electrode, 16 ... Gate wiring, 17 ... Gate pad, 18 ... Source pad, 19 ... Drain pad, 20 ... Air bridge .

Claims (6)

化合物半導体基板に形成される動作領域と、
前記動作領域上に形成されるゲート電極と、
前記動作領域上に前記ゲート電極を挟んで交互に形成されるソース電極及びドレイン電極と、
外部回路と接続されるためのボンディングパッドと、
一方の端部が前記ソース電極又は前記ドレイン電極と前記動作領域外上で接続され、他方の端部が前記ボンディングパッドと接続されるエアブリッジを備えることを特徴とする高周波用半導体装置。 An operating region formed in the compound semiconductor substrate;
A gate electrode formed on the operating region;
A source electrode and a drain electrode alternately formed on the operation region with the gate electrode interposed therebetween;
A bonding pad for connection to an external circuit;
A high-frequency semiconductor device comprising an air bridge having one end connected to the source electrode or the drain electrode outside the operating region and the other end connected to the bonding pad. 前記エアブリッジは、Ａｕ層を備えることを特徴とする請求項１に記載の高周波用半導体装置。   The high-frequency semiconductor device according to claim 1, wherein the air bridge includes an Au layer. 前記Ａｕ層は、単層メッキ層であることを特徴とする請求項２に記載の高周波用半導体装置。   The high-frequency semiconductor device according to claim 2, wherein the Au layer is a single-layer plating layer. 前記エアブリッジと前記ソース電極又は前記ドレイン電極との接続部の終端が、前記動作領域の前記エアブリッジ側の端部上に近接していることを特徴とする請求項１乃至請求項３のいずれか1項に記載の高周波用半導体装置。   The terminal of the connection part of the said air bridge and the said source electrode or the said drain electrode is adjoining on the edge part by the side of the said air bridge of the said operation area | region, The any one of Claim 1 thru | or 3 characterized by the above-mentioned. 2. A high-frequency semiconductor device according to claim 1. 前記エアブリッジと、前記ソース電極又は前記ドレイン電極との接続面積が、前記エアブリッジの幅方向における断面の面積より大きいことを特徴とする請求項１乃至請求項４のいずれか1項に記載の高周波用半導体装置。   The connection area between the air bridge and the source electrode or the drain electrode is larger than an area of a cross section in the width direction of the air bridge. High frequency semiconductor devices. 前記化合物半導体基板はＧａＡｓ基板であることを特徴とする請求項１乃至請求項４のいずれか1項に記載の高周波用半導体装置。   5. The high-frequency semiconductor device according to claim 1, wherein the compound semiconductor substrate is a GaAs substrate.
JP2007181996A 2006-07-12 2007-07-11 Semiconductor device for high frequency Abandoned JP2008042184A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056388A (en) * 2008-08-29 2010-03-11 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP2012114330A (en) * 2010-11-26 2012-06-14 Toshiba Corp Power amplification device and coupled power amplification device
JP2012142498A (en) * 2011-01-05 2012-07-26 Mitsubishi Electric Corp Wiring pattern

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056388A (en) * 2008-08-29 2010-03-11 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP2012114330A (en) * 2010-11-26 2012-06-14 Toshiba Corp Power amplification device and coupled power amplification device
US8482354B2 (en) 2010-11-26 2013-07-09 Kabushiki Kaisha Toshiba Power amplifying device and coupled power amplifying device
JP2012142498A (en) * 2011-01-05 2012-07-26 Mitsubishi Electric Corp Wiring pattern

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