JP2008022020A - Semiconductor device fabrication method - Google Patents

Semiconductor device fabrication method Download PDF

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JP2008022020A
JP2008022020A JP2007223401A JP2007223401A JP2008022020A JP 2008022020 A JP2008022020 A JP 2008022020A JP 2007223401 A JP2007223401 A JP 2007223401A JP 2007223401 A JP2007223401 A JP 2007223401A JP 2008022020 A JP2008022020 A JP 2008022020A
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forming
insulating film
semiconductor
semiconductor chip
external connection
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JP5064938B2 (en
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Hiromi Morita
博美 森田
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device fabrication method capable of suppressing an increase in dimension and improving a packaging density even when the size of a semiconductor chip increases or the number of external connection pins increases. <P>SOLUTION: This method comprises a step for preparing a semiconductor wafer with a plurality of semiconductor chip areas each of which is almost square and a peripheral area surrounding the semiconductor chip areas, a step for forming a device body with a device electrode 7 in each semiconductor chip area, a step for forming a trench in the periphery area along a circumference of each semiconductor chip area, a step for forming a first insulating film 2 which exposes a part of the device electrode 7 in the device body area, a step for forming on the device electrode 7 exposed from the first insulating film 2 and the first insulating film 2 itself an electrode wiring 3 extending up to an external connection pin lead-out area A in each semiconductor chip area, a step for forming a second insulating film in the inside of the trench as well as on the electrode wiring 3 and first insulating film 2, and a step for forming an external connection terminal 4 to electrically connect the electrode wiring 3 and external device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、外部接続端子がその表面に露出した半導体素子の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor element having an external connection terminal exposed on the surface thereof.

一般に半導体素子は、セラミックやモールド樹脂を用いてパッケージされている。この場合、複数の素子が形成された略四方形の半導体基板、通常半導体チップとよばれるものは、略四方形の各辺に対向するように並べられた複数の外部端子と金線等により接続される。この半導体チップ、金線および外部端子の一部がセラミックやモールド樹脂により覆われる。   Generally, a semiconductor element is packaged using a ceramic or a mold resin. In this case, a substantially rectangular semiconductor substrate on which a plurality of elements are formed, generally called a semiconductor chip, is connected to a plurality of external terminals arranged so as to face each side of the substantially square shape by a gold wire or the like. Is done. A part of the semiconductor chip, the gold wire, and the external terminal is covered with ceramic or mold resin.

このような構造では、半導体チップのサイズが大きくなった場合、複数の外部端子は、大きくなった半導体チップの周囲に配置されるためその外形を大きくせざるを得ない。また、外部端子の数が増加した場合も、外部端子のピッチには限界があるためその外形を大きくせざるを得ない。   In such a structure, when the size of the semiconductor chip is increased, the plurality of external terminals are arranged around the enlarged semiconductor chip, and thus the outer shape thereof must be enlarged. Also, when the number of external terminals increases, the external terminals must be enlarged because the pitch of the external terminals is limited.

このような場合、実装密度の向上を図ることが困難であった。
なお、本願発明に関連する先行技術文献としては次のようなものがある。
特開平１０−７９３６２号公報 特開平５−２９１３５２号公報 特開平４−１５９７３９号公報 特開平６−７７２３３号公報 特開平１−２７６７４８号公報 In such a case, it was difficult to improve the mounting density.
In addition, there are the following as prior art documents related to the present invention.
JP-A-10-79362 Japanese Patent Laid-Open No. 5-291352 Japanese Patent Laid-Open No. 4-15939 JP-A-6-77233 JP-A-1-276748

本発明は、半導体チップのサイズが大きくなった場合、もしくは外部端子の数が増加した場合であっても、その外形の増大を抑えることができ、実装密度の向上を図れる半導体素子の製造方法を提供することを目的とする。   The present invention provides a method for manufacturing a semiconductor element capable of suppressing an increase in the outer shape and improving the mounting density even when the size of a semiconductor chip is increased or the number of external terminals is increased. The purpose is to provide.

第１の発明の半導体素子の製造方法は、略四方形の半導体チップ領域を複数有する半導体ウェハであって、半導体チップ領域内に形成され、素子電極を含む素子本体と、半導体チップ領域の外周に沿って形成される溝と、溝の内側に形成され、素子本体を覆うとともに素子電極を露出して形成される第１の絶縁膜とを含む半導体ウェハを準備する工程と、少なくとも第１の絶縁層を覆い、溝内部まで延在している第２の絶縁膜を形成する工程と、を有する。 According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor wafer having a plurality of substantially rectangular semiconductor chip regions; and an element body formed in the semiconductor chip region and including an element electrode; Preparing a semiconductor wafer including a groove formed along the groove, a first insulating film formed inside the groove, covering the element body and exposing the element electrode, and at least a first insulation Forming a second insulating film covering the layer and extending to the inside of the trench.

ここで、第１の絶縁膜とは例えば絶縁膜２であり、第２の絶縁膜とは例えば保護膜５である。   Here, the first insulating film is, for example, the insulating film 2, and the second insulating film is, for example, the protective film 5.

第２の発明の半導体素子の製造方法は、複数の略四方形の半導体チップ領域と、半導体チップ領域を囲う周辺領域とを有する半導体ウェハを準備する工程と、半導体チップ領域に素子電極を含む素子本体を形成する工程と、半導体チップ領域の外周に沿って周辺領域に溝を形成する工程と、素子本体領域に素子電極の一部を露出させる第１の絶縁膜を形成する工程と、第１の絶縁膜から露出した素子電極及び第１の絶縁膜上に、半導体チップ領域上の外部接続端子取出領域まで延在する電極用配線を形成する工程と、電極用配線上、第１の絶縁膜上及び溝内部に第２の絶縁膜を形成する工程と、電極用配線と外部装置とを電気的に接続する外部接続端子を形成する工程と、を有する。 According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor wafer having a plurality of substantially square semiconductor chip regions and a peripheral region surrounding the semiconductor chip region; A step of forming a main body, a step of forming a groove in the peripheral region along the outer periphery of the semiconductor chip region, a step of forming a first insulating film exposing a part of the device electrode in the device main body region, Forming an electrode wiring extending to the external connection terminal extraction region on the semiconductor chip region on the element electrode and the first insulating film exposed from the insulating film, and the first insulating film on the electrode wiring Forming a second insulating film on the top and inside the groove; and forming an external connection terminal for electrically connecting the electrode wiring and the external device.

ここで、第１の絶縁膜とは例えば絶縁膜２であり、第２の絶縁膜とは例えば保護膜５である。   Here, the first insulating film is, for example, the insulating film 2, and the second insulating film is, for example, the protective film 5.

本発明では、外部接続端子４が半導体チップ表面を覆う保護膜５の上部に露出するように形成されているので、たとえ半導体チップのサイズが大きくなった場合でもその表面に外部接続手段が配置されるため、従来のような半導体チップの周囲に外部接続端子が配置されることによる外形の増大を抑えることができる。   In the present invention, the external connection terminals 4 are formed so as to be exposed above the protective film 5 covering the surface of the semiconductor chip. Therefore, even when the size of the semiconductor chip is increased, the external connection means is arranged on the surface. Therefore, it is possible to suppress an increase in the outer shape due to the external connection terminals arranged around the conventional semiconductor chip.

また、外部接続端子の数が増加した場合も、半導体チップの表面に外部接続端子が配置されるため外部接続端子の配置にゆとりができ、外形の増大を抑えることができる。   Further, even when the number of external connection terminals increases, the external connection terminals are arranged on the surface of the semiconductor chip, so that the arrangement of the external connection terminals can be relaxed, and an increase in the outer shape can be suppressed.

また、本発明では、半導体基板の外周に沿って溝６が形成され、その溝内部及び上部には保護膜５が形成されているため、素子本体と外部との距離が長くなり、半導体基板１と保護膜５との界面から外部雰囲気が浸入するのを防止することができ、さらに、熱的ストレスによる保護膜５のダメージを防止することができる。また、この溝６により半導体基板と保護膜との接触面積が増加するため、切断時の機械的ストレスを緩和できる。   In the present invention, since the groove 6 is formed along the outer periphery of the semiconductor substrate and the protective film 5 is formed inside and above the groove, the distance between the element body and the outside becomes long, and the semiconductor substrate 1 It is possible to prevent the external atmosphere from entering from the interface between the protective film 5 and the protective film 5, and to prevent damage to the protective film 5 due to thermal stress. Further, since the contact area between the semiconductor substrate and the protective film is increased by the groove 6, mechanical stress at the time of cutting can be alleviated.

さらに、半導体チップの表面を保護膜５で覆う構造となっているため、セラミックもしくはモールド樹脂によるさらなる実装が不要となり、外形の小型化、実装密度の向上を図ることができる。   Furthermore, since the surface of the semiconductor chip is covered with the protective film 5, no further mounting with ceramic or mold resin is required, and the size of the outer shape can be reduced and the mounting density can be improved.

また、第１の発明では、素子電極７と外部接続端子４との間を電極用配線３を用いて接続しているため、外部接続端子４を半導体チップ表面内で、任意の位置に、任意の数量・ピッチで形成することができ、外形の小型化が実現でき実装密度の向上を図ることができる。   In the first invention, since the element electrode 7 and the external connection terminal 4 are connected using the electrode wiring 3, the external connection terminal 4 is arbitrarily placed at an arbitrary position within the semiconductor chip surface. Thus, the outer shape can be miniaturized and the mounting density can be improved.

（第１の実施の形態）図１（ａ）は、本発明の第１の実施形態を示す図で、（ｂ）は（ａ）の溝部の平面図である。   (First Embodiment) FIG. 1A is a view showing a first embodiment of the present invention, and FIG. 1B is a plan view of a groove portion of FIG.

まず、この外部接続端子付半導体素子の構造について説明する。   First, the structure of the semiconductor element with external connection terminals will be described.

１は略四方形の半導体基板で、この半導体基板１の内部若しくは上部には素子本体が形成されている。この素子本体上には素子電極７が形成され、この素子電極７上には、外部接続端子取出領域Ａまで延在する電極用配線３が形成されている。この電極用配線３上の外部接続端子取出領域Ａには外部接続端子４が形成されている。   Reference numeral 1 denotes a substantially rectangular semiconductor substrate, and an element body is formed in or on the semiconductor substrate 1. An element electrode 7 is formed on the element body, and an electrode wiring 3 extending to the external connection terminal extraction region A is formed on the element electrode 7. An external connection terminal 4 is formed in the external connection terminal extraction region A on the electrode wiring 3.

また、電気的に接続されている素子電極７、電極用配線３および外部接続端子４は、絶縁膜２と保護膜５により他の素子や電極と絶縁されている。もちろん外部接続端子４の表面は保護膜５の上部に露出している。   Further, the electrically connected element electrode 7, electrode wiring 3 and external connection terminal 4 are insulated from other elements and electrodes by the insulating film 2 and the protective film 5. Of course, the surface of the external connection terminal 4 is exposed above the protective film 5.

６は溝であり、図１（ｂ）に示すようにこの半導体基板１の外周に沿って形成されている。   A groove 6 is formed along the outer periphery of the semiconductor substrate 1 as shown in FIG.

次に、この外部接続端子付半導体素子の製造方法を説明する。   Next, a method for manufacturing the semiconductor element with external connection terminals will be described.

その内部若しくは上部には素子本体が形成されている略四方形の半導体基板１が複数形成されている半導体ウェハを準備し、それぞれの半導体基板１の外周に沿ってエッチングにより溝を形成する（図１（ｂ））。   A semiconductor wafer in which a plurality of substantially rectangular semiconductor substrates 1 having element bodies formed therein is formed is prepared inside or on the top, and grooves are formed by etching along the outer periphery of each semiconductor substrate 1 (FIG. 1 (b)).

次に、素子本体と接続するよう素子電極７を形成し、この素子電極７上に絶縁膜２を形成する。このとき、溝６条には絶縁膜２を形成しない。   Next, the element electrode 7 is formed so as to be connected to the element body, and the insulating film 2 is formed on the element electrode 7. At this time, the insulating film 2 is not formed in the groove 6.

次に、エッチングにより絶縁膜２上に素子電極７まで到達するコンタクトホールを形成し、コンタクトホール上から外部接続端子取出領域Ａまで延在するようパターニングを行う。   Next, a contact hole reaching the device electrode 7 is formed on the insulating film 2 by etching, and patterning is performed so as to extend from the contact hole to the external connection terminal extraction region A.

次に、溝６、絶縁膜２及び電極用配線３上に保護膜５を形成し、外部端子取出領域Ａに電極用配線３まで到達するコンタクトホールを形成する。このコンタクトホール内に外部接続端子４をその表面が保護膜５上に露出するよう形成する。   Next, a protective film 5 is formed on the groove 6, the insulating film 2, and the electrode wiring 3, and a contact hole reaching the electrode wiring 3 is formed in the external terminal extraction region A. The external connection terminal 4 is formed in the contact hole so that the surface thereof is exposed on the protective film 5.

このように、外部接続端子４は、保護膜５のコンタクトホールを介して電極用配線３に接続され、この電極用配線３は絶縁膜２上に延在し素子電極７に接続される。   Thus, the external connection terminal 4 is connected to the electrode wiring 3 through the contact hole of the protective film 5, and the electrode wiring 3 extends on the insulating film 2 and is connected to the element electrode 7.

最後に、図１（ｂ）に示す各半導体基板１を切り放す。   Finally, each semiconductor substrate 1 shown in FIG.

このように、本発明の第１の実施形態では、外部接続端子４が半導体チップ表面を覆う保護膜５の上部に露出するように形成されているので、たとえ半導体チップのサイズが大きくなった場合でも、その表面に外部接続端子が配置されるため、従来のような半導体チップの周囲に外部接続端子が配置されることによる外形の増大を抑えることができる。   Thus, in the first embodiment of the present invention, the external connection terminal 4 is formed so as to be exposed on the upper portion of the protective film 5 covering the surface of the semiconductor chip, so that even when the size of the semiconductor chip is increased However, since the external connection terminals are arranged on the surface, it is possible to suppress an increase in the outer shape due to the arrangement of the external connection terminals around the conventional semiconductor chip.

また、外部接続端子の数が増加した場合も、半導体チップの表面に外部接続端子４が配置されるため外部接続端子の配置にゆとりができ、外形の増大を抑えることができる。特に、本発明の第１の実施形態では、素子電極７と外部接続端子４との間を電極用配線３を用いて接続しているため、外部接続端子４を半導体チップ表面の所望の位置に形成することができ、外部接続端子４のピッチを適宜設定できる。   Further, even when the number of external connection terminals increases, the external connection terminals 4 are arranged on the surface of the semiconductor chip, so that the arrangement of the external connection terminals can be relaxed, and an increase in the outer shape can be suppressed. In particular, in the first embodiment of the present invention, since the element electrode 7 and the external connection terminal 4 are connected using the electrode wiring 3, the external connection terminal 4 is placed at a desired position on the surface of the semiconductor chip. The pitch of the external connection terminals 4 can be set as appropriate.

図１（ｃ）は、外部接続端子４がマトリクス状に配置された半導体チップの上面図で、（ｄ）は（ｃ）のＡ−Ａ´断面図である。   FIG. 1C is a top view of a semiconductor chip in which the external connection terminals 4 are arranged in a matrix, and FIG. 1D is a cross-sectional view taken along line AA ′ in FIG.

このように、外部接続端子がマトリクス状に配置されるように各素子電極７から電極用配線３を引き廻せば、外形を大きくすることなく外部接続端子の増加に対応できる。   Thus, if the electrode wiring 3 is routed from each element electrode 7 so that the external connection terminals are arranged in a matrix, it is possible to cope with an increase in the number of external connection terminals without increasing the outer shape.

また、本発明の第１の実施形態では、半導体基板１の外周に沿って溝６が形成され、その溝内部及び上部には保護膜５が形成されているため、素子本体と外部との距離が長くなり、半導体基板１と保護膜５との界面から外部雰囲気が浸入することを防止することができる。また、この溝６により半導体基板１と保護膜５との接触面積が増大するため、切断時の機械的ストレスを緩和できる。   In the first embodiment of the present invention, the groove 6 is formed along the outer periphery of the semiconductor substrate 1, and the protective film 5 is formed inside and above the groove. Therefore, the distance between the element body and the outside It is possible to prevent the external atmosphere from entering from the interface between the semiconductor substrate 1 and the protective film 5. Moreover, since the contact area between the semiconductor substrate 1 and the protective film 5 is increased by the groove 6, mechanical stress at the time of cutting can be alleviated.

さらに、半導体チップの表面を保護膜５で覆う構造となっているため、セラミック若しくはモールド樹脂等によるさらなる実装が不必要となり、外形の小型化、実装密度の向上を図ることができる。   Further, since the surface of the semiconductor chip is covered with the protective film 5, further mounting with ceramic or mold resin is unnecessary, and the outer shape can be reduced and the mounting density can be improved.

（第２の実施形態）図２は、本発明の第２の実施形態を示す図である。
図１（ａ）と対応する箇所には同じ符号を付し、その詳細な説明を省略する。 (Second Embodiment) FIG. 2 is a diagram showing a second embodiment of the present invention.
The portions corresponding to those in FIG. 1A are denoted by the same reference numerals, and detailed description thereof is omitted.

図２の外部接続端子付半導体素子では、素子電極７上に直接外部接続端子４が形成されており、図１（ａ）の外部接続端子付半導体素子の電極用配線３が形成されていない。   In the semiconductor element with an external connection terminal in FIG. 2, the external connection terminal 4 is formed directly on the element electrode 7, and the electrode wiring 3 of the semiconductor element with an external connection terminal in FIG. 1 (a) is not formed.

このように、例えば、複数の素子電極７の間隔にゆとりがあるような場合は、電極用配線３を用いず、直接、素子電極７上に外部接続端子４を形成しても良い。   Thus, for example, when there is a space between the plurality of element electrodes 7, the external connection terminals 4 may be formed directly on the element electrodes 7 without using the electrode wiring 3.

この外部接続端子付半導体素子の製造方法は、絶縁膜２の形成工程までは、第１の実施形態と同じである。この絶縁膜２および溝６条に保護膜５を形成する。   The manufacturing method of the semiconductor element with external connection terminals is the same as that of the first embodiment until the step of forming the insulating film 2. A protective film 5 is formed on the insulating film 2 and the groove 6.

次に、素子電極７まで到達するコンタクトホールを形成し、このコンタクトホール内に外部接続端子４をその表面が保護膜５上に露出するように形成する。   Next, a contact hole reaching the element electrode 7 is formed, and the external connection terminal 4 is formed in the contact hole so that the surface thereof is exposed on the protective film 5.

この場合、外部接続端子４は、コンタクトホールを介して直接素子電極７に接続される。   In this case, the external connection terminal 4 is directly connected to the element electrode 7 through the contact hole.

最後に、図１（ｂ）に示す各半導体基板１を切り放す。   Finally, each semiconductor substrate 1 shown in FIG.

このように、本発明の第２の実施形態では、外部接続端子４が半導体チップ表面を覆う保護膜５の上部に露出するように形成されているので、たとえ半導体チップのサイズが大きくなった場合でも、その表面に外部接続端子が配置されるため、従来のような半導体チップの周囲に外部接続端子が配置されることによる外形の増大を抑えることができる。   As described above, in the second embodiment of the present invention, the external connection terminal 4 is formed so as to be exposed on the upper portion of the protective film 5 covering the surface of the semiconductor chip, so that even when the size of the semiconductor chip is increased. However, since the external connection terminals are arranged on the surface, it is possible to suppress an increase in the outer shape due to the arrangement of the external connection terminals around the conventional semiconductor chip.

また、外部接続端子の数が増加した場合も、半導体チップの表面に外部接続端子が配置されるため外部接続端子の配置にゆとりができ、外形の増大を抑えることができる。   Further, even when the number of external connection terminals increases, the external connection terminals are arranged on the surface of the semiconductor chip, so that the arrangement of the external connection terminals can be relaxed, and an increase in the outer shape can be suppressed.

第１の実施形態と比較し、電極用配線３を形成する必要がないため、その構成がシンプルになり、短時間、低コストでの製造が可能である。先述したように、複数の素子電極７の間隔にゆとりがあるような場合には、このような構成が適する。   Compared to the first embodiment, since it is not necessary to form the electrode wiring 3, the configuration is simplified, and manufacturing in a short time and at a low cost is possible. As described above, such a configuration is suitable when there is a space between the plurality of element electrodes 7.

（第３の実施の形態）図３は、本発明の第３の実施形態を示す図である。
図１（ａ）と対応する箇所には同じ符号を付し、その詳細な説明を省略する。 (Third Embodiment) FIG. 3 is a diagram showing a third embodiment of the present invention.
Parts corresponding to those in FIG. 1A are denoted by the same reference numerals, and detailed description thereof is omitted.

図３の外部接続端子付半導体素子では、外部接続端子としてピン型の金属棒３４が使用されており、ピングリッドアレー（ＰＧＡ）型に適用したものである。金属棒３４には銅材料等が用いられる。   In the semiconductor element with external connection terminals in FIG. 3, a pin-type metal bar 34 is used as an external connection terminal, which is applied to a pin grid array (PGA) type. A copper material or the like is used for the metal rod 34.

この外部接続端子付半導体素子の製造方法は、第１の実施形態と同じであるためその詳細な説明を省略する。   Since the manufacturing method of this semiconductor element with an external connection terminal is the same as that of the first embodiment, its detailed description is omitted.

（第４の実施の形態）図４は、本発明の第４の実施形態を示す図である。
図１（ａ）と対応する箇所には同じ符号を付し、その詳細な説明を省略する。 (Fourth Embodiment) FIG. 4 is a diagram showing a fourth embodiment of the present invention.
The portions corresponding to those in FIG. 1A are denoted by the same reference numerals, and detailed description thereof is omitted.

図４の外部接続用端子付半導体素子では、外部接続端子として外部接続用の凹部４４ａを有するソケット４４が使用されており、このソケット４４に凸部を有する配線を接続することにより外部素子若しくは外部装置への接続がなされる。   In the semiconductor element with an external connection terminal in FIG. 4, a socket 44 having an external connection recess 44a is used as an external connection terminal. A connection to the device is made.

この外部接続端子付半導体素子の製造方法は、第１の実施形態と同じであるためその詳細な説明を省略する。   Since the manufacturing method of this semiconductor element with an external connection terminal is the same as that of the first embodiment, its detailed description is omitted.

本発明の第１の実施形態を示す図The figure which shows the 1st Embodiment of this invention 本発明の第２の実施形態を示す図The figure which shows the 2nd Embodiment of this invention 本発明の第３の実施形態を示す図The figure which shows the 3rd Embodiment of this invention 本発明の第４の実施形態を示す図The figure which shows the 4th Embodiment of this invention

符号の説明Explanation of symbols

１ 半導体基板
２ 絶縁膜
３ 電極用配線
４ 外部接続端子
５ 保護膜
６ 溝
７ 素子電極
Ａ 外部接続端子取出領域
３４ 金属棒
４４ ソケット
４４ａ 凹部
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Electrode wiring 4 External connection terminal 5 Protective film 6 Groove 7 Element electrode A External connection terminal extraction area 34 Metal rod 44 Socket 44a Recess

Claims (8)

略四方形の半導体チップ領域を複数有する半導体ウェハであって、該半導体チップ領域内に形成され、素子電極を含む素子本体と、該半導体チップ領域の外周に沿って形成される溝と、該溝の内側に形成され、該素子本体を覆うとともに該素子電極を露出して形成される第１の絶縁膜とを含む該半導体ウェハを準備する工程と、
少なくとも前記第１の絶縁層を覆い、前記溝内部まで延在している第２の絶縁膜を形成する工程と、
を有することを特徴とする半導体素子の製造方法。 A semiconductor wafer having a plurality of substantially square semiconductor chip regions, the device main body including element electrodes formed in the semiconductor chip region, grooves formed along the outer periphery of the semiconductor chip region, and the grooves Preparing the semiconductor wafer including a first insulating film formed on the inside of the substrate and covering the element body and exposing the element electrode;
Forming a second insulating film covering at least the first insulating layer and extending into the trench;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の半導体素子の製造方法において、
前記素子電極と電気的に接続される外部接続端子を形成する工程をさらに有することを特徴とする半導体素子の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, further comprising a step of forming an external connection terminal electrically connected to the device electrode. 請求項１又は２に記載の半導体素子の製造方法において、
前記半導体ウェハを準備する工程の後に、前記素子電極及び前記第１の絶縁膜上に電極用配線を形成する工程をさらに有することを特徴とする半導体素子の製造方法。 In the manufacturing method of the semiconductor element according to claim 1 or 2,
A method of manufacturing a semiconductor device, further comprising a step of forming electrode wiring on the device electrode and the first insulating film after the step of preparing the semiconductor wafer. 複数の略四方形の半導体チップ領域と、該半導体チップ領域を囲う周辺領域とを有する半導体ウェハを準備する工程と、
前記半導体チップ領域に素子電極を含む素子本体を形成する工程と、
前記半導体チップ領域の外周に沿って前記周辺領域に溝を形成する工程と、
前記素子本体領域に前記素子電極の一部を露出させる第１の絶縁膜を形成する工程と、
前記第１の絶縁膜から露出した前記素子電極及び前記第１の絶縁膜上に、前記半導体チップ領域上の外部接続端子取出領域まで延在する電極用配線を形成する工程と、
前記電極用配線上、前記第１の絶縁膜上及び前記溝内部に第２の絶縁膜を形成する工程と、
前記電極用配線と外部装置とを電気的に接続する外部接続端子を形成する工程と、
を有することを特徴とする半導体素子の製造方法。 Preparing a semiconductor wafer having a plurality of substantially rectangular semiconductor chip regions and a peripheral region surrounding the semiconductor chip regions;
Forming an element body including an element electrode in the semiconductor chip region;
Forming a groove in the peripheral region along an outer periphery of the semiconductor chip region;
Forming a first insulating film exposing a part of the device electrode in the device body region;
Forming an electrode wiring extending to the external connection terminal extraction region on the semiconductor chip region on the element electrode and the first insulating film exposed from the first insulating film;
Forming a second insulating film on the electrode wiring, on the first insulating film, and in the groove;
Forming an external connection terminal for electrically connecting the electrode wiring and an external device;
A method for manufacturing a semiconductor device, comprising: 請求項４に記載の半導体素子の製造方法において、
前記第２の絶縁膜を形成する工程は、前記外部接続端子取出領域に位置する前記電極用配線上を除く、前記電極用配線上、前記第１の絶縁膜上及び前記溝部内に第２の絶縁膜を形成する工程であり、
前記外部接続端子を形成する工程は、前記外部接続端子取出領域に位置する前記電極用配線上に該電極用配線と外部装置とを電気的に接続する外部接続端子を形成する工程であることを特徴とする半導体素子の製造方法。 In the manufacturing method of the semiconductor device according to claim 4,
The step of forming the second insulating film includes a second step on the electrode wiring, on the first insulating film, and in the groove except for the electrode wiring located in the external connection terminal extraction region. A step of forming an insulating film,
The step of forming the external connection terminal is a step of forming an external connection terminal for electrically connecting the electrode wiring and an external device on the electrode wiring located in the external connection terminal extraction region. A method for manufacturing a semiconductor device. 複数の略四方形の半導体チップ領域と、該半導体チップ領域を囲う周辺領域とを有する半導体ウェハを準備する工程と、
前記半導体チップ領域に素子電極を含む素子本体を形成する工程と、
前記半導体チップ領域の外周に沿って前記周辺領域に溝を形成する工程と、
前記素子本体領域に前記素子電極の一部を露出させる第１の絶縁膜を形成する工程と、
前記第１の絶縁膜上及び前記溝内部に第２の絶縁膜を形成する工程と、
前記素子電極と外部装置とを電気的に接続する外部接続端子を形成する工程と、
を有することを特徴とする半導体素子の製造方法。 Preparing a semiconductor wafer having a plurality of substantially rectangular semiconductor chip regions and a peripheral region surrounding the semiconductor chip regions;
Forming an element body including an element electrode in the semiconductor chip region;
Forming a groove in the peripheral region along an outer periphery of the semiconductor chip region;
Forming a first insulating film exposing a part of the device electrode in the device body region;
Forming a second insulating film on the first insulating film and in the groove;
Forming an external connection terminal for electrically connecting the element electrode and an external device;
A method for manufacturing a semiconductor device, comprising: 請求項４乃至６のいずれか一つに記載の半導体素子の製造方法において、
前記周辺領域を切り放すことによって個々の半導体素子に分離する工程をさらに含むことを特徴とする半導体素子の製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 4 to 6,
A method of manufacturing a semiconductor device, further comprising a step of separating the peripheral region into individual semiconductor devices by cutting away the peripheral region. 請求項１乃至７のいずれか一つに記載の半導体素子の製造方法において、
前記第１の絶縁膜は、前記溝が形成される位置よりも若干内側までを覆うことを特徴とする半導体素子の製造方法。 In the manufacturing method of the semiconductor element according to any one of claims 1 to 7,
The method of manufacturing a semiconductor element, wherein the first insulating film covers a portion slightly inside from a position where the groove is formed.
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Citations (4)

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Publication number Priority date Publication date Assignee Title
JPS5827349A (en) * 1981-08-12 1983-02-18 Hitachi Ltd Semiconductor device
JPS62149846A (en) * 1985-12-25 1987-07-03 Toshiba Corp Metal for compressor
JPH0541469A (en) * 1991-08-06 1993-02-19 Nec Corp Resin sealed semiconductor device
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827349A (en) * 1981-08-12 1983-02-18 Hitachi Ltd Semiconductor device
JPS62149846A (en) * 1985-12-25 1987-07-03 Toshiba Corp Metal for compressor
JPH0541469A (en) * 1991-08-06 1993-02-19 Nec Corp Resin sealed semiconductor device
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof

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