JP2008021807A - 半導体配線の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 127
- 239000010409 thin film Substances 0.000 claims abstract description 118
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims description 36
- 238000003825 pressing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
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- 238000000034 method Methods 0.000 description 23
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- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000011156 evaluation Methods 0.000 description 9
- 229910020177 SiOF Inorganic materials 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 229910017945 Cu—Ti Inorganic materials 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 229910010413 TiO 2 Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
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- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
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- 239000002244 precipitate Substances 0.000 description 2
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- 239000011800 void material Substances 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002585 base Substances 0.000 description 1
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- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】半導体基板上の絶縁膜に最小幅が0.15μm以下、該最小幅に対する深さの比(深さ/最小幅)が1以上の凹部を形成し、この絶縁膜の凹部に、Tiを0.5〜10原子%含有するCu合金薄膜を凹部形状に沿って10〜50nmの厚さで形成した後、Cu合金薄膜付き凹部に純Cu薄膜を形成し、350℃以上に加熱して絶縁膜とCu合金薄膜との間にTiを析出させればよい。
【選択図】図1
Description
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、純Cu薄膜または下記表1に示す量のTiを含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜をDCマグネトロンスパッタリング法で膜厚が700nmとなるように成膜した。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、純Cu薄膜または下記表2に示す量のTiを含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜を電解メッキ法で膜厚が700nmとなるように成膜した。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、Tiを7.0原子%含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜をDCマグネトロンスパッタリング法で膜厚が700nmとなるように成膜した。スパッタリングは、上記実験例1と同じ条件で行った。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、幅0.13μm(130nm)、深さ0.3μm(300nm)、長さ2.0mmの配線パターン(ストライプパターン)を設けた評価素子(TEG)を用いた。このTEGの表面に、Tiを7.0原子%含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜をDCマグネトロンスパッタリング法で膜厚が700nmとなるように成膜し、配線パターン部分を薄膜で覆った。スパッタリングは、上記実験例1と同じ条件で行った。
埋め込み率(%)=[(配線パターンに埋め込まれている純Cuの断面積)/(配線パターンの断面積)]×100 ・・・(1)
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、幅0.13μm(130nm)、深さ0.3μm(300nm)、長さ2.0mmの配線パターン(ストライプパターン)を設けた評価素子(TEG)を用いた。このTEGの表面に、Tiを7.0原子%含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜を電解メッキ法で膜厚が700nmとなるように成膜し、配線パターン部分を薄膜で覆った。スパッタリングは、上記実験例1と同じ条件で行い、電解メッキは、上記実験例2と同じ条件で行った。
下記試験片Aと試験片Bについて、成膜したCu薄膜をフォトリソグラフィーおよびウェットエッチングにより電気抵抗率測定用パターンに加工し、長さ10mmの配線抵抗を4探針法により測定した。配線抵抗(電気抵抗率)は、まず室温で測定し、次に、Ar雰囲気下、常圧で、所定温度(200℃、300℃、350℃、400℃、500℃、600℃、700℃)で各2時間ずつ保持する熱処理を行い、各温度で配線抵抗(電気抵抗率)の測定を行った。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、Tiを7.0原子%含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜をDCマグネトロンスパッタリング法で膜厚が700nmとなるように成膜した。スパッタリングは、上記実験例1と同じ条件で行った。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、Tiを7.0原子%含有するCu合金薄膜をDCマグネトロンスパッタリング法で膜厚が50nmとなるように成膜し、次いで純Cu薄膜を電解メッキ法で膜厚が700nmとなるように成膜した。スパッタリングは、上記実験例1と同じ条件で行い、電解メッキは、上記実験例2と同じ条件で行った。
2:絶縁膜
3:凹部
4:Tiを含有するCu合金薄膜
5:純Cu薄膜
6:Ti濃化層
Claims (4)
- 半導体基板上の絶縁膜に最小幅が0.15μm以下、該最小幅に対する深さの比(深さ/最小幅)が1以上の凹部を形成し、この絶縁膜の凹部に、Tiを0.5〜10原子%含有するCu合金薄膜を凹部形状に沿って10〜50nmの厚さで形成した後、Cu合金薄膜付き凹部に純Cu薄膜を形成し、350℃以上に加熱して絶縁膜とCu合金薄膜との間にTiを析出させることを特徴とする半導体配線の製造方法。
- 前記Cu合金薄膜をスパッタリング法で形成する請求項1に記載の製造方法。
- 前記純Cu薄膜をスパッタリング法で形成し、押圧して純Cu薄膜をCu合金薄膜付き凹部に押し込む請求項1または2に記載の製造方法。
- 前記押圧を50MPa以上で行なう請求項3に記載の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2006192153A JP2008021807A (ja) | 2006-07-12 | 2006-07-12 | 半導体配線の製造方法 |
US11/765,006 US7781339B2 (en) | 2006-07-12 | 2007-06-19 | Method of fabricating semiconductor interconnections |
TW096122919A TWI357128B (en) | 2006-07-12 | 2007-06-25 | Method of fabricating semiconductor interconnectio |
KR1020070069377A KR100871042B1 (ko) | 2006-07-12 | 2007-07-11 | 반도체 상호 접속부 제조 방법 |
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JP2006192153A JP2008021807A (ja) | 2006-07-12 | 2006-07-12 | 半導体配線の製造方法 |
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US (1) | US7781339B2 (ja) |
JP (1) | JP2008021807A (ja) |
KR (1) | KR100871042B1 (ja) |
TW (1) | TWI357128B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010084844A1 (ja) * | 2009-01-20 | 2010-07-29 | 株式会社神戸製鋼所 | 半導体配線の製造方法 |
WO2012117853A1 (ja) | 2011-03-01 | 2012-09-07 | Jx日鉱日石金属株式会社 | 銅チタン合金製スパッタリングターゲット、同スパッタリングターゲットを用いて形成した半導体配線並びに同半導体配線を備えた半導体素子及びデバイス |
WO2013058234A1 (ja) * | 2011-10-17 | 2013-04-25 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置 |
JP2013105753A (ja) * | 2011-11-10 | 2013-05-30 | Toshiba Corp | 半導体装置の製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010021490A (ja) * | 2008-07-14 | 2010-01-28 | Kobe Steel Ltd | 半導体配線 |
Citations (3)
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JPH1154458A (ja) * | 1997-05-08 | 1999-02-26 | Applied Materials Inc | メタライゼーション構造体 |
JP2001007049A (ja) * | 1999-06-25 | 2001-01-12 | Hitachi Ltd | 半導体集積回路装置の製造方法およびその製造装置 |
JP2004071960A (ja) * | 2002-08-08 | 2004-03-04 | Kobe Steel Ltd | 配線膜の形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3892621B2 (ja) | 1999-04-19 | 2007-03-14 | 株式会社神戸製鋼所 | 配線膜の形成方法 |
US6451177B1 (en) * | 2000-01-21 | 2002-09-17 | Applied Materials, Inc. | Vault shaped target and magnetron operable in two sputtering modes |
JP3449960B2 (ja) * | 2000-02-25 | 2003-09-22 | 沖電気工業株式会社 | 半導体装置の製造方法 |
KR100550505B1 (ko) * | 2001-03-01 | 2006-02-13 | 가부시끼가이샤 도시바 | 반도체 장치 및 반도체 장치의 제조 방법 |
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- 2007-06-19 US US11/765,006 patent/US7781339B2/en not_active Expired - Fee Related
- 2007-06-25 TW TW096122919A patent/TWI357128B/zh not_active IP Right Cessation
- 2007-07-11 KR KR1020070069377A patent/KR100871042B1/ko not_active IP Right Cessation
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010084844A1 (ja) * | 2009-01-20 | 2010-07-29 | 株式会社神戸製鋼所 | 半導体配線の製造方法 |
JP2010171063A (ja) * | 2009-01-20 | 2010-08-05 | Kobe Steel Ltd | 半導体配線の製造方法 |
WO2012117853A1 (ja) | 2011-03-01 | 2012-09-07 | Jx日鉱日石金属株式会社 | 銅チタン合金製スパッタリングターゲット、同スパッタリングターゲットを用いて形成した半導体配線並びに同半導体配線を備えた半導体素子及びデバイス |
WO2013058234A1 (ja) * | 2011-10-17 | 2013-04-25 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置 |
JP2013105753A (ja) * | 2011-11-10 | 2013-05-30 | Toshiba Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20080006479A (ko) | 2008-01-16 |
US7781339B2 (en) | 2010-08-24 |
KR100871042B1 (ko) | 2008-11-27 |
US20080014743A1 (en) | 2008-01-17 |
TW200818394A (en) | 2008-04-16 |
TWI357128B (en) | 2012-01-21 |
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