JP2007220893A - Multilayer circuit board and its manufacturing method - Google Patents

Multilayer circuit board and its manufacturing method Download PDF

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JP2007220893A
JP2007220893A JP2006039380A JP2006039380A JP2007220893A JP 2007220893 A JP2007220893 A JP 2007220893A JP 2006039380 A JP2006039380 A JP 2006039380A JP 2006039380 A JP2006039380 A JP 2006039380A JP 2007220893 A JP2007220893 A JP 2007220893A
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circuit board
interlayer connection
connection hole
layer
multilayer circuit
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JP4813204B2 (en
JP2007220893A5 (en
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Fumihiko Matsuda
田 文 彦 松
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Nippon Mektron KK
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Nippon Mektron KK
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Priority to JP2006039380A priority Critical patent/JP4813204B2/en
Priority to TW095141333A priority patent/TWI391063B/en
Priority to KR1020060111952A priority patent/KR101170764B1/en
Priority to CN200610166785A priority patent/CN100594758C/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer circuit board capable of forming a minute circuit that allows high-density mounting, and also, to provide a method for inexpensively and stably manufacturing such a multilayer circuit board. <P>SOLUTION: The multilayer circuit board is composed so that an outer-layer build-up layer is laminated on an inner-layer core substrate so as to be connected by an interlayer connection hole. A thickness of a conductor provided to the inner-layer core substrate so as to constitute a receiving land 6 of the interlayer connection hole is thicker than that of a conductor of a wiring pattern of the inner-layer core substrate excluding the part of the interlayer connection hole. The multilayer circuit board and its manufacturing method are provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ビルドアップ型多層回路基板およびその製造方法に係わり、特にビルドアップ層の配線パターンを微細化する多層回路基板およびその製造方法に関する。   The present invention relates to a build-up type multilayer circuit board and a method for manufacturing the same, and more particularly to a multilayer circuit board for miniaturizing a wiring pattern of a build-up layer and a method for manufacturing the same.

近年、電子機器の小型化および高機能化は益々促進されてきており、そのために回路基板に対する高密度化の要求が高まってきている。   In recent years, downsizing and higher functionality of electronic devices have been promoted more and more, and therefore, there is an increasing demand for higher density of circuit boards.

そこで、高密度実装を実現するため、両面あるいは多層フレキシブル回路基板をコア基板として、１〜２層程度のビルドアップ層を両面あるいは片面に有するビルドアップ型多層フレキシブル回路基板も実用化されている（特許文献１）。   Therefore, in order to realize high-density mounting, a build-up type multilayer flexible circuit board having a double-sided or multilayer flexible circuit board as a core substrate and having about one or two build-up layers on both sides or one side has been put into practical use ( Patent Document 1).

しかしながら、上述のビルドアップ型多層フレキシブル回路基板には、高密度実装を必ずしも容易に行えない問題がある。すなわち、ビルドアップ層と内層の両面コア基板を電気的に接続する有底型の導通部、いわゆるビアホールで内層コア基板の回路と最外層の回路を電気的に接続する際に、ビアホールの深さが深くなるにつれて、各構成部材の厚み方向の熱膨張によるビア導通部が破壊されたり、めっき皮膜形成工程でめっき液が底部で滞留し易くなったりして、厚みを十分に得られないことがある。   However, the above-described build-up type multilayer flexible circuit board has a problem that high-density mounting cannot always be performed easily. That is, the depth of the via hole when electrically connecting the circuit of the inner layer core substrate and the circuit of the outermost layer with a so-called via hole having a bottom, which electrically connects the build-up layer and the inner layer double-sided core substrate As the thickness becomes deeper, the via conduction part due to thermal expansion in the thickness direction of each component member is destroyed, or the plating solution tends to stay at the bottom in the plating film forming process, and the thickness may not be sufficiently obtained. is there.

そこで、電気的信頼性を確保するために、ビアホール壁面のめっき厚を厚くすることになり最外層導体層の厚さが厚くなってしまい、微細回路の形成が困難なものとなり、高密度実装の要求を満たすことが困難となる。   Therefore, in order to ensure electrical reliability, the plating thickness of the via hole wall surface is increased, and the thickness of the outermost conductor layer is increased, making it difficult to form a fine circuit, and high density mounting. It becomes difficult to meet the requirements.

図５は、従来の多層回路基板の製造方法を示す断面工程図であって、先ず、図５(1)に示すように、ポリイミド等の可撓性絶縁ベース材１５１（ここでは、厚さ25μmのポリイミド）の両面に厚さ8μmの銅箔１５２，１５３を有する、いわゆる両面銅張積層板に対し、層間接続孔１５４をNCドリル等で形成すると共に、層間接続孔１５４とその周辺部を除いて、部分めっき用レジスト層１５５を形成する。   FIG. 5 is a cross-sectional process diagram illustrating a conventional method for manufacturing a multilayer circuit board. First, as shown in FIG. 5 (1), a flexible insulating base material 151 such as polyimide (in this case, a thickness of 25 μm). An interlayer connection hole 154 is formed with a NC drill or the like on a so-called double-sided copper clad laminate having copper foils 152 and 153 having a thickness of 8 μm on both sides of the polyimide), and the interlayer connection hole 154 and its peripheral portion are excluded. Then, a partial plating resist layer 155 is formed.

次に図５(2)に示すように、層間接続孔１５４に対し、導電化処理とそれに続く電解メッキ処理により、10μm程度の電解めっき皮膜１５６を形成して層間接続路を完成する。ここまでの工程で貫通型の導通部であるスルーホールが形成される。このように、両面の導通部にのみめっき皮膜を形成し、配線パターンを形成する領域の銅箔上にはめっき皮膜を形成しない構成は、配線パターンのための導電層を薄く構成できることから、微細回路を形成するのに好適である。   Next, as shown in FIG. 5 (2), an interlayer connection path is completed by forming an electroplating film 156 of about 10 μm in the interlayer connection hole 154 by conducting treatment and subsequent electrolytic plating treatment. Through-holes that are through-type conductive portions are formed through the steps up to here. In this way, the configuration in which the plating film is formed only on the conductive portions on both sides and the plating film is not formed on the copper foil in the region where the wiring pattern is to be formed is because the conductive layer for the wiring pattern can be made thin. Suitable for forming a circuit.

次いで、図５(3)に示すように、両面の配線パターンをフォトファブリケーション手法により形成するためのレジスト層の形成、露光、現像、エッチング、レジスト層剥離等の一連の工程によって、スルーホールランド１５７を含む配線パターン１５８を形成する。   Next, as shown in FIG. 5 (3), through-hole lands are formed through a series of processes such as resist layer formation, exposure, development, etching, and resist layer peeling for forming a wiring pattern on both sides by a photofabrication technique. A wiring pattern 158 including 157 is formed.

続いて、図５(4)に示すように、例えば12μm厚のポリイミドフィルム１５９を厚さ20μmのアクリル・エポキシ等の接着材１６０を用いて、接着して、カバーレイ１６１を形成する。   Subsequently, as shown in FIG. 5 (4), for example, a 12 μm-thick polyimide film 159 is bonded using an adhesive 160 such as acrylic / epoxy having a thickness of 20 μm to form a coverlay 161.

両面にカバーレイ１６１を接着するには、回路間隙や、層間接続孔への気泡の混入を防止するべく、真空プレス、真空ラミネータ等を用いて接着される。   In order to adhere the cover lay 161 to both surfaces, it is adhered using a vacuum press, a vacuum laminator or the like in order to prevent air bubbles from being mixed into the circuit gap and the interlayer connection hole.

ここまでの工程で、両面型のコア基板１６２を得る。   The double-sided core substrate 162 is obtained through the steps so far.

この後、図６(5)に示すように、ポリイミド等の可撓性絶縁ベース材１６３（ここでは厚さ25μmのポリイミド）の片面に厚さ12μmの銅箔を有する、いわゆる片面銅張積層板の銅箔に対し、レーザ加工によって樹脂を除去して有底の層間接続孔を形成するための開口１６４を、レジスト層の形成、露光、現像、エッチング、レジスト層の剥離等の一連の工程によるフォトファブリケーション手法にて形成して、レーザの遮光用コンフォーマルマスク１６５とすると共に、両面コア基板１６２にビルドアップするための接着材１６６により、両面コア基板１６２に積層接着する。接着剤１６６としては、ローフロータイプのプリプレグ、ボンディングシート等の流れ出しの少ないものが好ましい。   Thereafter, as shown in FIG. 6 (5), a so-called single-sided copper-clad laminate having a 12 μm thick copper foil on one side of a flexible insulating base material 163 such as polyimide (here, a polyimide having a thickness of 25 μm). An opening 164 for forming a bottomed interlayer connection hole by removing the resin by laser processing is formed in a series of processes such as resist layer formation, exposure, development, etching, and resist layer peeling. It is formed by a photofabrication technique to form a laser light-shielding conformal mask 165 and is laminated and adhered to the double-sided core substrate 162 by an adhesive 166 for building up the double-sided core substrate 162. The adhesive 166 is preferably a low-flow type prepreg, a bonding sheet, or the like with little flow-out.

次に図６(6)に示すように、上記工程で作製したコンフォーマルマスク１６５を用い、レーザ加工を行い、層間接続孔１６７を形成する。レーザ加工法は、UV-YAGレーザ、炭酸レーザ、エキシマレーザ等を選択可能である。   Next, as shown in FIG. 6 (6), laser processing is performed using the conformal mask 165 manufactured in the above process to form an interlayer connection hole 167. As the laser processing method, a UV-YAG laser, a carbonic acid laser, an excimer laser, or the like can be selected.

次いで、図６(7)に示すように、導電化処理とそれに続く電解メッキ処理により、層間接続のための25〜30μm程度の厚みを有する電解めっき皮膜１６８の形成を行い、有底のビアホールによる層間接続路を形成する。   Next, as shown in FIG. 6 (7), an electroplating film 168 having a thickness of about 25 to 30 μm for interlayer connection is formed by a conductive process followed by an electroplating process, and a bottomed via hole is used. An interlayer connection path is formed.

続いて、図７(8)に示すように、外層のパターン１６９を通常のフォトファブリケーション手法により形成する。この後、必要に応じてフォトソルダーレジスト層の形成、半田めっき、ニッケルめっき、金めっき等の表面処理を施し、外形加工を行うことで多層回路基板を得る。   Subsequently, as shown in FIG. 7 (8), an outer layer pattern 169 is formed by a normal photofabrication technique. Thereafter, surface treatment such as formation of a photo solder resist layer, solder plating, nickel plating, and gold plating is performed as necessary, and outer shape processing is performed to obtain a multilayer circuit board.

上述のように、25〜30μm程度の電解めっきを12μm厚の銅箔上に行うと、外層の総導体厚は37〜42μmになり、回路ピッチ100μmの微細パターンを歩留まりよく形成することは困難であるため、高密度実装の要求を満足することができない。
特開2004-200260号公報 As mentioned above, when electrolytic plating of about 25-30 μm is performed on 12 μm thick copper foil, the total conductor thickness of the outer layer becomes 37-42 μm, and it is difficult to form a fine pattern with a circuit pitch of 100 μm with high yield. Therefore, the demand for high-density mounting cannot be satisfied.
Japanese Patent Laid-Open No. 2004-200260

このように、従来の手法では、ビルドアップ層と内層の両面コア基板を電気的に接続するビアホールの接続信頼性を確保するために必要なビルドアップ層のビアホールめっき厚が厚くなり、微細回路の形成が困難なものとなり、高密度実装の要求を満足することができない。このため、高密度実装が可能な多層回路基板を安価かつ安定的に製造する方法の出現が望まれている。   Thus, in the conventional method, the via-hole plating thickness of the build-up layer necessary to ensure the connection reliability of the via hole that electrically connects the build-up layer and the double-sided core substrate of the inner layer is increased, and the fine circuit It becomes difficult to form, and the demand for high-density mounting cannot be satisfied. For this reason, the advent of a method for stably and inexpensively manufacturing a multilayer circuit board capable of high-density mounting is desired.

本発明は上述の点を考慮してなされたもので、微細で高密度実装が可能な回路を形成し得る多層回路基板を提供するとともに、そのような多層回路基板を安価かつ安定的に製造する方法を提供することを目的とする。   The present invention has been made in consideration of the above-described points, and provides a multilayer circuit board capable of forming a fine and high-density circuit that can be manufactured at low cost and stably. It aims to provide a method.

上記目的達成のため、本願では、次の各発明を提供する。   In order to achieve the above object, the present invention provides the following inventions.

第１の発明によれば、
内層コア基板に外層ビルドアップ層を積層し、層間接続孔により接続した多層回路基板において、
前記内層コア基板に設けられ前記層間接続孔の受けランドを構成する導体の厚みが、前記層間接続孔の部分を除く前記内層コア基板の配線パターンの導体の厚みよりも厚いことを特徴とする。 According to the first invention,
In the multilayer circuit board in which the outer layer build-up layer is laminated on the inner core board and connected by the interlayer connection hole,
A thickness of a conductor provided on the inner layer core substrate and constituting a receiving land of the interlayer connection hole is larger than a thickness of a conductor of the wiring pattern of the inner layer core substrate excluding the portion of the interlayer connection hole.

また、第２の発明によれば、
内層コア基板に外層ビルドアップ層を積層し、層間接続孔により接続した多層回路基板の製造方法において、
a)回路基板の層間接続部を、配線パターンの厚みよりも厚く部分めっきすることにより受けランドを形成して内層コア基板を製造する工程、
b)片面型銅張積層板における前記層間接続孔を形成する部位に、穿孔用の開口を形成して外層ビルドアップ層を製造する工程、
c)前記外層ビルドアップ層のベース絶縁樹脂側を前記内層コア基板に対向させ、接着材を介して前記内層コア基板に積層接着する工程、
d)前記工程c)までで形成された積層回路基材に対し、前記開口を用いて穿孔し、前記受けランドに達する有底の層間接続孔を形成する工程、および
e)前記層間接続孔に対し導電化処理および電解めっきを行ってビアホールを形成する工程、
をそなえたことを特徴とする。 According to the second invention,
In the manufacturing method of the multilayer circuit board in which the outer layer buildup layer is laminated on the inner layer core board and connected by the interlayer connection hole,
a) a step of producing an inner core substrate by forming a receiving land by partially plating the interlayer connection portion of the circuit board thicker than the thickness of the wiring pattern;
b) a step of producing an outer buildup layer by forming an opening for perforation at a portion where the interlayer connection hole is formed in the single-sided copper clad laminate;
c) a step of causing the base insulating resin side of the outer buildup layer to face the inner core substrate, and laminating and bonding to the inner core substrate via an adhesive;
d) perforating the laminated circuit substrate formed up to step c) using the opening to form a bottomed interlayer connection hole reaching the receiving land; and
e) a step of forming a via hole by conducting a conductive treatment and electrolytic plating on the interlayer connection hole;
It is characterized by having.

これらの特徴により、本発明は次のような効果を奏する。   Due to these features, the present invention has the following effects.

本発明による多層回路基板は、ビアホールの受けランドのめっきを厚付けしているため、この受けランドを底面として利用するビアホールの深さを浅くして壁面が短縮されたビアホールを形成できる。このため、壁面へのめっき皮膜の電着が容易となり構成部材の熱膨張の影響を受け難くなる。このため、歩留まりの向上や信頼性を確保するのに必要なめっき厚の低減が図れて、微細な配線パターンを外層に歩留まり良く形成することができ、回路基板の高密度実装化ができる。   In the multilayer circuit board according to the present invention, since the via hole receiving land is thickened, the via hole using the receiving land as a bottom surface can be made shallow to form a via hole with a shortened wall surface. For this reason, the electrodeposition of the plating film on the wall surface is facilitated and it is difficult to be affected by the thermal expansion of the constituent members. For this reason, the plating thickness necessary for improving the yield and ensuring the reliability can be reduced, and a fine wiring pattern can be formed in the outer layer with a good yield, and the circuit board can be mounted at a high density.

この結果、本発明によれば、従来の製造方法では困難であった高密度実装が可能な多層回路基板を安価かつ安定的に製造する方法を提供できる。   As a result, according to the present invention, it is possible to provide a method for stably and inexpensively manufacturing a multilayer circuit board capable of high-density mounting, which has been difficult with the conventional manufacturing method.

以下、添付図面を参照して本発明の実施形態を説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

実施形態１Embodiment 1

図１は、本発明の実施形態１による多層回路基板の構造を示す概念的な断面構成図である。この実施形態１は、内層の両面コア基板１４に対して、片面の外層回路基板を積層し、内層回路とビルドアップした外層回路基板の回路を、有底のビアホールで接合する構成である。   FIG. 1 is a conceptual cross-sectional configuration diagram showing the structure of a multilayer circuit board according to Embodiment 1 of the present invention. In the first embodiment, a single-sided outer layer circuit board is laminated on the inner-layer double-sided core substrate 14, and the inner-layer circuit and the built-up circuit of the outer-layer circuit board are joined by a bottomed via hole.

この多層回路基板では、内層回路基板および外層回路基板が可撓性を有するフレキシブル回路基板用の素材を用いており、フレキシブルな内層の両面基板の一部が多層部の外部に伸張してケーブル部を構成するフレキシブル多層回路基板となっている。   In this multilayer circuit board, the inner layer circuit board and the outer layer circuit board use flexible circuit board materials that are flexible, and a part of the flexible inner layer double-sided board extends to the outside of the multilayer part and the cable part. Is a flexible multilayer circuit board.

そして、この実施形態１の特徴は、内層回路基板の回路と外層回路基板の回路とを電気的に接続するビアホールの受けランド部１０に、電解メッキ皮膜７が形成されている点にある。   The feature of the first embodiment is that an electrolytic plating film 7 is formed on the receiving land portion 10 of the via hole that electrically connects the circuit of the inner layer circuit board and the circuit of the outer layer circuit board.

図２は、本発明の実施形態１による多層回路基板の製造方法を示す断面工程図である。この実施形態１では、図１に示したフレキシブル多層回路基板を構造例として取り上げて説明する。   FIG. 2 is a cross-sectional process diagram illustrating a method of manufacturing a multilayer circuit board according to Embodiment 1 of the present invention. In the first embodiment, the flexible multilayer circuit board shown in FIG. 1 will be described as a structural example.

まず、ポリイミド等の可撓性絶縁ベース材１（ここでは厚さ25μmのポリイミド）の図示上下両面に、厚さ8μmの銅箔２および３を有する、いわゆる両面銅張積層板を用意する。このときの銅箔は、屈曲性に優れる圧延銅箔あるいは特殊電解銅箔が好ましい。   First, a so-called double-sided copper-clad laminate having 8 μm-thick copper foils 2 and 3 on both upper and lower sides of a flexible insulating base material 1 such as polyimide (here, polyimide having a thickness of 25 μm) is prepared. The copper foil at this time is preferably a rolled copper foil or a special electrolytic copper foil having excellent flexibility.

続いて図２(1)に示すように、この両面銅張積層板に対し、層間接続孔４をNCドリル等で形成する。さらに、層間接続孔４とその周辺部、および後工程で形成される層間接続用孔の底部に位置するビアホール受けランド形成部５を除いて、部分めっき用レジスト層６を形成する。   Subsequently, as shown in FIG. 2 (1), an interlayer connection hole 4 is formed in the double-sided copper-clad laminate with an NC drill or the like. Further, a resist layer 6 for partial plating is formed except for the interlayer connection hole 4 and its peripheral part, and the via hole receiving land forming part 5 located at the bottom of the interlayer connection hole formed in a later process.

次に図２(2)に示すように、層間接続孔４および受けランド形成部５に対し、導電化処理とそれに続く電解メッキ処理により、10μm程度の電解めっき皮膜７を形成して層間接続孔とする。この際、受けランド部５の導体厚を厚く構成する。ここまでの工程で、貫通型の導通部であるスルーホールが形成される。   Next, as shown in FIG. 2 (2), the interlayer connection hole 4 and the receiving land forming portion 5 are formed with an electroplating film 7 of about 10 μm by conducting a conductive process and subsequent electrolytic plating process. And At this time, the receiving land portion 5 is configured to have a large conductor thickness. Through the steps up to here, a through hole which is a through-type conductive portion is formed.

次いで、両面の配線パターンをフォトファブリケーション手法によって形成するためのレジスト層の形成、露光、現像、エッチング、レジスト層剥離等の一連の工程を施し、図２(3)に示すスルーホールランド８を含む配線パターン９および受けランド部１０を形成する。   Next, a series of steps such as resist layer formation, exposure, development, etching, resist layer peeling and the like for forming a wiring pattern on both sides by a photofabrication method are performed, and the through-hole land 8 shown in FIG. The wiring pattern 9 and the receiving land portion 10 are formed.

続いて、図２(4)に示すように、例えば12μm厚のポリイミドフィルム１１を厚さ20μmのアクリル・エポキシ等の接着材１２を用いて接着することにより、カバーレイ１３を形成する。このカバーレイ１３を形成する際、例えば平板プレス等の平行度、平滑性のある熱盤を持ったプレス装置で貼り付ける。   Subsequently, as shown in FIG. 2 (4), for example, a 12 μm-thick polyimide film 11 is adhered using an adhesive 12 such as acrylic / epoxy having a thickness of 20 μm, thereby forming a coverlay 13. When this cover lay 13 is formed, the cover lay 13 is pasted with a press device having a parallel and smooth hot plate such as a flat plate press.

ここで、平板プレス等を用いる理由は、導体厚みの異なる場所でもカバーレイ表面が平滑に処理される必要があるからである。また、鏡面処理されたステンレス板等を中間板として用いても同様の効果が得られる。   Here, the reason for using a flat plate press or the like is that the coverlay surface needs to be processed smoothly even at places where the conductor thickness is different. The same effect can be obtained even if a mirror-finished stainless plate or the like is used as the intermediate plate.

さらに、逐次ラミネート工程を適用する場合には、最初のラミネートを接着剤の流動性がなくならない温度で、真空ラミネータ等の充填性の良い装置で行い、続いて上述の平板プレス等を用いる方法も採用できる。ここまでの工程で、多層回路基板のコア基板となる両面コア基板１４を得る。   Furthermore, when applying the sequential laminating process, the first laminating is performed at a temperature at which the adhesive does not lose its fluidity, using a device with good filling properties such as a vacuum laminator, and then using the above-described flat plate press or the like. Can be adopted. Through the steps so far, the double-sided core substrate 14 to be the core substrate of the multilayer circuit board is obtained.

この後、図３(5)に示すように、片面銅張積層板の銅箔に開口１６を形成してコンフォーマルマスク１７とし、両面コア基板１４の図示上下両面に積層する。   Thereafter, as shown in FIG. 3 (5), an opening 16 is formed in the copper foil of the single-sided copper-clad laminate to form a conformal mask 17, which is laminated on the upper and lower surfaces of the double-sided core substrate 14 as shown.

すなわち、ポリイミド等の可撓性絶縁ベース材１５（ここでは厚さ25μmのポリイミド）の片面に厚さ12μmの銅箔を有する、いわゆる片面銅張積層板の銅箔に対し、レーザ加工によって樹脂を除去して有底の層間接続孔を形成するための開口１６を、レジスト層の形成、露光、現像、エッチング、レジスト層の剥離等の一連の工程によるフォトファブリケーション手法にて形成して、レーザの遮光用コンフォーマルマスク１７とする。これと共に、両面コア基板１４にビルドアップするための接着材１８により、両面コア基板１４に積層接着する。接着剤１８としては、ローフロータイプのプリプレグやボンディングシート等の流れ出しの少ないものが好ましい。   That is, a resin is applied by laser processing to a copper foil of a so-called single-sided copper clad laminate having a 12 μm thick copper foil on one side of a flexible insulating base material 15 such as polyimide (here, a polyimide having a thickness of 25 μm). An opening 16 for removing and forming a bottomed interlayer connection hole is formed by a photofabrication technique through a series of steps such as resist layer formation, exposure, development, etching, and resist layer peeling. The light shielding conformal mask 17 is used. At the same time, it is laminated and adhered to the double-sided core substrate 14 by an adhesive 18 for building up the double-sided core substrate 14. The adhesive 18 is preferably a low-flow type prepreg, bonding sheet, or the like with little flow-out.

次に図３(6)に示すように、上記工程で作製したコンフォーマルマスク１７を用いてレーザ加工を行い、層間接続孔１９を形成する。レーザ加工法は、UV-YAGレーザ、炭酸レーザ、エキシマレーザ等を選択して実施することができる。   Next, as shown in FIG. 3 (6), laser processing is performed using the conformal mask 17 produced in the above-described process to form an interlayer connection hole 19. The laser processing method can be performed by selecting a UV-YAG laser, a carbonic acid laser, an excimer laser, or the like.

次いで、図４(7)に示すように、導電化処理とそれに続く電解メッキ処理により、層間接続のための25〜30μm程度の厚みを有する電解めっき皮膜２０の形成を行い、有底のビアホール層間接続路とする。   Next, as shown in FIG. 4 (7), an electroplating film 20 having a thickness of about 25 to 30 μm for interlayer connection is formed by conductive treatment and subsequent electrolytic plating treatment, and a bottomed via-hole interlayer is formed. A connection path.

続いて、図４(8)に示すように、外層のパターン２１を通常のフォトファブリケーション手法により形成する。この後、必要に応じてフォトソルダーレジスト層の形成、半田めっき、ニッケルめっき、金めっき等の表面処理を施し、外形加工を行うことで、多層回路基板を得る。   Subsequently, as shown in FIG. 4 (8), an outer layer pattern 21 is formed by a normal photofabrication technique. Thereafter, surface treatment such as formation of a photo solder resist layer, solder plating, nickel plating, gold plating, or the like is performed as necessary, and an outer shape process is performed to obtain a multilayer circuit board.

上記製造方法によれば、層間接続孔の受けランド部１０にめっき皮膜７が形成されているため、層間接続孔１９の深さが、従来の構造に比べて１０μm程度浅くなり、層間接続孔１９に対するビアホールの壁面めっき皮膜の電着容易性の向上が図れること、構成部材の熱膨張の影響を受け難いこと等の有利な構造となる。このため、歩留まりの向上や信頼性を確保するのに必要なめっき厚の低減が図れる。   According to the above manufacturing method, since the plating film 7 is formed on the receiving land portion 10 of the interlayer connection hole, the depth of the interlayer connection hole 19 becomes shallower by about 10 μm than the conventional structure, and the interlayer connection hole 19. Therefore, it is possible to improve the ease of electrodeposition of the wall-plated film of the via hole with respect to the above, and it is advantageous in that it is hardly affected by the thermal expansion of the constituent members. For this reason, it is possible to reduce the plating thickness necessary for improving the yield and ensuring the reliability.

また、この受けランド部１０にもめっきを付けている構造は、層間接続孔を形成するためのレーザ加工時の熱ダメージを緩和する効果も有する。   Further, the structure in which the receiving land portion 10 is also plated has an effect of alleviating thermal damage during laser processing for forming the interlayer connection hole.

更に、層間接続孔を、NCドリルを用いた非貫通加工により形成すれば、従来工法では深さ方向に高い加工精度が要求され作業が難しかったのに比べ、加工マージンを増やす効果もある。このことから、設計仕様によっては、レーザ加工よりも、さらに安価なNCドリルによる非貫通加工を選択することも可能となる。   Furthermore, if the interlayer connection hole is formed by non-penetration processing using an NC drill, the conventional method requires a high processing accuracy in the depth direction and has an effect of increasing the processing margin. Therefore, depending on the design specifications, it is possible to select non-penetrating machining with an NC drill that is even cheaper than laser machining.

実施形態１では、めっきの厚付けにより、層間接続孔の深さを浅くする手法を選択したが、受けランドに導電性のペースト・インキ等を印刷する等の手法も選択できる。   In the first embodiment, the method of decreasing the depth of the interlayer connection hole by thickening the plating is selected, but a method of printing conductive paste / ink or the like on the receiving land can also be selected.

なお、レーザ加工には、上記のようにコンフォーマルマスクを用いた加工以外にも、予めレーザのビーム径よりも大きく銅マスクを開口しておき、そこへレーザ加工を行うラージウインドウ法も適用可能である。   In addition to the processing using a conformal mask as described above, a large window method in which a copper mask larger than the laser beam diameter is opened in advance and laser processing is applied to the laser processing is also applicable. It is.

さらに、銅箔と樹脂とを直接レーザ光で貫通させるダイレクトレーザ法も適用可能である。加えて、上記コンフォーマルマスクを用いた加工とラージウインドウ法、ダイレクトレーザ法とを組み合わせてもよい。なお、ダイレクトレーザ法を用いる場合、実施形態１のように銅箔の厚さは20μm以下であることが好ましい。   Furthermore, a direct laser method in which the copper foil and the resin are directly penetrated with laser light is also applicable. In addition, the process using the conformal mask may be combined with the large window method and the direct laser method. In the case of using the direct laser method, the thickness of the copper foil is preferably 20 μm or less as in the first embodiment.

他の実施形態Other embodiments

図２ないし図４に示した多層回路基板は、コア基板を可撓性回路基板とし、その一部を可撓性ケーブル部２２として、多層の部品実装部から伸張する構成のフレキシブル多層回路基板としてあるが、コア基板が可撓性ケーブルを構成しない多層回路基板であってもまた、同様である。   The multilayer circuit board shown in FIGS. 2 to 4 is a flexible multilayer circuit board having a structure in which a core board is a flexible circuit board and a part thereof is a flexible cable part 22 and extends from a multilayer component mounting part. The same applies to a multilayer circuit board in which the core board does not constitute a flexible cable.

また、多層回路基板は、コア基板の両面ではなく片面だけに外層ビルドアップ層を積層する構成としてもよい。   Further, the multilayer circuit board may have a configuration in which the outer buildup layer is laminated only on one side, not on both sides of the core board.

本発明の実施形態１による多層回路基板の構造を示す断面図。Sectional drawing which shows the structure of the multilayer circuit board by Embodiment 1 of this invention. 本発明の実施形態１による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by Embodiment 1 of this invention. 本発明の実施形態１による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by Embodiment 1 of this invention. 本発明の実施形態１による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by Embodiment 1 of this invention. 従来工法による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by a conventional construction method. 従来工法による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by a conventional construction method. 従来工法による多層回路基板の製造方法を示す断面工程図。Sectional process drawing which shows the manufacturing method of the multilayer circuit board by a conventional construction method.

符号の説明Explanation of symbols

１ 可撓性絶縁ベース材
２，３ 銅箔
４ 層間接続孔
５ 受けランド形成部
６ 部分めっき用レジスト層
７ 電解めっき皮膜
８ スルーホールランド
９ 配線パターン
１０ 受けランド部
１１ ポリイミドフィルム
１２ 接着材
１３ カバーレイ
１４ 両面コア基板
１５ 可撓性絶縁ベース材
１６ 開口
１７ コンフォーマルマスク
１８ 接着剤
１９ 層間接続孔
２０ 電解めっき皮膜
２１ 外層のパターン
２２ 可撓性ケーブル部 DESCRIPTION OF SYMBOLS 1 Flexible insulating base material 2,3 Copper foil 4 Interlayer connection hole 5 Receiving land formation part 6 Resist layer for partial plating 7 Electrolytic plating film 8 Through-hole land 9 Wiring pattern 10 Receiving land part 11 Polyimide film 12 Adhesive material 13 Cover Lay 14 Double-sided core substrate 15 Flexible insulating base material 16 Opening 17 Conformal mask 18 Adhesive 19 Interlayer connection hole 20 Electroplating film 21 Pattern of outer layer 22 Flexible cable portion

Claims (2)

内層コア基板に外層ビルドアップ層を積層し、層間接続孔により接続した多層回路基板において、
前記内層コア基板に設けられ前記層間接続孔の受けランドを構成する導体の厚みが、前記層間接続孔の部分を除く前記内層コア基板の配線パターンの導体の厚みよりも厚いことを特徴とする多層回路基板。 In the multilayer circuit board in which the outer layer build-up layer is laminated on the inner core board and connected by the interlayer connection hole,
The multilayer provided in the inner layer core substrate, the conductor constituting the receiving land of the interlayer connection hole is thicker than the conductor thickness of the wiring pattern of the inner layer core substrate excluding the portion of the interlayer connection hole Circuit board. 内層コア基板に外層ビルドアップ層を積層し、層間接続孔により接続した多層回路基板の製造方法において、
a)回路基板の層間接続部を、配線パターンの厚みよりも厚く部分めっきすることにより受けランドを形成して内層コア基板を製造する工程、
b)片面型銅張積層板における前記層間接続孔を形成する部位に、穿孔用の開口を形成して外層ビルドアップ層を製造する工程、
c)前記外層ビルドアップ層のベース絶縁樹脂側を前記内層コア基板に対向させ、接着材を介して前記内層コア基板に積層する工程、
d)前記工程c)までで形成された積層回路基材に対し、前記開口を用いて穿孔し、前記受けランドに達する有底の層間接続孔を形成する工程、および
e)前記層間接続孔に対し導電化処理および電解めっきを行ってビアホールを形成する工程、
をそなえたことを特徴とする多層回路基板の製造方法。 In the manufacturing method of the multilayer circuit board in which the outer layer buildup layer is laminated on the inner layer core board and connected by the interlayer connection hole,
a) a step of producing an inner core substrate by forming a receiving land by partially plating the interlayer connection portion of the circuit board thicker than the thickness of the wiring pattern;
b) a step of producing an outer buildup layer by forming an opening for perforation at a portion where the interlayer connection hole is formed in the single-sided copper clad laminate;
c) a step of causing the base insulating resin side of the outer buildup layer to face the inner core substrate and laminating the inner core substrate via an adhesive;
d) perforating the laminated circuit substrate formed up to step c) using the opening to form a bottomed interlayer connection hole reaching the receiving land; and
e) a step of forming a via hole by conducting a conductive treatment and electrolytic plating on the interlayer connection hole;
A method for producing a multilayer circuit board, comprising:
JP2006039380A 2006-02-16 2006-02-16 Multilayer circuit board manufacturing method Active JP4813204B2 (en)

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KR1020060111952A KR101170764B1 (en) 2006-02-16 2006-11-14 Method for manufacturing Multi-layer circuit board
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KR101946989B1 (en) * 2011-12-09 2019-02-12 엘지이노텍 주식회사 The printed circuit board and the method for manufacturing the same
CN106163141A (en) * 2016-07-08 2016-11-23 台山市精诚达电路有限公司 The manufacture method of four layers of FPC
JP7381323B2 (en) * 2019-12-17 2023-11-15 日東電工株式会社 Method for manufacturing double-sided printed circuit board and double-sided printed circuit board

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