JP2007220816A - Thin-film transistor and manufacturing method thereof - Google Patents

Thin-film transistor and manufacturing method thereof Download PDF

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JP2007220816A
JP2007220816A JP2006038425A JP2006038425A JP2007220816A JP 2007220816 A JP2007220816 A JP 2007220816A JP 2006038425 A JP2006038425 A JP 2006038425A JP 2006038425 A JP2006038425 A JP 2006038425A JP 2007220816 A JP2007220816 A JP 2007220816A
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thin film
insulating film
gate electrode
oxide semiconductor
gate insulating
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JP5015470B2 (en
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Takashi Hirao
孝 平尾
Mamoru Furuta
守 古田
Hiroshi Furuta
寛 古田
Tokiyoshi Matsuda
時宜 松田
Takahiro Hiramatsu
孝浩 平松
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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<P>PROBLEM TO BE SOLVED: To form source and drain regions by executing ionization by plasma discharge easily forming a large area, selecting an element forming a shallow impurity level in an oxide semiconductor thin-film layer, forming ions over a large area without performing mass separation for a gas made of this element by plasma decomposition or the like and introducing the ionized element into the oxide semiconductor thin-film layer. <P>SOLUTION: In the thin-film transistor, a gate insulating film and a gate electrode are self-alignedly formed into the same shape, and the oxide semiconductor thin-film layer is source-drain regions including a region where the concentration of at least one kind of elements of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe) and oxygen (O) is higher in a range other than the lower side of the gate electrode than in a range of the lower side of the gate electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は薄膜トランジスタ及びその製法に係り、より詳しくは少なくとも酸化物半導体薄膜層を活性層に有する薄膜トランジスタ（以下、TFTと略）及びその製法に関する。   The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor (hereinafter abbreviated as TFT) having at least an oxide semiconductor thin film layer as an active layer and a manufacturing method thereof.

酸化亜鉛あるいは酸化マグネシウム亜鉛等の酸化物が優れた半導体(活性層)の性質を示すことは古くから知られており、近年薄膜トランジスタ、発光デバイス、透明導電膜等の電子デバイス応用を目指し、これらの化合物を用いた半導体薄膜層の研究開発が活発化している。
酸化亜鉛や酸化マグネシウム亜鉛を半導体薄膜層として用いたTFTは、従来液晶ディスプレイに主に用いられているアモルファスシリコン(a−Si：H)を半導体薄膜層として用いたアモルファスシリコンTFTに比較して電子移動度が大きく、優れたTFT特性を有し、また、室温付近の低温でも多結晶薄膜が得られることで高い移動度が期待できる等の利点もあり、積極的な開発が進められている。 It has been known for a long time that oxides such as zinc oxide or magnesium zinc oxide exhibit excellent semiconductor (active layer) properties.In recent years, with the aim of application to electronic devices such as thin film transistors, light-emitting devices, transparent conductive films, etc. Research and development of semiconductor thin film layers using compounds has been activated.
TFTs using zinc oxide or magnesium zinc oxide as semiconductor thin film layers are electrons compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as semiconductor thin film layers. Active development is underway, with advantages such as high mobility, excellent TFT characteristics, and the expectation of high mobility by obtaining a polycrystalline thin film even at low temperatures near room temperature.

酸化亜鉛を酸化物半導体薄膜層として用いたTFT(酸化亜鉛TFT)としては、ボトムゲート型及びトップゲート型の構造が報告されている。   As TFTs (zinc oxide TFTs) using zinc oxide as an oxide semiconductor thin film layer, bottom-gate and top-gate structures have been reported.

ボトムゲート型構造の一例としては、基板上より順にゲート電極およびゲート絶縁膜が形成され、その上面を被覆して酸化亜鉛を主成分とする酸化物半導体薄膜層が形成されている構造が知られている。該構造は、液晶ディスプレイの駆動素子として現在事業化されているボトムゲート型アモルファスシリコンTFTと製造プロセスにおいて類似する。そのため、該構造は、該アモルファスシリコンTFTの製造設備等で比較的容易に作成でき、酸化亜鉛TFTとしても多く用いられている。   An example of a bottom-gate structure is a structure in which a gate electrode and a gate insulating film are formed in order from the substrate, and an oxide semiconductor thin film layer mainly composed of zinc oxide is formed covering the upper surface. ing. This structure is similar in manufacturing process to the bottom gate type amorphous silicon TFT currently commercialized as a driving element of a liquid crystal display. Therefore, the structure can be created relatively easily with the production equipment of the amorphous silicon TFT, and is often used as a zinc oxide TFT.

しかしながら、ボトムゲート型の薄膜トランジスタは、構造上、酸化物半導体薄膜層がゲート絶縁膜上に積層されているため、結晶性が不十分な成膜初期の領域を活性層として用いざるを得ず、十分な移動度が得られないという問題点を抱えている。一方、トップゲート型の薄膜トランジスタは、酸化物半導体薄膜層の上部にゲート絶縁膜を設ける構造を有するので、酸化物半導体薄膜層の上部の結晶性の良好な領域を活性層として用いることができるという点でボトムゲート型の薄膜トランジスタより有効である。   However, since the bottom gate type thin film transistor has a structure in which an oxide semiconductor thin film layer is stacked on a gate insulating film, an area of initial film formation with insufficient crystallinity must be used as an active layer, There is a problem that sufficient mobility cannot be obtained. On the other hand, a top-gate thin film transistor has a structure in which a gate insulating film is provided over an oxide semiconductor thin film layer, so that a region with good crystallinity above the oxide semiconductor thin film layer can be used as an active layer. This is more effective than a bottom gate type thin film transistor.

トップゲート型構造の一例としては、基板上より順にソース・ドレイン電極、酸化物半導体薄膜層、ゲート絶縁膜、ゲート電極を積層して形成される構造を例示することができる。
しかしながらこの構造は、ソース・ドレイン電極からチャネルに至るまでの酸化物半導体薄膜層が寄生抵抗となり、電流律速が生じるという問題がある。
酸化亜鉛TFTと同様の問題が既にアモルファスシリコンTFTにおいても存在し、下記特許文献１において、図７に示す構造が解決策として開示されている。該構造は基板１０１上に一対のソース・ドレイン電極１０２、半導体薄膜層１０３、ゲート絶縁膜１０４、ゲート電極１０５が順に形成されている。また、ゲート絶縁膜１０４とゲート電極１０５が自己整合的に同じ形状を有している。加えて、半導体薄膜層１０３の膜厚方向全体において、ゲート電極の直下方以外の領域に不純物が導入され、ゲート電極の直下方の範囲より低抵抗化したソース・ドレイン領域となっている。そのため、前記電流律速を抑制することができる。なお、アモルファスシリコンTFTにおけるソース・ドレイン領域形成の方法としては、半導体薄膜層の主成分であるアモルファスシリコンに対してドナーとなる元素、例えば燐(P)をイオンの状態で外部から注入するイオン注入法が示されている。また、該構造では、イオンのドーピングをゲート絶縁膜を介さずに行えるため、イオン注入法での加圧電圧を小さくすることができる。 As an example of the top gate structure, a structure in which a source / drain electrode, an oxide semiconductor thin film layer, a gate insulating film, and a gate electrode are stacked in this order from the substrate can be exemplified.
However, this structure has a problem that the oxide semiconductor thin film layer extending from the source / drain electrodes to the channel becomes a parasitic resistance, resulting in current limiting.
A problem similar to that of the zinc oxide TFT already exists in the amorphous silicon TFT, and the structure shown in FIG. 7 is disclosed as a solution in Patent Document 1 below. In this structure, a pair of source / drain electrodes 102, a semiconductor thin film layer 103, a gate insulating film 104, and a gate electrode 105 are sequentially formed on a substrate 101. Further, the gate insulating film 104 and the gate electrode 105 have the same shape in a self-aligning manner. In addition, impurities are introduced into a region other than the region directly below the gate electrode in the entire thickness direction of the semiconductor thin film layer 103 to form a source / drain region having a lower resistance than the region immediately below the gate electrode. Therefore, the current rate limiting can be suppressed. As a method for forming source / drain regions in an amorphous silicon TFT, ion implantation is performed in which an element that serves as a donor, for example, phosphorus (P), is implanted from the outside in the form of ions into amorphous silicon that is a main component of a semiconductor thin film layer. The law is shown. Further, in this structure, since ion doping can be performed without using a gate insulating film, a pressurization voltage in the ion implantation method can be reduced.

このアモルファスシリコンTFTにおける解決方法を酸化亜鉛TFTに応用しようとした場合、酸化亜鉛に対してドナーとなる不純物としてはインジウム、ガリウム、アルミニウム等が考えられる。しかしながら、これらの不純物をイオン化してドーピングするためにはイオン注入装置が必要であるが、イオン注入装置は質量分離を行わなければならず、広い面積に高生産性にてドーピングするための制約となるという問題があった。   When the solution in the amorphous silicon TFT is applied to the zinc oxide TFT, indium, gallium, aluminum, and the like can be considered as impurities serving as donors to the zinc oxide. However, in order to ionize and dope these impurities, an ion implantation apparatus is necessary. However, the ion implantation apparatus must perform mass separation, and there are restrictions for doping a large area with high productivity. There was a problem of becoming.

特開平８−５１２０９号公報Japanese Patent Laid-Open No. 8-51209

本発明は、上記問題に鑑みてなされたものであり、その解決課題は以下に記載するものである。まず、不純物をイオン化してドーピングする際、質量分離を行わず、大面積にわたりイオンを形成する方法を確立する。そして、該方法を用いることにより、酸化亜鉛TFTにおいて、アモルファスシリコンTFTと同様の自己整合型の薄膜トランジスタを形成し、ソース・ドレイン領域からチャネルまでの寄生抵抗を減少させ、電流律速の発生を抑制する。そして、ゲート電極とソース・ドレイン領域間の寄生容量を低減させ高速動作の薄膜トランジスタを提供する。加えて、酸化亜鉛に対してイオンをドーピングすることによるダメージを低減する。   This invention is made | formed in view of the said problem, The solution subject is described below. First, when ionizing and doping impurities, a method for forming ions over a large area without mass separation is established. By using this method, a self-aligned thin film transistor similar to the amorphous silicon TFT is formed in the zinc oxide TFT, the parasitic resistance from the source / drain region to the channel is reduced, and the occurrence of current rate control is suppressed. . A high-speed thin film transistor is provided by reducing the parasitic capacitance between the gate electrode and the source / drain regions. In addition, damage caused by doping ions into zinc oxide is reduced.

請求項１に係る発明は、絶縁基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、該酸化物半導体薄膜層の少なくとも一定範囲を被覆するゲート絶縁膜と、該ゲート絶縁膜の上に積載されたゲート電極とを有する薄膜トランジスタにおいて、前記ゲート絶縁膜と前記ゲート電極が自己整合的に同一形状に形成されており、前記酸化物半導体薄膜層であって、該ゲート電極の直下方以外の範囲が、該ゲート電極の直下方の範囲よりも、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高い領域を含むソース・ドレイン領域であることを特徴とする薄膜トランジスタに関する。   The invention according to claim 1 is an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film covering at least a certain range of the oxide semiconductor thin film layer, A thin film transistor having a gate electrode stacked on a gate insulating film, wherein the gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, and are the oxide semiconductor thin film layer, A range other than directly below the electrode is greater than the range directly below the gate electrode, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), The present invention relates to a thin film transistor characterized by being a source / drain region including a region having a high concentration of at least one element group of xenon (Xe) and oxygen (O).

請求項２に係る発明は、絶縁基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、該酸化物半導体薄膜層上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に積載されたゲート電極とを有する薄膜トランジスタにおいて、前記ゲート絶縁膜が前記酸化物半導体薄膜層の少なくとも上側全面を被覆する第一ゲート絶縁膜と、該第一ゲート絶縁膜の上に形成され、且つ前記ゲート電極と自己整合的に同一形状に形成される第二ゲート絶縁膜からなり、該酸化物半導体薄膜層であって、該ゲート電極の直下方以外の範囲が、該ゲート電極の直下方の範囲よりも、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高い領域を含むソース・ドレイン領域であることを特徴とする薄膜トランジスタに関する。   The invention according to claim 2 is an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film formed on the oxide semiconductor thin film layer, and the gate insulation In a thin film transistor having a gate electrode stacked on a film, the gate insulating film is formed on the first gate insulating film and a first gate insulating film covering at least the entire upper surface of the oxide semiconductor thin film layer. And a second gate insulating film formed in the same shape as the gate electrode in a self-aligned manner, wherein the oxide semiconductor thin film layer has a range other than immediately below the gate electrode, directly below the gate electrode. From the group of elements of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) Saw that contains at least one highly concentrated area - regarding the thin film transistor, wherein the drain is region.

請求項３に係る発明は、前記第一ゲート絶縁膜が前記酸化物半導体薄膜層の上側全面のみを被覆することを特徴とする請求項２記載の薄膜トランジスタに関する。   The invention according to claim 3 relates to the thin film transistor according to claim 2, wherein the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer.

請求項４に係る発明は、絶縁基板上にチャネルとして働く酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層を被覆してゲート絶縁膜を形成する工程と、該ゲート絶縁膜の上にゲート電極を積載する行程を有する薄膜トランジスタの製法において、前記ゲート電極をマスクとして前記ゲート絶縁膜をエッチング処理し、該ゲート電極をマスクにして自己整合的に前記酸化物半導体薄膜層の該ゲート電極の直下方以外の領域に、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種をイオンの状態でドーピングすることにより、該ゲート電極の直下方以外の範囲に、該ゲート電極の直下方の範囲よりも該元素群のうち少なくとも1種の濃度が高いソース・ドレイン領域を形成することを特徴とする薄膜トランジスタの製法に関する。   The invention according to claim 4 is a step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on an insulating substrate, and a step of forming a gate insulating film by covering the oxide semiconductor thin film layer And etching the gate insulating film using the gate electrode as a mask, and self-aligning the oxidation in a self-aligned manner in a method of manufacturing a thin film transistor having a process of stacking a gate electrode on the gate insulating film In a region other than directly below the gate electrode of the semiconductor thin film layer, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe) , By doping at least one element group of oxygen (O) in an ionic state, at least in the element group in a range other than directly below the gate electrode than in a range immediately below the gate electrode. 1 type of dark The present invention relates to a method for manufacturing a thin film transistor, characterized by forming a source / drain region having a high degree.

請求項５に係る発明は、絶縁基板上にチャネルとして働く酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層の少なくとも上側全面を被覆して第一ゲート絶縁膜を形成する工程と、該第一ゲート絶縁膜の上に第二ゲート絶縁膜を形成する工程と、該第二ゲート絶縁膜の上にゲート電極を積載する行程を含む薄膜トランジスタの製法において、前記ゲート電極をマスクとして前記第二ゲート絶縁膜をエッチング処理し、該ゲート電極をマスクにして自己整合的に前記酸化物半導体薄膜層の該ゲート電極の直下方以外の領域に、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種をイオンの状態でドーピングすることにより、該ゲート電極の直下方以外の範囲に、該ゲート電極の直下方の範囲よりも該元素群のうち少なくとも1種の濃度が高いソース・ドレイン領域を形成することを特徴とする薄膜トランジスタの製法に関する。   According to a fifth aspect of the invention, there is provided a step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on an insulating substrate, and covering at least the entire upper surface of the oxide semiconductor thin film layer to form a first gate. In a method of manufacturing a thin film transistor including a step of forming an insulating film, a step of forming a second gate insulating film on the first gate insulating film, and a step of loading a gate electrode on the second gate insulating film, Etching the second gate insulating film using the gate electrode as a mask, and using the gate electrode as a mask, in a region other than directly below the gate electrode of the oxide semiconductor thin film layer in a self-aligned manner, hydrogen (H) , Helium (He), Neon (Ne), Argon (Ar), Krypton (Kr), Fluorine (F), Xenon (Xe), Oxygen (O) The gate In the range other than immediately below the pole, to a thin film transistor manufacturing method, characterized in that at least one concentration of said original pixel group than the range of just below of the gate electrode to form a high source-drain region.

請求項６に係る発明は、前記酸化物半導体薄膜層と前記第一ゲート絶縁膜を一括してエッチングすることを特徴とする請求項５記載の薄膜トランジスタに関する。   The invention according to claim 6 relates to the thin film transistor according to claim 5, wherein the oxide semiconductor thin film layer and the first gate insulating film are etched together.

請求項７に係る発明は、前記ソース・ドレイン領域の形成のためのイオンのドーピングを、イオンを加速して行うことを特徴とする請求項４乃至６いずれか記載の薄膜トランジスタの製法に関する。   The invention according to claim 7 relates to a method of manufacturing a thin film transistor according to any one of claims 4 to 6, wherein the ion doping for forming the source / drain regions is performed by accelerating the ions.

請求項８に係る発明は、前記ソース・ドレイン領域の形成において、前記元素群のうち少なくとも1種のガスをプラズマ分解し、該プラズマ雰囲気に、前記酸化物半導体薄膜層における前記ゲート電極の直下方以外の範囲を暴露することを特徴とする請求項４乃至６いずれか記載の薄膜トランジスタの製法に関する。   According to an eighth aspect of the present invention, in the formation of the source / drain regions, at least one gas of the element group is plasma-decomposed, and the plasma atmosphere is directly below the gate electrode in the oxide semiconductor thin film layer. 7. The method of manufacturing a thin film transistor according to claim 4, wherein a range other than the above is exposed.

請求項９に係る発明は、前記ソース・ドレイン領域の形成の工程において、前記絶縁基板にバイアス電力を印加することを特徴とする請求項８記載の薄膜トランジスタの製法に関する。   The invention according to claim 9 relates to a method of manufacturing a thin film transistor according to claim 8, wherein bias power is applied to the insulating substrate in the step of forming the source / drain regions.

請求項１に係る発明によれば、ゲート絶縁膜とゲート電極が自己整合的に同一形状に形成されるので、ソース・ドレイン領域となる領域上にゲート絶縁膜が存在しなくなり、イオンをドーピングする方法で低抵抗化を行う際、印加電圧を小さいものとすることができ、酸化亜鉛に対してイオンをドーピングすることによるダメージを低減することができる。
また、ゲート電極の直下方以外の範囲が、ゲート電極の直下方の範囲より、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高い領域を含むことにより、ゲート電極の直下方以外の範囲が低抵抗化したソース・ドレイン領域を有するため、ソース・ドレイン電極からチャネルまでの寄生抵抗を抑えることができ、電流律速を抑制することができる。
また、ゲート電極の直下方以外の領域がソース・ドレイン領域となっているため、ソース・ドレイン領域の内側端とゲート電極の両端が膜厚方向に揃った位置に存在することとなり、ソース・ドレイン領域とゲート電極間の寄生容量が低減し、動作速度の低下を防ぐことができる。 According to the first aspect of the present invention, since the gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, the gate insulating film does not exist on the region to be the source / drain region, and ions are doped. When the resistance is reduced by this method, the applied voltage can be reduced, and damage caused by doping ions into zinc oxide can be reduced.
In addition, the range other than directly below the gate electrode is more than the range directly below the gate electrode, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F) By including a region having a high concentration of at least one of the element groups of xenon (Xe) and oxygen (O), the region other than directly below the gate electrode has a low resistance source / drain region. -Parasitic resistance from the drain electrode to the channel can be suppressed, and current rate limiting can be suppressed.
In addition, since the regions other than the region directly below the gate electrode are the source / drain regions, the inner ends of the source / drain regions and both ends of the gate electrode are present at the positions aligned in the film thickness direction. The parasitic capacitance between the region and the gate electrode is reduced, and a reduction in operation speed can be prevented.

請求項２に係る発明によれば、第二ゲート絶縁膜がゲート電極と自己整合的に同一形状に形成されているので、ソース・ドレイン領域となる領域上にはゲート絶縁膜として、第一ゲート絶縁膜のみしか存在せず、ゲート電極下に存在するゲート絶縁膜よりも膜厚が薄くなる。そのため、イオンをドーピングする方法で低抵抗化を行う際、印加電圧を小さいものとすることができる。加えて、第一ゲート絶縁膜が、ソース・ドレイン領域を保護する役割を果たし、ソース・ドレイン領域のさらなる抵抗低減を図れる。
また、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高いソース・ドレイン領域を有するため、ソース・ドレイン電極からチャネルまでの寄生抵抗を抑えることができ、電流律速を抑制することができる。
また、ゲート電極の直下方以外の領域がソース・ドレイン領域となっているため、ソース・ドレイン領域とゲート電極間の寄生容量が低減し、動作速度の低下を防ぐことができる。 According to the second aspect of the present invention, since the second gate insulating film is formed in the same shape as the gate electrode in a self-aligned manner, the first gate is formed as a gate insulating film on the region to be the source / drain region. Only the insulating film exists, and the film thickness becomes thinner than the gate insulating film existing under the gate electrode. Therefore, when the resistance is reduced by the ion doping method, the applied voltage can be reduced. In addition, the first gate insulating film serves to protect the source / drain regions, and the resistance of the source / drain regions can be further reduced.
Further, at least one element group selected from the group consisting of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), and oxygen (O). Since the source / drain region has a high concentration, parasitic resistance from the source / drain electrode to the channel can be suppressed, and current rate control can be suppressed.
In addition, since the region other than the region directly below the gate electrode is the source / drain region, the parasitic capacitance between the source / drain region and the gate electrode is reduced, and a reduction in operation speed can be prevented.

請求項３に係る発明によれば、請求項２に係る発明による効果に加え、第一ゲート絶縁膜が酸化物半導体薄膜層の上側全面のみを被覆する構造をとるため、酸化物半導体薄膜層をレジスト剥離液といった各種薬液から保護する役割を果たすことができる。そのため、酸化物半導体薄膜層の表面あれを防ぐことができ、酸化物半導体薄膜層とゲート絶縁膜の界面特性を良好に維持することができる。   According to the invention of claim 3, in addition to the effect of the invention of claim 2, the first gate insulating film has a structure covering only the entire upper surface of the oxide semiconductor thin film layer. It can play a role of protecting from various chemicals such as a resist stripping solution. Therefore, surface roughness of the oxide semiconductor thin film layer can be prevented, and the interface characteristics between the oxide semiconductor thin film layer and the gate insulating film can be favorably maintained.

請求項４に係る発明によれば、ゲート電極をマスクとしてゲート絶縁膜をエッチング処理することで、ゲート絶縁膜を介さずにソース・ドレイン領域を形成できるので、イオンをドーピングする際、印加電圧等を小さいものとすることができる。
また、ゲート電極の直下方以外の領域にソース・ドレイン領域を形成することにより、ソース・ドレイン領域の内側端とゲート電極の両端が膜厚方向に揃った位置に存在することとなるので、ソース・ドレイン領域とゲート電極間の寄生容量が低減し、動作速度の低下を防ぐことができる。
また、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)といった元素は、プラズマ分解等により容易にイオン化できるので、質量分離を行わずに、大面積にわたってイオンをドーピングすることができる。 According to the fourth aspect of the present invention, the source / drain regions can be formed without the gate insulating film by etching the gate insulating film using the gate electrode as a mask. Can be made small.
In addition, by forming the source / drain region in a region other than directly below the gate electrode, the inner end of the source / drain region and both ends of the gate electrode exist at positions aligned in the film thickness direction. -Parasitic capacitance between the drain region and the gate electrode is reduced, and a reduction in operating speed can be prevented.
Also, elements such as hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) can be easily decomposed by plasma decomposition. Thus, ions can be doped over a large area without mass separation.

請求項５に係る発明によれば、ゲート電極をマスクとして第二ゲート絶縁膜をエッチング処理することで、ソース・ドレイン領域上に第一ゲート絶縁膜が残り、第一ゲート絶縁膜だけを介してソース・ドレイン領域を形成できる。そのため、第一ゲート絶縁膜を薄膜化することで、イオンをドーピングする方法で低抵抗化を行う際、印加電圧等を小さいものとすることができる。さらに、ソース・ドレイン領域上を第一ゲート絶縁膜が被膜しているため、製造工程においてソース・ドレイン領域を保護することもできる。そのため、ソース・ドレイン領域のさらなる抵抗低減を図ることができる。
また、ゲート電極の直下方以外の領域にソース・ドレイン領域を形成することにより、ソース・ドレイン領域とゲート電極間の寄生容量が低減し、動作速度の低下を防ぐことができる。
また、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)といった元素は、プラズマ分解等により容易にイオン化できるので、質量分離を行わずに、大面積にわたってイオンをドーピングすることができる。 According to the invention of claim 5, by etching the second gate insulating film using the gate electrode as a mask, the first gate insulating film remains on the source / drain regions, and only through the first gate insulating film. Source / drain regions can be formed. Therefore, by reducing the thickness of the first gate insulating film, the applied voltage or the like can be reduced when the resistance is reduced by the ion doping method. Furthermore, since the first gate insulating film covers the source / drain regions, the source / drain regions can be protected in the manufacturing process. Therefore, the resistance of the source / drain regions can be further reduced.
Further, by forming the source / drain regions in regions other than directly below the gate electrode, the parasitic capacitance between the source / drain regions and the gate electrode can be reduced, and a reduction in operating speed can be prevented.
Also, elements such as hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) can be easily decomposed by plasma decomposition. Thus, ions can be doped over a large area without mass separation.

請求項６に係る発明によれば、請求項５に係る発明の効果に加え、酸化物半導体薄膜層と第一ゲート絶縁膜を一括してエッチング処理することで、酸化物半導体薄膜層をレジスト剥離液といった各種薬液から保護することができ、酸化物半導体薄膜層の表面あれを防ぐことができる。そのため、酸化物半導体薄膜層とゲート絶縁膜の界面特性が良好に維持される。   According to the invention of claim 6, in addition to the effect of the invention of claim 5, the oxide semiconductor thin film layer and the first gate insulating film are collectively etched to remove the oxide semiconductor thin film layer from the resist. It can be protected from various chemicals such as liquids, and surface roughness of the oxide semiconductor thin film layer can be prevented. Therefore, favorable interface characteristics between the oxide semiconductor thin film layer and the gate insulating film are maintained.

請求項７に係る発明によれば、ソース・ドレイン領域の形成のためのイオンを加速して酸化物半導体薄膜層にドーピングすることで、層全体において、より確実にイオンをドーピングすることができる。   According to the invention of claim 7, by accelerating ions for forming the source / drain regions and doping the oxide semiconductor thin film layer, the ions can be more reliably doped in the entire layer.

請求項８に係る発明によれば、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の少なくとも1種のガスをプラズマ分解し、該プラズマ雰囲気に、酸化物半導体薄膜層におけるゲート電極の直下方以外の範囲を暴露することで、広範囲にわたり低抵抗化されたソース・ドレイン領域を形成することができる。   According to the invention of claim 8, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) At least one kind of gas is plasma-decomposed, and a source / drain region having a low resistance over a wide range is formed by exposing the plasma atmosphere to a region other than the region immediately below the gate electrode in the oxide semiconductor thin film layer. Can do.

請求項９に係る発明によれば、ソース・ドレイン領域の形成の工程において、絶縁基板にバイアス電力を印加することで、広範囲にわたり、且つ、層全体がより確実に低抵抗化されたソース・ドレイン領域を形成することができる。   According to the ninth aspect of the present invention, in the step of forming the source / drain region, by applying bias power to the insulating substrate, the resistance of the entire layer can be reduced more reliably over a wide range. Regions can be formed.

以下、図面を参照しながら、本発明の薄膜トランジスタの実施形態について説明する。
図１は本発明に係る薄膜トランジスタの第一の実施形態を示す断面図である。 Hereinafter, embodiments of the thin film transistor of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a first embodiment of a thin film transistor according to the present invention.

本発明の第一の実施形態に係る薄膜トランジスタ１００は、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、ゲート絶縁膜４、ゲート電極６、層間絶縁膜７、コンタクト部８ａ、一対のソース・ドレイン外部電極２ａ、表示電極９を有しており、図１に示すように、これら各構成を積層して形成されており、通常、スタガ型といわれる。   A thin film transistor 100 according to the first embodiment of the present invention includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a gate insulating film 4, a gate electrode 6, an interlayer insulating film 7, a contact portion 8a, It has a pair of source / drain external electrodes 2a and a display electrode 9, and is formed by laminating these components as shown in FIG. 1, and is usually called a stagger type.

薄膜トランジスタ１００は、図１に示す通り、ガラス（SiO2とAl2O3を主成分とする無アルカリガラス）からなる基板１上に形成される。
基板１の材料は、ガラスに限定されず、プラスチックや金属箔に絶縁体をコーティングしたもの等、絶縁体であれば使用可能である。 As shown in FIG. 1, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO 2 and Al 2 O 3 as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulator such as a plastic or metal foil coated with an insulator.

基板１上には、一対のソース・ドレイン電極２が積層されている。この一対のソース・ドレイン電極２は、基板１上面に間隙を有して配置されている。
ソース・ドレイン電極２は、例えば、インジウムスズ酸化物(ITO)、n＋ZnO等の導電性酸化物、金属、もしくは前記導電性酸化物により少なくとも一部を被覆された金属により形成される。 A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are disposed on the upper surface of the substrate 1 with a gap.
The source / drain electrode 2 is formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n + ZnO, a metal, or a metal at least partially covered with the conductive oxide.

酸化物半導体薄膜層３は、一対のソース・ドレイン電極２の電極間にチャネルを形成するように配置されており、酸化亜鉛を主成分とする酸化物半導体から形成されている。ここで、酸化亜鉛を主成分とする酸化物半導体とは、真性の酸化亜鉛の他、Li、Na、N、C等のp型ドーパントおよびB、Al、Ga、In等のn型ドーパントがドーピングされた酸化亜鉛およびMg、Be等がドーピングされた酸化亜鉛を含む。
また、酸化物半導体薄膜層３はチャネル領域３１と一対のソース・ドレイン領域３２からなる。チャネル領域３１は酸化物半導体薄膜層３のチャネルとして利用される範囲である。一対のソース・ドレイン領域３２は酸化物半導体薄膜層３のゲート絶縁膜に被覆されない領域に自己整合的に形成され、チャネル領域３１より水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の少なくとも1種の濃度が高く、これにより、チャネル領域３１よりソース・ドレイン領域３２のほうが抵抗が低くなる。
この一対のソース・ドレイン領域３２を設けることにより、ソース・ドレイン電極からチャネルまでの寄生抵抗を抑えることができ、電流律速を抑制することができる。
この酸化物半導体薄膜層３の厚みは、特に限定されないが、例えば約25〜200nmに形成され、好ましくは、50〜100nm程度に形成される。なお、図１において、ソース・ドレイン領域３２は、各ソース・ドレイン電極２上に形成されている部分の厚さが、一対のソース・ドレイン電極２間に形成された部分よりも薄く図示されているが、これは単なる図示の都合であって、実際には、両者の厚さはほぼ同一である。 The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component is doped with intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C, and n-type dopants such as B, Al, Ga, and In. And zinc oxide doped with Mg, Be and the like.
The oxide semiconductor thin film layer 3 includes a channel region 31 and a pair of source / drain regions 32. The channel region 31 is a range used as a channel of the oxide semiconductor thin film layer 3. The pair of source / drain regions 32 is formed in a self-aligned manner in a region not covered with the gate insulating film of the oxide semiconductor thin film layer 3, and hydrogen (H), helium (He), neon (Ne), argon from the channel region 31. The concentration of at least one of (Ar), krypton (Kr), fluorine (F), xenon (Xe), and oxygen (O) is higher, so that the resistance of the source / drain region 32 is lower than that of the channel region 31. .
By providing the pair of source / drain regions 32, parasitic resistance from the source / drain electrodes to the channel can be suppressed, and current rate limiting can be suppressed.
Although the thickness of this oxide semiconductor thin film layer 3 is not specifically limited, For example, it forms in about 25-200 nm, Preferably, it forms in about 50-100 nm. In FIG. 1, the source / drain region 32 is illustrated such that the thickness of the portion formed on each source / drain electrode 2 is thinner than the portion formed between the pair of source / drain electrodes 2. However, this is merely for the convenience of illustration, and in fact, the thicknesses of both are almost the same.

ゲート絶縁膜４は、酸化物半導体薄膜層３のチャネル領域３１の上側全面のみを被覆するように形成されている。
ゲート絶縁膜４は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いて酸素をドーピングした膜により形成される。このゲート絶縁膜４は酸化珪素化合物（SiOx）や酸窒化珪素（SiON）に比較して誘電率の大きい、窒化珪素（SiNx）に酸素あるいは酸素を構成元素として含む化合物、例えば酸化窒素(N2O)、を用いて酸素をドーピングした膜が好ましく用いられる。これにより、誘電率が高く、酸化物半導体薄膜層の保護の観点からも優れた薄膜トランジスタとなる。 The gate insulating film 4 is formed so as to cover only the entire upper surface of the channel region 31 of the oxide semiconductor thin film layer 3.
The gate insulating film 4 is a silicon oxide (SiOx) film, silicon oxynitride (SiON) film, silicon nitride (SiNx) film, or silicon nitride (SiNx) doped with oxygen using oxygen or a compound containing oxygen as a constituent element. It is formed by a film. The gate insulating film 4 has a dielectric constant larger than that of a silicon oxide compound (SiOx) or silicon oxynitride (SiON), and a compound containing oxygen or oxygen as a constituent element in silicon nitride (SiNx), for example, nitrogen oxide (N 2 A film doped with oxygen using O) is preferably used. Accordingly, the thin film transistor has a high dielectric constant and is excellent from the viewpoint of protecting the oxide semiconductor thin film layer.

ゲート電極６は、ゲート絶縁膜４上に形成されている。このゲート電極６は、薄膜トランジスタに印加するゲート電圧により酸化物半導体薄膜層３中の電子密度を制御する役割を果たすものである。
ゲート電極６はCr、Tiで例示できる金属膜からなる。
また、ゲート電極６の両端は、ソース・ドレイン領域の内側端と膜厚方向に揃った位置に存在する。それにより、ソース・ドレイン領域とゲート電極間に寄生容量が低減し、動作速度の低下を防ぐことができる。
加えて、ゲート電極６の両端部はソース・ドレイン電極の内側端部より内側の位置にあることが好ましい。これにより、ゲート電極６とソース・ドレイン電極２間の寄生容量が低減し、動作速度の低下を起こさないからである。 The gate electrode 6 is formed on the gate insulating film 4. The gate electrode 6 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.
The gate electrode 6 is made of a metal film exemplified by Cr and Ti.
Further, both ends of the gate electrode 6 exist at positions aligned with the inner ends of the source / drain regions in the film thickness direction. As a result, parasitic capacitance is reduced between the source / drain regions and the gate electrode, and a reduction in operating speed can be prevented.
In addition, it is preferable that both end portions of the gate electrode 6 are located inside the inner end portions of the source / drain electrodes. This is because the parasitic capacitance between the gate electrode 6 and the source / drain electrode 2 is reduced, and the operating speed is not lowered.

層間絶縁膜７は一対のソース・ドレイン電極２及びゲート電極６の表面全面を被覆するように積層されている。   The interlayer insulating film 7 is laminated so as to cover the entire surface of the pair of source / drain electrodes 2 and the gate electrode 6.

一対のソース・ドレイン外部電極２ａはコンタクト部８ａを介してそれぞれ対応するソース・ドレイン電極２と接続される。   The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 8a.

表示電極９は、液晶ディスプレイに用いる液晶に薄膜トランジスタを介して電圧を印加するために形成される。この電極は可視光に対する高い透過率が要求されるため、酸化物導電性薄膜であるインジウムスズ酸化物(ITO)などにより形成される。   The display electrode 9 is formed to apply a voltage to the liquid crystal used in the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, it is formed of indium tin oxide (ITO), which is an oxide conductive thin film.

また、図３で示すような第二の実施形態も考えられる。第二の実施形態は、通常、コプラナー型といわれるもので、一対のソース・ドレイン領域の上にそれぞれ対応するソース・ドレイン電極を接続した構造を有している。第二の実施形態のTFT２００の一部は、第一の実施形態のTFTと同様の構造を有し、従って、同じ参照番号を示している。第二の実施形態のTFT２００の場合、一対のソース・ドレイン領域３２は少なくとも上表面だけが低抵抗化していればよい。   A second embodiment as shown in FIG. 3 is also conceivable. The second embodiment is generally called a coplanar type, and has a structure in which corresponding source / drain electrodes are connected to a pair of source / drain regions, respectively. A part of the TFT 200 of the second embodiment has the same structure as that of the TFT of the first embodiment, and therefore shows the same reference numerals. In the case of the TFT 200 of the second embodiment, it is sufficient that at least the upper surface of the pair of source / drain regions 32 has a low resistance.

また、図４で示すような第三の実施形態も考えられる。第三の実施形態に係るTFT３００の一部はTFT１００及びTFT２００と同じ構造を有しており、同じ参照番号を付してある。但し、ゲート絶縁膜４は第一ゲート絶縁膜と第二ゲート絶縁膜からなり、便宜上、第一ゲート絶縁膜４１及び第二ゲート絶縁膜５とする。   A third embodiment as shown in FIG. 4 is also conceivable. A part of the TFT 300 according to the third embodiment has the same structure as the TFT 100 and the TFT 200, and is given the same reference number. However, the gate insulating film 4 includes a first gate insulating film and a second gate insulating film. For convenience, the first gate insulating film 41 and the second gate insulating film 5 are used.

第一ゲート絶縁膜４１は、酸化物半導体薄膜層３の上側表面及び側面を全面に亘って被覆するように形成されている。この第一ゲート絶縁膜４１は、ソース・ドレイン領域３２を被覆しているため、製造工程におけるエッチング処理などからソース・ドレイン領域３２を保護することができる。   The first gate insulating film 41 is formed so as to cover the entire upper surface and side surfaces of the oxide semiconductor thin film layer 3. Since the first gate insulating film 41 covers the source / drain region 32, the source / drain region 32 can be protected from an etching process or the like in the manufacturing process.

第二ゲート絶縁膜５は、第一ゲート絶縁膜４１の上部の一部分を覆うように、ゲート電極６と自己整合的に同一形状で形成される。   The second gate insulating film 5 is formed in the same shape as the gate electrode 6 in a self-aligning manner so as to cover a part of the upper part of the first gate insulating film 41.

第一ゲート絶縁膜４１と第二ゲート絶縁膜５は異なる化合物で形成される。これにより、第一ゲート絶縁膜４１をエッチングせずに、第二ゲート絶縁膜のみをエッチングすることができる。具体的には、第一ゲート絶縁膜４１を酸化珪素（SiOx）膜、第二ゲート絶縁膜５を窒化珪素（SiNx）膜とする構成などが挙げられる。   The first gate insulating film 41 and the second gate insulating film 5 are formed of different compounds. Thereby, only the second gate insulating film can be etched without etching the first gate insulating film 41. Specifically, a configuration in which the first gate insulating film 41 is a silicon oxide (SiOx) film and the second gate insulating film 5 is a silicon nitride (SiNx) film is exemplified.

また、図６で示すような第四の実施形態も考えられる。第四の実施形態に係るTFT４００は、TFT３００の第一ゲート絶縁膜４１が、酸化物半導体薄膜層３の上表面のみを被覆した構造である。従って、TFT３００と同じ参照番号を付している。
TFT４００は、第一ゲート絶縁膜が酸化物半導体薄膜層の上側全面のみを被覆する構造をとる。このような構造をとるために、酸化物半導体薄膜層３と第一ゲート絶縁膜４１が一括してエッチングされることとなり、第一ゲート絶縁膜４１が酸化物半導体薄膜層３をレジスト剥離液といった各種薬液から保護する役割を果たす。なお、好ましくは、酸化物半導体薄膜層３と第一ゲート絶縁膜４１を真空中にて連続的に形成するのがよい。これにより、真空中で形成した酸化物半導体薄膜層３と第一ゲート絶縁膜４１の良好な界面が維持され、TFT特性の向上が期待できる。 A fourth embodiment as shown in FIG. 6 is also conceivable. The TFT 400 according to the fourth embodiment has a structure in which the first gate insulating film 41 of the TFT 300 covers only the upper surface of the oxide semiconductor thin film layer 3. Therefore, the same reference numbers as those of the TFT 300 are given.
The TFT 400 has a structure in which the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer. In order to adopt such a structure, the oxide semiconductor thin film layer 3 and the first gate insulating film 41 are collectively etched, and the first gate insulating film 41 forms the oxide semiconductor thin film layer 3 as a resist stripping solution. Plays a role in protecting against various chemicals. Preferably, the oxide semiconductor thin film layer 3 and the first gate insulating film 41 are continuously formed in a vacuum. Thereby, a good interface between the oxide semiconductor thin film layer 3 formed in vacuum and the first gate insulating film 41 is maintained, and an improvement in TFT characteristics can be expected.

なお、本発明には、ゲート絶縁膜が二層からなり、且つソース・ドレイン領域の上にソース・ドレイン電極を接続した構造（コプラナー型）も当然含まれる。また、ゲート絶縁膜が３層以上からなる構造も当然含まれる。   The present invention naturally includes a structure (coplanar type) in which the gate insulating film is formed of two layers and the source / drain electrodes are connected on the source / drain regions. Further, a structure in which the gate insulating film is composed of three or more layers is naturally included.

本発明の第一の実施形態の薄膜トランジスタ（TFT）の製造方法について、図２に基づいて以下に説明する。   A method of manufacturing the thin film transistor (TFT) according to the first embodiment of the present invention will be described below with reference to FIG.

まず、図２（１）に示される如く、基板１及び一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３として酸化亜鉛を主成分とする半導体薄膜、好適には真性酸化亜鉛(ZnO)、を例えば50〜100nm程度の膜厚でマグネトロンスパッタ法にて形成し、パターニングする。その上に酸化亜鉛表面が低抵抗化されない手法および条件でゲート絶縁膜４を形成する。
ゲート絶縁膜４の形成方法の一例として、プラズマ化学気相成長（PCVD）法でSiNxを50〜500nm厚で形成する方法が挙げられる。条件例としては、基板温度250℃でNH3とSiH4の混合ガスをNH3がSiH4の４倍の流量となるように調整して行う条件が例示される。 First, as shown in FIG. 2A, a semiconductor thin film mainly composed of zinc oxide as an oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, preferably intrinsic zinc oxide ( ZnO) is formed by magnetron sputtering with a film thickness of, for example, about 50 to 100 nm and patterned. A gate insulating film 4 is formed thereon by a technique and conditions that do not reduce the resistance of the zinc oxide surface.
An example of a method for forming the gate insulating film 4 is a method of forming SiNx with a thickness of 50 to 500 nm by plasma enhanced chemical vapor deposition (PCVD). Examples of conditions include conditions performed by adjusting the mixed gas of NH 3 and SiH 4 at a substrate temperature of 250 ° C. so that NH 3 has a flow rate four times that of SiH 4 .

図２（２）に示される如く、ゲート絶縁膜４上にゲート電極６を積載し、ゲート電極６をマスクとして、ゲート絶縁膜４をSF6等のガスを用いてドライエッチングする。 As shown in FIG. 2B, a gate electrode 6 is loaded on the gate insulating film 4, and the gate insulating film 4 is dry-etched using a gas such as SF 6 using the gate electrode 6 as a mask.

図２（３）はゲート絶縁膜４をドライエッチングした後の断面図を示しており、ゲート絶縁膜４とゲート電極６が自己整合的に同一形状に形成されている。また、酸化物半導体薄膜層３は当該処理でエッチングを行わないので、両端部分がゲート絶縁膜４で被覆されておらず露出した構造となる。   FIG. 2 (3) shows a cross-sectional view after the gate insulating film 4 is dry-etched. The gate insulating film 4 and the gate electrode 6 are formed in the same shape in a self-aligning manner. In addition, since the oxide semiconductor thin film layer 3 is not etched by the treatment, both end portions are not covered with the gate insulating film 4 and are exposed.

ゲート絶縁膜４のパターン形成後、図２（４）に示される如く、酸化物半導体薄膜層３の膜厚方向全体において、ゲート電極６をマスクとして露出した一対のソース・ドレイン領域３２にイオンをドーピングし低抵抗化を行う。低抵抗化は、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の少なくとも1種をイオンの状態でドーピングすることで行う。
これらの元素はゲート絶縁膜を介さずにドーピングするため、ドーピング時のエネルギーを抑制することができる。
また、これらの元素をドーピングする際、イオンドーピング法やプラズマ処理によるドーピング等を用いると、質量分離を行う必要がなく、大面積にわたってイオンをドーピングすることができる。イオンドーピング法によるイオンのドーピングは、プラズマ処理によるドーピングに比べ、膜全体において、より確実にイオンをドーピングすることができる。また、プラズマ処理によりドーピングする際、絶縁基板にバイアス電力を印加することで、イオンを層全体により確実にドーピングすることもできる。
イオンをドーピングする方法としては、質量分離を行ってイオン化するイオン注入法も挙げられる。イオン注入法を用いても、プラズマ処理によるドーピングに比べ、層全体において、より確実にイオンをドーピングすることができる。
なお、イオンをドーピングする方法は、上記された方法に限らない。 After the pattern formation of the gate insulating film 4, as shown in FIG. 2 (4), ions are applied to the pair of source / drain regions 32 exposed using the gate electrode 6 as a mask in the entire film thickness direction of the oxide semiconductor thin film layer 3. Doping to reduce resistance. Low resistance is achieved by ionizing at least one of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), and oxygen (O). This is done by doping in this state.
Since these elements are doped without going through the gate insulating film, energy during doping can be suppressed.
Further, when these elements are doped, if ion doping or plasma treatment is used, it is not necessary to perform mass separation, and ions can be doped over a large area. Ion doping by the ion doping method can more reliably dope ions in the entire film than doping by plasma treatment. In addition, when doping is performed by plasma treatment, ions can be reliably doped in the entire layer by applying a bias power to the insulating substrate.
As a method for doping ions, an ion implantation method in which ionization is performed by performing mass separation can also be used. Even if the ion implantation method is used, ions can be more reliably doped in the entire layer as compared with doping by plasma treatment.
The method for doping ions is not limited to the method described above.

図２（５）に示す如く、前記基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、ゲート電極６上全面に層間絶縁膜７を形成する。   As shown in FIG. 2 (5), an interlayer insulating film 7 is formed on the entire surface of the substrate 1, the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6.

その後、図２（６）に示す如く、フォトリソグラフィーを用いて、ソース・ドレイン電極２上にコンタクトホールを開口し、一対のソース・ドレイン外部電極２ａをコンタクト部８ａを介して、それぞれに対応するソース・ドレイン電極２に接続する。最後に、インジウムスズ酸化物(ITO)等からなる表示電極９を形成することでTFTアレイが完成する。   After that, as shown in FIG. 2 (6), contact holes are opened on the source / drain electrodes 2 by photolithography, and the pair of source / drain external electrodes 2a are respectively corresponded through the contact portions 8a. Connected to source / drain electrode 2. Finally, the display electrode 9 made of indium tin oxide (ITO) or the like is formed to complete the TFT array.

本発明の第二の実施形態の薄膜トランジスタ（TFT）の製造方法について、以下に説明する（図示せず）。
まず、基板１上の全面に酸化物半導体薄膜層３を形成し、パターニングする。その後、酸化物半導体薄膜層３上にゲート絶縁膜４を被覆して、その上にゲート電極７を積載する。ゲート電極７をマスクとして、ゲート絶縁膜４をエッチングし、酸化物半導体薄膜層３の該エッチング処理で露出した部分を低抵抗化して一対のソース・ドレイン領域３２を形成する。
低抵抗化の方法としては、第一の実施形態と同様に水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の少なくとも1種をイオンの状態でドーピングすることで行う。また、第二の実施形態ではソース・ドレイン領域は少なくとも上表面が低抵抗化されていればよい。
その後、層間絶縁膜７を形成し、コンタクトホールを開口して、ソース・ドレイン電極２をそれぞれに対応するソース・ドレイン領域３２と接続する。最後に表示電極９を形成して、第二の実施形態に係るTFTアレイが完成する。 A method for manufacturing a thin film transistor (TFT) according to the second embodiment of the present invention will be described below (not shown).
First, the oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and patterned. Thereafter, the gate insulating film 4 is coated on the oxide semiconductor thin film layer 3 and the gate electrode 7 is loaded thereon. The gate insulating film 4 is etched using the gate electrode 7 as a mask, and the resistance of the exposed portion of the oxide semiconductor thin film layer 3 is reduced to form a pair of source / drain regions 32.
As a method of reducing resistance, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe) as in the first embodiment. , By doping at least one kind of oxygen (O) in an ionic state. In the second embodiment, it is sufficient that at least the upper surface of the source / drain region has a low resistance.
Thereafter, an interlayer insulating film 7 is formed, contact holes are opened, and the source / drain electrodes 2 are connected to the corresponding source / drain regions 32. Finally, the display electrode 9 is formed, and the TFT array according to the second embodiment is completed.

次に、第三の実施形態に係るTFTの製造方法を説明する。
まず、図５（１）に示す如く、基板１及び一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３を被膜し、パターニングする。そして、図５（２）に示す如く、酸化亜鉛が低抵抗化されない手法および条件で第一ゲート絶縁膜４１を形成する。 Next, a method for manufacturing a TFT according to the third embodiment will be described.
First, as shown in FIG. 5A, an oxide semiconductor thin film layer 3 is coated on the entire surface of the substrate 1 and the pair of source / drain electrodes 2 and patterned. Then, as shown in FIG. 5 (2), the first gate insulating film 41 is formed by a technique and conditions that do not reduce the resistance of zinc oxide.

図５（３）に示す如く、第一ゲート絶縁膜４１を被覆するように第二ゲート絶縁膜５を形成する。第二ゲート絶縁膜５上にゲート電極６を積載し、ゲート電極６をマスクとして、第二ゲート絶縁膜５をSF6等のガスを用いてドライエッチングする。第一ゲート絶縁膜４１と第二ゲート絶縁膜５を異なる化合物とすることで、第一ゲート絶縁膜４１をエッチングせずに、第二ゲート絶縁膜５のみをエッチングすることができる。また、第一ゲート絶縁膜４１がソース・ドレイン領域３２を被覆しているため、ソース・ドレイン領域へのダメージを防ぐことができ、ソース・ドレイン領域のさらなる抵抗低減を図ることができる。
具体的には、第一ゲート絶縁膜４１としてSiH4とN2Oガスを用いたプラズマCVD法にて形成したSiO2膜を、第二ゲート絶縁膜として前述のプラズマCVD法にて形成したSiNx膜を用いることでエッチング選択性を確保でき、該構造が形成可能である。この場合、各層の膜厚は特に限定されないが、第一ゲート絶縁膜に関しては酸化亜鉛膜厚と同等レベルの50〜100nmとすることで、イオン注入の加速電圧の上昇を防ぐことが可能となる。 As shown in FIG. 5 (3), the second gate insulating film 5 is formed so as to cover the first gate insulating film 41. The gate electrode 6 is loaded on the second gate insulating film 5, and the second gate insulating film 5 is dry-etched using a gas such as SF 6 using the gate electrode 6 as a mask. By making the first gate insulating film 41 and the second gate insulating film 5 different compounds, only the second gate insulating film 5 can be etched without etching the first gate insulating film 41. Further, since the first gate insulating film 41 covers the source / drain regions 32, damage to the source / drain regions can be prevented, and the resistance of the source / drain regions can be further reduced.
Specifically, the SiO 2 film formed by the plasma CVD method using SiH 4 and N 2 O gas as the first gate insulating film 41, and the SiNx formed by the plasma CVD method as the second gate insulating film. By using a film, etching selectivity can be secured and the structure can be formed. In this case, the thickness of each layer is not particularly limited, but it is possible to prevent the acceleration voltage for ion implantation from increasing by setting the first gate insulating film to a level equivalent to the zinc oxide thickness of 50 to 100 nm. .

図５（４）は第二ゲート絶縁膜５をドライエッチングした後の断面図を示しており、第二ゲート絶縁膜５とゲート電極６が自己整合的に同一形状に形成されている。   FIG. 5 (4) shows a cross-sectional view after the second gate insulating film 5 is dry-etched. The second gate insulating film 5 and the gate electrode 6 are formed in the same shape in a self-aligning manner.

ゲート絶縁膜４のパターン形成後、図５（５）に示される如く、酸化物半導体薄膜層３の膜厚方向全体において、ゲート電極６をマスクとして、一対のソース・ドレイン領域３２にイオンをドーピングし低抵抗化を行う。低抵抗化は、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の少なくとも1種をイオンの状態でドーピングすることで行う。
このとき、第一ゲート絶縁膜を酸化物半導体薄膜層の膜厚と同等レベルの50〜100nmとすることで、ドーピング時のエネルギーを抑制することができる。これにより、膜中深くまでイオンをドーピングするのが難しいプラズマ処理によるドーピングを用いても、本発明の効果が期待できる。 After the pattern formation of the gate insulating film 4, as shown in FIG. 5 (5), ions are doped into the pair of source / drain regions 32 using the gate electrode 6 as a mask in the entire thickness direction of the oxide semiconductor thin film layer 3. And lower the resistance. Low resistance is achieved by ionizing at least one of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), and oxygen (O). This is done by doping in this state.
At this time, the energy at the time of doping can be suppressed by setting the first gate insulating film to 50 to 100 nm, which is the same level as the thickness of the oxide semiconductor thin film layer. As a result, the effect of the present invention can be expected even by using doping by plasma treatment, which is difficult to dope ions deeply into the film.

その後、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、ゲート電極６上全面に層間絶縁膜７を形成する。そして、フォトリソグラフィーを用いてソース・ドレイン電極２上にコンタクトホールを開口し、一対のソース・ドレイン外部電極２ａをコンタクト部８ａを介して、それぞれに対応するソース・ドレイン電極２に接続する。最後に、インジウムスズ酸化物(ITO)等からなる表示電極９を形成することでTFTアレイが完成する。   Thereafter, an interlayer insulating film 7 is formed on the entire surface of the substrate 1, the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6. Then, contact holes are opened on the source / drain electrodes 2 using photolithography, and the pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 8a. Finally, the display electrode 9 made of indium tin oxide (ITO) or the like is formed to complete the TFT array.

最後に、本発明の第四の実施形態に係るTFT４００の製造方法を説明する（図示せず）。
TFT４００の製造方法は、TFT３００の製造方法において、酸化物半導体薄膜層３をエッチングする際、第一ゲート絶縁膜４１とともに一括して行う。具体的には、基板１及び一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３を形成し、パターニングをせずに、第一ゲート絶縁膜４１を形成する。この時、酸化物半導体薄膜層をスパッタリング法を用いて真空中にて形成し、大気開放することなく連続してプラズマCVD法やスパッタリング法を用いてゲート絶縁膜を形成することが望ましい。これにより、酸化物半導体薄膜層３と第一ゲート絶縁膜４１の間に良好な界面が形成され、維持される。その後、該基板を大気中に取り出し、第一ゲート絶縁膜４１上にフォトレジストをコーティングし、パターニングされたフォトレジストを形成して、このフォトレジストをマスクとして、第一ゲート絶縁膜４１と酸化物半導体薄膜層３を一括してドライエッチングする。 Finally, a manufacturing method of the TFT 400 according to the fourth embodiment of the present invention will be described (not shown).
The manufacturing method of the TFT 400 is performed together with the first gate insulating film 41 when the oxide semiconductor thin film layer 3 is etched in the manufacturing method of the TFT 300. Specifically, the oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, and the first gate insulating film 41 is formed without patterning. At this time, it is desirable to form the oxide semiconductor thin film layer in a vacuum using a sputtering method, and continuously form a gate insulating film using a plasma CVD method or a sputtering method without opening to the atmosphere. Thereby, a favorable interface is formed and maintained between the oxide semiconductor thin film layer 3 and the first gate insulating film 41. Thereafter, the substrate is taken out into the atmosphere, a photoresist is coated on the first gate insulating film 41, a patterned photoresist is formed, and the first gate insulating film 41 and the oxide are formed using the photoresist as a mask. The semiconductor thin film layer 3 is dry etched at once.

これにより、酸化物半導体薄膜層３と同一形状の第一ゲート絶縁膜４１を有するTFT活性層領域が形成される。第一ゲート絶縁膜４１は、酸化物半導体薄膜層３との界面形成に加えて、活性領域をパターン形成する時の酸化物半導体薄膜層を保護する役目も同時に果たしている。すなわち、活性層パターニング後のフォトレジスト４ａを剥離する場合に使用するレジスト剥離液が酸化物半導体薄膜層３表面に接すると、薄膜表面や結晶粒界をエッチングで荒らしてしまうが、第一ゲート絶縁膜４１が酸化物半導体薄膜層３表面に存在することで、フォトリソグラフィー工程におけるレジスト剥離液といった各種薬液に対する保護膜としての機能を果たし、酸化物半導体薄膜層３の表面あれを防ぐことができる。また、ソース・ドレイン領域３２上に、第一ゲート絶縁膜４１が存在することとなり、第二ゲート絶縁膜５をエッチングする等の製造工程においてソース・ドレイン領域を保護することができる。そのため、ソース・ドレイン領域のさらなる抵抗低減を図ることができる。   As a result, a TFT active layer region having the first gate insulating film 41 having the same shape as the oxide semiconductor thin film layer 3 is formed. In addition to forming an interface with the oxide semiconductor thin film layer 3, the first gate insulating film 41 also plays a role of protecting the oxide semiconductor thin film layer when patterning the active region. That is, if the resist stripping solution used for stripping the photoresist 4a after patterning the active layer contacts the surface of the oxide semiconductor thin film layer 3, the surface of the thin film and the crystal grain boundary are roughened by etching, but the first gate insulation The presence of the film 41 on the surface of the oxide semiconductor thin film layer 3 serves as a protective film against various chemicals such as a resist stripping solution in a photolithography process, and the surface roughness of the oxide semiconductor thin film layer 3 can be prevented. Further, the first gate insulating film 41 exists on the source / drain region 32, and the source / drain region can be protected in a manufacturing process such as etching the second gate insulating film 5. Therefore, the resistance of the source / drain regions can be further reduced.

以上説明した如く、本発明に係る酸化亜鉛を半導体薄膜層に用いた薄膜トランジスタは、優れた性能を有するものであり、液晶表示装置等の駆動素子として好適に使用可能なものである。   As described above, the thin film transistor using the zinc oxide according to the present invention for the semiconductor thin film layer has excellent performance and can be suitably used as a driving element for a liquid crystal display device or the like.

本発明における薄膜トランジスタ（TFT）の第一実施形態を示す断面図である。It is sectional drawing which shows 1st embodiment of the thin-film transistor (TFT) in this invention. 本発明における薄膜トランジスタ（TFT）の第一の実施形態の製法を経時的に示す断面図であり、下記（１）から（６）よりなる。（１）基板上にソース・ドレイン電極、酸化物半導体薄膜層を形成し、ゲート絶縁膜を被膜した構造の断面図（２）ゲート電極を積載した断面図（３）ゲート絶縁膜をパターニングした構造の断面図（４）低抵抗化した後の断面図（５）層間絶縁膜を被膜した断面図（６）コンタクト部、ソース・ドレイン外部電極、表示電極を形成した構造の断面図It is sectional drawing which shows the manufacturing method of 1st embodiment of the thin-film transistor (TFT) in this invention over time, and consists of following (1) to (6). (1) Cross-sectional view of a structure in which source / drain electrodes and oxide semiconductor thin film layers are formed on a substrate and a gate insulating film is coated (2) Cross-sectional view of a stacked gate electrode (3) Structure in which a gate insulating film is patterned (4) Cross-sectional view after resistance reduction (5) Cross-sectional view coated with interlayer insulating film (6) Cross-sectional view of structure in which contact portion, source / drain external electrode and display electrode are formed 本発明における薄膜トランジスタ（TFT）の第二の実施形態を示す断面図である。It is sectional drawing which shows 2nd embodiment of the thin-film transistor (TFT) in this invention. 本発明における薄膜トランジスタ（TFT）の第三の実施形態を示す断面図である。It is sectional drawing which shows 3rd embodiment of the thin-film transistor (TFT) in this invention. 本発明における薄膜トランジスタ（TFT）の第三の実施形態の製法を経時的に示す断面図であり、下記（１）から（５）よりなる。（１）基板上にソース・ドレイン電極、酸化物半導体薄膜層を形成した構造の断面図（２）第一ゲート絶縁膜を形成した断面図（３）第二ゲート絶縁膜とゲート電極を積層した断面図（４）第二ゲート絶縁膜をパターニングした後の断面図（５）低抵抗化した後の断面図It is sectional drawing which shows temporally the manufacturing method of 3rd embodiment of the thin-film transistor (TFT) in this invention, and consists of following (1)-(5). (1) Cross-sectional view of a structure in which a source / drain electrode and an oxide semiconductor thin film layer are formed on a substrate (2) A cross-sectional view in which a first gate insulating film is formed (3) A second gate insulating film and a gate electrode are laminated Sectional view (4) Sectional view after patterning the second gate insulating film (5) Sectional view after lowering the resistance 本発明における薄膜トランジスタ（TFT）の第四の実施形態を示す断面図である。It is sectional drawing which shows 4th embodiment of the thin-film transistor (TFT) in this invention. アモルファスシリコンを半導体薄膜層として利用した薄膜トランジスタ(TFT)を示す断面図である。It is sectional drawing which shows the thin-film transistor (TFT) using an amorphous silicon as a semiconductor thin film layer.

符号の説明Explanation of symbols

１ 基板
２ ソース・ドレイン電極
３ 酸化物半導体薄膜層
３１ チャネル領域
３２ ソース・ドレイン領域
４ ゲート絶縁膜
４１ 第一ゲート絶縁膜
５ 第二ゲート絶縁膜
６ ゲート電極
１００、２００、３００、４００ 薄膜トランジスタ




DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Oxide semiconductor thin film layer 31 Channel region 32 Source / drain region 4 Gate insulating film 41 First gate insulating film 5 Second gate insulating film 6 Gate electrode 100, 200, 300, 400 Thin film transistor




Claims (9)

絶縁基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、該酸化物半導体薄膜層の少なくとも一定範囲を被覆するゲート絶縁膜と、該ゲート絶縁膜の上に積載されたゲート電極とを有する薄膜トランジスタにおいて、前記ゲート絶縁膜と前記ゲート電極が自己整合的に同一形状に形成されており、前記酸化物半導体薄膜層であって、該ゲート電極の直下方以外の範囲が、該ゲート電極の直下方の範囲よりも、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高い領域を含むソース・ドレイン領域であることを特徴とする薄膜トランジスタ。 An oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film covering at least a certain range of the oxide semiconductor thin film layer, and stacked on the gate insulating film In the thin film transistor having the gate electrode, the gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, and the oxide semiconductor thin film layer has a range other than immediately below the gate electrode. More than the range immediately below the gate electrode, hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O ) Is a source / drain region including a region having a high concentration of at least one of the element group. 絶縁基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、該酸化物半導体薄膜層上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に積載されたゲート電極とを有する薄膜トランジスタにおいて、前記ゲート絶縁膜が前記酸化物半導体薄膜層の少なくとも上側全面を被覆する第一ゲート絶縁膜と、該第一ゲート絶縁膜の上に形成され、且つ前記ゲート電極と自己整合的に同一形状に形成される第二ゲート絶縁膜からなり、該酸化物半導体薄膜層であって、該ゲート電極の直下方以外の範囲が、該ゲート電極の直下方の範囲よりも、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種の濃度が高い領域を含むソース・ドレイン領域であることを特徴とする薄膜トランジスタ。 An oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film formed on the oxide semiconductor thin film layer, and a gate electrode stacked on the gate insulating film In the thin film transistor, the gate insulating film is formed on the first gate insulating film covering at least the entire upper surface of the oxide semiconductor thin film layer, and is self-aligned with the gate electrode. The oxide semiconductor thin film layer is formed of a second gate insulating film formed in the same shape, and the region other than the region directly below the gate electrode is more hydrogen ( H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) element group high concentration region Source / drain regions containing Thin film transistor, wherein the door. 前記第一ゲート絶縁膜が前記酸化物半導体薄膜層の上側全面のみを被覆することを特徴とする請求項２記載の薄膜トランジスタ。 3. The thin film transistor according to claim 2, wherein the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer. 絶縁基板上にチャネルとして働く酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層を被覆してゲート絶縁膜を形成する工程と、該ゲート絶縁膜の上にゲート電極を積載する行程を有する薄膜トランジスタの製法において、前記ゲート電極をマスクとして前記ゲート絶縁膜をエッチング処理し、該ゲート電極をマスクにして自己整合的に前記酸化物半導体薄膜層の該ゲート電極の直下方以外の領域に、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種をイオンの状態でドーピングすることにより、該ゲート電極の直下方以外の範囲に、該ゲート電極の直下方の範囲よりも該元素群のうち少なくとも1種の濃度が高いソース・ドレイン領域を形成することを特徴とする薄膜トランジスタの製法。 Forming an oxide semiconductor thin film layer containing zinc oxide as a main component serving as a channel on an insulating substrate; forming a gate insulating film by covering the oxide semiconductor thin film layer; and In the method of manufacturing a thin film transistor having a process of loading a gate electrode on the gate electrode, the gate insulating film is etched using the gate electrode as a mask, and the gate electrode of the oxide semiconductor thin film layer is self-aligned using the gate electrode as a mask. In regions other than directly below, elements of hydrogen (H), helium (He), neon (Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) By doping at least one of these in the state of ions, a source having a concentration of at least one of the element groups higher than the range directly below the gate electrode in a range other than directly below the gate electrode. Dray Forming a thin film transistor region. 絶縁基板上にチャネルとして働く酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層の少なくとも上側全面を被覆して第一ゲート絶縁膜を形成する工程と、該第一ゲート絶縁膜の上に第二ゲート絶縁膜を形成する工程と、該第二ゲート絶縁膜の上にゲート電極を積載する行程を含む薄膜トランジスタの製法において、前記ゲート電極をマスクとして前記第二ゲート絶縁膜をエッチング処理し、該ゲート電極をマスクにして自己整合的に前記酸化物半導体薄膜層の該ゲート電極の直下方以外の領域に、水素(H)、ヘリウム(He)、ネオン(Ne)、アルゴン(Ar)、クリプトン(Kr)、フッ素(F)、キセノン(Xe)、酸素(O)の元素群のうち少なくとも1種をイオンの状態でドーピングすることにより、該ゲート電極の直下方以外の範囲に、該ゲート電極の直下方の範囲よりも該元素群のうち少なくとも1種の濃度が高いソース・ドレイン領域を形成することを特徴とする薄膜トランジスタの製法。 Forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on an insulating substrate; forming a first gate insulating film by covering at least the entire upper surface of the oxide semiconductor thin film layer; In the method of manufacturing a thin film transistor including a step of forming a second gate insulating film on the first gate insulating film and a step of mounting a gate electrode on the second gate insulating film, the first electrode is used as a mask. Etching the two-gate insulating film, and using the gate electrode as a mask in a region other than immediately below the gate electrode of the oxide semiconductor thin film layer in a self-aligned manner, hydrogen (H), helium (He), neon ( Ne), argon (Ar), krypton (Kr), fluorine (F), xenon (Xe), oxygen (O) at least one element group is doped in an ion state, thereby directly below the gate electrode. Range other than , Preparation of thin film transistors, wherein at least one concentration of said original pixel group than the range of just below of the gate electrode to form a high source-drain region. 前記酸化物半導体薄膜層と前記第一ゲート絶縁膜を一括してエッチングすることを特徴とする請求項５記載の薄膜トランジスタ。 6. The thin film transistor according to claim 5, wherein the oxide semiconductor thin film layer and the first gate insulating film are etched together. 前記ソース・ドレイン領域の形成のためのイオンのドーピングを、イオンを加速して行うことを特徴とする請求項４乃至６いずれか記載の薄膜トランジスタの製法。 7. The method of manufacturing a thin film transistor according to claim 4, wherein the doping of ions for forming the source / drain regions is performed by accelerating the ions. 前記ソース・ドレイン領域の形成において、前記元素群のうち少なくとも1種のガスをプラズマ分解し、該プラズマ雰囲気に、前記酸化物半導体薄膜層における前記ゲート電極の直下方以外の範囲を暴露することを特徴とする請求項４乃至６いずれか記載の薄膜トランジスタの製法。 In the formation of the source / drain regions, plasma decomposition of at least one gas of the element group is performed, and the plasma atmosphere is exposed to a range other than immediately below the gate electrode in the oxide semiconductor thin film layer. The method for producing a thin film transistor according to any one of claims 4 to 6. 前記ソース・ドレイン領域の形成の工程において、前記絶縁基板にバイアス電力を印加することを特徴とする請求項８記載の薄膜トランジスタの製法。
9. The method of manufacturing a thin film transistor according to claim 8, wherein bias power is applied to the insulating substrate in the step of forming the source / drain regions.
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