JP2007214286A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2007214286A JP2007214286A JP2006031538A JP2006031538A JP2007214286A JP 2007214286 A JP2007214286 A JP 2007214286A JP 2006031538 A JP2006031538 A JP 2006031538A JP 2006031538 A JP2006031538 A JP 2006031538A JP 2007214286 A JP2007214286 A JP 2007214286A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- silicide layer
- etching
- insulating film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 137
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 89
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 89
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 64
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 168
- 239000012535 impurity Substances 0.000 claims description 56
- 238000009792 diffusion process Methods 0.000 claims description 53
- 125000006850 spacer group Chemical group 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 40
- 239000007789 gas Substances 0.000 description 27
- 238000001312 dry etching Methods 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 238000004380 ashing Methods 0.000 description 5
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910005881 NiSi 2 Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65B—MACHINES, APPARATUS OR DEVICES FOR, OR METHODS OF, PACKAGING ARTICLES OR MATERIALS; UNPACKING
- B65B31/00—Packaging articles or materials under special atmospheric or gaseous conditions; Adding propellants to aerosol containers
- B65B31/04—Evacuating, pressurising or gasifying filled containers or wrappers by means of nozzles through which air or other gas, e.g. an inert gas, is withdrawn or supplied
- B65B31/06—Evacuating, pressurising or gasifying filled containers or wrappers by means of nozzles through which air or other gas, e.g. an inert gas, is withdrawn or supplied the nozzle being arranged for insertion into, and withdrawal from, the mouth of a filled container and operating in conjunction with means for sealing the container mouth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05B—SPRAYING APPARATUS; ATOMISING APPARATUS; NOZZLES
- B05B1/00—Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means
- B05B1/02—Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means designed to produce a jet, spray, or other discharge of particular shape or nature, e.g. in single drops, or having an outlet of particular shape
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65B—MACHINES, APPARATUS OR DEVICES FOR, OR METHODS OF, PACKAGING ARTICLES OR MATERIALS; UNPACKING
- B65B65/00—Details peculiar to packaging machines and not otherwise provided for; Arrangements of such details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Engineering (AREA)
- Dispersion Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】ニッケルシリサイド層7が十分な膜厚を有する領域にコンタクトホール11を形成するとともに、金属シリサイド層7のエッチングを行い金属シリサイド層7に凹部を形成する。次いで、コンタクトホール11を所望のコンタクト径まで拡大する。これにより、コンタクトホールの底部を占めるシリサイド面積率を下げることなく、所望のコンタクトホール11のボトム面積を確保することができ、コンタクト抵抗上昇に起因する製造歩留まり低下を抑制することができる。
【選択図】図3
Description
図1〜図4は、本発明の第1の実施形態における半導体装置の製造過程を示す工程断面図である。
上記第1の実施形態では、まず、ニッケルシリサイド層7が十分な厚みを有する領域にコンタクトホール及び金属シリサイド層の凹部を形成し、その後にコンタクトホール径を拡大する手法を説明した。しかしながら、第1の実施形態のコンタクトと同様の構造は、他の手法によっても形成可能である。図5〜図7は、本発明の第2の実施形態における半導体装置の製造過程を示す工程断面図である。
上記各実施形態では、金属シリサイド層に一段の凹部を形成したが、当該凹部は、多段で構成されていてもよい。図8及び図9は、本発明の第3の実施形態における半導体装置の製造過程を示す工程断面図である。
上記各実施形態では、絶縁膜9に形成したコンタクトホール自体をマスクとしたエッチングにより金属シリサイド層に凹部を形成した。本実施形態では、コンタクトホールに代えて、マスクパターンを半導体基板上に形成することで、金属シリサイド層の凹部を形成する手法について説明する。図10〜図12は、本発明の第4の実施形態における半導体装置の製造過程を示す工程断面図である。
さて、上記各実施形態では、平坦な半導体基板1上にコンタクトを形成した。しかしながら、上記各実施形態のようなコンタクト構造では、コンタクトプラグと金属シリサイド層との接触面を曲面とした方が接触面積をより大きくすることができる。そこで、本実施形態では、コンタクト形成部位の半導体基板表面に凹曲面を形成している。図13〜図15は、本発明における第5の実施形態における半導体装置の製造過程を示す工程断面図である。
第5の実施形態では、シリサイド化を行う前に、半導体基板表面に凹曲面を形成したが、シリサイド化を行った後であっても、凹曲面を形成することは可能である。図16は、本発明の第6の実施形態における半導体装置の製造過程を示す工程断面図である。
2 ゲート絶縁膜
3 ゲート電極
4 低濃度不純物拡散領域
5 サイドウォールスペーサ
6 高濃度不純物拡散領域
7 ニッケルシリサイド層
8 ストッパ膜
9 絶縁膜
10、20、30、40、50、60 フォトレジスト
11、21、31、41、51、61 コンタクトホール
12、22、32、42、52、62 凹部
15 導電体(コンタクトプラグ)
24 スペーサ
44 第2のサイドウォール
53 凹曲面
Claims (23)
- 半導体層の表面部に形成された不純物拡散領域と、前記不純物拡散領域の表面に形成された金属シリサイド層と、前記金属シリサイド層上に形成された層間絶縁膜を貫通して前記金属シリサイド層に電気的に接続するコンタクトプラグとを備えた半導体装置において、
コンタクトプラグとの接触面に凹部を有する金属シリサイド層と、
前記金属シリサイド層との接触面の一部に、前記凹部に嵌合する突部を有するコンタクトプラグと、
を備えたことを特徴とする半導体装置。 - 前記凹部が多段構造を有する請求項1記載の半導体装置。
- 前記金属シリサイド層のコンタクトプラグとの接触面が凹曲面である請求項1記載の半導体装置。
- 前記半導体層の主成分がシリコンである請求項1記載の半導体装置。
- 前記層間絶縁膜が、第1の絶縁膜上に第2の絶縁膜が形成された多層構造を有し、前記第1の絶縁膜は、前記第2の絶縁膜に貫通孔を形成する際にエッチングストッパとして機能する請求項4記載の半導体装置。
- 前記第2の絶縁膜が、シリコン酸化膜、ボロン・リンドープシリコン酸化膜、またはリンドープシリコン酸化膜である請求項5記載の半導体装置。
- 前記第1の絶縁膜が、シリコン窒化膜、または炭化シリコン膜である請求項5記載の半導体装置。
- 前記金属シリサイド層がニッケルシリサイドである請求項4記載の半導体装置。
- 金属シリサイド層を介して半導体層表面部の不純物拡散領域に電気的に接続されるコンタクトプラグを備えた半導体装置の製造方法において、
半導体層の表面部に不純物拡散領域を形成する工程と、
前記不純物拡散領域の表面部に金属シリサイド層を形成する工程と、
前記金属シリサイド層が形成された半導体層上に層間絶縁膜を形成する工程と、
前記層間絶縁膜上に、コンタクトプラグ形成位置に開口を有するマスクパターンを形成する工程と、
前記マスクパターンを介したエッチングにより、前記層間絶縁膜に貫通孔を形成する工程と、
前記貫通孔を介したエッチングにより、前記金属シリサイド層に凹部を形成する工程と、
前記貫通孔の径を拡大する工程と、
前記径が拡大された貫通孔に導電体を充填しコンタクトプラグを形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記貫通孔を形成するエッチングの際に前記凹部が形成される請求項9記載の半導体装置の製造方法。
- 前記貫通孔の形成後に、当該貫通孔の内壁にスペーサを形成する工程をさらに有し、
前記スペーサが形成された貫通孔を介したエッチングにより前記凹部が形成されるとともに、当該凹部形成後に前記スペーサを除去することにより前記貫通孔径が拡大される請求項9記載の半導体装置の製造方法。 - 前記凹部の形成と前記貫通孔径の拡大とが交互に繰り返して行われ、前記金属シリサイド層に多段構造が形成される請求項9記載の半導体装置の製造方法。
- 前記金属シリサイド層の形成後に、前記貫通孔底部の径を規制するパターンを形成する工程をさらに有し、
前記規制パターンを介したエッチングにより前記凹部が形成されるとともに、当該凹部形成後に前記規制パターンを除去することにより前記貫通孔径が拡大される請求項9記載の半導体装置の製造方法。 - 前記規制パターンが、前記貫通孔に隣接するゲート電極に形成されたサイドウォールである請求項13記載の半導体装置の製造方法。
- 前記金属シリサイド層形成前に、前記半導体層の等方性エッチングを行うことにより、当該半導体層表面の前記コンタクトプラグの接触面を含む領域に凹曲面を形成する工程をさらに有する請求項9記載の半導体装置の製造方法。
- 前記等方性エッチングが、前記貫通孔に隣接するゲート電極に形成されたサイドウォールをマスクとして行われる請求項15記載の半導体装置の製造方法。
- 前記貫通孔径の拡大後に、当該拡大された貫通孔を介した等方性エッチングにより前記金属シリサイド層の一部を除去する工程をさらに有する請求項9記載の半導体装置の製造方法。
- 前記等方性エッチングがウェットエッチングである請求項15または17記載の半導体装置の製造方法。
- 前記半導体層の主成分がシリコンである請求項9記載の半導体装置の製造方法。
- 前記層間絶縁膜が、第1の絶縁膜上に第2の絶縁膜が形成された多層構造を有し、前記第1の絶縁膜は、前記第2の絶縁膜に貫通孔を形成するエッチングの際にエッチングストッパとして機能する請求項19記載の半導体装置の製造方法。
- 前記第2の絶縁膜が、シリコン酸化膜、ボロン・リンドープシリコン酸化膜、または、リンドープシリコン酸化膜である請求項20記載の半導体装置の製造方法。
- 前記第1の絶縁膜が、シリコン窒化膜、または炭化シリコン膜である請求項20記載の半導体装置の製造方法。
- 前記金属シリサイド層は、ニッケルシリサイドである請求項19記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006031538A JP4717653B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体装置及び半導体装置の製造方法 |
KR1020070008262A KR20070080819A (ko) | 2006-02-08 | 2007-01-26 | 반도체장치 및 반도체장치의 제조방법 |
US11/703,671 US20070181954A1 (en) | 2006-02-08 | 2007-02-08 | Semiconductor device and method of manufacture thereof |
CNA2007100070818A CN101017807A (zh) | 2006-02-08 | 2007-02-08 | 半导体装置和半导体装置的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006031538A JP4717653B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007214286A true JP2007214286A (ja) | 2007-08-23 |
JP4717653B2 JP4717653B2 (ja) | 2011-07-06 |
Family
ID=38333182
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006031538A Expired - Fee Related JP4717653B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体装置及び半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070181954A1 (ja) |
JP (1) | JP4717653B2 (ja) |
KR (1) | KR20070080819A (ja) |
CN (1) | CN101017807A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009278053A (ja) * | 2008-05-19 | 2009-11-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR20220118284A (ko) * | 2021-02-18 | 2022-08-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 트랜지스터 소스/드레인 접촉부 및 그 형성 방법 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101376260B1 (ko) * | 2008-04-14 | 2014-03-20 | 삼성전자 주식회사 | 반도체 소자 및 그 제조 방법 |
DE102010031197A1 (de) * | 2010-07-09 | 2012-01-12 | Robert Bosch Gmbh | Piezoresistiver Drucksensor |
JP5696543B2 (ja) * | 2011-03-17 | 2015-04-08 | セイコーエプソン株式会社 | 半導体基板の製造方法 |
US8569127B2 (en) * | 2012-03-13 | 2013-10-29 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US9236345B2 (en) | 2014-03-24 | 2016-01-12 | Globalfoundries Inc. | Oxide mediated epitaxial nickel disilicide alloy contact formation |
US20170194454A1 (en) * | 2016-01-06 | 2017-07-06 | International Business Machines Corporation | NiPt AND Ti INTERSECTING SILICIDE PROCESS AND STRUCTURE |
KR102600998B1 (ko) | 2016-09-28 | 2023-11-13 | 삼성전자주식회사 | 반도체 장치 |
EP3920212A1 (en) | 2016-12-30 | 2021-12-08 | INTEL Corporation | Contact architecture for capacitance reduction and satisfactory contact resistance |
US10199260B1 (en) * | 2017-10-05 | 2019-02-05 | United Microelectronics Corp. | Contact hole structure and method of fabricating the same |
US11380781B2 (en) * | 2019-12-17 | 2022-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact and via structures for semiconductor devices |
US11637018B2 (en) * | 2020-10-27 | 2023-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for contact structures of semiconductor devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228956A (ja) * | 1988-07-19 | 1990-01-31 | Sony Corp | 半導体集積回路装置 |
JPH11297987A (ja) * | 1998-04-10 | 1999-10-29 | Sony Corp | 半導体装置およびその製造方法 |
JP2000236090A (ja) * | 1999-02-15 | 2000-08-29 | Sony Corp | 半導体装置の製造方法 |
JP2001196327A (ja) * | 2000-01-06 | 2001-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789317A (en) * | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
US6121134A (en) * | 1998-04-21 | 2000-09-19 | Micron Technology, Inc. | High aspect ratio metallization structures and processes for fabricating the same |
KR100339683B1 (ko) * | 2000-02-03 | 2002-06-05 | 윤종용 | 반도체 집적회로의 자기정렬 콘택 구조체 형성방법 |
KR100400031B1 (ko) * | 2001-01-17 | 2003-09-29 | 삼성전자주식회사 | 반도체 소자의 콘택 플러그 및 그 형성 방법 |
US7098536B2 (en) * | 2004-10-21 | 2006-08-29 | International Business Machines Corporation | Structure for strained channel field effect transistor pair having a member and a contact via |
-
2006
- 2006-02-08 JP JP2006031538A patent/JP4717653B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-26 KR KR1020070008262A patent/KR20070080819A/ko not_active Application Discontinuation
- 2007-02-08 CN CNA2007100070818A patent/CN101017807A/zh active Pending
- 2007-02-08 US US11/703,671 patent/US20070181954A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228956A (ja) * | 1988-07-19 | 1990-01-31 | Sony Corp | 半導体集積回路装置 |
JPH11297987A (ja) * | 1998-04-10 | 1999-10-29 | Sony Corp | 半導体装置およびその製造方法 |
JP2000236090A (ja) * | 1999-02-15 | 2000-08-29 | Sony Corp | 半導体装置の製造方法 |
JP2001196327A (ja) * | 2000-01-06 | 2001-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009278053A (ja) * | 2008-05-19 | 2009-11-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR20220118284A (ko) * | 2021-02-18 | 2022-08-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 트랜지스터 소스/드레인 접촉부 및 그 형성 방법 |
KR102618415B1 (ko) | 2021-02-18 | 2023-12-27 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 트랜지스터 소스/드레인 접촉부 및 그 형성 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20070080819A (ko) | 2007-08-13 |
CN101017807A (zh) | 2007-08-15 |
US20070181954A1 (en) | 2007-08-09 |
JP4717653B2 (ja) | 2011-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4717653B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
US6406963B2 (en) | Method of manufacturing a semiconductor device | |
KR20120036185A (ko) | 반도체 소자 및 그 제조 방법 | |
JP2001250791A (ja) | 半導体装置およびその製造方法 | |
TWI807104B (zh) | 半導體裝置及其製造方法 | |
JP2007043177A (ja) | 半導体素子の製造方法 | |
JP2006196821A (ja) | 半導体装置とその製造方法 | |
TW201926556A (zh) | 半導體製作方法 | |
TWI708390B (zh) | 半導體結構及其形成方法 | |
JP2005116633A (ja) | 半導体装置及びその製造方法 | |
JP5277628B2 (ja) | 半導体装置の製造方法 | |
JP2011176372A (ja) | 半導体装置およびその製造方法 | |
JP2006073846A (ja) | 絶縁ゲート型電界効果トランジスタの製法 | |
JP2007150249A (ja) | 半導体装置およびその製造方法 | |
JP2007081347A (ja) | 半導体装置の製造方法 | |
JP4221429B2 (ja) | 半導体装置の製造方法 | |
JP2001077189A (ja) | 半導体装置の製造方法 | |
JP2009212364A (ja) | 半導体装置およびその製造方法 | |
JP2007012823A (ja) | 半導体装置及びその製造方法 | |
JP2003077859A (ja) | 半導体装置及びその製造方法 | |
JP2008103385A (ja) | 半導体装置の製造方法 | |
US6191019B1 (en) | Method for forming a polysilicon layer in a polycide process flow | |
KR100467642B1 (ko) | 반도체 소자 제조방법 | |
KR100652361B1 (ko) | 자기정렬 방식에 의한 반도체 소자의 제조방법 | |
JP2006080321A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080912 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110118 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110304 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110323 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110330 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140408 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |