JP2007206515A - Light emitting diode driving circuit and display device using the same - Google Patents

Light emitting diode driving circuit and display device using the same Download PDF

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JP2007206515A
JP2007206515A JP2006027050A JP2006027050A JP2007206515A JP 2007206515 A JP2007206515 A JP 2007206515A JP 2006027050 A JP2006027050 A JP 2006027050A JP 2006027050 A JP2006027050 A JP 2006027050A JP 2007206515 A JP2007206515 A JP 2007206515A
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field effect
effect transistor
emitting diode
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Yasuichiro Kurita
泰市郎 栗田
Toshihiro Yamamoto
敏裕 山本
Yoshiki Nakajima
宜樹 中嶋
Yoji Inoue
陽司 井上
Shizuo Tokito
静士 時任
Yoshihide Fujisaki
好英 藤崎
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Japan Broadcasting Corp
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Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting diode driving circuit allowing an n-type field effect transistor to be used as a driving transistor. <P>SOLUTION: The light emitting diode driving circuit includes an organic light emitting diode (LED) 11, an n-type field effect transistor (FET) 12 having a drain connected to a first DC voltage source, a first SW 13 having one terminal connected to an anode of the LED 11 and having the other terminal connected to a source of the FET 12, a second SW 14 having one terminal connected to a gate of the FET 12 and having the other terminal connected to a data voltage source, a third SW 15 having one terminal connected to a source of the FET 12 and having the other terminal connected to a second DC voltage source, a fourth SW 16 having one terminal connected to the anode of the LED 11 and having the other terminal connected to a third DC voltage source, and a holding capacitor 17 having one terminal connected to a gate of the FET 12 and having the other terminal connected to the source of the FET 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、発光ダイオード駆動回路およびそれを用いたディスプレイ装置に係り、特に、駆動トランジスタとしてｎ型電界効果トランジスタを使用することのできる発光ダイオード駆動回路およびそれを用いたディスプレイ装置に関する。   The present invention relates to a light emitting diode driving circuit and a display device using the same, and more particularly to a light emitting diode driving circuit capable of using an n-type field effect transistor as a driving transistor and a display device using the same.

近年、有機発光ダイオード（ＯＬＥＤ）をはじめとする素子を流れる電流に応じた輝度で発光する発光ダイオードの駆動回路およびそれを用いたディスプレイ装置が種々提案されている。   2. Description of the Related Art In recent years, various driving circuits for light emitting diodes that emit light with a luminance corresponding to current flowing through an element such as an organic light emitting diode (OLED) and display devices using the same have been proposed.

発光ダイオードにより高輝度かつ高コントラストな表示を実現するとともに発光ダイオードの長寿命化を図るためには、ＴＦＴ（Thin Film Transistor）によるアクティブ駆動とすることが必要である。   In order to realize a display with high brightness and high contrast by the light emitting diode and to extend the life of the light emitting diode, it is necessary to perform active driving by a TFT (Thin Film Transistor).

発光ダイオードは上記のように電流駆動素子であるので、表示輝度に応じた電荷をいったんコンデンサに蓄積し、ＴＦＴである電界効果トランジスタによりコンデンサに蓄積された電荷に比例した電流を供給する駆動回路が基本駆動回路として使用されている。   Since the light emitting diode is a current driving element as described above, a driving circuit that temporarily accumulates charges according to display luminance in a capacitor and supplies a current proportional to the charges accumulated in the capacitor by a field effect transistor that is a TFT. Used as a basic drive circuit.

そして、電界効果トランジスタのばらつきの影響を軽減しつつコンデンサに電荷を供給する方法としては、電流原から電荷を供給する電流プログラム型（例えば、非特許文献１参照）が知られており、２つの電流源から供給される電流の差でコンデンサに電荷を蓄積することにより低輝度の場合の誤差を低減可能な駆動回路も提案されている（例えば、特許文献１参照）。   As a method of supplying charges to a capacitor while reducing the influence of variations in field effect transistors, a current program type (see, for example, Non-Patent Document 1) that supplies charges from a current source is known. There has also been proposed a drive circuit capable of reducing an error in the case of low luminance by accumulating electric charge in a capacitor by a difference in current supplied from a current source (see, for example, Patent Document 1).

しかし、電流プログラム型駆動回路は、低輝度状態において輝度は駆動回路の浮遊容量の影響を受け易いだけでなく、表示輝度が印加電圧に比例する液晶用の外部駆動素子を流用できず専用の外部駆動素子を開発しなければならないという課題があった。   However, the current-programmed drive circuit is not only susceptible to the stray capacitance of the drive circuit in the low-brightness state, but also cannot use a liquid crystal external drive element whose display brightness is proportional to the applied voltage. There was a problem that a drive element had to be developed.

そこで、電界効果トランジスタのばらつきの影響を軽減しつつ、低輝度状態においても輝度は駆動回路の浮遊容量に影響されず、液晶用の駆動素子を流用できる電圧プログラム型駆動回路も既に提案されている（非特許文献２）。   Thus, a voltage-programmed driving circuit has been already proposed in which the luminance is not affected by the stray capacitance of the driving circuit even in a low luminance state while reducing the influence of variations in field effect transistors, and the driving element for liquid crystal can be used. (Non-patent document 2).

さらに、寄生容量で消費される電力を低減して発光効率を向上するとともに所定期間発光ダイオードに逆バイアスを印加して発光ダイオードの長寿命化を達成できる電圧プログラミング型駆動回路も提案されている（例えば、特許文献２および特許文献３参照）。   Furthermore, a voltage programming type drive circuit has been proposed that can improve the light emission efficiency by reducing the power consumed by the parasitic capacitance and at the same time apply a reverse bias to the light emitting diode for a predetermined period to achieve a long life of the light emitting diode ( For example, see Patent Document 2 and Patent Document 3).

図９は、特許文献３に開示されている有機発光ダイオード駆動回路の回路図およびタイミング図であって、流れる電流に比例した輝度で発光しカソード端子が基準電位に接続される有機発光ダイオード９１と、ソース端子が第１の電位の直流電圧源に接続されるｐ型電界効果トランジスタ９２と、ソース（または、ドレン）端子が有機発光ダイオード９１のアノード端子にドレン（または、ソース）端子がｐ型電界効果トランジスタ９２のドレン端子に接続され発光期間に閉状態となる第１の電界効果トランジスタ９３と、一方の端子がｐ型電界効果トランジスタ９２のゲート端子に接続される入力コンデンサ９４と、ソース（または、ドレン）端子が入力コンデンサ９４の他方の端子にドレン（または、ソース）端子がデータ信号に接続され発光期間前のデータ書き込み期間に閉状態となる第２の電界効果トランジスタ９５と、一方の端子がｐ型電界効果トランジスタ９２のソースに他方の端子がｐ型電界効果トランジスタ９２のゲートに接続される保持コンデンサ９６と、ソース（または、ドレン）端子がｐ型電界効果トランジスタ９２のゲート端子にドレン（または、ソース）端子がｐ型電界効果トランジスタ９２のドレンに接続され閾値書き込み期間に閉状態となる第３の電界効果トランジスタ９７と、ソース（または、ドレン）端子が有機発光ダイオード９１のアノード端子にドレン（または、ソース）端子が逆バイアス電位の逆バイアス電圧源に接続され発光期間後の逆バイアス期間に閉状態となる第４の電界効果トランジスタ９８とを含む。   FIG. 9 is a circuit diagram and timing diagram of the organic light emitting diode driving circuit disclosed in Patent Document 3, and emits light with a luminance proportional to the flowing current, and the organic light emitting diode 91 whose cathode terminal is connected to a reference potential. , A p-type field effect transistor 92 whose source terminal is connected to a DC voltage source having a first potential, a source (or drain) terminal is an anode terminal of the organic light emitting diode 91, and a drain (or source) terminal is p-type. A first field effect transistor 93 connected to the drain terminal of the field effect transistor 92 and being closed during the light emission period, an input capacitor 94 having one terminal connected to the gate terminal of the p-type field effect transistor 92, and a source ( Alternatively, the drain terminal is connected to the other terminal of the input capacitor 94 and the drain (or source) terminal is connected to the data signal. The second field effect transistor 95 that is closed in the data writing period before the light emission period, one terminal is connected to the source of the p-type field effect transistor 92, and the other terminal is connected to the gate of the p-type field effect transistor 92. The holding capacitor 96, the source (or drain) terminal is connected to the gate terminal of the p-type field effect transistor 92, and the drain (or source) terminal is connected to the drain of the p-type field effect transistor 92, and is closed during the threshold writing period. The third field effect transistor 97, the source (or drain) terminal is connected to the anode terminal of the organic light emitting diode 91, and the drain (or source) terminal is connected to the reverse bias voltage source having the reverse bias potential. And a fourth field effect transistor 98 which is closed during the period.

即ち、１フレーム期間毎に出力される逆バイアスパルスにより、有機発光ダイオード９１に逆バイアスされ、有機発光ダイオード９１の発光輝度の劣化が防止される。   That is, reverse bias is output to the organic light emitting diode 91 by a reverse bias pulse output every frame period, and deterioration of the light emission luminance of the organic light emitting diode 91 is prevented.

逆バイアスパルスがオフとなると、発光パルスがオンとなってｐ型電界効果トランジスタ９２および第１の電界効果トランジスタ９３がオンとなり、保持コンデンサ９６に蓄積された電荷に応じた電流が有機発光ダイオード９１に流れ、有機発光ダイオード９１は発光する。   When the reverse bias pulse is turned off, the light emission pulse is turned on, the p-type field effect transistor 92 and the first field effect transistor 93 are turned on, and a current corresponding to the charge accumulated in the holding capacitor 96 is supplied to the organic light emitting diode 91. The organic light emitting diode 91 emits light.

発光パルスがオンである期間に選択パルスがオンとなると第２の電界効果トランジスタ９５がオンとなる。その後、閾値書き込みパルスがオンとなり、発光パルスがオンからオフに遷移すると保持コンデンサ９６にはｐ型電界効果トランジスタ９２の閾値電圧が保持される。さらに、その後、選択パルスがオンである期間内の適切なタイミングでデータ信号が閾値電圧に重畳され、選択パルスがオフとなった後もデータ信号と閾値電圧との重畳電圧が保持される。   When the selection pulse is turned on while the light emission pulse is on, the second field effect transistor 95 is turned on. Thereafter, when the threshold write pulse is turned on and the light emission pulse transitions from on to off, the holding capacitor 96 holds the threshold voltage of the p-type field effect transistor 92. Further, after that, the data signal is superimposed on the threshold voltage at an appropriate timing within the period in which the selection pulse is on, and the superimposed voltage between the data signal and the threshold voltage is held even after the selection pulse is turned off.

上記の駆動回路において、第１の電界効果トランジスタ９３から第４の電界効果トランジスタ９８もｐ型電界効果トランジスタであるとしているが、パルスの極性を反転すればｎ型電界効果トランジスタを適用することが可能である。   In the above driving circuit, the first field effect transistor 93 to the fourth field effect transistor 98 are also p-type field effect transistors. However, if the polarity of the pulse is reversed, an n-type field effect transistor can be applied. Is possible.

なお、特許文献３では駆動対象を有機発光ダイオードとしているが、シリコン等の無機発光ダイオードにも適用可能である。
特開２００４−３５４８８３公報（［００２０］、図３） 特開２００４−２７９５４８公報（［００１４］、図３） 特開２００４−３６１７３７公報（［００２０］、図３） Dawson, et al. “The Impact of the Transient Response of Organic Light Emitting Diodes on the Design of Active Matrix OLED Displays” IEDM 98, 32.6, pp875-878 (1998) Dawson, et al. “Design of an Improved Pixel for a Polysilicon Active-Matrix Organic LED Display” SID ’98 DIGEST, 4.2, pp.11-14 (1998) In Patent Document 3, the driving target is an organic light emitting diode, but it can also be applied to an inorganic light emitting diode such as silicon.
Japanese Patent Laying-Open No. 2004-354883 ([0020], FIG. 3) JP 2004-279548 A ([0014], FIG. 3) JP 2004-361737 A ([0020], FIG. 3) Dawson, et al. “The Impact of the Transient Response of Organic Light Emitting Diodes on the Design of Active Matrix OLED Displays” IEDM 98, 32.6, pp875-878 (1998) Dawson, et al. “Design of an Improved Pixel for a Polysilicon Active-Matrix Organic LED Display” SID '98 DIGEST, 4.2, pp.11-14 (1998)

しかしながら、基本駆動回路および電圧プログラム型駆動回路においては、ｐ型電界効果トランジスタ９２をｎ型電界効果トランジスタに置換することは、パルス極性の反転だけでは不可能である。   However, in the basic drive circuit and the voltage-programmed drive circuit, it is impossible to replace the p-type field effect transistor 92 with the n-type field effect transistor only by reversing the pulse polarity.

即ち、ｐ型電界効果トランジスタではソースを直流電圧源に接続できるので、ゲート電圧をデータ電圧にするだけで、ゲート・ソース間に接続される保持コンデンサにデータ電圧を書き込むことができる。これに対し、ｎ型電界効果トランジスタではソースを直接電圧源に接続できないため、ゲート電圧をデータ電圧にしても、保持コンデンサにデータ電圧を書き込むことはできないため、電界効果トランジスタとしては動作特性が悪いｐ型を使用せざるを得ないという課題がある。   That is, since the source can be connected to the DC voltage source in the p-type field effect transistor, the data voltage can be written in the holding capacitor connected between the gate and the source only by changing the gate voltage to the data voltage. On the other hand, since the source cannot be directly connected to the voltage source in the n-type field effect transistor, even if the gate voltage is set to the data voltage, the data voltage cannot be written to the holding capacitor. There is a problem that the p-type must be used.

本発明は、従来の課題を解決するためになされたものであって、駆動トランジスタとして、動作特性が良好なｎ型電界効果トランジスタを使用することのできる電圧プログラム型の発光ダイオード駆動回路およびそれを用いたディスプレイ装置を提供することを目的とする。   The present invention has been made in order to solve the conventional problems, and a voltage-programmed light-emitting diode driving circuit capable of using an n-type field effect transistor having good operating characteristics as a driving transistor, and the same An object of the present invention is to provide a display device used.

本発明に係る発光ダイオード駆動回路は、流れる電流に応じた輝度で発光しカソード端子が基準電位に接続される発光ダイオードと、ドレン端子が第１の電位の第１の直流電圧源に接続されるｎ型電界効果トランジスタと、一方の端子が前記発光ダイオードのアノード端子に他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続され発光期間に閉状態となる第１のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのゲート端子に他方の端子がデータ電位のデータ電圧源に接続され前記発光期間前の選択期間に閉状態となる第２のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのソース端子に他方の端子が第２の電位の第２の直流電圧源に接続され前記選択期間に閉状態となる第３のスイッチング素子と、一方の端子が前記発光ダイオードのアノード端子に他方の端子が第３の電位の第３の直流電圧源に接続され前記発光期間後の逆バイアス期間に閉状態となる第４のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのゲート端子に他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続される保持コンデンサとを含む構成を有している。   The light emitting diode driving circuit according to the present invention emits light with a luminance corresponding to a flowing current and has a cathode terminal connected to a reference potential and a drain terminal connected to a first DC voltage source having a first potential. an n-type field effect transistor, a first switching element that has one terminal connected to the anode terminal of the light-emitting diode and the other terminal connected to the source terminal of the n-type field-effect transistor; A second switching element whose terminal is connected to the gate terminal of the n-type field effect transistor and whose other terminal is connected to the data voltage source of the data potential and is closed in the selection period before the light emission period; The third switched-on field-effect transistor is connected to the second DC voltage source of the second potential and the other terminal is connected to the second DC voltage source of the second potential and is closed during the selection period. And a fourth switching element having one terminal connected to the anode terminal of the light emitting diode and the other terminal connected to a third DC voltage source having a third potential, and being closed during a reverse bias period after the light emitting period. And a holding capacitor having one terminal connected to the gate terminal of the n-type field effect transistor and the other terminal connected to the source terminal of the n-type field effect transistor.

この構成により、逆バイアス効果を利用する発光ダイオード駆動回路の駆動トランジスタとしてｎ型電界効果トランジスタを使用することができることとなる。   With this configuration, an n-type field effect transistor can be used as a drive transistor of a light emitting diode drive circuit that uses the reverse bias effect.

本発明に係る発光ダイオード駆動回路は、流れる電流に応じた輝度で発光しカソード端子が基準電位に接続される発光ダイオードと、ドレン端子が第１の電位の第１の直流電圧源に接続されるｎ型電界効果トランジスタと、一方の端子が前記発光ダイオードのアノード端子に他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続され発光期間に閉状態となる第１のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのゲート端子に接続される入力コンデンサと、一方の端子が前記入力コンデンサの他方の端子に他方の端子がデータ電圧を供給するデータ電圧源に接続され前記発光期間終了前に始まり前記発光期間終了後に終了する選択期間に閉状態となる第２のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのゲート端子に他方の端子が前記第１の直流電圧源に接続され前記発光期間終了前に始まり、前記選択期間内かつ前記発光期間終了後に終了する閾値書き込み期間に閉状態となる第３のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのソース端子に他方の端子が第２の電位の第２の直流電圧源に接続され前記閾値書き込み期間終了後に始まり前記選択期間終了前または終了と同時に終了するデータ書き込み期間に閉状態となる第４のスイッチング素子と、一方の端子が前記発光ダイオードのアノード端子に他方の端子が第３の直流電位の第３の直流電圧源に接続され前記選択期間後の逆バイアス期間に閉状態となる第５のスイッチング素子と、一方の端子が前記ｎ型電界効果トランジスタのゲート端子に、他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続される保持コンデンサとを含む構成を有している。   The light emitting diode driving circuit according to the present invention emits light with a luminance corresponding to a flowing current and has a cathode terminal connected to a reference potential and a drain terminal connected to a first DC voltage source having a first potential. an n-type field effect transistor, a first switching element that has one terminal connected to the anode terminal of the light-emitting diode and the other terminal connected to the source terminal of the n-type field-effect transistor; The terminal is connected to the gate terminal of the n-type field effect transistor, one terminal is connected to the other terminal of the input capacitor and the other terminal is connected to the data voltage source supplying the data voltage, and the light emission period ends. A second switching element that starts before and ends in a selection period that ends after the end of the light emission period, and one terminal of which is the n-type field effect A third terminal that is connected to the first DC voltage source and starts before the end of the light emission period, and is closed during a threshold writing period that ends within the selection period and after the end of the light emission period. The switching element, one terminal is connected to the source terminal of the n-type field effect transistor and the other terminal is connected to the second DC voltage source of the second potential, and starts after the threshold writing period ends or before or ends the selection period A fourth switching element that is closed during a data writing period that ends simultaneously; one terminal connected to the anode terminal of the light emitting diode and the other terminal connected to a third DC voltage source of a third DC potential; A fifth switching element that is closed in a reverse bias period after the selection period, and one terminal serving as the gate terminal of the n-type field effect transistor; The terminal has a structure including a holding capacitor connected to the source terminal of the n-type field effect transistor.

この構成により、逆バイアス効果を利用し、電界効果トランジスタの閾値電圧を補償可能な電圧プログラム型の発光ダイオード駆動回路の駆動トランジスタとしてｎ型電界効果トランジスタを使用することができることとなる。   With this configuration, an n-type field effect transistor can be used as a drive transistor of a voltage-programmed light-emitting diode drive circuit that can use the reverse bias effect and compensate the threshold voltage of the field-effect transistor.

本発明に係るディスプレイ装置は、前記いずれかの発光ダイオード駆動回路を複数マトリックス状に配置して構成される構成を有している。   The display device according to the present invention has a configuration in which any one of the light-emitting diode driving circuits is arranged in a matrix.

この構成により、液晶表示装置用の駆動回路によりディスプレイ装置を駆動できることとなる。   With this configuration, the display device can be driven by the drive circuit for the liquid crystal display device.

本発明は、所定期間中にｎ型電界効果トランジスタのソースを一定電位に維持することにより、駆動トランジスタとして動作特性が良好なｎ型電界効果トランジスタを使用できるという効果を有する発光ダイオード駆動回路を提供することができるものである。   The present invention provides a light emitting diode driving circuit having an effect that an n-type field effect transistor having good operating characteristics can be used as a driving transistor by maintaining the source of the n-type field effect transistor at a constant potential during a predetermined period. Is something that can be done.

以下、本発明に係る発光ダイオードの駆動回路の実施形態について、図面を用いて説明する。なお、以下の実施形態においては、発光ダイオードは有機発光ダイオードであるとしている。
（第１の実施形態）
本発明に係る有機発光ダイオードの駆動回路の第１の実施形態は、図１のブロック図に示すように、流れる電流に応じた輝度で発光しカソード端子が基準電位に接続される有機発光ダイオード１１と、ドレン端子が第１の電位Ｖddの第１の直流電圧源に接続されるｎ型電界効果トランジスタ１２と、一方の端子が有機発光ダイオード１１のアノード端子に他方の端子がｎ型電界効果トランジスタ１２のソース端子に接続され発光期間に閉状態となる第１のスイッチング素子１３と、一方の端子がｎ型電界効果トランジスタ１２のゲート端子に他方の端子がデータ電圧Ｖdataのデータ信号に接続され発光期間前の選択期間に閉状態となる第２のスイッチング素子１４と、一方の端子がｎ型電界効果トランジスタ１２のソース端子に他方の端子が第２の電位Ｖeの第２の直流電圧源に接続され選択期間に閉状態となる第３のスイッチング素子１５と、一方の端子が有機発光ダイオード１１のアノード端子に他方の端子が第３の電位Ｖrの第３の直流電圧源に接続され発光期間後の逆バイアス期間に閉状態となる第４のスイッチング素子１６と、一方の端子がｎ型電界効果トランジスタ１２のゲート端子に他方の端子がｎ型電界効果トランジスタ１２のソース端子に接続される保持コンデンサ１７とを含む。 DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a light emitting diode driving circuit according to the present invention will be described with reference to the drawings. In the following embodiments, the light emitting diode is an organic light emitting diode.
(First embodiment)
As shown in the block diagram of FIG. 1, the organic light emitting diode driving circuit according to the first embodiment of the present invention emits light with a luminance corresponding to a flowing current and has a cathode terminal connected to a reference potential. An n-type field effect transistor 12 having a drain terminal connected to a first DC voltage source having a first potential Vdd, one terminal being an anode terminal of the organic light emitting diode 11, and the other terminal being an n-type field effect transistor The first switching element 13 connected to the source terminal 12 and closed during the light emission period; one terminal connected to the gate terminal of the n-type field effect transistor 12 and the other terminal connected to the data signal of the data voltage Vdata; The second switching element 14 which is closed in the selection period before the period, one terminal being the source terminal of the n-type field effect transistor 12 and the other terminal being the first terminal A third switching element 15 connected to a second DC voltage source having a potential Ve of 1 and being closed during a selection period; one terminal being the anode terminal of the organic light emitting diode 11 and the other terminal being a third potential Vr; The fourth switching element 16 connected to the third DC voltage source and closed in the reverse bias period after the light emission period, one terminal being the gate terminal of the n-type field effect transistor 12 and the other terminal being the n-type electric field. And a holding capacitor 17 connected to the source terminal of the effect transistor 12.

なお、電界効果トランジスタにあっては、ソースとドレンを特に区別する必要はないが、ｎ型電界効果トランジスタ１２のように電流の流れる方向が一定である場合には、キャリアである電子を供給する側をソース、第１の直流電圧源に電子を排出する側をドレンと呼ぶ。   In the field effect transistor, it is not necessary to distinguish between the source and the drain, but when the direction of current flow is constant as in the n-type field effect transistor 12, electrons as carriers are supplied. The side that discharges electrons to the first DC voltage source is called the drain.

また、第１のスイッチング素子１３、第２のスイッチング素子１４、第３のスイッチング素子１５および第４のスイッチング素子１６として、図２の回路図に示すように、電界効果トランジスタを適用することが望ましいが、これらの電界効果トランジスタにあっては、ソースとドレンとを区別する必要はない。   Further, as the first switching element 13, the second switching element 14, the third switching element 15, and the fourth switching element 16, it is desirable to apply a field effect transistor as shown in the circuit diagram of FIG. However, in these field effect transistors, it is not necessary to distinguish between a source and a drain.

なお、図２の回路図では、第１のスイッチング素子１３、第２のスイッチング素子１４、第３のスイッチング素子１５および第４のスイッチング素子１６はｎ型電界効果トランジスタであるとしているが、ゲートに印加するパルスの極性を逆にすればｐ型電界効果トランジスタを使用することもできる。   In the circuit diagram of FIG. 2, the first switching element 13, the second switching element 14, the third switching element 15 and the fourth switching element 16 are n-type field effect transistors. If the polarity of the applied pulse is reversed, a p-type field effect transistor can be used.

次に、図２の回路図および図３のタイミング図を参照しつつ、第１の実施形態の動作を説明する。   Next, the operation of the first embodiment will be described with reference to the circuit diagram of FIG. 2 and the timing chart of FIG.

即ち、１フレーム期間（１／６０秒）毎に選択パルスがオンとなり、第２の電界効果トランジスタ２４および第３の電界効果トランジスタ２５が閉状態となる。なお、第１の電界効果トランジスタ２３および第４の電界効果トランジスタ２６は開状態である。   That is, the selection pulse is turned on every frame period (1/60 seconds), and the second field effect transistor 24 and the third field effect transistor 25 are closed. The first field effect transistor 23 and the fourth field effect transistor 26 are in an open state.

この状態では、ｎ型電界効果トランジスタ２２のゲートにデータ電圧Ｖdataが、ｎ型電界効果トランジスタ２２のソースに第２の直流電位Ｖeが印加される。すると、ｎ型電界効果トランジスタ１２のゲートとソースの間に接続された保持コンデンサ２７は、データ電圧Ｖdataと第２の直流電圧Ｖeの差電圧に比例した電荷を蓄積する。なお、保持コンデンサ２７をｎ型電界効果トランジスタ２２のソースとドレンに存在する寄生コンデンサで代用することも可能である。   In this state, the data voltage Vdata is applied to the gate of the n-type field effect transistor 22, and the second DC potential Ve is applied to the source of the n-type field effect transistor 22. Then, the holding capacitor 27 connected between the gate and the source of the n-type field effect transistor 12 accumulates a charge proportional to the difference voltage between the data voltage Vdata and the second DC voltage Ve. The holding capacitor 27 can be replaced by a parasitic capacitor present in the source and drain of the n-type field effect transistor 22.

選択パルスがオンからオフに遷移して第２の電界効果トランジスタ２４および第３の電界効果トランジスタ２５が開状態となると、発光パルスがオンとなり第１の電界効果トランジスタ２３が閉状態となる。すると、保持コンデンサ２７に蓄積されている電荷に応じた電流が有機発光ダイオード２１に流れてアノード電圧はＶ1まで上昇し、有機発光ダイオード２１は所定の輝度Ｌ1で発光する。 When the selection pulse transitions from on to off and the second field effect transistor 24 and the third field effect transistor 25 are opened, the light emission pulse is turned on and the first field effect transistor 23 is closed. Then, a current corresponding to the charge accumulated in the holding capacitor 27 is the anode voltage flows to the organic light emitting diode 21 is increased to V 1, the organic light emitting diode 21 emits light with predetermined luminance L 1.

発光パルスがオンからオフに遷移して第１の電界効果トランジスタ２３は開状態となり、有機発光ダイオード２１のアノード電圧は降下を開始し、有機発光ダイオード２１は発光を停止する。その後、逆バイアスパルスがオン状態となって第４の電界効果トランジスタ２６が閉状態となり、有機発光ダイオード２１のアノードは第３の直流電圧Ｖrに接続される。第３の直流電圧Ｖrは負電圧であるので、有機発光ダイオード２１は第３の直流電圧Ｖrに逆バイアスされ、その結果有機発光ダイオード２１の寿命を延ばすことが可能となる。逆バイアスパルスは、次の選択パルスがオンとなる前にオフとなり、走査線期間内の動作が終了する。   The light emission pulse transitions from on to off, the first field effect transistor 23 is opened, the anode voltage of the organic light emitting diode 21 starts to drop, and the organic light emitting diode 21 stops emitting light. Thereafter, the reverse bias pulse is turned on, the fourth field effect transistor 26 is closed, and the anode of the organic light emitting diode 21 is connected to the third DC voltage Vr. Since the third DC voltage Vr is a negative voltage, the organic light emitting diode 21 is reverse-biased to the third DC voltage Vr. As a result, the life of the organic light emitting diode 21 can be extended. The reverse bias pulse is turned off before the next selection pulse is turned on, and the operation within the scanning line period is completed.

なお、第１の実施形態において、図４の回路図に示すように、発光パルスのオフ時電圧を第２の直流電圧Ｖeおよび第３の直流電圧Ｖrに等しい負電圧に設定し、第３の電界効果トランジスタ２５の他方の端子および第４の電界効果トランジスタ２６の他方の端子を共通に発光パルス線に接続することにより、第２の直流電圧源および第３の直流電圧源を省略して回路を簡略化してもよい。
（第２の実施形態）
本発明に係る有機発光ダイオードの駆動回路の第２の実施形態は、図５のブロック図に示すように、流れる電流に応じた輝度で発光しカソード端子がアースに接続される有機発光ダイオード５１と、ドレン端子が第１の直流電圧Ｖddを供給する第１の直流電圧源に接続されるｎ型電界効果トランジスタ５２と、一方の端子が有機発光ダイオード５１のアノード端子に他方の端子がｎ型電界効果トランジスタ５２のソース端子に接続され発光期間に閉状態となる第１のスイッチング素子５３と、一方の端子がｎ型電界効果トランジスタ５２のゲート端子に接続される入力コンデンサ５４と、一方の端子が入力コンデンサ５４の他方の端子に他方の端子がデータ電圧Ｖdataを供給するデータ信号に接続され発光期間終了前に始まり発光期間終了後に終了する選択期間に閉状態となる第２のスイッチング素子５５と、一方の端子がｎ型電界効果トランジスタ５２のゲート端子に他方の端子が第１の直流電圧源に接続され発光期間終了前に始まり、選択期間内かつ発光期間終了後に終了するリセット期間に閉状態となる第３のスイッチング素子５６と、一方の端子がｎ型電界効果トランジスタ５２のソース端子に他方の端子が第２の直流電圧Ｖeを供給する第２の直流電圧源に接続されリセット期間終了後に始まり選択期間終了前または終了と同時に終了するデータ書き込み期間に閉状態となる第４のスイッチング素子５７と、一方の端子が有機発光ダイオード５１のアノード端子に他方の端子が第３の直流電圧Ｖrを供給する第３の直流電圧源に接続され選択期間後の逆バイアス期間に閉状態となる第５のスイッチング素子５８と、一方の端子がｎ型電界効果トランジスタ５２のゲート端子に他方の端子がｎ型電界効果トランジスタ５２のソース端子に接続される保持コンデンサ５９とを含む。 In the first embodiment, as shown in the circuit diagram of FIG. 4, the off-time voltage of the light emission pulse is set to a negative voltage equal to the second DC voltage Ve and the third DC voltage Vr. By connecting the other terminal of the field effect transistor 25 and the other terminal of the fourth field effect transistor 26 to the light emission pulse line in common, the second DC voltage source and the third DC voltage source are omitted. May be simplified.
(Second Embodiment)
As shown in the block diagram of FIG. 5, the second embodiment of the organic light emitting diode drive circuit according to the present invention emits light with a luminance corresponding to the flowing current and the cathode terminal is connected to the ground. The n-type field effect transistor 52 whose drain terminal is connected to the first DC voltage source supplying the first DC voltage Vdd, one terminal being the anode terminal of the organic light emitting diode 51 and the other terminal being the n-type electric field. The first switching element 53 connected to the source terminal of the effect transistor 52 and closed during the light emission period, the input capacitor 54 having one terminal connected to the gate terminal of the n-type field effect transistor 52, and one terminal being The other terminal of the input capacitor 54 is connected to the data signal for supplying the data voltage Vdata and the other terminal starts before the end of the light emission period and after the end of the light emission period. The second switching element 55 that is closed during the selection period to end, one terminal is connected to the gate terminal of the n-type field effect transistor 52 and the other terminal is connected to the first DC voltage source, and starts before the light emission period ends. The third switching element 56 which is in a closed state within the selection period and after the end of the light emission period, one terminal is the source terminal of the n-type field effect transistor 52 and the other terminal is the second DC voltage Ve. A fourth switching element 57 connected to a second DC voltage source that supplies the first switching element 57 and enters a closed state in a data writing period starting after the end of the reset period and ending before or after the selection period, and one terminal being an organic light emitting diode The other terminal is connected to the third DC voltage source for supplying the third DC voltage Vr to the anode terminal of 51, and is closed during the reverse bias period after the selection period. And a holding capacitor 59 having one terminal connected to the gate terminal of the n-type field effect transistor 52 and the other terminal connected to the source terminal of the n-type field effect transistor 52.

第１のスイッチング素子５３、第２のスイッチング素子５５、第３のスイッチング素子５６、第４のスイッチング素子５７および第５のスイッチング素子５８としては、図６に示すように電界効果トランジスタを適用することが望ましいが、これらの電界効果トランジスタは、ｐ型であってもｎ型であってもよく、また、ソースとドレンとを区別する必要もない。   As the first switching element 53, the second switching element 55, the third switching element 56, the fourth switching element 57, and the fifth switching element 58, field effect transistors are applied as shown in FIG. However, these field effect transistors may be p-type or n-type, and there is no need to distinguish between source and drain.

次に、図６の回路図および図７のタイミング図を参照しつつ、第２の実施形態の動作を説明する。   Next, the operation of the second embodiment will be described with reference to the circuit diagram of FIG. 6 and the timing chart of FIG.

即ち、１フレーム期間（１／６０秒）毎に選択パルスがオンとなり、第２の電界効果トランジスタ６５が閉状態となる。   That is, the selection pulse is turned on every frame period (1/60 seconds), and the second field effect transistor 65 is closed.

選択パルスがオン状態となると同時に閾値書き込みパルスもオンとなり、第３の電界効果トランジスタ６６が閉状態となる。すると、ｎ型電界効果トランジスタ６２のゲートとソースに接続された保持コンデンサ６９の一方の端子が第１の電位Ｖddを供給する第１の直流電圧源に接続され、その後発光パルスがオフになるとｎ型電界効果トランジスタ６２のドレン電流が零となり、保持コンデンサ６９にｎ型電界効果トランジスタ６２の閾値電圧が記憶される。なお、保持コンデンサ６９としてｎ型電界効果トランジスタ６２のソース・ドレン間に存在する寄生コンデンサを使用してもよい。   At the same time as the selection pulse is turned on, the threshold write pulse is also turned on, and the third field effect transistor 66 is closed. Then, one terminal of the holding capacitor 69 connected to the gate and the source of the n-type field effect transistor 62 is connected to the first DC voltage source that supplies the first potential Vdd. The drain current of the n-type field effect transistor 62 becomes zero, and the threshold voltage of the n-type field effect transistor 62 is stored in the holding capacitor 69. Note that a parasitic capacitor existing between the source and drain of the n-type field effect transistor 62 may be used as the holding capacitor 69.

保持コンデンサ６９の一方の端子がｎ型電界効果トランジスタ６２の閾値電圧に到達した後に閾値書き込みパルスがオフとなり第３の電界効果トランジスタ６６が開状態となり、その後データ書き込みパルスがオンとなり第４の電界効果トランジスタ６７が閉状態となる。すると、ｎ型電界効果トランジスタ６２のソースは第２の電圧Ｖeを供給する第２の直流電圧源に接続され、保持コンデンサ６９にｎ型電界効果トランジスタ６２の閾値電圧に重畳してデータ電圧Ｖdataと第２の電圧Ｖeの差電圧を入力コンデンサ６４と保持コンデンサ６９の容量比で分圧した電圧に比例した電荷が蓄積される。   After one terminal of the holding capacitor 69 reaches the threshold voltage of the n-type field effect transistor 62, the threshold write pulse is turned off and the third field effect transistor 66 is opened, and then the data write pulse is turned on and the fourth electric field is turned on. The effect transistor 67 is closed. Then, the source of the n-type field effect transistor 62 is connected to the second DC voltage source that supplies the second voltage Ve, and the data voltage Vdata and the storage capacitor 69 are superimposed on the threshold voltage of the n-type field effect transistor 62. Charges proportional to the voltage obtained by dividing the difference voltage of the second voltage Ve by the capacitance ratio of the input capacitor 64 and the holding capacitor 69 are accumulated.

電荷の蓄積が終了すると、データ書き込みパルスおよび選択パルスがオフとなり、第２の電界効果トランジスタ６５および第４の電界効果トランジスタ６７が開状態となる。   When the charge accumulation is completed, the data write pulse and the selection pulse are turned off, and the second field effect transistor 65 and the fourth field effect transistor 67 are opened.

その後、発光パルスがオンとなると、第１の電界効果トランジスタ６３が閉状態となり、保持コンデンサ６９に蓄積されている電荷に応じた電流が有機発光ダイオード６１に流れアノード電圧はＶ1まで上昇し、有機発光ダイオード２１は所定の輝度Ｌ1で発光する。 Thereafter, when the light emission pulse is turned on, the first field effect transistor 63 is closed, a current corresponding to the electric charge stored in the holding capacitor 69 flows into the organic light emitting diode 61, and the anode voltage rises to V 1 . The organic light emitting diode 21 emits light with a predetermined luminance L 1 .

発光パルスがオンからオフに遷移すると、第１の電界効果トランジスタ６３は開状態となり、有機発光ダイオード６１は発光を停止する。その後、次の選択パルスがオンとなる前に逆バイアスパルスがオンとなって第５の電界効果トランジスタ６８は閉状態となり、有機発光ダイオード６１のアノードは第３の直流電圧Ｖrに接続される。第３の直流電圧Ｖrは負電圧であるので、有機発光ダイオード６１は第３の直流電圧Ｖrに逆バイアスされ、その結果有機発光ダイオード６１の寿命を延ばすことが可能となる。逆バイアスパルスは、次のデータ書き込みパルスがオンとなる前にオフとなる。
（第３の実施形態）
第１の実施形態および第２の実施形態で説明した発光ダイオード駆動回路をディスプレイ装置に適用することも可能である。 When the light emission pulse transitions from on to off, the first field effect transistor 63 is opened, and the organic light emitting diode 61 stops emitting light. Thereafter, the reverse bias pulse is turned on before the next selection pulse is turned on, the fifth field effect transistor 68 is closed, and the anode of the organic light emitting diode 61 is connected to the third DC voltage Vr. Since the third DC voltage Vr is a negative voltage, the organic light emitting diode 61 is reverse-biased to the third DC voltage Vr. As a result, the life of the organic light emitting diode 61 can be extended. The reverse bias pulse is turned off before the next data write pulse is turned on.
(Third embodiment)
It is also possible to apply the light emitting diode driving circuit described in the first embodiment and the second embodiment to a display device.

図８は、第１の実施形態の有機発光ダイオード駆動回路を水平方向にＭ個、垂直方向にＮ個マトリックス状に配置して構成したディスプレイ装置のブロック図である。即ち、各画素（ｉ，ｊ）（１≦ｉ≦Ｍ、１≦ｊ≦Ｎ）として、図２または図４に示す有機発光ダイオード駆動回路が使用される。   FIG. 8 is a block diagram of a display device in which M organic light emitting diode driving circuits according to the first embodiment are arranged in a matrix form with M in the horizontal direction and N in the vertical direction. That is, the organic light emitting diode driving circuit shown in FIG. 2 or FIG. 4 is used as each pixel (i, j) (1 ≦ i ≦ M, 1 ≦ j ≦ N).

また、ディスプレイ装置は、図２または図４に示す有機発光ダイオード駆動回路をマトリックス状に配置した表示パネル８１と、映像信号を入力し、データ信号および行駆動信号を出力する映像信号処理回路８２と、データ信号から列データ信号を生成する外部駆動回路である列ドライバ８３と、行駆動信号から行毎駆動信号を生成する外部駆動回路である行ドライバ８４と、すべての有機発光ダイオード駆動回路に第１の電圧Ｖddを供給する第１の直流電源８５、第２の電圧Ｖeを供給する第２の直流電源８６および第３の電圧Ｖrを供給する第３の直流電源８７とから構成される。   The display device includes a display panel 81 in which the organic light emitting diode driving circuits shown in FIG. 2 or FIG. 4 are arranged in a matrix, a video signal processing circuit 82 for inputting a video signal and outputting a data signal and a row driving signal. The column driver 83 that is an external drive circuit that generates a column data signal from the data signal, the row driver 84 that is an external drive circuit that generates a row-by-row drive signal from the row drive signal, and all the organic light emitting diode drive circuits. The first DC power supply 85 supplies the first voltage Vdd, the second DC power supply 86 supplies the second voltage Ve, and the third DC power supply 87 supplies the third voltage Vr.

映像信号処理回路８２は、映像信号を入力して、データ信号Ｖdataと行駆動信号（Ｓ1、Ｓ2、Ｓ3）に変換する。列ドライバ８３は、データ信号Ｖdataを列毎データ信号Ｖdataiに分離し、表示パネル８１を構成する有機発光ダイオード駆動回路列ｉに供給する。行ドライバ８４は、行駆動信号（Ｓ1、Ｓ2、Ｓ3）を行毎駆動信号（Ｓ1j、Ｓ2j、Ｓ3j）に分離し、表示パネル８１を構成する有機発光ダイオード駆動回路行ｊに供給する。その結果、列毎データ信号Ｖdataiと行毎駆動信号（Ｓ1j、Ｓ2j、Ｓ3j）のオン・オフ状態に従って画素（ｉ、ｊ）が発光する。 The video signal processing circuit 82 receives the video signal and converts it into a data signal Vdata and row drive signals (S 1 , S 2 , S 3 ). The column driver 83 separates the data signal Vdata into the column-by-column data signal Vdatai and supplies the data signal Vdata to the organic light-emitting diode drive circuit row i constituting the display panel 81. The row driver 84 separates the row drive signals (S 1 , S 2 , S 3 ) into row-by-row drive signals (S 1j , S 2j , S 3j ), and the organic light emitting diode drive circuit row j constituting the display panel 81. To supply. As a result, the pixel (i, j) emits light according to the on / off state of the column-by-column data signal Vdatai and the row-by-row drive signals (S 1j , S 2j , S 3j ).

なお、画素として図６に示す有機発光ダイオード駆動回路も同様な構成で適用できることはいうまでもない。
なお、上記実施形態においては発光ダイオード駆動回路で駆動する発光ダイオードは有機発光ダイオードであるとしているが、発光ダイオードは有機発光ダイオードに限定されることはなく、シリコン等の無機発光ダイオードにも適用できることは、当業者にとって明らかである。 Needless to say, the organic light-emitting diode driving circuit shown in FIG.
In the above embodiment, the light-emitting diode driven by the light-emitting diode driving circuit is an organic light-emitting diode, but the light-emitting diode is not limited to the organic light-emitting diode and can be applied to an inorganic light-emitting diode such as silicon. Will be apparent to those skilled in the art.

以上のように、本発明に係る発光ダイオード駆動回路は、ｎ型電界効果トランジスタを駆動トランジスタとして使用できるという効果を有し、半導体表示装置等として有効である。   As described above, the light emitting diode driving circuit according to the present invention has an effect that an n-type field effect transistor can be used as a driving transistor, and is effective as a semiconductor display device or the like.

本発明に係る発光ダイオード駆動回路の第１の実施形態のブロック図1 is a block diagram of a first embodiment of a light-emitting diode driving circuit according to the present invention. 本発明に係る発光ダイオード駆動回路の第１の実施形態の回路図1 is a circuit diagram of a first embodiment of a light-emitting diode driving circuit according to the present invention; 本発明に係る発光ダイオード駆動回路の第１の実施形態のタイミング図Timing chart of the first embodiment of the light-emitting diode driving circuit according to the present invention 本発明に係る発光ダイオード駆動回路の第１の実施形態の変更例の回路図The circuit diagram of the example of a change of 1st Embodiment of the light emitting diode drive circuit which concerns on this invention 本発明に係る発光ダイオード駆動回路の第２の実施形態のブロック図The block diagram of 2nd Embodiment of the light emitting diode drive circuit based on this invention. 本発明に係る発光ダイオード駆動回路の第２の実施形態の回路図The circuit diagram of 2nd Embodiment of the light emitting diode drive circuit which concerns on this invention 本発明に係る発光ダイオード駆動回路の第２の実施形態のタイミング図Timing Diagram of Second Embodiment of Light Emitting Diode Drive Circuit According to the Present Invention 第１の実施形態および第２の実施形態で説明した発光ダイオード駆動回路を適用したディスプレイ装置のブロック図The block diagram of the display apparatus to which the light emitting diode drive circuit demonstrated in 1st Embodiment and 2nd Embodiment is applied. 従来の有機発光ダイオード駆動回路の回路図およびタイミング図Circuit diagram and timing diagram of conventional organic light emitting diode driving circuit

符号の説明Explanation of symbols

１１ 有機発光ダイオード
１２ ｎ型電界効果トランジスタ
１３ 第１のスイッチング素子
１４ 第２のスイッチング素子
１５ 第３のスイッチング素子
１６ 第４のスイッチング素子
１７ 保持コンデンサ DESCRIPTION OF SYMBOLS 11 Organic light emitting diode 12 N-type field effect transistor 13 1st switching element 14 2nd switching element 15 3rd switching element 16 4th switching element 17 Holding capacitor

Claims (3)

流れる電流に応じた輝度で発光し、カソード端子が基準電位に接続される発光ダイオードと、
ドレン端子が第１の電位の第１の直流電圧源に接続されるｎ型電界効果トランジスタと、
一方の端子が前記発光ダイオードのアノード端子に、他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続され、発光期間に閉状態となる第１のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのゲート端子に、他方の端子がデータ電位のデータ電圧源に接続され、前記発光期間前の選択期間に閉状態となる第２のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのソース端子に、他方の端子が第２の電位の第２の直流電圧源に接続され、前記選択期間に閉状態となる第３のスイッチング素子と、
一方の端子が前記発光ダイオードのアノード端子に、他方の端子が第３の電位の第３の直流電圧源に接続され、前記発光期間後の逆バイアス期間に閉状態となる第４のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのゲート端子に、他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続される保持コンデンサとを含む発光ダイオード駆動回路。 A light emitting diode that emits light with a luminance according to the flowing current and whose cathode terminal is connected to a reference potential;
An n-type field effect transistor having a drain terminal connected to a first DC voltage source at a first potential;
A first switching element having one terminal connected to the anode terminal of the light-emitting diode and the other terminal connected to the source terminal of the n-type field effect transistor;
A second switching element having one terminal connected to the gate terminal of the n-type field effect transistor and the other terminal connected to a data voltage source having a data potential, and being closed during a selection period before the light emission period;
A third switching element having one terminal connected to the source terminal of the n-type field effect transistor and the other terminal connected to a second DC voltage source having a second potential, and being closed during the selection period;
A fourth switching element having one terminal connected to the anode terminal of the light emitting diode and the other terminal connected to a third DC voltage source having a third potential, and being in a closed state in a reverse bias period after the light emitting period; ,
A light-emitting diode driving circuit including a holding capacitor having one terminal connected to a gate terminal of the n-type field effect transistor and the other terminal connected to a source terminal of the n-type field effect transistor. 流れる電流に応じた輝度で発光し、カソード端子が基準電位に接続される発光ダイオードと、
ドレン端子が第１の電位の第１の直流電圧源に接続されるｎ型電界効果トランジスタと、
一方の端子が前記発光ダイオードのアノード端子に、他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続され、発光期間に閉状態となる第１のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのゲート端子に接続される入力コンデンサと、
一方の端子が前記入力コンデンサの他方の端子に、他方の端子がデータ電圧を供給するデータ電圧源に接続され、前記発光期間終了前に始まり前記発光期間終了後に終了する選択期間に閉状態となる第２のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのゲート端子に、他方の端子が前記第１の直流電圧源に接続され、前記発光期間終了前に始まり、前記選択期間内かつ前記発光期間終了後に終了する閾値書き込み期間に閉状態となる第３のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのソース端子に、他方の端子が第２の電位の第２の直流電圧源に接続され、前記閾値書き込み期間終了後に始まり前記選択期間終了前または終了と同時に終了するデータ書き込み期間に閉状態となる第４のスイッチング素子と、
一方の端子が前記発光ダイオードのアノード端子に、他方の端子が第３の直流電位の第３の直流電圧源に接続され、前記選択期間後の逆バイアス期間に閉状態となる第５のスイッチング素子と、
一方の端子が前記ｎ型電界効果トランジスタのゲート端子に、他方の端子が前記ｎ型電界効果トランジスタのソース端子に接続される保持コンデンサとを含む発光ダイオード駆動回路。 A light emitting diode that emits light with a luminance according to the flowing current and whose cathode terminal is connected to a reference potential;
An n-type field effect transistor having a drain terminal connected to a first DC voltage source at a first potential;
A first switching element having one terminal connected to the anode terminal of the light-emitting diode and the other terminal connected to the source terminal of the n-type field effect transistor;
An input capacitor having one terminal connected to the gate terminal of the n-type field effect transistor;
One terminal is connected to the other terminal of the input capacitor, and the other terminal is connected to a data voltage source that supplies a data voltage, and is closed during a selection period that starts before the light emission period ends and ends after the light emission period ends. A second switching element;
One terminal is connected to the gate terminal of the n-type field effect transistor and the other terminal is connected to the first DC voltage source, starting before the end of the light emitting period, and ending within the selection period and after the end of the light emitting period. A third switching element that is closed during the threshold writing period;
One terminal is connected to the source terminal of the n-type field effect transistor, and the other terminal is connected to the second DC voltage source having the second potential, and starts after the threshold writing period ends or before or simultaneously with the end of the selection period. A fourth switching element that is closed during the data writing period to be terminated;
A fifth switching element in which one terminal is connected to the anode terminal of the light emitting diode, the other terminal is connected to a third DC voltage source having a third DC potential, and is closed in a reverse bias period after the selection period When,
A light-emitting diode driving circuit including a holding capacitor having one terminal connected to a gate terminal of the n-type field effect transistor and the other terminal connected to a source terminal of the n-type field effect transistor. 請求項１から請求項４のいずれか一項に記載の発光ダイオード駆動回路を複数マトリックス状に配置して構成されるディスプレイ装置。 The display apparatus comprised by arrange | positioning the light-emitting-diode drive circuit as described in any one of Claim 1 to 4 in multiple matrix form.
JP2006027050A 2006-02-03 2006-02-03 Light emitting diode driving circuit and display device using the same Pending JP2007206515A (en)

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