JP2007202237A - Power converter and control method of the same - Google Patents

Power converter and control method of the same Download PDF

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JP2007202237A
JP2007202237A JP2006014976A JP2006014976A JP2007202237A JP 2007202237 A JP2007202237 A JP 2007202237A JP 2006014976 A JP2006014976 A JP 2006014976A JP 2006014976 A JP2006014976 A JP 2006014976A JP 2007202237 A JP2007202237 A JP 2007202237A
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gate
semiconductor element
current
failure
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Tatsuto Nakajima
達人 中島
Jiyunya Sugano
純弥 菅野
Satoshi Miyazaki
聡 宮崎
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Tokyo Electric Power Company Holdings Inc
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Tokyo Electric Power Co Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To continuously operate a power converter even if a plurality of semiconductor elements for composing the power converter and connected in parallel are failed. <P>SOLUTION: In the power converter, a gate driving circuit 13 outputs gate signals to gates of the semiconductor elements 12 for composing a power conversion section composed by serially connecting a plurality of parallel element groups 11 in multiple stages which are formed by connecting a plurality of the semiconductor elements 12 in parallel. A failure detector 14 turns off a switch S provided between the gates of the semiconductor elements 12 and the gate driving circuit 13 when failures are detected in the semiconductor elements 12. Even if a portion of the semiconductor elements 12 is failed, an operation can be continued. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、複数個の半導体素子により構成される電力変換器及び半導体素子に故障が発生した時の電力変換器の制御方法に関する。   The present invention relates to a power converter composed of a plurality of semiconductor elements and a method for controlling the power converter when a failure occurs in a semiconductor element.

一般に、電力変換器では、１個の半導体素子だけでは容量が不足する場合、複数個の半導体素子を並列接続したり直列接続したりして所定容量を得るようにしている。また、並列接続と直列接続とを組み合わせた電力変換器も採用されている。   Generally, in a power converter, when a capacity is insufficient with only one semiconductor element, a predetermined capacity is obtained by connecting a plurality of semiconductor elements in parallel or in series. Moreover, the power converter which combined the parallel connection and the series connection is also employ | adopted.

このような複数個の半導体素子で構成された電力変換器においては、１個の半導体素子の故障が健全な半導体素子に悪影響を及ぼすことがあるので、半導体素子の故障は速やかに検出できることが要請されている。そして、複数個の半導体素子のいずれかが故障した場合には、安全性を確保するために電力変換器の運転を停止するようにしている。   In such a power converter composed of a plurality of semiconductor elements, a failure of one semiconductor element may adversely affect a healthy semiconductor element. Therefore, it is required that the failure of the semiconductor element can be detected promptly. Has been. When any of the plurality of semiconductor elements fails, the operation of the power converter is stopped in order to ensure safety.

電力変換器を構成する半導体素子には、ＩＧＢＴ（Insulated Gate Bipolar Transistor）などの絶縁ゲート形パワー半導体素子が用いられる。この絶縁ゲート形パワー半導体素子の故障には短絡故障と断線故障とがある。まず、絶縁ゲート形パワー半導体素子の短絡故障については、オフ時のコレクタ−エミッタ間電圧により故障検出を行う方法が広く知られている。絶縁ゲート形パワー半導体素子に短絡故障が発生するとオフ時のコレクタ−エミッタ間電圧がほぼ０Ｖになるため、短絡していることが検出できる。また、絶縁ゲート形パワー半導体素子の短絡故障を検出するものとして、ゲート電流のピーク値の大きさで短絡故障を判定し、絶縁ゲート形パワー半導体素子の故障を速やかに検出可能としたものがある（例えば、特許文献１参照）。   An insulated gate power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) is used as a semiconductor element constituting the power converter. There are a short circuit failure and a disconnection failure in the failure of the insulated gate power semiconductor element. First, as for a short-circuit fault of an insulated gate power semiconductor element, a method of detecting a fault by using a collector-emitter voltage when OFF is widely known. When a short circuit failure occurs in the insulated gate type power semiconductor element, the collector-emitter voltage at the time of OFF becomes almost 0 V, so that it can be detected that the short circuit has occurred. In addition, there is one that detects a short-circuit failure in the insulated gate power semiconductor element by determining the short-circuit failure based on the magnitude of the peak value of the gate current, so that the failure of the insulated gate power semiconductor element can be detected quickly. (For example, refer to Patent Document 1).

一方、絶縁ゲート形パワー半導体素子の断線故障については、半導体素子を並列接続していない場合は、電力変換器の断線故障となるため、各々の半導体素子の断線故障を特に検出する必要はなかった。また、半導体素子を並列接続している場合には、制御異常等で検出するまで運転を継続したり、微少抵抗を直列に接続してコレクタ−エミッタ間の電流を検出することなどで電力変換器を停止させていた。
特開２００２−２８１７３６号公報 On the other hand, with regard to the disconnection failure of the insulated gate type power semiconductor element, if the semiconductor elements are not connected in parallel, the power converter will be disconnected, so there is no need to detect the disconnection failure of each semiconductor element. . In addition, when semiconductor elements are connected in parallel, the power converter can be operated by continuing operation until it is detected due to a control abnormality or by detecting a current between the collector and emitter by connecting a small resistance in series. Had stopped.
JP 2002-281736 A

しかし、複数個の半導体素子で構成された電力変換器を構成する１個の半導体素子の故障で、電力変換器の運転を停止するようにしているので、電力変換器の稼働率が低下する。   However, since the operation of the power converter is stopped due to the failure of one semiconductor element constituting the power converter composed of a plurality of semiconductor elements, the operating rate of the power converter is lowered.

そこで、予め容量の大きい半導体素子を使用し、１個の半導体素子が故障となっても残りの健全な半導体素子で容量を確保して電力変換器の停止を回避することも考えられるが、半導体素子の利用率が悪くなる。   Therefore, it is conceivable that a semiconductor element having a large capacity is used in advance, and even if one semiconductor element fails, it is possible to secure the capacity with the remaining healthy semiconductor elements to avoid stopping the power converter. The utilization factor of the element deteriorates.

例えば、３個の半導体素子を並列接続し、その３個の並列素子群を３段に直列接続して構成された電力変換器の場合、いずれかの半導体素子に断線故障が発生した場合には、その断線故障した半導体素子に並列接続された２個の半導体素子で３個分の電流を負担することになる。一方、いずれかの半導体素子に短絡故障が発生した場合には、その短絡故障した半導体素子に直列接続された残り２段の半導体素子で３段分の電圧を負担することになる。   For example, in the case of a power converter configured by connecting three semiconductor elements in parallel and connecting the three parallel element groups in series in three stages, if a disconnection failure occurs in any of the semiconductor elements Then, two semiconductor elements connected in parallel to the broken semiconductor element bear a current of three. On the other hand, when a short circuit failure occurs in any of the semiconductor elements, the remaining two stages of semiconductor elements connected in series with the short circuit semiconductor element bear the voltage for three stages.

なお、半導体素子の短絡故障の場合には、予め容量の大きい半導体素子を使用しても電力変換器の停止を回避することができない場合がある。すなわち、半導体素子が並列接続の場合には各々の半導体素子のオンオフ信号のタイミングを合わせるためにゲート駆動回路を共通としている場合があり、その場合、短絡故障の発生により、短絡故障が発生した半導体素子を含む並列素子群の健全な半導体素子についても、オフ時にはコレクターエミッタ間電圧が上昇せずにほぼ０Ｖとなる。オフ時の半導体素子のコレクターエミッタ間電圧がほぼ０Ｖであると、ゲート電源自給方式（ゲート駆動回路に必要な電力を別電源から受けることなく主回路自体から供給できる方式）では、健全な半導体素子のゲート電圧が確保できない。従って、健全素子がオフ状態となるので短絡故障が発生した半導体素子に電流が集中することになり、短絡故障が発生した半導体素子が熱破壊を起こす可能性がある。また、短絡故障が発生した半導体素子がある程度抵抗を持った状態で短絡故障している場合には、短絡故障が発生した半導体素子の影響で健全な半導体素子のゲート電圧が変動し、健全な半導体素子は不完全なオンオフを繰り返すことになる。この場合には、予め容量の大きい半導体素子を使用しても、さらなる素子故障に至る可能性がある。   In the case of a short circuit failure of a semiconductor element, it may not be possible to avoid stopping the power converter even if a semiconductor element having a large capacity is used in advance. That is, when the semiconductor elements are connected in parallel, the gate drive circuit may be shared in order to synchronize the timing of the on / off signals of the respective semiconductor elements. In this case, the semiconductor in which the short-circuit fault has occurred due to the occurrence of a short-circuit fault. Even in the case of a healthy semiconductor element of a parallel element group including elements, the collector-emitter voltage does not increase when turned off, and becomes approximately 0V. When the collector-emitter voltage of the semiconductor element at the time of off is almost 0 V, the gate power supply self-sufficiency system (a system that can supply power required for the gate drive circuit from the main circuit itself without receiving power from another power source) The gate voltage cannot be secured. Therefore, since the healthy element is turned off, the current is concentrated on the semiconductor element in which the short circuit failure has occurred, and the semiconductor element in which the short circuit failure has occurred may cause thermal destruction. In addition, when a semiconductor element in which a short-circuit fault has occurred has a short-circuit fault with a certain degree of resistance, the gate voltage of the sound semiconductor element fluctuates due to the influence of the semiconductor element in which the short-circuit fault has occurred. The element is repeatedly turned on and off incompletely. In this case, even if a semiconductor element having a large capacity is used in advance, there is a possibility of further element failure.

一方、半導体素子の故障検出に関しては、並列接続された複数個の絶縁ゲート形パワー半導体素子のいずれかに短絡故障が発生した場合には、短絡故障が発生した絶縁ゲート形パワー半導体素子のオフ時のコレクタ−エミッタ間電圧がほぼ０Ｖになるので、いずれかの絶縁ゲート形パワー半導体素子に短絡故障が発生していることは分かるが、どの絶縁ゲート形パワー半導体素子が短絡故障しているのかを検出することができない。   On the other hand, regarding the failure detection of a semiconductor element, when a short circuit failure occurs in any of a plurality of insulated gate power semiconductor elements connected in parallel, the insulated gate power semiconductor element in which the short circuit failure has occurred is turned off. Since the collector-emitter voltage of the semiconductor device is almost 0 V, it can be seen that a short circuit failure has occurred in any of the insulated gate type power semiconductor elements. It cannot be detected.

また、特許文献１のものでは、ゲート電流のピーク値の大きさで短絡故障を判定しているので、大きなピーク値が出ない故障電流を検出することができない。例えば、短絡故障が発生した素子のオンゲート電流が健全な半導体素子と比べて、継続時間が長く電流増加量が少ない場合には、故障を検出することはできなない。   Moreover, in the thing of patent document 1, since the short circuit fault is determined by the magnitude | size of the peak value of gate current, the fault current which does not produce a big peak value cannot be detected. For example, a failure cannot be detected when the duration of the device is long and the amount of increase in current is small compared to a semiconductor device in which the on-gate current of the device in which the short circuit failure has occurred is healthy.

さらに、特許文献１のものは絶縁ゲート形パワー半導体素子の断線故障を検出する機能を有していない。一般に、絶縁ゲート形パワー半導体素子の断線故障は、半導体素子を並列接続していない場合には、主電流が遮断されるため変換器が停止となる。一方、半導体素子を並列接続している場合には、ゲートよりオン信号が出されているにも係わらす断線故障が発生した半導体素子には電流は流れず、他の健全素子にその分の電流を加えた電流が流れ、健全な半導体素子も素子故障に至る可能性があった。このため、瞬時に断線を検出し、電力変換器を停止する必要があった。しかしながら、断線故障の検出回路を設けずに、健全な半導体素子が異常を起こすまで運転したり、コレクタ−エミッタ間の電流により、断線故障を検出するなどにより電力変換器を停止させていた。   Furthermore, the thing of patent document 1 does not have a function which detects the disconnection failure of an insulated gate type power semiconductor element. In general, a disconnection failure of an insulated gate power semiconductor device stops the converter because the main current is cut off when the semiconductor devices are not connected in parallel. On the other hand, when the semiconductor elements are connected in parallel, no current flows through the semiconductor element in which the disconnection failure occurs even though the ON signal is output from the gate, and the corresponding current flows to other healthy elements. As a result, a healthy semiconductor device may also fail. For this reason, it was necessary to detect disconnection instantaneously and stop the power converter. However, without providing a disconnection failure detection circuit, the power converter is stopped by operating until a healthy semiconductor element is abnormal or by detecting a disconnection failure by a current between the collector and the emitter.

本発明の目的は、複数個の半導体素子で構成された電力変換器の並列接続された半導体素子に故障が発生した場合であっても運転を継続できる電力変換器及びその制御方法を提供することである。   An object of the present invention is to provide a power converter capable of continuing operation even when a failure occurs in a semiconductor element connected in parallel to a power converter composed of a plurality of semiconductor elements, and a control method thereof. It is.

請求項１の本発明に係わる電力変換器は、複数個の半導体素子を並列接続された電力変換器において、前記電力変換器を構成する各々の半導体素子のゲートにゲート信号を出力するゲート駆動回路と、前記半導体素子のゲートと前記ゲート駆動回路との間に設けられたスイッチと、前記各々の半導体素子の故障を検出したときは故障した半導体素子のゲートとゲート駆動回路との間のスイッチをオフする故障検出装置とを備えたことを特徴とする。   The power converter according to the present invention of claim 1 is a power converter in which a plurality of semiconductor elements are connected in parallel, and a gate drive circuit for outputting a gate signal to the gate of each semiconductor element constituting the power converter. And a switch provided between the gate of the semiconductor element and the gate drive circuit, and a switch between the gate of the failed semiconductor element and the gate drive circuit when a failure of each of the semiconductor elements is detected. And a failure detection device that is turned off.

請求項２の本発明に係わる電力変換器の制御方法は、複数個の半導体素子を並列接続して形成された並列素子群を多段に直列接続して構成された電力変換器の制御方法において、前記半導体素子の故障を検出し、故障した半導体素子のゲートとゲート駆動回路との間に設けられたスイッチをオフし、故障した半導体素子に並列接続された半導体素子にオンのゲート信号を出し続けることを特徴とする。   The method for controlling a power converter according to the present invention of claim 2 is a method for controlling a power converter configured by connecting a plurality of semiconductor elements connected in parallel to each other in a multistage series connection. The failure of the semiconductor element is detected, the switch provided between the gate of the failed semiconductor element and the gate drive circuit is turned off, and the ON gate signal is continuously output to the semiconductor elements connected in parallel to the failed semiconductor element. It is characterized by that.

本発明によれば、複数個の半導体素子で構成された電力変換器の半導体素子の故障を検出したときは、ゲート駆動回路と半導体素子のゲートとの間に設けられたスイッチをオフするので、健全な半導体素子に対しゲート電流の安定した供給が可能となり、半導体素子に故障が発生した場合であっても故障が発生した半導体素子に並列接続された半導体素子を活用することにより運転継続が可能となる。   According to the present invention, when the failure of the semiconductor element of the power converter composed of a plurality of semiconductor elements is detected, the switch provided between the gate drive circuit and the gate of the semiconductor element is turned off. Stable supply of gate current to healthy semiconductor elements is possible, and even if a failure occurs in a semiconductor element, operation can be continued by using a semiconductor element connected in parallel to the semiconductor element in which the failure has occurred It becomes.

図１は本発明の実施の形態に係わる電力変換部の構成図である。本実施例の電力変換部は、複数個の半導体素子が並列接続して形成された並列素子群を多段に直列接続して構成されている。図１では３個の半導体素子が並列接続された並列素子群を３段に直列接続した電力変換部を示している。   FIG. 1 is a configuration diagram of a power conversion unit according to an embodiment of the present invention. The power conversion unit of the present embodiment is configured by serially connecting multiple parallel element groups formed by connecting a plurality of semiconductor elements in parallel. FIG. 1 shows a power conversion unit in which parallel element groups in which three semiconductor elements are connected in parallel are connected in series in three stages.

例えば、第１段の並列素子群１１ａには３個の半導体素子１２ａ１、１２ａ２、１２ａ３が並列接続され、第２段の並列素子群１１ｂには３個の半導体素子１２ｂ１、１２ｂ２、１２ｂ３が並列接続され、第３段の並列素子群１１ｃには３個の半導体素子１２ｃ１、１２ｃ２、１２ｃ３が並列接続され、これら第１段の並列素子群１１ａ、第２段の並列素子群１１ｂ、第３段の並列素子群１１ｃが３段に直列接続されて電力変換部が構成されている。電力変換器は、この電力変換部を複数組み合わせて構成される。   For example, three semiconductor elements 12a1, 12a2, and 12a3 are connected in parallel to the first-stage parallel element group 11a, and three semiconductor elements 12b1, 12b2, and 12b3 are connected in parallel to the second-stage parallel element group 11b. In addition, three semiconductor elements 12c1, 12c2, and 12c3 are connected in parallel to the third-stage parallel element group 11c. The first-stage parallel element group 11a, the second-stage parallel element group 11b, and the third-stage parallel-element group 11c The parallel element group 11c is connected in series in three stages to constitute a power conversion unit. The power converter is configured by combining a plurality of power converters.

各々の並列素子群１１ａ、１１ｂ、１１ｃには、それぞれゲート駆動回路１３ａ、１３ｂ、１３ｃが設けられている。ゲート駆動回路１３は、電力変換部を構成する各々の半導体素子１２のゲートにゲート信号を出力するものであり、それぞれ並列素子群１１の並列接続された半導体素子１２に対して共通に設けられている。例えば、ゲート駆動回路１３ａは第１段の並列素子群１１ａの並列接続された３個の半導体素子１２ａ１、１２ａ２、１２ａ３に対して共通に設けられ、３個の半導体素子１２ａ１、１２ａ２、１２ａ３のゲートにほぼ同じタイミングでゲート信号を出力する。ゲート駆動回路１３ｂ、１３ｃについても同様である。ここで、ゲート駆動回路１３を並列素子群１１の並列接続された半導体素子１２に対して共通に設けているのは、並列接続された半導体素子１２のオンオフのタイミングをほぼ同時に行えるようにするためであり、並列素子群１１を構成する各々の半導体素子１２それぞれに対し駆動回路を設け、並列接続された半導体素子１２のオンオフのタイミングをほぼ同時とするように制御することも可能である。   Each parallel element group 11a, 11b, and 11c is provided with gate drive circuits 13a, 13b, and 13c, respectively. The gate drive circuit 13 outputs a gate signal to the gate of each semiconductor element 12 constituting the power conversion unit, and is provided in common for the semiconductor elements 12 connected in parallel in the parallel element group 11. Yes. For example, the gate drive circuit 13a is provided in common for the three semiconductor elements 12a1, 12a2, and 12a3 connected in parallel in the first-stage parallel element group 11a, and the gates of the three semiconductor elements 12a1, 12a2, and 12a3. The gate signal is output at almost the same timing. The same applies to the gate drive circuits 13b and 13c. Here, the reason why the gate drive circuit 13 is provided in common to the parallel-connected semiconductor elements 12 of the parallel element group 11 is to enable the on-off timing of the parallel-connected semiconductor elements 12 to be performed almost simultaneously. It is also possible to provide a drive circuit for each of the semiconductor elements 12 constituting the parallel element group 11 and control the on / off timing of the semiconductor elements 12 connected in parallel to be substantially the same.

第１段のゲート駆動回路１３ａからのゲート信号は、並列接続されたゲート入力抵抗Ｒａ１、Ｒａ２、Ｒａ３にそれぞれ入力され、スイッチＳａ１、Ｓａ２、Ｓａ３を介して、第１段の並列素子群１１ａの並列接続された３個の半導体素子１２ａ１、１２ａ２、１２ａ３にゲート信号を出力する。第２段のゲート駆動回路１３ｂ及び第３のゲート駆動回路１３ｃのゲート信号についても同様に、並列接続されたゲート入力抵抗Ｒｂ１、Ｒｂ２、Ｒｂ３（Ｒｃ１、Ｒｃ２、Ｒｃ３）にそれぞれ入力され、スイッチＳｂ１、Ｓｂ２、Ｓｂ３（Ｓｃ１、Ｓｃ２、Ｓｃ３）を介して、第２段の並列素子群１１ｂ（第３段の並列素子群１１ｃ）の並列接続された３個の半導体素子１２ｂ１、１２ｂ２、１２ｂ３（１２ｃ１、１２ｃ２、１２ｃ３）にゲート信号を出力する。   Gate signals from the first-stage gate drive circuit 13a are respectively input to the gate input resistors Ra1, Ra2, and Ra3 connected in parallel, and the first-stage parallel element group 11a is connected via the switches Sa1, Sa2, and Sa3. A gate signal is output to the three semiconductor elements 12a1, 12a2, and 12a3 connected in parallel. Similarly, the gate signals of the second stage gate drive circuit 13b and the third gate drive circuit 13c are respectively input to the gate input resistors Rb1, Rb2, and Rb3 (Rc1, Rc2, and Rc3) connected in parallel, and the switch Sb1. , Sb2, Sb3 (Sc1, Sc2, Sc3), three semiconductor elements 12b1, 12b2, 12b3 (12c1) connected in parallel in the second-stage parallel element group 11b (third-stage parallel element group 11c) , 12c2, 12c3).

故障検出装置１４は電力変換部を構成する個々の半導体素子１２の故障を個別に検出するものである。すなわち、第１段の並列素子群１１ａの並列接続された３個の半導体素子１２ａ１、１２ａ２、１２ａ３、第２段の並列素子群１１ｂの並列接続された３個の半導体素子１２ｂ１、１２ｂ２、１２ｂ３、第３段の並列素子群１１ｃの並列接続された３個の半導体素子１２ｃ１、１２ｃ２、１２ｃ３の各々のゲート電流Ｉｇａ１〜Ｉｇｃ１に基づいて、個々の半導体素子１２の故障を個別に検出する。そして、例えば、半導体素子１２ａ１の故障を検出したときは、故障した半導体素子１２ａ１のスイッチＳａ１をオフするように、いずれかの半導体素子１２の故障を検出したときは、故障した半導体素子１２のスイッチＳをオフする。なお、スイッチＳとしては小容量のＭＯＳＦＥＴ等が使用できる。   The failure detection device 14 is for individually detecting failures of the individual semiconductor elements 12 constituting the power conversion unit. That is, three semiconductor elements 12a1, 12a2, 12a3 connected in parallel in the first-stage parallel element group 11a, and three semiconductor elements 12b1, 12b2, 12b3 connected in parallel in the second-stage parallel element group 11b, Based on the gate currents Iga1 to Igc1 of the three semiconductor elements 12c1, 12c2, and 12c3 connected in parallel in the third-stage parallel element group 11c, a failure of each semiconductor element 12 is individually detected. For example, when a failure of one of the semiconductor elements 12 is detected so that the switch Sa1 of the failed semiconductor element 12a1 is turned off when a failure of the semiconductor element 12a1 is detected, the switch of the failed semiconductor element 12 is switched Turn off S. As the switch S, a small capacity MOSFET or the like can be used.

これにより、短絡故障が発生した半導体素子へのゲート電流の供給が遮断されるので、健全な半導体素子へのゲート信号発生時にゲート電源電圧の低下を防止できる。従って、健全な半導体素子に対しゲート電流の供給が可能となり、半導体素子に短絡故障が発生した場合であっても電力変換器の運転継続が可能となる。   As a result, the supply of the gate current to the semiconductor element in which the short-circuit failure has occurred is interrupted, so that it is possible to prevent the gate power supply voltage from being lowered when the gate signal is generated to the healthy semiconductor element. Accordingly, it is possible to supply a gate current to a healthy semiconductor element, and it is possible to continue the operation of the power converter even when a short circuit failure occurs in the semiconductor element.

さらに、短絡故障が発生した半導体素子と並列接続された健全な半導体素子のゲートにオン信号を出し続けるようにすれば、健全な半導体素子をオフすることがなくなり、短絡故障が発生した半導体素子の影響による過電圧や過電流を防止できる。   Furthermore, if the ON signal is continuously output to the gate of the healthy semiconductor element connected in parallel with the semiconductor element in which the short-circuit fault has occurred, the sound semiconductor element will not be turned off, and the semiconductor element in which the short-circuit fault has occurred can be prevented. Overvoltage and overcurrent due to influence can be prevented.

また、断線故障が発生した半導体素子に対してもゲート電流の供給が遮断されるので、ゲートからゲート駆動回路への回り込み電流を防止でき、断線故障が発生した半導体素子に発生する異常電圧や異常電流の発生を防止できる。従って、健全な半導体素子に対しゲート電流の供給が可能となり、半導体素子に断線故障が発生した場合であっても電力変換器の運転継続が可能となる。   In addition, since the gate current supply is cut off even for the semiconductor element in which the disconnection failure has occurred, the sneak current from the gate to the gate drive circuit can be prevented, and the abnormal voltage or abnormality generated in the semiconductor element in which the disconnection failure has occurred. Generation of current can be prevented. Accordingly, it is possible to supply a gate current to a healthy semiconductor element, and it is possible to continue operation of the power converter even when a disconnection failure occurs in the semiconductor element.

次に、故障検出装置１４での半導体素子１２の故障検出について説明する。図２は、半導体素子１２の故障検出装置のブロック構成図である。ただし、説明のため、一つの半導体素子の故障検出について示したものである。半導体素子１２は、コレクタＣ、エミッタＥ、ゲートＧを有し、ゲートＧとエミッタＥとの間にゲート駆動回路１３からゲート電圧Ｖｇｅを印加して、オンオフ制御を行う。ゲートＧにはゲート入力抵抗Ｒｇが設けられ、このゲート入力抵抗Ｒｇを流れるゲート電流Ｉｇが故障検出装置１４の電流検出部１５で検出される。電流検出部１５はゲート入力抵抗Ｒｇの両端電圧によりゲート電流Ｉｇを検出する。なお、本実施例ではゲート電流をゲート入力抵抗の両端電圧より検出しているが、例えばゲート入力抵抗とは別にゲート電流検出用抵抗を設け、その両端電圧からゲート電流を検出するなどの別の方法を用いてもよい。   Next, failure detection of the semiconductor element 12 by the failure detection device 14 will be described. FIG. 2 is a block configuration diagram of the failure detection apparatus for the semiconductor element 12. However, for the sake of explanation, the failure detection of one semiconductor element is shown. The semiconductor element 12 has a collector C, an emitter E, and a gate G. The gate drive circuit 13 applies a gate voltage Vge between the gate G and the emitter E to perform on / off control. The gate G is provided with a gate input resistance Rg, and the gate current Ig flowing through the gate input resistance Rg is detected by the current detection unit 15 of the failure detection device 14. The current detector 15 detects the gate current Ig based on the voltage across the gate input resistor Rg. In this embodiment, the gate current is detected from the voltage across the gate input resistor. For example, a gate current detection resistor is provided separately from the gate input resistor and the gate current is detected from the voltage across the gate input resistor. A method may be used.

故障検出装置１４の電流検出部１５で検出されたゲート電流Ｉｇは、断線故障検出部１６及び短絡故障検出部１７に入力される。短絡故障検出部１７はゲート駆動回路１３からゲートＧに流れ込むオンゲート電流またはゲートＧよりゲート駆動回路１３へ流れ込むオフゲート電流を健全時の電流と比較して短絡故障を検出する。また、断線故障検出部１６は、少なくともゲートＧよりゲート駆動回路１３へ流れ込むオフゲート電流を健全時の電流と比較して断線故障を検出する。   The gate current Ig detected by the current detection unit 15 of the failure detection device 14 is input to the disconnection failure detection unit 16 and the short circuit failure detection unit 17. The short-circuit fault detection unit 17 detects a short-circuit fault by comparing the on-gate current flowing from the gate drive circuit 13 to the gate G or the off-gate current flowing from the gate G to the gate drive circuit 13 with the current in the healthy state. Further, the disconnection failure detection unit 16 detects a disconnection failure by comparing at least an off-gate current flowing from the gate G into the gate drive circuit 13 with a current in a healthy state.

図３は半導体素子がＩＧＢＴ（Insulated Gate Bipolar Transistor）などの絶縁ゲート形パワー半導体素子である場合のオンゲート電流及びオフゲート電流の説明図である。いま、時点ｔ１で半導体素子のゲートＧとエミッタＥとの間にゲート電圧Ｖｇｅを印加したとするとオンゲート電流Ｉｇ１が流れる。オンゲート電流Ｉｇ１は、時点ｔ１〜時点ｔ２のゲート電圧Ｖｇｅの急峻な立ち上がり期間Ｔ１において比較的大きな値のオンゲート電流Ｉｇ１１となり、時点ｔ２〜時点ｔ３のゲート電圧Ｖｇｅの緩慢な立ち上がり期間Ｔ２において比較的小さな値のオンゲート電流Ｉｇ１２となる。つまり、時点ｔ１でのゲート電圧Ｖｇｅの印加によりオンゲート電流Ｉｇ１１が流れて、半導体素子はオンを開始し時点ｔ３でオン状態となる。   FIG. 3 is an explanatory diagram of on-gate current and off-gate current when the semiconductor element is an insulated gate power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor). Assuming that a gate voltage Vge is applied between the gate G and the emitter E of the semiconductor element at time t1, an on-gate current Ig1 flows. The on-gate current Ig1 becomes a relatively large on-gate current Ig11 in the steep rising period T1 of the gate voltage Vge from the time point t1 to the time point t2, and is relatively small in the slow rising period T2 of the gate voltage Vge from the time point t2 to the time point t3. Value of the on-gate current Ig12. That is, the on-gate current Ig11 flows due to the application of the gate voltage Vge at time t1, and the semiconductor element starts to turn on and is turned on at time t3.

そして、時点ｔ４でゲート電圧Ｖｇｅを低下させたとするとオフゲート電流Ｉｇ２が流れる。オフゲート電流Ｉｇ２は、ゲート電圧Ｖｇｅの立ち下がりにより時点ｔ４〜時点ｔ５の期間Ｔ５において比較的大きな値のオフゲート電流Ｉｇ２１となり、時点ｔ５〜時点ｔ６のゲート電圧Ｖｇｅの急峻な立ち下がり期間Ｔ４において比較的小さな値のオフゲート電流Ｉｇ２２となる。つまり、時点ｔ４でゲート電圧Ｖｇｅを低下によりオフゲート電流Ｉｇ２１が流れて、半導体素子はオフを開始し時点ｔ６でオフ状態となる。   If the gate voltage Vge is reduced at time t4, an off-gate current Ig2 flows. The off-gate current Ig2 becomes a relatively large off-gate current Ig21 in the period T5 from the time point t4 to the time point t5 due to the fall of the gate voltage Vge, and the off-gate current Ig2 is relatively large in the sharp fall period T4 of the gate voltage Vge from the time point t5 to the time point t6. The off-gate current Ig22 has a small value. That is, the off-gate current Ig21 flows due to the decrease in the gate voltage Vge at time t4, the semiconductor element starts to turn off, and is turned off at time t6.

図４は半導体素子が健全時のオンゲート電流及びオフゲート電流の説明図であり、図４（ａ）はオンゲート電流Ｉｇ１１、Ｉｇ１２の説明図、図４（ｂ）はオフゲート電流Ｉｇ２１、Ｉｇ２２の説明図である。半導体素子が健全であるときは、ゲート電圧Ｖｇｅを印加すると、所定範囲内の大きさの図３に示した特性のオンゲート電流Ｉｇ１１、Ｉｇ１２が流れ、ゲート電圧Ｖｇｅを低下させると所定範囲内の大きさの図３に示した特性のオフゲート電流Ｉｇ２１、Ｉｇ２２が流れる。   4 is an explanatory diagram of the on-gate current and off-gate current when the semiconductor element is healthy, FIG. 4A is an explanatory diagram of the on-gate currents Ig11 and Ig12, and FIG. 4B is an explanatory diagram of the off-gate currents Ig21 and Ig22. is there. When the semiconductor element is healthy, when the gate voltage Vge is applied, the on-gate currents Ig11 and Ig12 having the characteristics shown in FIG. 3 having a magnitude within a predetermined range flow, and when the gate voltage Vge is lowered, the magnitude is within a predetermined range. The off-gate currents Ig21 and Ig22 having the characteristics shown in FIG.

この半導体素子の健全時のオンゲート電流Ｉｇ１及びオフゲート電流Ｉｇ２は所定値として予め故障検出装置１４に記憶される。この予め定めた所定値は、例えば、オンゲート電流Ｉｇ１やオフゲート電流Ｉｇ２の絶対値を積分して、その積分値をオンゲート電流Ｉｇ１やオフゲート電流Ｉｇ２の値とする。この場合、健全な複数個の半導体素子のオンゲート電流またはオフゲート電流の平均値を採用することも可能である。また、故障検出対象となる自己の半導体素子の過去のオンゲート電流またはオフゲート電流のデータ値を用いることも可能である。さらに、所定値に安全率を見込むことも可能である。   The on-gate current Ig1 and off-gate current Ig2 when the semiconductor element is healthy are stored in advance in the failure detection device 14 as predetermined values. For example, the predetermined value is obtained by integrating the absolute values of the on-gate current Ig1 and the off-gate current Ig2, and setting the integrated values as the values of the on-gate current Ig1 and the off-gate current Ig2. In this case, it is also possible to employ the average value of the on-gate current or off-gate current of a plurality of healthy semiconductor elements. It is also possible to use the data value of the past on-gate current or off-gate current of the self semiconductor element that is the target of failure detection. Furthermore, it is possible to expect a safety factor for the predetermined value.

そして、故障検出装置１４では、オンゲート電流Ｉｇ１またはオフゲート電流Ｉｇ２の絶対値を積分し、その積分値と予め定めた所定値との比較により、短絡故障や断線故障を検出することになる。   Then, the failure detection device 14 integrates the absolute value of the on-gate current Ig1 or off-gate current Ig2, and detects a short-circuit failure or a disconnection failure by comparing the integrated value with a predetermined value.

次に、短絡故障検出部１７での短絡故障の検出方法について説明する。図５は絶縁ゲート形パワー半導体素子が短絡故障時であるときのオンゲート電流及びオフゲート電流の説明図であり、図５（ａ）はオンゲート電流Ｉｇ１１、Ｉｇ１２の説明図、図５（ｂ）はオフゲート電流Ｉｇ２１、Ｉｇ２２の説明図である。   Next, a short-circuit fault detection method in the short-circuit fault detection unit 17 will be described. FIG. 5 is an explanatory diagram of on-gate current and off-gate current when the insulated gate type power semiconductor device is in a short circuit failure state, FIG. 5 (a) is an explanatory diagram of on-gate currents Ig11 and Ig12, and FIG. 5 (b) is an off-gate current. It is explanatory drawing of electric current Ig21 and Ig22.

絶縁ゲート形パワー半導体素子の短絡故障は、コレクタＣとエミッタＥとの間が短絡している状態であるので、図５（ａ）に示すように絶縁ゲート形パワー半導体素子のオンゲート電流Ｉｇ１１、Ｉｇ１２は健全時のオンゲート電流Ｉｇ１１、Ｉｇ１２より大きくなる。同様に、絶縁ゲート形パワー半導体素子のオフゲート電流Ｉｇ２１、Ｉｇ２２も、図５（ｂ）に示すように健全時のオフゲート電流Ｉｇ２１、Ｉｇ２２より大きくなる。   Since the short-circuit failure of the insulated gate type power semiconductor element is a state where the collector C and the emitter E are short-circuited, the on-gate currents Ig11 and Ig12 of the insulated gate type power semiconductor element as shown in FIG. Becomes larger than the on-gate currents Ig11 and Ig12 in a healthy state. Similarly, the off-gate currents Ig21 and Ig22 of the insulated gate power semiconductor element are also larger than the off-gate currents Ig21 and Ig22 in a healthy state as shown in FIG. 5B.

表１は半導体素子が短絡故障時のゲート電流のこの特性を示す表である。すなわち、短絡故障時と健全時とのオンゲート電流Ｉｇ１１、Ｉｇ１２、オフゲート電流Ｉｇ２１、Ｉｇ２２の比及び検出の可否を示す。   Table 1 is a table showing this characteristic of the gate current when the semiconductor element is short-circuited. That is, the ratio of on-gate currents Ig11 and Ig12 and off-gate currents Ig21 and Ig22 at the time of a short circuit failure and a healthy state and the availability of detection are shown.


Figure 2007202237
Figure 2007202237

短絡故障検出部１７は、この短絡故障時の状態を検出する。すなわち、絶縁ゲート形パワー半導体素子のオンゲート電流Ｉｇ１またはオフゲート電流Ｉｇ２が健全時の電流より大きいときに絶縁ゲート形パワー半導体素子の短絡故障として検出する。この場合、短絡故障検出の精度を向上させるために、判定回数を設定し同じ現象が複数回続いたときに短絡故障として判定するようにしても良い。また、オンゲート電流Ｉｇ１及びオフゲート電流Ｉｇ２の双方が健全時の電流より大きいときに絶縁ゲート形パワー半導体素子の短絡故障として検出するようにしてもよい。   The short circuit failure detection unit 17 detects the state at the time of this short circuit failure. That is, when the on-gate current Ig1 or the off-gate current Ig2 of the insulated gate power semiconductor element is larger than the current at the time of soundness, it is detected as a short-circuit failure of the insulated gate power semiconductor element. In this case, in order to improve the accuracy of short-circuit fault detection, the number of determinations may be set so that a short-circuit fault is determined when the same phenomenon continues a plurality of times. Further, when both the on-gate current Ig1 and the off-gate current Ig2 are larger than the current at the time of health, it may be detected as a short-circuit failure of the insulated gate type power semiconductor element.

次に、断線故障検出部１６での断線故障の検出方法について説明する。図６は絶縁ゲート形パワー半導体素子のコレクタ側の断線故障時であるときのオンゲート電流及びオフゲート電流の説明図であり、図６（ａ）はオンゲート電流Ｉｇ１１、Ｉｇ１２の説明図、図６（ｂ）はオフゲート電流Ｉｇ２１、Ｉｇ２２の説明図である。   Next, a disconnection failure detection method in the disconnection failure detection unit 16 will be described. FIG. 6 is an explanatory diagram of on-gate current and off-gate current at the time of disconnection failure on the collector side of the insulated gate type power semiconductor element, FIG. 6 (a) is an explanatory diagram of on-gate currents Ig11 and Ig12, and FIG. ) Is an explanatory diagram of the off-gate currents Ig21 and Ig22.

図６（ａ）に示すように、絶縁ゲート形パワー半導体素子のコレクタ側のＦ１点で断線故障しているとすると、コレクタＣとエミッタＥとの間は断線状態となるが、ゲートＧとエミッタＥとの間は健全状態とほぼ同じ状態である。従って、ゲートＧとエミッタＥとの間にゲート電圧Ｖｇｅが印加されると、健全時と同様なオンゲート電流Ｉｇ１１、Ｉｇ１２が流れる。   As shown in FIG. 6A, if a disconnection failure occurs at the F1 point on the collector side of the insulated gate type power semiconductor element, a disconnection state occurs between the collector C and the emitter E, but the gate G and the emitter. Between E, the state is almost the same as the healthy state. Therefore, when the gate voltage Vge is applied between the gate G and the emitter E, the on-gate currents Ig11 and Ig12 similar to those in the normal state flow.

一方、オフゲート電流Ｉｇ２１、Ｉｇ２２は、図６（ｂ）に示すように、健全時のオフゲート電流Ｉｇ２１、Ｉｇ２２より小さくなる。これは、健全時においては、絶縁ゲート形パワー半導体素子が導通しているときにコレクタＣとエミッタＥとの間に蓄積された電荷がオフゲート電流Ｉｇ２１、Ｉｇ２２に重畳されて流れるが、コレクタ側のＦ１点で断線故障している場合においては、コレクタＣとエミッタＥとの間に電荷は蓄積されないので、オフゲート電流Ｉｇ２１、Ｉｇ２２に重畳される電荷がないからである。   On the other hand, the off-gate currents Ig21 and Ig22 are smaller than the off-gate currents Ig21 and Ig22 in a healthy state, as shown in FIG. 6B. In a healthy state, the charge accumulated between the collector C and the emitter E flows while being superimposed on the off-gate currents Ig21 and Ig22 when the insulated gate power semiconductor element is conducting. This is because when a disconnection failure occurs at the point F1, no charge is accumulated between the collector C and the emitter E, so that there is no charge superimposed on the off-gate currents Ig21 and Ig22.

表２は半導体素子がコレクタ側で断線故障した場合のゲート電流の特性を示す表である。すなわち、コレクタ側での断線故障時と健全時とのオンゲート電流Ｉｇ１１、Ｉｇ１２、オフゲート電流Ｉｇ２１、Ｉｇ２２の比及び検出の可否を示す。

Figure 2007202237
Table 2 is a table showing the characteristics of the gate current when the semiconductor element breaks down on the collector side. That is, the ratio of the on-gate currents Ig11 and Ig12 and the off-gate currents Ig21 and Ig22 between the disconnection failure and the healthy state on the collector side and the possibility of detection are shown.
Figure 2007202237

断線故障検出部１６は、このコレクタ側の断線故障時の状態を検出する。すなわち、絶縁ゲート形パワー半導体素子のオンゲート電流Ｉｇ１（Ｉｇ１１、Ｉｇ１２）が健全時の電流とほぼ同じであり、かつ、オフゲート電流Ｉｇ２（Ｉｇ２１、Ｉｇ２２）が健全時の電流より小さいときは絶縁ゲート形パワー半導体素子のコレクタ側の断線故障として検出する。   The disconnection failure detection unit 16 detects the state at the time of the disconnection failure on the collector side. That is, when the on-gate current Ig1 (Ig11, Ig12) of the insulated gate type power semiconductor element is substantially the same as the current during the healthy state and the off-gate current Ig2 (Ig21, Ig22) is smaller than the current during the healthy state, the insulated gate type It is detected as a disconnection failure on the collector side of the power semiconductor element.

図７は絶縁ゲート形パワー半導体素子のエミッタ側の断線故障時であるときのオンゲート電流及びオフゲート電流の説明図であり、図７（ａ）はオンゲート電流Ｉｇ１１、Ｉｇ１２の説明図、図７（ｂ）はオフゲート電流Ｉｇ２１、Ｉｇ２２の説明図である。   FIG. 7 is an explanatory diagram of on-gate current and off-gate current at the time of disconnection failure on the emitter side of an insulated gate power semiconductor element, FIG. 7 (a) is an explanatory diagram of on-gate currents Ig11 and Ig12, and FIG. ) Is an explanatory diagram of the off-gate currents Ig21 and Ig22.

図７（ａ）に示すように、絶縁ゲート形パワー半導体素子のエミッタ側のＦ２点で断線故障しているとすると、コレクタＣとエミッタＥとの間は断線状態となり、ゲートＧとエミッタＥとの間も断線状態となる。従って、ゲートＧとエミッタＥとの間にゲート電圧Ｖｇｅが印加されても、オンゲート電流Ｉｇ１１、Ｉｇ１２はほとんど流れない。完全に断線している場合にはオンゲート電流Ｉｇ１１、Ｉｇ１２は零である。オフゲート電流Ｉｇ２１、Ｉｇ２２も同様に、図７（ｂ）に示すように、ほとんど流れなくなる。   As shown in FIG. 7 (a), if a disconnection failure occurs at point F2 on the emitter side of the insulated gate type power semiconductor element, the collector C and the emitter E are disconnected, and the gate G and the emitter E During this period, the wire is disconnected. Therefore, even when the gate voltage Vge is applied between the gate G and the emitter E, the on-gate currents Ig11 and Ig12 hardly flow. In the case of complete disconnection, the on-gate currents Ig11 and Ig12 are zero. Similarly, as shown in FIG. 7B, the off-gate currents Ig21 and Ig22 hardly flow.

表３は半導体素子がエミッタ側で断線故障した場合のゲート電流の特性を示す表である。すなわち、エミッタ側での断線故障時と健全時とのオンゲート電流Ｉｇ１１、Ｉｇ１２、オフゲート電流Ｉｇ２１、Ｉｇ２２の比及び検出の可否を示す。

Figure 2007202237
Table 3 is a table showing the characteristics of the gate current when the semiconductor element breaks down on the emitter side. That is, the ratio of the on-gate currents Ig11 and Ig12 and the off-gate currents Ig21 and Ig22 between the disconnection failure and the sound state on the emitter side and the possibility of detection are shown.
Figure 2007202237

断線故障検出部１６は、このエミッタ側の断線故障時の状態を検出する。すなわち、半導体素子のオンゲート電流Ｉｇ１（Ｉｇ１１、Ｉｇ１２）及びオフゲート電流Ｉｇ２（Ｉｇ２１、Ｉｇ２２）が健全時の電流より小さいときは半導体素子のエミッタ側の断線故障として検出する。   The disconnection failure detection unit 16 detects the state at the time of the disconnection failure on the emitter side. That is, when the on-gate current Ig1 (Ig11, Ig12) and the off-gate current Ig2 (Ig21, Ig22) of the semiconductor element are smaller than the current at the normal state, it is detected as a disconnection failure on the emitter side of the semiconductor element.

このように、断線故障検出部１６は、ゲート駆動回路１３よりゲートＧへ流れ込むオンゲート電流は変化しないが、ゲートＧよりゲート駆動回路１３へ流れ込むオフゲート電流が減少することを検出したときは、コレクタ側の断線故障であると判断し、ゲート駆動回路１３よりゲートＧへ流れ込むオンゲート電流が減少し、ゲートＧよりゲート駆動回路１３へ流れ込むオフゲート電流がほぼ零になったことを検出したときは、エミッタ側の断線故障であると判断する。   As described above, the disconnection failure detection unit 16 does not change the on-gate current flowing from the gate drive circuit 13 to the gate G, but detects that the off-gate current flowing from the gate G to the gate drive circuit 13 decreases. When it is determined that the on-gate current flowing from the gate drive circuit 13 to the gate G decreases and the off-gate current flowing from the gate G to the gate drive circuit 13 becomes almost zero, It is determined that this is a disconnection failure.

また、コレクタ側の断線故障か、エミッタ側の断線故障化の識別が必要ないときは、オフゲート電流が健全時の電流より小さいときは絶縁ゲート形パワー半導体素子の断線故障として検出することも可能である。   In addition, when it is not necessary to identify the collector-side disconnection failure or the emitter-side disconnection failure, it is also possible to detect the disconnection failure of the insulated gate type power semiconductor element when the off-gate current is smaller than the normal current. is there.

本発明の実施の形態によれば、絶縁ゲート形パワー半導体素子の主回路（コレクタ−エミッタ間）の電流を検出することなく、ゲートＧに流れるゲート電流を健全時の電流と比較して短絡故障や断線故障を検出できる。また、絶縁ゲート形パワー半導体素子の短絡故障だけでなく断線故障も検出でき、しかも断線故障の場合はコレクタ側の断線故障かエミッタ側の断線故障かも判断できるので、絶縁ゲート形パワー半導体素子の故障検出の信頼性を向上できる。   According to the embodiment of the present invention, the gate current flowing through the gate G is compared with the current in the normal state without detecting the current in the main circuit (between the collector and the emitter) of the insulated gate type power semiconductor element, and thus the short circuit failure. And disconnection failure can be detected. In addition to detecting short circuit failures in insulated gate type power semiconductor elements, disconnection faults can also be detected, and in the case of disconnection faults, it is possible to determine whether a collector side disconnection fault or an emitter side disconnection fault has occurred. The reliability of detection can be improved.

また、故障検出装置１４は故障の半導体素子を検出すると、当該故障素子のスイッチをオフにして、故障の半導体素子をゲート駆動回路から切り離す。ゲート電源自給方式の場合、半導体素子に短絡故障が発生するとゲート電源電圧の低下を招くが、短絡故障の半導体素子をゲート駆動回路から切り離すのでゲート電源電圧の低下を防止できる。従って、健全な半導体素子が不完全なオンオフを繰り返すことによる素子故障を回避できる。また、ゲート電源を確保できることにより、健全な半導体素子は通常のオンオフができ、短絡故障の半導体素子に集中して流れる電流防止により運転継続が可能となる。また、断線故障の半導体素子に対しては不要なゲートへのゲート電流流入を防止できる。すなわち、半導体素子を並列接続した場合の短絡故障や断線故障を検出し、その故障半導体素子をゲート駆動回路から切り離して継続運転継続することが可能となるので、電力変換器の信頼性を向上できる。   Further, when the failure detection device 14 detects a failed semiconductor element, the failure detection device 14 turns off the switch of the failed element and separates the failed semiconductor element from the gate drive circuit. In the case of the gate power supply self-sufficiency method, when a short circuit failure occurs in the semiconductor element, the gate power supply voltage is lowered. However, since the semiconductor element having the short circuit failure is separated from the gate drive circuit, the gate power supply voltage can be prevented from lowering. Therefore, it is possible to avoid an element failure due to repeated incomplete ON / OFF of a healthy semiconductor element. In addition, since the gate power supply can be secured, a healthy semiconductor element can be normally turned on and off, and the operation can be continued by preventing a current flowing in a concentrated manner in the semiconductor element having a short circuit failure. Further, unnecessary gate current inflow to the gate can be prevented for a semiconductor element having a disconnection failure. That is, it is possible to detect a short-circuit failure or a disconnection failure when semiconductor elements are connected in parallel, and to disconnect the failed semiconductor element from the gate drive circuit and continue the operation, thereby improving the reliability of the power converter. .

本発明の実施の形態に係わる電力変換部の構成図。The lineblock diagram of the power converter concerning an embodiment of the invention. 本発明の実施の形態に係わる半導体素子の故障検出装置のブロック構成図。The block block diagram of the failure detection apparatus of the semiconductor element concerning embodiment of this invention. 絶縁ゲート形パワー半導体素子のオンゲート電流及びオフゲート電流の説明図。Explanatory drawing of the on-gate current and off-gate current of an insulated gate power semiconductor element. 絶縁ゲート形パワー半導体素子が健全時のオンゲート電流及びオフゲート電流の説明図。Explanatory drawing of the on-gate current and off-gate current when an insulated gate power semiconductor element is healthy. 絶縁ゲート形パワー半導体素子が短絡故障時であるときのオンゲート電流及びオフゲート電流の説明図。Explanatory drawing of an on-gate current and an off-gate current when an insulated gate power semiconductor element is at the time of a short circuit failure. 絶縁ゲート形パワー半導体素子のコレクタ側の断線故障時であるときのオンゲート電流及びオフゲート電流の説明図。Explanatory drawing of an on-gate current and an off-gate current at the time of the disconnection failure on the collector side of an insulated gate power semiconductor element. 絶縁ゲート形パワー半導体素子のエミッタ側の断線故障時であるときのオンゲート電流及びオフゲート電流の説明図。Explanatory drawing of an on-gate current and an off-gate current at the time of the disconnection failure on the emitter side of an insulated gate type power semiconductor element.

符号の説明Explanation of symbols

１１…並列素子群、１２…半導体素子、１３…ゲート駆動回路、１４…故障検出装置、１５…電流検出部、１６…断線故障検出部、１７…短絡故障検出部
DESCRIPTION OF SYMBOLS 11 ... Parallel element group, 12 ... Semiconductor element, 13 ... Gate drive circuit, 14 ... Fault detection apparatus, 15 ... Current detection part, 16 ... Disconnection fault detection part, 17 ... Short-circuit fault detection part

Claims (2)

複数個の半導体素子を並列接続された電力変換器において、
前記電力変換器を構成する各々の半導体素子のゲートにゲート信号を出力するゲート駆動回路と、
前記半導体素子のゲートと前記ゲート駆動回路との間に設けられたスイッチと、
前記各々の半導体素子の故障を検出したときは故障した半導体素子のゲートとゲート駆動回路との間のスイッチをオフする故障検出装置とを備えたことを特徴とする電力変換器。 In a power converter in which a plurality of semiconductor elements are connected in parallel,
A gate driving circuit for outputting a gate signal to the gate of each semiconductor element constituting the power converter;
A switch provided between the gate of the semiconductor element and the gate driving circuit;
A power converter comprising: a failure detection device that turns off a switch between a gate of a failed semiconductor element and a gate drive circuit when a failure of each of the semiconductor elements is detected. 複数個の半導体素子を並列接続して形成された並列素子群を多段に直列接続して構成された電力変換器の制御方法において、
前記半導体素子の故障を検出し、
故障した半導体素子のゲートとゲート駆動回路との間に設けられたスイッチをオフし、
故障した半導体素子に並列接続された半導体素子にオンのゲート信号を出し続けることを特徴とする電力変換器の制御方法。
In a method for controlling a power converter configured by connecting a plurality of semiconductor elements connected in parallel to each other in parallel in a multistage series connection,
Detecting a failure of the semiconductor element;
Turn off the switch provided between the gate of the failed semiconductor element and the gate drive circuit,
A control method for a power converter, characterized in that an on-gate signal is continuously output to a semiconductor element connected in parallel to a failed semiconductor element.
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Publication number Priority date Publication date Assignee Title
JP2009100512A (en) * 2007-10-15 2009-05-07 Sharp Corp Dc power supply unit
JP2012055125A (en) * 2010-09-03 2012-03-15 Fuji Electric Co Ltd Protection circuit for power conversion device
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JP2012186937A (en) * 2011-03-07 2012-09-27 Denso Corp Circuit for driving switching element
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EP3076549A4 (en) * 2013-11-26 2017-01-04 Sanken Electric Co., Ltd. Gate drive circuit and intelligent power module
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