JP2007184315A - Resin-sealed power semiconductor module - Google Patents

Resin-sealed power semiconductor module Download PDF

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JP2007184315A
JP2007184315A JP2006000018A JP2006000018A JP2007184315A JP 2007184315 A JP2007184315 A JP 2007184315A JP 2006000018 A JP2006000018 A JP 2006000018A JP 2006000018 A JP2006000018 A JP 2006000018A JP 2007184315 A JP2007184315 A JP 2007184315A
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power semiconductor
sealing
circuit pattern
semiconductor module
insulating substrate
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JP4569473B2 (en
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Akihiro Tanba
昭浩 丹波
Kazuhiro Suzuki
和弘 鈴木
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Hitachi Ltd
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Hitachi Ltd
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain an epoxy resin sealed IGBT module in which miniaturization, high output, high reliability, and long lifetime are attained. <P>SOLUTION: In the power semiconductor module, a ceramics substrate, to which an Si chip is bonded, is soldered to a copper base, two rows or more of trench are formed in the surface of the copper base around the ceramics substrate, the entire region to be sealed is coated uniformly with polyamide resin with a thickness of 10 μm or smaller and then transfer-molding of epoxy resin is carried out. Furthermore, connectors employed are all female connectors and are exposed only to the upper surface of the sealing region, only the inside of the upper surface of copper base are made to serve as the sealing region, and a plurality of attaching holes are provided in the copper base on the outside of the sealing region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パワー半導体モジュール、特に、車載用途等の信頼性が高く、寿命が長いＩＧＢＴモジュールの構造に関する。   The present invention relates to a power semiconductor module, and more particularly to a structure of an IGBT module having a high reliability and a long life for in-vehicle applications.

定格電流が百アンペア程度以上の大容量ＩＧＢＴモジュール等、大容量パワー半導体モジュールの封止形態は、パワー半導体チップ、絶縁基板、金属ベース他が接着され内蔵されている樹脂ケース中を、シリコーンゲル等のソフトレジンで封止する構造が一般的である。これは、各種異種部材が接合されているため、歪や、応力が内在した構造体を、剛性の高い樹脂で封止すると、封止時に新たに大きな応力を発生させ、内蔵部材を破壊させる懸念があり、構造的に成立しにくいためである。   Large capacity power semiconductor modules, such as large capacity IGBT modules with rated currents of about 100 amps or higher, are sealed in a resin case in which a power semiconductor chip, an insulating substrate, a metal base, etc. are bonded. A structure sealed with a soft resin is generally used. This is because various dissimilar members are joined, and if a structure containing strain or stress is sealed with a highly rigid resin, a large stress is newly generated during sealing, and the built-in member may be destroyed. This is because it is difficult to establish structurally.

一方、定格電流数十アンペア以下の低容量パワー半導体モジュールでは、非絶縁性ディスクリートパッケージに代表されるように、構造が比較的単純で、かつ小型であるため、ハードレジンであるエポキシ樹脂で封止しても、上述の大容量パワー半導体モジュールで生じた応力による問題が、発生しづらい。そのために、これらの低容量パワー半導体モジュールでは、エポキシ樹脂でトランスファモールドする構造が、採用されている。このようにトランスファモールドされたパッケージでは、内蔵された部材間の接合応力が分散・低減されることが知られている。   On the other hand, low-capacity power semiconductor modules with a rated current of several tens of amperes or less, as represented by non-insulating discrete packages, have a relatively simple structure and are small, so they are sealed with hard resin epoxy resin. Even so, problems due to stress generated in the above-described large-capacity power semiconductor module are unlikely to occur. Therefore, in these low-capacity power semiconductor modules, a structure in which transfer molding is performed with an epoxy resin is employed. In such a transfer molded package, it is known that the joint stress between the built-in members is dispersed and reduced.

特許文献１には、図１２に断面模式図を示すような、トランスファモールドを大容量パワー半導体モジュールに適用したものが開示されている。特許文献１では、パッケージ１２００の絶縁を、大容量品では一般的なセラミックス基板ではなく、応力発生の少ない柔らかい絶縁樹脂シート１２０４で実現し、熱伝導率が低い絶縁樹脂シート１２０４の欠点を解消するために、厚く、大きな銅製のヒートスプレッダ１２０６を採用し、この上にパワー半導体チップ１２０２をはんだ１２０３で接着し、熱を大きく拡散させて伝熱面積を大きくして熱抵抗の低下を図っている。線膨張係数が大きく異なるＳｉと銅を接着する場合、接着はんだ層の応力が大きくなり、亀裂が発生がするが、特許文献１では全体をエポキシ樹脂１２０１で封止して、はんだ１２０３の応力・歪を分散、低減し、温度サイクルによるクラック防止を図っている。   Patent Document 1 discloses a transfer mold applied to a large-capacity power semiconductor module as shown in a schematic cross-sectional view in FIG. In Patent Document 1, the insulation of the package 1200 is realized by a soft insulating resin sheet 1204 with less stress generation rather than a general ceramic substrate in a large-capacity product, and the drawbacks of the insulating resin sheet 1204 with low thermal conductivity are eliminated. Therefore, a thick and large copper heat spreader 1206 is employed, and a power semiconductor chip 1202 is bonded thereto with solder 1203, and heat is diffused greatly to increase a heat transfer area to reduce thermal resistance. When bonding Si and copper having greatly different linear expansion coefficients, the stress of the bonded solder layer increases and cracks occur. However, in Patent Document 1, the whole is sealed with an epoxy resin 1201, and the stress of the solder 1203 Strain is dispersed and reduced to prevent cracking due to temperature cycling.

特許文献２には、パワー半導体モジュールの一箇所で良好な熱的接触を実現するために、封止樹脂にボルト用貫通孔を備え、特別な取り付け治具を用いるものが開示されている。   Japanese Patent Application Laid-Open No. H10-228561 discloses a device in which a sealing resin is provided with a through-hole for a bolt and a special mounting jig is used in order to achieve good thermal contact at one location of the power semiconductor module.

エポキシ樹脂で封止するパッケージは、上述したように、内蔵物の応力が分散・低減することが特徴である。しかしながら、この効果は、内蔵物と封止エポキシ樹脂の接着性が良好であって初めて達成される。しかしながら、エポキシ樹脂の接着性は十分ではないのが現状である。そこで、特許文献３では、エポキシ樹脂と内蔵物の界面にポリアミド樹脂をコーティングして接着性を確保している。   As described above, the package sealed with the epoxy resin is characterized in that the stress of the built-in material is dispersed and reduced. However, this effect is achieved only when the adhesion between the built-in material and the sealing epoxy resin is good. However, at present, the adhesiveness of the epoxy resin is not sufficient. Therefore, in Patent Document 3, a polyamide resin is coated on the interface between the epoxy resin and the built-in material to ensure adhesion.

特開２００４−１６５２８１号公報（図２と、（００５６）段落から（００６０）段落の記載。）JP 2004-165281 A (Description of FIG. 2 and paragraphs (0056) to (0060)) 特開２００４−８７５５２号公報（図１、図２と、（０００８）段落から（００１０）段落の記載。）JP 2004-87552 A (FIGS. 1 and 2 and descriptions from paragraphs (0008) to (0010)). 特開２００３−１２４４０６号公報（図１と、（００２４）段落から（００２５）段落の記載。）JP 2003-124406 A (Description of FIG. 1 and paragraphs (0024) to (0025))

前記特許文献１に開示のパワーモジュールでは、パッケージの放熱器への取り付けが困難である。また、特許文献２に開示のパワーモジュールでは取り付けに特別な冶具が必要になるので、工数を含め実装コストが増大する。また、特許文献２の構造では、中央の取り付けボルト用貫通穴はパッケージに穴を穿って作られており、ボルトが封止樹脂を締結するので、樹脂のクリープによる締結力の経年劣化の懸念がある。   In the power module disclosed in Patent Document 1, it is difficult to attach the package to a heat radiator. Moreover, since the power module disclosed in Patent Document 2 requires a special jig for mounting, the mounting cost including man-hours increases. Moreover, in the structure of Patent Document 2, the through hole for the mounting bolt in the center is formed by making a hole in the package, and the bolt fastens the sealing resin, so there is a concern that the fastening force may deteriorate over time due to resin creep. is there.

また、特許文献３に開示のパワーモジュールでは、コーティング樹脂がエポキシ樹脂に比べて柔らかいために、接着性が改善される一方、エポキシ樹脂の応力分散・低減効果が減少する可能性がある。   Further, in the power module disclosed in Patent Document 3, since the coating resin is softer than the epoxy resin, the adhesiveness is improved, while the stress dispersion / reduction effect of the epoxy resin may be reduced.

本発明の目的は、パワー半導体素子をトランスファモールド等によりエポキシ封止するモジュールで、モジュールのサイズを大型にすることなく、放熱ベースへの固定や配線部材の取り付けが容易で、内蔵部材とエポキシ樹脂の接着性を、エポキシ封止による部材の応力分散・低減を損なうことなく実現したパワー半導体モジュールを提供することである。   An object of the present invention is a module in which a power semiconductor element is epoxy-sealed by a transfer mold or the like, and can be easily fixed to a heat radiating base or attached to a wiring member without increasing the size of the module. It is to provide a power semiconductor module that realizes the adhesive property without impairing the stress dispersion / reduction of the member by epoxy sealing.

本発明は、モジュールサイズを増大させること無く、放熱板（金属ベース）のボルト締めによるモジュール取り付けを実現するため、エポキシ封止領域を金属ベースの内側とし、封止領域外側の金属ベース領域をモジュール取り付け領域としている。本構造は、封止領域の最外周に、溝、突起等の封止樹脂かしめ手段を設けるとともに、封止樹脂と内蔵部材の接着層となる、エポキシ樹脂よりも硬度の低いコーティング層を内蔵部材に設けることで、封止エポキシ樹脂と部材との接着性を強固にして実現される。また、従来技術のエポキシ封止パッケージでは、パッケージの側面から出していた端子を、エポキシ樹脂封止領域の上面に露出させることで、上記、金属ベース内側の封止領域を実現し、モジュールの大幅な小型化を実現している。さらに、本構造は、必要に応じ、端子の強度を低減させ、内蔵物に過度な応力を発生させないようにして実現している。   In the present invention, in order to realize module mounting by bolting a heat sink (metal base) without increasing the module size, the epoxy sealing area is inside the metal base, and the metal base area outside the sealing area is the module. The mounting area. In this structure, sealing resin caulking means such as grooves and protrusions are provided on the outermost periphery of the sealing region, and a coating layer having a hardness lower than that of epoxy resin, which serves as an adhesive layer between the sealing resin and the built-in member, is provided. By providing in, the adhesiveness of a sealing epoxy resin and a member is strengthened and implement | achieved. Moreover, in the epoxy sealing package of the prior art, the above-mentioned sealing region inside the metal base is realized by exposing the terminal that has been taken out from the side of the package to the upper surface of the epoxy resin sealing region. Realized miniaturization. Furthermore, this structure is realized by reducing the strength of the terminals as needed and not generating excessive stress in the built-in objects.

本発明のパワー半導体モジュールは放熱器との良好な熱的接触を実現した。さらに、本発明のパワー半導体モジュールは、エポキシ樹脂の内蔵物歪分散・低減効果を損なうことなく、モジュールの信頼性・寿命を大幅に向上させることができる。   The power semiconductor module of the present invention achieves good thermal contact with the radiator. Furthermore, the power semiconductor module of the present invention can greatly improve the reliability and life of the module without impairing the effect of dispersing and reducing the internal resin strain of the epoxy resin.

本発明のＩＧＢＴモジュールは、従来技術のシリコーンゲル封止に代えて、エポキシ樹脂でトランスファモールド封止し、長寿命と、高い信頼性とを実現できる構造とした。本発明のエポキシ樹脂でトランスファモールド封止したＩＧＢＴモジュールは、封止樹脂と部材の接着性改善を、部材の応力分散・低減効果を損なわないように実現し、かつ、モジュールサイズを大型化させずに、信頼性が高いモジュール取り付け手段である金属ベースをボルト締結する取り付けとした。以下、本発明の詳細を図面を用いながら説明する。   The IGBT module of the present invention has a structure capable of realizing a long life and high reliability by performing transfer mold sealing with an epoxy resin in place of the conventional silicone gel sealing. The IGBT module encapsulated in the transfer mold with the epoxy resin of the present invention realizes an improvement in the adhesion between the sealing resin and the member without impairing the stress dispersion / reduction effect of the member, and without increasing the module size. In addition, a metal base, which is a highly reliable module attachment means, is attached by bolt fastening. The details of the present invention will be described below with reference to the drawings.

図１は、本実施例ＩＧＢＴモジュールの断面摸式図であり、図７は本実施例に使用される放熱ベースである銅ベースの平面模式図、図８は、図７中のモールド樹脂かしめ領域の断面摸式図である。本実施例では、銅ベース１０９が、放熱フィン１１０を裏面に有するフィン付き銅ベースである。すなわち、本実施例のＩＧＢＴモジュールでは、放熱フィン１１０が付いた銅ベース１０９に直接冷却水が当てられることによりモジュールが冷却される。図１１は、本実施例のモジュール長手方向の断面構造模式図である。   FIG. 1 is a schematic cross-sectional view of the IGBT module of this embodiment, FIG. 7 is a schematic plan view of a copper base as a heat dissipation base used in this embodiment, and FIG. 8 is a mold resin caulking region in FIG. FIG. In this embodiment, the copper base 109 is a finned copper base having the radiation fins 110 on the back surface. That is, in the IGBT module of this embodiment, the module is cooled by directly applying cooling water to the copper base 109 with the heat radiation fins 110 attached thereto. FIG. 11 is a schematic cross-sectional view of the module longitudinal direction of the present embodiment.

本実施例のＩＧＢＴモジュール１００の定格電圧／電流は、各々６００Ｖ／４００Ａである。ＩＧＢＴチップ１０４とこのＩＧＢＴチップ１０４の主電極に逆並列に接続したFree Wheeling Diodeチップ（ＦＷＤチップ１０５と以下略す。）は、シリコンの各２チップが並列で一枚の銅貼りの回路パターンが付いたＡｌＮ基板１０７に、はんだ１０６で接着されている。図１ではＩＧＢＴ、ＦＷＤ各々１チップの断面が示されている。銅貼りの回路パターンが付いたＡｌＮ基板１０７の部材厚さは、以下の通りである。表面回路パタン厚さ０.３mm、裏面銅板厚さ０.２mm、ＡｌＮ厚さ０.６３５mm である。ＩＧＢＴチップ１０４、ＦＷＤチップ１０５の厚さは０.３５mmであり、はんだ１０６の厚さは０.１mmである。このはんだ１０６は、融点３００℃程度の高融点はんだである。   The rated voltage / current of the IGBT module 100 of the present embodiment is 600V / 400A, respectively. The IGBT chip 104 and a Free Wheeling Diode chip (hereinafter abbreviated as FWD chip 105) connected in reverse parallel to the main electrode of the IGBT chip 104 are each provided with a circuit pattern in which two silicon chips are arranged in parallel and one piece of copper is attached. The AlN substrate 107 is bonded with solder 106. FIG. 1 shows a cross section of one chip each of IGBT and FWD. The member thickness of the AlN substrate 107 with the circuit pattern attached with copper is as follows. The surface circuit pattern thickness is 0.3 mm, the back surface copper plate thickness is 0.2 mm, and the AlN thickness is 0.635 mm. The thickness of the IGBT chip 104 and the FWD chip 105 is 0.35 mm, and the thickness of the solder 106 is 0.1 mm. This solder 106 is a high melting point solder having a melting point of about 300 ° C.

パワー半導体チップが搭載されたＡｌＮ基板１０７は、融点１８０℃程度の低融点のはんだ１０８で、銅ベース１０９にはんだ接着されている。このはんだ１０８の厚さは０.２mmである。銅ベース１０９の材質は無酸素銅であり、平板部厚さが３mmである。放熱フィン１１０の高さ、幅、間隔は各々８mm、１mm、１.５mm である。これらの寸法は、冷却水を通流した際の圧力損失を可能な限り低減し、かつ、冷却能力向上に配慮した構造となっている。銅貼りのＡｌＮ基板１０７の銅板、及び銅ベース１０９の表面は、いずれもニッケルメッキ処理されている。このニッケルメッキ層の厚さは、６μｍ程度であり、はんだ１０６、１０８による接着の信頼性を考慮してニッケルメッキ処理を実施している。銅ベース１０９には貫通穴１１２が設けられ、この貫通穴１１２にボルトなどを通して、ＩＧＢＴモジュール１００を図示していないヒートシンクへ取り付ける。   The AlN substrate 107 on which the power semiconductor chip is mounted is soldered to the copper base 109 with a low melting point solder 108 having a melting point of about 180 ° C. The thickness of the solder 108 is 0.2 mm. The material of the copper base 109 is oxygen-free copper, and the thickness of the flat plate portion is 3 mm. The height, width, and spacing of the radiating fins 110 are 8 mm, 1 mm, and 1.5 mm, respectively. These dimensions have a structure in which the pressure loss when cooling water is passed is reduced as much as possible and the cooling capacity is improved. The copper plate of the AlN substrate 107 attached with copper and the surface of the copper base 109 are both subjected to nickel plating. The thickness of the nickel plating layer is about 6 μm, and the nickel plating process is performed in consideration of the reliability of adhesion by the solders 106 and 108. The copper base 109 is provided with a through hole 112, and a bolt or the like is passed through the through hole 112 to attach the IGBT module 100 to a heat sink (not shown).

本実施例では、Ｍ６ボルトでの締結を想定しており、貫通穴１１２は６.６mmφとしている。Ｓｉパワー半導体チップであるＩＧＢＴチップ１０４と、ＦＷＤチップ１０５とから主端子１０１への電気的接続は、線径４００μｍのＡｌワイヤ１０３で実施され、本Ａｌワイヤ１０３での接続、及び、銅ベース１０９へのＡｌＮ基板１０７へのはんだ接着が完了した構造で、トランスファモールドされる。   In this embodiment, it is assumed that M6 bolts are fastened, and the through hole 112 is 6.6 mmφ. The electrical connection from the IGBT chip 104, which is a Si power semiconductor chip, and the FWD chip 105 to the main terminal 101 is performed by the Al wire 103 having a wire diameter of 400 μm, the connection by the Al wire 103, and the copper base 109. Transfer molding is performed with a structure in which solder bonding to the AlN substrate 107 is completed.

図１の符号１１１が封止樹脂を示し、この領域がトランスファモールドされたエポキシ樹脂の領域である。封止樹脂１１１の高さである封止領域厚さ１１３は、７mmである。この高さは、Ａｌワイヤ１０３が封止樹脂から露出せず、かつ十分な絶縁が確保できるような余裕がある高さにしてある。本実施例に用いたエポキシ樹脂の線膨張係数αは１６ppm 程度で、弾性係数Ｅは、１６ＧＰａ程度である。本実施例のパワーモジュールでは、このような物性にしたので、モジュール底面の反りを０.１mm程度以下にできた。この理由は、封止樹脂１１１であるエポキシ樹脂の線膨張係数αが銅ベースの線膨張係数αとほぼ一致しているためである。   Reference numeral 111 in FIG. 1 indicates a sealing resin, and this region is an epoxy resin region that is transfer-molded. The sealing region thickness 113 which is the height of the sealing resin 111 is 7 mm. This height is high enough to prevent the Al wire 103 from being exposed from the sealing resin and to ensure sufficient insulation. The linear expansion coefficient α of the epoxy resin used in this example is about 16 ppm, and the elastic coefficient E is about 16 GPa. In the power module of the present embodiment, such physical properties were adopted, so that the warp of the module bottom surface could be reduced to about 0.1 mm or less. This is because the linear expansion coefficient α of the epoxy resin that is the sealing resin 111 substantially matches the linear expansion coefficient α of the copper base.

本実施例の特徴は、トランスファモールドした封止樹脂１１１と銅ベース１０９のかしめ用溝１０２、及び、外部接続用の主端子１０１である。まず、かしめ用溝１０２を配置したかしめ領域について、図７と図８を使用して説明する。トランスファモールドは、高圧力下でエポキシ樹脂を注入硬化させるため、大気圧下で樹脂を滴下させた後に硬化させる、いわゆるポッティング法と比べ、接着性が向上すると考えている。しかしながら、ニッケルメッキとエポキシ樹脂の接着性が悪いことが知られている。そこで、本実施例では、ニッケルメッキされた部材である、銅貼りのＡｌＮ基板１０７と銅ベース１０９とエポキシ樹脂との接着性を確保することは極めて重要である。また、ＡｌＮ基板１０７を接着するはんだ１０８は、本実施例のＩＧＢＴモジュール１００の熱疲労耐量を決定する部材であり、はんだ１０８と周囲の樹脂との接着性に対してもっとも配慮しなければならない。そこで、本実施例のＩＧＢＴモジュールでは、封止樹脂１１１であるエポキシ樹脂と銅ベース１０９のかしめ領域のかしめ用溝１０２をＡｌＮ基板１０７の極近傍に配置している。   The features of the present embodiment are a transfer molded sealing resin 111, a caulking groove 102 of a copper base 109, and a main terminal 101 for external connection. First, a caulking region in which the caulking groove 102 is disposed will be described with reference to FIGS. Since the transfer mold injects and cures an epoxy resin under a high pressure, it is considered that the adhesive property is improved as compared with a so-called potting method in which a resin is dropped after being dropped under an atmospheric pressure and then cured. However, it is known that the adhesion between nickel plating and epoxy resin is poor. Therefore, in the present embodiment, it is extremely important to ensure adhesion between the copper-plated AlN substrate 107, the copper base 109, and the epoxy resin, which are nickel-plated members. The solder 108 to which the AlN substrate 107 is bonded is a member that determines the thermal fatigue resistance of the IGBT module 100 of the present embodiment, and the most consideration must be given to the adhesion between the solder 108 and the surrounding resin. Therefore, in the IGBT module of this embodiment, the caulking groove 102 in the caulking region of the epoxy resin as the sealing resin 111 and the copper base 109 is disposed in the very vicinity of the AlN substrate 107.

図７に示すように、２列のかしめ用溝７０１間の突起７０２を、封止樹脂１１１のエポキシ樹脂は成形硬化過程で、自身の収縮により強く圧縮し、かしめる。また、図７中、２０箇所設けられたかしめ用逆テーパ領域７０３は、このかしめ力をより強固にするための領域である。断面を図８に示す。かしめ用逆テーパ領域７０３は、２本の溝を製造した後に、プレスにより、溝の一部をつぶして、図８示したように逆テーパ構造を形成して、封止樹脂の剥離を防止できる構造になっている。本実施例ではこのような構造になっているので、封止領域が銅ベース１０９の内側上面のみにもかかわらず、良好な接着性を確保できる。このため、モジュール取り付けボルト用の貫通穴１１２を封止領域の外側に、モジュールサイズを大きくする事なく配置することが可能となった。   As shown in FIG. 7, the projections 702 between the two rows of caulking grooves 701 are strongly compressed and crimped by the shrinkage of the epoxy resin of the sealing resin 111 during the molding and hardening process. Further, in FIG. 7, the caulking reverse taper regions 703 provided at 20 locations are regions for further strengthening the caulking force. A cross section is shown in FIG. The reverse taper region 703 for caulking can prevent peeling of the sealing resin by manufacturing two grooves and then crushing a part of the groove by pressing to form a reverse taper structure as shown in FIG. It has a structure. Since this embodiment has such a structure, good adhesiveness can be ensured regardless of the sealing region only on the inner upper surface of the copper base 109. For this reason, the through holes 112 for module mounting bolts can be arranged outside the sealing region without increasing the module size.

次に、本実施例の端子構造を説明する。従来技術のトランスファモールドによるモジュール構造は、図１２に示すように、エポキシ樹脂１２０１の側面から主端子１２０７、制御端子１２０８を取り出す形状である。この形状をそのまま本実施例のモジュールに採用すると、銅ベース１０９の外側に主端子や、制御端子が横に張り出し、大型化は避けられない。そこで本実施例では、図１に示すように主端子１０１を銅ブロックとし、ＡｌＮ基板１０７上にはんだ等で接着する構造とした。主端子１０１の銅ブロックの材質は無酸素銅であり、表面は厚さ６μｍ程度のニッケルメッキが形成されている。このような構造とすることで、図示していないが、トランスファモールド成型時に上型で主端子１０１上面を固定する事ができ、封止領域上面に主端子１０１表面を露出させる事ができる。本実施例のような構造では、成型時の金型プレス圧力は、主端子１０１である銅ブロックを介してＡｌＮ基板１０７等の部材に印加されるため、主端子１０１の銅ブロックを予め高温で焼きなまして、降伏応力を５０ＭＰａ程度以下にしておき、金型で押さえた時の部材破損の懸念をなくしている。本実施例の構造で、封止領域上面に露出した主端子１０１と外部配線との接続は、はんだ接着、あるいは、専用の固定治具等を使用する。   Next, the terminal structure of the present embodiment will be described. As shown in FIG. 12, the module structure by the transfer mold of the prior art is a shape which takes out the main terminal 1207 and the control terminal 1208 from the side surface of the epoxy resin 1201. If this shape is used in the module of this embodiment as it is, the main terminals and control terminals project laterally outside the copper base 109, and an increase in size is inevitable. Therefore, in this embodiment, as shown in FIG. 1, the main terminal 101 is made of a copper block, and is bonded to the AlN substrate 107 with solder or the like. The material of the copper block of the main terminal 101 is oxygen-free copper, and the surface is nickel-plated with a thickness of about 6 μm. With such a structure, although not shown, the upper surface of the main terminal 101 can be fixed with an upper mold during transfer molding, and the surface of the main terminal 101 can be exposed on the upper surface of the sealing region. In the structure as in the present embodiment, the mold press pressure at the time of molding is applied to the member such as the AlN substrate 107 via the copper block which is the main terminal 101, so that the copper block of the main terminal 101 is previously heated at a high temperature. Annealing is performed so that the yield stress is set to about 50 MPa or less, and there is no fear of member breakage when pressed by a mold. In the structure of this embodiment, the main terminal 101 exposed on the upper surface of the sealing area and the external wiring are connected by solder bonding or a dedicated fixing jig.

本実施例では、モジュール中の絶縁基板はＡｌＮ基板１０７であったがこれだけには限らず、セラミックスの材質は、アルミナ、ＳｉＮ等であってもよい。特に、高い熱伝導率と高い強度を兼ね備えた銅貼りＳｉＮ基板は、本実施例のパワー半導体モジュールに適したセラミックス基板である。また、本実施例ではＩＧＢＴモジュールの金属ベースとして、一般的な銅ベースを用いたが、軽量化を考慮して、アルミをベース材として使用してもよい。アルミをベース材として使用する場合は、セラミックス基板の材質はアルミナが好ましい。この理由は、アルミとＡｌＮあるいはＳｉＮとでは線膨張係数αの差が大きすぎ、パワーモジュールの製造過程での反りが許容量（例えば０.２mm）を超えたり、あるいは、セラミックス基板に割れを生じる可能性があるためである。そこで、ＡｌＮ、ＳｉＮとくらべて線膨張係数αの大きなアルミナ基板とを用いることで、この不具合を回避できる。この場合、封止エポキシ樹脂の線膨張係数αをアルミと合わせる事が望まれ、封止エポキシ樹脂の線膨張係数αを２３ｐｐｍ程度とすることが望ましい。   In this embodiment, the insulating substrate in the module is the AlN substrate 107. However, the present invention is not limited to this, and the material of the ceramic may be alumina, SiN or the like. In particular, the copper-coated SiN substrate having both high thermal conductivity and high strength is a ceramic substrate suitable for the power semiconductor module of this example. In this embodiment, a general copper base is used as the metal base of the IGBT module. However, aluminum may be used as the base material in consideration of weight reduction. When aluminum is used as the base material, the material of the ceramic substrate is preferably alumina. The reason for this is that the difference in linear expansion coefficient α between aluminum and AlN or SiN is too large, and the warp in the power module manufacturing process exceeds an allowable amount (for example, 0.2 mm), or the ceramic substrate is cracked. This is because there is a possibility. Therefore, this problem can be avoided by using an alumina substrate having a larger linear expansion coefficient α as compared with AlN and SiN. In this case, it is desirable to match the linear expansion coefficient α of the sealing epoxy resin with aluminum, and it is desirable to set the linear expansion coefficient α of the sealing epoxy resin to about 23 ppm.

本実施例のＩＧＢＴモジュールのフィン長手方向構造を図１１に示す。図１１のＩＧＢＴモジュール１１００は、三相モジュールであって、図１１では、ＩＧＢＴチップ、Ａｌワイヤ、はんだ層等を省略し、銅貼りのＡｌＮ基板１１０３、フィン付きの銅ベース１１０１、封止樹脂１１０２を示した。図１１に示すＩＧＢＴモジュールは、１アームを１基板に搭載した構成であり、計６枚のＡｌＮ基板１１０３から構成されている。１相分、即ち２枚のＡｌＮ基板１１０３を１つの封止樹脂１１０２で封止しており、各封止樹脂１１０２毎に、銅ベース１１０１上に樹脂かしめ領域１１０５を設けている。   The fin longitudinal direction structure of the IGBT module of the present embodiment is shown in FIG. The IGBT module 1100 in FIG. 11 is a three-phase module. In FIG. 11, the IGBT chip, Al wire, solder layer, and the like are omitted, an AlN substrate 1103 with copper, a copper base 1101 with fins, and a sealing resin 1102. showed that. The IGBT module shown in FIG. 11 has a configuration in which one arm is mounted on one substrate, and includes a total of six AlN substrates 1103. One phase, that is, two AlN substrates 1103 are sealed with one sealing resin 1102, and a resin caulking region 1105 is provided on the copper base 1101 for each sealing resin 1102.

１枚のＡｌＮ基板１１０３毎に樹脂封止すると、この樹脂かしめ領域１１０５を含め、モジュール全体が大型化してしまう。逆に、例えば全体を一つの封止領域とすると、封止領域が大きすぎて、モールド時の樹脂ボイド、未封止領域発生の懸念がある。また、例えモールドが問題なくできたとしても、封止樹脂と部材界面の熱応力が大きくなり、界面剥離、他の問題が顕在化する恐れがある。放熱フィン１１０４は、１相分ごとに区切られており、銅ベース１１０１の剛性増大を低減し、同時に製造時に、金型で銅ベース１１０１を固定可能とし、封止領域を分割可能としている。   If resin sealing is performed for each AlN substrate 1103, the entire module including the resin caulking region 1105 is enlarged. On the other hand, for example, if the whole is a single sealing region, the sealing region is too large, and there is a concern that resin voids during molding and unsealed regions may occur. Even if the mold can be produced without any problem, the thermal stress at the interface between the sealing resin and the member is increased, and there is a risk that interface peeling and other problems will become apparent. The heat radiating fins 1104 are divided for each phase, and the increase in rigidity of the copper base 1101 is reduced. At the same time, the copper base 1101 can be fixed by a mold during manufacturing, and the sealing region can be divided.

本実施例のパワー半導体モジュールを図２に示す。本実施例は、図２に示すように、実施例１の封止樹脂のかしめ用溝１０２に加えて、封止樹脂の接着手段を追加した。本実施例のＩＧＢＴモジュール２００の定格電圧／電流、内蔵基板構成、銅ベース１０９等は実施例１と同一であり、トランスファモールドに使用したエポキシ樹脂も実施例１と同一である。   The power semiconductor module of this example is shown in FIG. In this example, as shown in FIG. 2, in addition to the sealing resin caulking groove 102 of Example 1, a sealing resin bonding means was added. The rated voltage / current, built-in substrate configuration, copper base 109 and the like of the IGBT module 200 of this embodiment are the same as those of the first embodiment, and the epoxy resin used for the transfer mold is also the same as that of the first embodiment.

本実施例では、封止エポキシ樹脂と部材の接着向上を実現するコーティング層２０１を設けたことが実施例１とは異なる。コーティング層２０１の材質は、ポリアミド樹脂であって、このポリアミド樹脂は、エポキシ樹脂、及び、シリコンチップやアルミボンディングワイヤや銅貼りＡｌＮ基板などの内蔵各部材と良く接着することを確認している。コーティング層２０１の代表物性である線膨張係数αは５０ｐｐｍ、弾性係数Ｅは２.６ＧＰａ程度である。即ち、実施例１に示した封止樹脂１１１の物性と、比べるとコーティング層２０１が大幅に柔らかい事が分かる。エポキシ樹脂封止のメリットは前述したように、硬いエポキシ樹脂で封止して、内蔵物の応力・歪を分散・低減し、長寿命にできることである。従って、本実施例において、接着性を改善するために導入したコーティング層２０１は、単に柔らかいだけではエポキシ樹脂封止応力・歪を分散・低減する効果を損なう懸念がある。   The present embodiment is different from the first embodiment in that a coating layer 201 that realizes improved adhesion between the sealing epoxy resin and the member is provided. The material of the coating layer 201 is a polyamide resin, and it has been confirmed that the polyamide resin adheres well to the epoxy resin and each built-in member such as a silicon chip, an aluminum bonding wire, or a copper-coated AlN substrate. The linear expansion coefficient α, which is a representative physical property of the coating layer 201, is 50 ppm, and the elastic coefficient E is about 2.6 GPa. That is, it can be seen that the coating layer 201 is significantly softer than the physical properties of the sealing resin 111 shown in Example 1. As described above, the advantage of the epoxy resin sealing is that it can be sealed with a hard epoxy resin to disperse / reduce the stress and strain of the built-in material, thereby extending the service life. Therefore, in this embodiment, the coating layer 201 introduced to improve the adhesion may be impaired in the effect of dispersing and reducing the epoxy resin sealing stress / strain if it is merely soft.

そこで、本実施例では、コーティング層２０１の厚さを可能な限り薄くした。コーティング層２０１は接着性も確保するため、できるだけ均一に塗布する必要あるので、その厚さを概略１０μｍとしている。このような厚さに塗布することで、例えば、ＡｌＮ基板１０７に接着するはんだ１０８の層を常温（２０℃）から１２５℃まで昇温した場合に生じる歪は、コーティング層２０１がない場合と同等であることを、応力解析で確認した。即ち、シリコーンゲル封止を、エポキシ樹脂封止に変えることにより、はんだ歪は半減し、この効果は、厚さ１０μｍのコーティング層２０１が存在しても変わらなかった。   Therefore, in this embodiment, the thickness of the coating layer 201 is made as thin as possible. The coating layer 201 needs to be applied as uniformly as possible in order to ensure adhesiveness, so the thickness is approximately 10 μm. By applying to such a thickness, for example, the distortion generated when the temperature of the solder 108 layer bonded to the AlN substrate 107 is raised from room temperature (20 ° C.) to 125 ° C. is the same as when the coating layer 201 is not provided. It was confirmed by stress analysis. That is, by changing the silicone gel sealing to the epoxy resin sealing, the solder strain was reduced by half, and this effect was not changed even when the coating layer 201 having a thickness of 10 μm was present.

一方、コーティング層２０１の厚さが０.１mm（１００μｍ）程度になると、はんだ歪を低減する効果が１／２程度から、３／４程度になった。従って、単にコーティング層２０１を設けただけでは、エポキシ樹脂で封止する歪の低減が、必ずしも十分ではないので、コーティング層２０１の厚さを１０μｍ程度にして塗布することが重要である。本実施例ＩＧＢＴモジュールはコーティング層２０１を備えているので、−４０℃〜室温（２０℃）〜１２５℃〜室温（２０℃）、２時間／サイクルの条件で３０００サイクルの試験を実施しても、界面には剥離が見られなかった。   On the other hand, when the thickness of the coating layer 201 is about 0.1 mm (100 μm), the effect of reducing solder strain is reduced from about 1/2 to about 3/4. Therefore, simply providing the coating layer 201 does not necessarily reduce the strain sealed with the epoxy resin, so it is important to apply the coating layer 201 with a thickness of about 10 μm. Since the IGBT module of this example is provided with the coating layer 201, even if the test of 3000 cycles is performed under the condition of −40 ° C. to room temperature (20 ° C.) to 125 ° C. to room temperature (20 ° C.), 2 hours / cycle. No peeling was observed at the interface.

本実施例のＩＧＢＴモジュールの断面構造の模式図を図３に、外部主配線を接続した断面模式図を図５に示す。本実施例のＩＧＢＴモジュール３００では、ネジ穴が付いた円筒形の主端子３０１に特徴がある。その他の部材構成、寸法、材質は図１に示した実施例１と同じである。主端子３０１は、材質が無酸素銅であり、その表面がニッケルメッキ処理されている。本実施例では主端子３０１に、Ｍ５ボルト用のネジ穴を内部に設けてあり、このネジ穴が封止樹脂３０２の上面に露出している。図５に示すように、ＰＮバスバー５００がＭ５ボルトの取り付けボルト５０１で、出力配線５０２が同じくＭ５ボルトの取り付けボルト５０１で主端子３０１に接続されている。   FIG. 3 shows a schematic diagram of a cross-sectional structure of the IGBT module of this embodiment, and FIG. 5 shows a schematic cross-sectional diagram of the external main wiring connected thereto. The IGBT module 300 of this embodiment is characterized by a cylindrical main terminal 301 with a screw hole. Other member configurations, dimensions, and materials are the same as those of the first embodiment shown in FIG. The main terminal 301 is made of oxygen-free copper and has a nickel-plated surface. In this embodiment, the main terminal 301 is provided with a screw hole for the M5 bolt inside, and this screw hole is exposed on the upper surface of the sealing resin 302. As shown in FIG. 5, the PN bus bar 500 is connected to the main terminal 301 by an M5 bolt mounting bolt 501 and the output wiring 502 is also an M5 bolt mounting bolt 501.

また、外部配線との接触抵抗をできるだけ低減させるために、主端子３０１の外部配線との接触部は、外径１５mmφと、それ以外の接続端子の外径９mmφに比べて大きくなっている。また、部材の破損を防止するために、実施例１、実施例２と同様に主端子３０１を焼鈍してある。さらに、主端子３０１の封止樹脂３０２との接触面は、樹脂との密着を強固にするため、網目型の凹凸（ローレット処理）が設けてある。このようにローレット処理を施したので、この種のボルト締めの標準的な締め付けトルクである、２.４５Ｎ・ｍのトルクを印加しても、封止樹脂３０２から主端子３０１が剥離する等の問題は全く発生しなかった。このように、本実施例のＩＧＢＴモジュールは実装性が優れている。   In order to reduce the contact resistance with the external wiring as much as possible, the contact portion of the main terminal 301 with the external wiring is larger than the outer diameter of 15 mmφ and the outer diameter of other connection terminals of 9 mmφ. Further, in order to prevent the member from being damaged, the main terminal 301 is annealed in the same manner as in the first and second embodiments. Further, the contact surface of the main terminal 301 with the sealing resin 302 is provided with a mesh-type unevenness (knurling treatment) in order to strengthen the adhesion with the resin. Since the knurling process is performed in this way, the main terminal 301 is peeled off from the sealing resin 302 even when a torque of 2.45 N · m, which is a standard tightening torque of this type of bolt tightening, is applied. No problem occurred. Thus, the IGBT module of the present embodiment is excellent in mountability.

本実施例のパワー半導体モジュールの断面構造の模式図を図４に、制御基板を接続した断面模式図を図６に示す。本実施例は、制御端子の接続に特徴がある。図４に示すＩＧＢＴモジュール４００は、ＩＧＢＴチップ４０４のゲートワイヤ４０２が、ボンディングされて回路パタンに接続し、制御端子４０１が回路パタンにはんだ等で接着されている。図４に示す制御端子４０１は、電気的な接触を高い信頼性で実現するメスコネクタになっている。制御端子４０１の上面が封止樹脂４０５に露出されている点は実施例３と同様である。図６は、ＩＧＢＴモジュール４００を制御する制御基板６０１に設けたピンタイプの信号端子６００をＩＧＢＴモジュール４００のメスコネクタになっている制御端子４０１に実装した断面模式図である。図６の信号端子６００のピンは１mm角である。制御基板６０１の固定手段は特に図示していないが、ＩＧＢＴモジュール４００と一体で固定されているので、振動等による接続信頼性の劣化は問題にならない。   FIG. 4 shows a schematic diagram of a cross-sectional structure of the power semiconductor module of this example, and FIG. 6 shows a schematic diagram of a cross-section to which a control board is connected. This embodiment is characterized by connection of control terminals. In the IGBT module 400 shown in FIG. 4, the gate wire 402 of the IGBT chip 404 is bonded and connected to the circuit pattern, and the control terminal 401 is bonded to the circuit pattern with solder or the like. The control terminal 401 shown in FIG. 4 is a female connector that realizes electrical contact with high reliability. The point that the upper surface of the control terminal 401 is exposed to the sealing resin 405 is the same as in the third embodiment. FIG. 6 is a schematic cross-sectional view in which a pin-type signal terminal 600 provided on a control board 601 that controls the IGBT module 400 is mounted on a control terminal 401 that is a female connector of the IGBT module 400. The pin of the signal terminal 600 in FIG. 6 is 1 mm square. The fixing means of the control board 601 is not particularly shown, but since it is fixed integrally with the IGBT module 400, deterioration of connection reliability due to vibration or the like does not pose a problem.

本実施例は、放熱板／セラミックス一体構造を実現した実施例である。本実施例のＩＧＢＴモジュール９００の断面構造の模式図を図９に示す。図９で、符号９０１は回路パタン、９０２はセラミックス層、９０３は銅ベース、９０４は基板、９０５は放熱フィンである。   The present embodiment is an embodiment that realizes a heat sink / ceramic integrated structure. A schematic diagram of a cross-sectional structure of the IGBT module 900 of this embodiment is shown in FIG. In FIG. 9, reference numeral 901 is a circuit pattern, 902 is a ceramic layer, 903 is a copper base, 904 is a substrate, and 905 is a radiation fin.

封止樹脂を従来技術の柔らかいシリコーンゲルから硬いエポキシ樹脂へと替えることは、実施例１や実施例２で説明したように、内蔵部品の歪分散、低減を実現し、長寿命化できる。本実施例では、エポキシ樹脂が硬質樹脂であるという特性そのものを活かした。従来技術で、銅ベースとセラミックス基板との一体構造が実現できなかったのは、銅ベースが通常３mm以上と厚く、ロー付け等の手段で銅ベースにセラミックス基板を接着すると、反りが激しく、最悪の場合、セラミックス基板の破壊をもたらす可能性があるためであった。一方、セラミックス基板を、例えば１mm程度以下と薄くすると、反りは低減し、セラミックス基板の破壊の懸念は低減するが、従来技術の柔らかいシリコーンゲル封止ではモジュールの強度に問題が残るので、モジュールを放熱フィンなどに取り付けることが困難であった。   Replacing the sealing resin from the soft silicone gel of the prior art to the hard epoxy resin can realize the strain dispersion and reduction of the built-in components and extend the life as described in the first and second embodiments. In this example, the characteristic itself that the epoxy resin is a hard resin was utilized. The integrated structure of the copper base and the ceramic substrate could not be realized with the prior art because the copper base is usually thicker than 3mm, and if the ceramic substrate is bonded to the copper base by means such as brazing, the warp is severe and the worst In this case, the ceramic substrate may be destroyed. On the other hand, if the ceramic substrate is thinned to about 1 mm or less, for example, the warpage is reduced and the concern about the destruction of the ceramic substrate is reduced. It was difficult to attach to heat radiating fins.

しかし、本実施例では、硬いエポキシ樹脂で封止して、この問題を解決した。本実施例では銅ベース９０３の厚さは１mm、回路パタン９０１厚さは１.２mmである。セラミックス層９０２の材質はＳｉＮであり、その厚さは０.６mmである。表裏面の銅板厚さは、基板９０４が反らないように配慮して決めた。セラミックスとしてＳｉＮを選択した理由は、ＳｉＮがＡｌＮに比べて、高強度であり、銅ベースとセラミックスとを一体にした基板９０４を、ロー付けで製造する際の応力に耐えることができるためである。本実施例の放熱フィン９０５の形状は、実施例１から実施例４で説明したものと同じである。   However, in this example, this problem was solved by sealing with a hard epoxy resin. In this embodiment, the thickness of the copper base 903 is 1 mm and the thickness of the circuit pattern 901 is 1.2 mm. The material of the ceramic layer 902 is SiN, and its thickness is 0.6 mm. The copper plate thicknesses on the front and back surfaces were determined in consideration of the substrate 904 not warping. The reason for selecting SiN as the ceramic is that SiN has higher strength than AlN, and can withstand the stress when brazing the substrate 904 in which the copper base and the ceramic are integrated. . The shape of the radiating fin 905 of the present embodiment is the same as that described in the first to fourth embodiments.

本実施例のモジュールの場合、ＩＧＢＴチップ１０４、ＦＷＤチップ１０５からの発熱が、グリースを介して放熱器に銅ベースを固着したモジュールの場合のように、銅ベース中で横方向への熱が広がるのではなく、銅ベースの厚さ方向に熱が流れる。従って、本実施例のパワーモジュールのような薄い銅ベース９０３では、熱が多く流れて来る放熱フィン９０５側を、直接水冷する直接水冷型モジュール構造が適している。本実施例のＩＧＢＴモジュール９００の寿命を支配する部分は、Ａｌワイヤ１０３の接合部、及びはんだ１０６の接合部のみである。本実施例のＩＧＢＴモジュールでは、エポキシ樹脂によって歪を分散しているので、飛躍的に長い寿命を実現できる。   In the case of the module of the present embodiment, the heat generated from the IGBT chip 104 and the FWD chip 105 spreads in the lateral direction in the copper base as in the case of the module in which the copper base is fixed to the radiator via grease. Instead, heat flows in the thickness direction of the copper base. Therefore, in the thin copper base 903 like the power module of the present embodiment, a direct water cooling type module structure in which the heat radiation fin 905 side where a lot of heat flows is directly water cooled is suitable. The only part that dominates the life of the IGBT module 900 of this embodiment is the joint part of the Al wire 103 and the joint part of the solder 106. In the IGBT module of the present embodiment, since the strain is dispersed by the epoxy resin, a significantly long life can be realized.

本実施例のＩＧＢＴモジュール１０００の断面構造を図１０に模式図で示す。本実施例では、端子を樹脂でモールドした主端子ブロック１００１と、制御端子ブロック１００４とを備えている。これらの端子ブロックは、銅ベース１００５上に固着され、封止部材と一緒にトランスファモールドされる。封止される際、封止樹脂１０１０上面に露出され、外部配線と接続される点は、実施例１から実施例５と同様である。また、封止樹脂と銅ベースとのかしめ領域１００９は、図１０に示すように、端子ブロック近傍の外側に配置される。端子をモールドする樹脂は、ＰＰＳ樹脂（ポリフェニレンスルフェート樹脂）である。主端子ブロック１００１と、制御端子ブロック１００４とには、Ａｌワイヤ１００２、１００３の接続用パッドが露出しており、Ａｌワイヤ１００２、１００３によって内部回路と接続される。主端子ブロック１００１は配線をボルト接続するためのナット１００７と、ボルト逃げ用空隙１００８を有しており、制御端子ブロック１００４の制御ピン接続部の形状は、実施例４で説明した制御端子４０１と同一である。本実施例のＩＧＢＴモジュールでは、以上説明した構造で、ＡｌＮ基板１００６の大きさを小さくでき、はんだ１０１１の寿命を長くできるとともに、モジュールのコストも低くできる。   A cross-sectional structure of the IGBT module 1000 of this embodiment is schematically shown in FIG. In this embodiment, a main terminal block 1001 in which terminals are molded with resin and a control terminal block 1004 are provided. These terminal blocks are fixed on the copper base 1005 and transfer molded together with the sealing member. When sealed, it is exposed to the top surface of the sealing resin 1010 and connected to external wiring, as in the first to fifth embodiments. Further, the caulking region 1009 between the sealing resin and the copper base is arranged outside the vicinity of the terminal block as shown in FIG. The resin for molding the terminal is PPS resin (polyphenylene sulfate resin). In the main terminal block 1001 and the control terminal block 1004, connection pads for Al wires 1002 and 1003 are exposed, and are connected to the internal circuit by the Al wires 1002 and 1003. The main terminal block 1001 has a nut 1007 for connecting the wiring with bolts and a bolt escape clearance 1008. The shape of the control pin connection portion of the control terminal block 1004 is the same as that of the control terminal 401 described in the fourth embodiment. Are the same. In the IGBT module of this embodiment, with the structure described above, the size of the AlN substrate 1006 can be reduced, the life of the solder 1011 can be increased, and the cost of the module can be reduced.

実施例１のパワー半導体モジュールの断面模式図である。1 is a schematic cross-sectional view of a power semiconductor module of Example 1. FIG. 実施例２のパワー半導体モジュールの断面模式図である。6 is a schematic cross-sectional view of a power semiconductor module of Example 2. FIG. 実施例３のパワー半導体モジュールの断面模式図である。6 is a schematic cross-sectional view of a power semiconductor module of Example 3. FIG. 実施例４のパワー半導体モジュールの一部断面の模式図である。It is a schematic diagram of a partial cross section of the power semiconductor module of Example 4. 実施例３のパワー半導体モジュールに外部配線を実装した説明図である。It is explanatory drawing which mounted the external wiring in the power semiconductor module of Example 3. FIG. 実施例４のパワー半導体モジュールに制御基板を接続した説明図である。It is explanatory drawing which connected the control board to the power semiconductor module of Example 4. FIG. 実施例１のパワー半導体モジュールの金属ベースの平面模式図である。3 is a schematic plan view of a metal base of the power semiconductor module of Example 1. FIG. 図７のかしめ領域の部分拡大図である。It is the elements on larger scale of the crimping area | region of FIG. 実施例５のパワー半導体モジュールの断面模式図である。10 is a schematic cross-sectional view of a power semiconductor module of Example 5. FIG. 実施例６のパワー半導体モジュールの断面模式図である。10 is a schematic cross-sectional view of a power semiconductor module of Example 6. FIG. 実施例１のパワー半導体モジュールのフィン長手方向の断面模式図である。It is a cross-sectional schematic diagram of the fin longitudinal direction of the power semiconductor module of Example 1. FIG. 従来技術のエポキシ樹脂封止型ＩＧＢＴモジュールの断面構造模式図である。It is a cross-sectional structure schematic diagram of the epoxy resin sealing type IGBT module of a prior art.

符号の説明Explanation of symbols

１００、２００、３００、４００、９００、１０００、１１００…ＩＧＢＴモジュール、１０１、３０１、１２０７…主端子、１０２、７０１…かしめ用溝、１０３、１００２、１００３、１２０９…Ａｌワイヤ、１０４、４０４…ＩＧＢＴチップ、１０５…ＦＷＤチップ、１０６、１０８、１０１１、１２０３…はんだ、１０７、１００６、１１０３…ＡｌＮ基板、１０９、９０３、１００５、１１０１…銅ベース、１１０、９０５、１１０４…放熱フィン、１１１、３０２、４０５、１０１０、１１０２…封止樹脂、１１２…貫通穴、１１３…封止領域厚さ、２０１…コーティング層、４０１、１２０８…制御端子、４０２…ゲートワイヤ、４０３…エミッタワイヤ、５００…ＰＮバスバー、５０１…取り付けボルト、５０２…出力配線、６００…信号端子、６０１…制御基板、７０２…突起、７０３…かしめ用逆テーパ領域、９０１…回路パタン、９０２…セラミックス層、９０４…基板、１００１…主端子ブロック、１００４…制御端子ブロック、１００７…ナット、１００８…ボルト逃げ用空隙、１００９…かしめ領域、１１０５…樹脂かしめ領域、１２００…パッケージ、１２０１…エポキシ樹脂、１２０２…パワー半導体チップ、１２０４…絶縁樹脂シート、１２０５…絶縁樹脂シート保護用銅箔、１２０６…ヒートスプレッダ。
100, 200, 300, 400, 900, 1000, 1100 ... IGBT module, 101, 301, 1207 ... main terminal, 102, 701 ... caulking groove, 103, 1002, 1003, 1209 ... Al wire, 104, 404 ... IGBT Chip, 105 ... FWD chip, 106, 108, 1011, 1203 ... Solder, 107, 1006, 1103 ... AlN substrate, 109, 903, 1005, 1101 ... Copper base, 110, 905, 1104 ... Radiation fin, 111, 302, 405, 1010, 1102 ... sealing resin, 112 ... through hole, 113 ... sealing region thickness, 201 ... coating layer, 401, 1208 ... control terminal, 402 ... gate wire, 403 ... emitter wire, 500 ... PN bus bar, 501 ... Mounting bolt, 502 ... Output wiring 600 ... Signal terminal, 601 ... Control board, 702 ... Protrusion, 703 ... Reverse taper area for caulking, 901 ... Circuit pattern, 902 ... Ceramic layer, 904 ... Board, 1001 ... Main terminal block, 1004 ... Control terminal block, 1007 ... Nut, 1008 ... Bolt clearance gap, 1009 ... Caulking area, 1105 ... Resin caulking area, 1200 ... Package, 1201 ... Epoxy resin, 1202 ... Power semiconductor chip, 1204 ... Insulating resin sheet, 1205 ... Copper foil for insulating resin sheet protection 1206 ... Heat spreader.

Claims (17)

少なくとも、電流をスイッチングするパワー半導体素子、該パワー半導体素子が接着され電気的に接続される回路パタン付絶縁基板、該回路パタン付絶縁基板を接着する金属ベース、を有し、前記パワー半導体素子は、アルミ等の金属ワイヤ或いは銅等のリードフレームにより、前記回路パタン付絶縁基板の回路パタン或いは前記回路パタン付絶縁基板外に配置された端子に電気的に接続されるパワー半導体モジュールにおいて、
前記回路パタン付絶縁基板周囲近傍の前記金属ベース表面に、２列以上の溝、或いは１本以上の突起を配置し、前記回路パタン付絶縁基板は、前記溝或いは突起とともに硬質樹脂で封止され、該封止領域は前記金属ベースの最外周を直線的に結んだ領域の内側であり、前記封止領域外側の露出した金属ベースには、金属ベースの取り付け穴が存在することを特徴とするパワー半導体モジュール。 At least a power semiconductor element for switching current, an insulating substrate with a circuit pattern to which the power semiconductor element is bonded and electrically connected, and a metal base to which the insulating substrate with a circuit pattern is bonded. In a power semiconductor module that is electrically connected to a circuit pattern of the insulating substrate with a circuit pattern or a terminal disposed outside the insulating substrate with a circuit pattern by a metal wire such as aluminum or a lead frame such as copper,
Two or more grooves or one or more protrusions are arranged on the surface of the metal base near the periphery of the insulating substrate with circuit patterns, and the insulating substrate with circuit patterns is sealed with a hard resin together with the grooves or protrusions. The sealing region is inside the region where the outermost periphery of the metal base is linearly connected, and the exposed metal base outside the sealing region has a mounting hole for the metal base. Power semiconductor module. 請求項１において、前記封止樹脂の室温での線膨張係数は、前記金属ベースの線膨張係数と概略一致していることを特徴とするパワー半導体モジュール。   2. The power semiconductor module according to claim 1, wherein a linear expansion coefficient of the sealing resin at room temperature is approximately equal to a linear expansion coefficient of the metal base. 請求項２において、前記金属ベースは銅、前記回路パタン付絶縁基板は銅貼りＳｉＮ基板であり、前記封止樹脂の室温での線膨張係数は概略１６ppm であることを特徴とするパワー半導体モジュール。   3. The power semiconductor module according to claim 2, wherein the metal base is copper, the insulating substrate with circuit pattern is a copper-coated SiN substrate, and the linear expansion coefficient of the sealing resin at room temperature is approximately 16 ppm. 請求項２において、前記金属ベースは銅、前記回路パタン付絶縁基板は銅又はアルミ貼りＡｌＮ基板であり、前記封止樹脂の室温での線膨張係数は概略１６ppm であることを特徴とするパワー半導体モジュール。   3. The power semiconductor according to claim 2, wherein the metal base is copper, the insulating substrate with circuit pattern is an AlN substrate with copper or aluminum, and the linear expansion coefficient of the sealing resin at room temperature is approximately 16 ppm. module. 請求項２において、前記金属ベースはアルミ又はアルミ合金、前記回路パタン付絶縁基板は銅貼りアルミナ基板であり、前記封止樹脂の室温での線膨張係数は概略２３ppm であることを特徴とするパワー半導体モジュール。   3. The power according to claim 2, wherein the metal base is aluminum or an aluminum alloy, the insulating substrate with a circuit pattern is a copper-coated alumina substrate, and the linear expansion coefficient of the sealing resin at room temperature is approximately 23 ppm. Semiconductor module. 請求項１において、前記硬質封止樹脂と、前記絶縁基板、Ｓｉチップ、金属ベース等の被封止物の界面には、全領域に渡って前記封止樹脂よりも硬度が低いコーティング樹脂が介在していることを特徴とするパワー半導体モジュール。   2. The coating resin having a hardness lower than that of the sealing resin over the entire region is interposed at an interface between the hard sealing resin and an object to be sealed such as the insulating substrate, Si chip, and metal base. A power semiconductor module characterized by that. 請求項６において、前記コーティング樹脂はポリアミド樹脂であり、線膨張係数、弾性係数は各々封止樹脂の２倍以上、１／５以下であり、厚さは１０μｍ以下であることを特徴とするパワー半導体モジュール。   7. The power according to claim 6, wherein the coating resin is a polyamide resin, the linear expansion coefficient and the elastic coefficient are each not less than twice and not more than 1/5 of the sealing resin, and the thickness is not more than 10 μm. Semiconductor module. 請求項１において、前記回路パタン付絶縁基板周囲近傍の前記金属ベース表面の溝は矩形であり、該溝の各一辺には、少なくとも一箇所、溝間の突起が先端に向かって広くなる、逆テーパ形状の領域が存在することを特徴とするパワー半導体モジュール。   2. The groove on the surface of the metal base in the vicinity of the periphery of the insulating substrate with circuit pattern is a rectangle, and at least one point on each side of the groove has a protrusion between the grooves that widens toward the tip. A power semiconductor module having a tapered region. 請求項１において、前記回路パタン付絶縁基板の回路パタン上に銅等の金属体を接合し、該金属体をパワー半導体の主電流が流れる主端子、及び、パワー半導体を制御する制御端子とし、これらの端子は、硬質樹脂で封止された領域の表面に全て露出することを特徴とするパワー半導体モジュール。   In claim 1, a metal body such as copper is joined on a circuit pattern of the insulating substrate with a circuit pattern, and the metal body is used as a main terminal through which a main current of a power semiconductor flows, and a control terminal for controlling the power semiconductor, The power semiconductor module is characterized in that all of these terminals are exposed on the surface of the region sealed with the hard resin. 請求項９において、封止領域の表面に露出する端子は、全て窪みを有しているメス型コネクタであり、該窪みに外部接続端子が差し込まれる事により接続される、或いは、該窪みを利用して外部配線に接続されることを特徴とするパワー半導体モジュール。   The terminal exposed to the surface of the sealing region according to claim 9 is a female connector that has a depression, and is connected by inserting an external connection terminal into the depression or uses the depression. The power semiconductor module is connected to external wiring. 請求項１０において、封止領域の表面に露出する主端子は、中心部にネジ穴が形製されていることを特徴とするパワー半導体モジュール。   11. The power semiconductor module according to claim 10, wherein the main terminal exposed on the surface of the sealing region is formed with a screw hole at the center. 請求項１０において、封止領域の表面に露出する制御端子は、中心部に窪みが設けられ、該窪みにピン端子が挿入されると、該ピン端子はかしめられる手段が形成されていることを特徴とするパワー半導体モジュール。   11. The control terminal exposed on the surface of the sealing region according to claim 10, wherein a depression is provided in a central portion, and means for caulking the pin terminal when the pin terminal is inserted into the depression is formed. A featured power semiconductor module. 請求項９から請求項１２の何れか１つにおいて、封止領域の表面に露出する端子は、その降伏応力が概略５０ＭＰａ以下であることを特徴とするパワー半導体モジュール。   13. The power semiconductor module according to claim 9, wherein the terminal exposed on the surface of the sealing region has a yield stress of approximately 50 MPa or less. 請求項１３において、前記端子は、銅、又は、銅合金、或いは、アルミ、又は、アルミ合金製で、焼鈍されていることを特徴とするパワー半導体モジュール。   14. The power semiconductor module according to claim 13, wherein the terminal is made of copper, copper alloy, aluminum, or aluminum alloy, and is annealed. 請求項１において、前記回路パタン付絶縁基板は、一枚の前記金属ベース上に複数接着されており、一枚以上の前記回路パタン付絶縁基板を内蔵した前記封止領域が、一枚の前記金属ベース上に複数存在することを特徴とするパワー半導体モジュール。   The insulating substrate with circuit pattern according to claim 1, wherein a plurality of the insulating substrates with circuit patterns are bonded onto one metal base, and the sealing region containing one or more insulating substrates with circuit patterns is one piece of the one. A power semiconductor module comprising a plurality of metal bases. 請求項１５において、一つの前記封止領域は、三相モジュール中の一相分の回路を封止しており、全体で三つの封止領域を有し、かつ、金属ベースはフィン付き銅ベースであって、前記三つの封止領域境界の下でフィンが分割されており、全体で３分割されていることを特徴とするパワー半導体モジュール。   16. The sealing area according to claim 15, wherein one sealing area seals a circuit for one phase in a three-phase module, and has three sealing areas as a whole, and the metal base is a finned copper base. The power semiconductor module is characterized in that the fin is divided under the boundary of the three sealing regions, and is divided into three as a whole. 少なくとも、電流をスイッチングするパワー半導体素子、該パワー半導体素子が接着され電気的に接続される回路パタン付絶縁基板、該回路パタン付絶縁基板を接着する金属ベース、パワー半導体素子の主電流を通電する主端子、パワー半導体の制御信号を入力する制御端子を有し、前記パワー半導体素子は、アルミ等の金属ワイヤ或いは銅等のリードフレームにより、前記回路パタン付絶縁基板の回路パタン及び前記回路パタン付絶縁基板外の前記金属ベース上に配置された前記主端子、制御端子に電気的に接続されるパワー半導体モジュールにおいて、
前記回路パタン付絶縁基板、前記主端子、及び、前記制御端子を包含する最小領域の周囲近傍の前記金属ベース表面に、２列以上の溝、或いは１本以上の突起が存在し、
前記回路パタン付絶縁基板、前記主端子、及び、前記制御端子は、前記溝或いは突起とともに硬質樹脂で封止され、
該封止領域は前記金属ベース領域表面の内側であり、前記主端子、及び、前記制御端子は該封止領域の上面に露出し、
前記封止領域外側の露出した金属ベースには、金属ベースの取り付け穴が存在することを特徴とするパワー半導体モジュール。

At least a power semiconductor element for switching current, an insulating substrate with a circuit pattern to which the power semiconductor element is bonded and electrically connected, a metal base to which the insulating substrate with a circuit pattern is bonded, and a main current of the power semiconductor element to energize The power semiconductor element has a control terminal for inputting a control signal for a main terminal and a power semiconductor, and the power semiconductor element has a circuit pattern of the insulating substrate with a circuit pattern and a circuit pattern with a metal wire such as aluminum or a lead frame such as copper. In the power semiconductor module electrically connected to the main terminal and the control terminal disposed on the metal base outside the insulating substrate,
There are two or more rows of grooves or one or more protrusions on the surface of the metal base in the vicinity of the minimum region including the insulating substrate with circuit pattern, the main terminal, and the control terminal,
The insulating substrate with circuit pattern, the main terminal, and the control terminal are sealed with a hard resin together with the groove or protrusion,
The sealing region is inside the surface of the metal base region, and the main terminal and the control terminal are exposed on an upper surface of the sealing region,
The power semiconductor module is characterized in that a metal base mounting hole exists in the exposed metal base outside the sealing region.

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Cited By (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008090734A1 (en) * 2007-01-22 2008-07-31 Mitsubishi Electric Corporation Semiconductor device for power
JP2008199022A (en) * 2007-02-12 2008-08-28 Infineon Technologies Ag Power semiconductor module and its manufacturing method
JP2009059923A (en) * 2007-08-31 2009-03-19 Mitsubishi Electric Corp Semiconductor device
JP2009088386A (en) * 2007-10-02 2009-04-23 Rohm Co Ltd Power module
JP2009123953A (en) * 2007-11-15 2009-06-04 Omron Corp Transfer mold power module
JP2010027814A (en) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp Power semiconductor device
JP2010027813A (en) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp Power semiconductor device
JP2010056186A (en) * 2008-08-27 2010-03-11 Hitachi Ltd Electrical and electronic module
JP2010118429A (en) * 2008-11-12 2010-05-27 Denso Corp Electronic apparatus and manufacturing method for the same
JP2010129670A (en) * 2008-11-26 2010-06-10 Mitsubishi Electric Corp Power semiconductor module
JP2010129795A (en) * 2008-11-28 2010-06-10 Mitsubishi Electric Corp Semiconductor module for power
DE102009055882A1 (en) 2008-11-28 2010-07-01 Mitsubishi Electric Corporation, Tokyo Power semiconductor device
DE102009042600A1 (en) 2008-11-28 2010-07-08 Mitsubishi Electric Corp. Power semiconductor module and manufacturing method for this
DE102009055648A1 (en) 2008-11-25 2010-07-22 Mitsubishi Electric Corp. The power semiconductor module
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DE102009055691A1 (en) 2008-11-26 2010-08-19 Mitsubishi Electric Corp. The power semiconductor module
DE102009042390A1 (en) 2009-02-04 2010-08-19 Mitsubishi Electric Corp. Power semiconductor module and method for its production
DE102009049613A1 (en) 2009-02-13 2010-08-26 Mitsubishi Electric Corp. Power semiconductor device
DE102009042399A1 (en) 2009-02-13 2010-10-14 Mitsubishi Electric Corp. Power semiconductor device and manufacturing method therefor
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DE102010038826A1 (en) 2009-08-27 2011-03-03 Mitsubishi Electric Corp. Power semiconductor device and method of manufacturing the same
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DE102010043839A1 (en) 2010-01-20 2011-07-21 Mitsubishi Electric Corp. Semiconductor device, has outer base whose upper section is arranged higher than upper section of inner base, where inner peripheral surface of outer base is in contact with outer peripheral surface of inner base
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US10361294B2 (en) 2016-11-02 2019-07-23 Fuji Electric Co., Ltd. Semiconductor device
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US11031355B2 (en) 2017-07-03 2021-06-08 Mitsubishi Electric Corporation Semiconductor device
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DE112016002302B4 (en) 2015-05-21 2022-05-05 Mitsubishi Electric Corporation power semiconductor device
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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KR101668035B1 (en) * 2016-06-15 2016-10-21 제엠제코(주) Improved semiconductor chip package

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283681A (en) * 1996-04-16 1997-10-31 Hitachi Ltd Semiconductor device
JP2003124406A (en) * 2001-08-06 2003-04-25 Denso Corp Semiconductor device
JP2004228286A (en) * 2003-01-22 2004-08-12 Mitsubishi Electric Corp Power semiconductor device
JP2004349324A (en) * 2003-05-20 2004-12-09 Hitachi Ltd Direct water-cooled power semiconductor module structure
JP2005191178A (en) * 2003-12-25 2005-07-14 Mitsubishi Electric Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283681A (en) * 1996-04-16 1997-10-31 Hitachi Ltd Semiconductor device
JP2003124406A (en) * 2001-08-06 2003-04-25 Denso Corp Semiconductor device
JP2004228286A (en) * 2003-01-22 2004-08-12 Mitsubishi Electric Corp Power semiconductor device
JP2004349324A (en) * 2003-05-20 2004-12-09 Hitachi Ltd Direct water-cooled power semiconductor module structure
JP2005191178A (en) * 2003-12-25 2005-07-14 Mitsubishi Electric Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299603B2 (en) 2007-01-22 2012-10-30 Mitsubishi Electric Corporation Power semiconductor device
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US8253236B2 (en) 2008-07-18 2012-08-28 Mitsubishi Electric Corporation Power semiconductor device
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CN113437026B (en) * 2020-03-23 2024-04-26 株式会社东芝 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
WO2023214500A1 (en) * 2022-05-02 2023-11-09 ローム株式会社 Semiconductor device
CN115565971A (en) * 2022-10-26 2023-01-03 弘大芯源(深圳)半导体有限公司 Chip packaging structure with good heat dissipation performance
CN115565971B (en) * 2022-10-26 2024-02-23 弘大芯源(深圳)半导体有限公司 Chip packaging structure with good heat dissipation performance

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