JP2007184052A - コマンド生成回路及びこれらを備えた半導体記憶装置 - Google Patents
コマンド生成回路及びこれらを備えた半導体記憶装置 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
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Abstract
【解決手段】本発明のコマンド生成回路では,コマンド信号/CS,/RAS,/CAS,/WEをデコードして決まる動作モード信号(ACTIVE,READ,WRITE,PRECHARGE等の内部動作を決める信号)とバンクセレクト信号(BS0,BS1,BS2,BS3)を内部クロックでラッチした後に論理積をとることにより,セットアップ(tIS)マージンを約25%拡大する効果が得られる。
【選択図】 図1
Description
ΔTc-(ΔTi-tIS+4Δt)=Tsl ・・・・・・(1)
となる。式(1)より,
tIS=Tsl+ΔTi+4Δt-ΔTc ・・・・・・(2)
これが回路構成上,最低限必要なセットアップ時間(tIS)となる。外部クロックCLKから内部クロックCCLK_Tの遅延時間ΔTcを大きくすれば,セットアップ時間を小さくすることができるが,ΔTcを大きくとることは,回路が動作可能な周波数が低くなることにつながる。周波数が高速化し,セットアップ時間のスペックが厳しくなりつつある今日,回路的な工夫が必要になっている。そのために高いクロック周波数で、充分なセットアップ時間(tIS)が確保できるコマンド生成回路が望まれている。
ΔTc-(ΔTi-tIS+3Δt)=Tsl ・・・・・・(3)
式(3)より,
tIS=Tsl+ΔTi+3Δt-ΔTc ・・・・・・(4)
これが回路構成上,最低限必要なコマンド及びバンクアドレスのセットアップ時間となる。従来例の結果(式(2))と比較すると,回路構成上,最低限必要なセットアップ時間(tIS)はΔtだけ小さいことがわかる。
NA10、NA11、NA12、NA13、NA20、NA21,NA22、NA23 2入力NAND回路
NA30、NA31,NA32、NA33、NA35、NA36,NA37,NA38,NA39 3入力NAND回路
NO25、NO30 NOR回路
IN1、IN2、IN3、IN10、IN11,IN12,IN13、IN30、IN31,IN32,IN33、IN35、In36,IN37,IN38 インバータ回路
Claims (7)
- コマンド生成回路において、動作モード信号とバンクセレクト信号とをそれぞれラッチしたラッチ動作モード信号とラッチバンクセレクト信号とを論理処理しコマンドを生成することを特徴とするコマンド生成回路。
- 前記ラッチ動作モード信号とラッチバンクセレクト信号とは、相補の内部クロックに同期して前記動作モード信号とバンクセレクト信号をラッチし生成することを特徴とする請求項1に記載のコマンド生成回路。
- 前記動作モード信号とバンクセレクト信号をラッチするラッチ回路は、前記相補の内部クロックをゲート入力とするトランスファーゲートと、前記トランスファーゲートの出力をラッチするフリップフロップと、前記トランスファーゲートの出力を反転して出力するインバータ回路から構成されることを特徴とする請求項2に記載のコマンド生成回路。
- 前記論理処理は、前記相補の内部クロックの一方の内部クロックをイネーブル信号とし前記ラッチ動作モード信号と前記ラッチバンクセレクト信号との論理積として出力することを特徴とする請求項2に記載のコマンド生成回路。
- 前記動作モード信号とバンクセレクト信号とがラッチされるタイミングは、内部コマンド信号及び内部バンクアドレスが入力されたタイミングから論理ゲート3段分の遅延時間以上遅れることを特徴とする請求項1に記載のコマンド生成回路。
- 前記動作モード信号は内部カラムアドレスストローブ信号と内部ライトイネーブル信号を入力されるノア回路と、前記ノア回路の出力とチップ選択信号とロウアドレスストローブ信号が入力されるナンド回路から構成されることを特徴とする請求項1に記載のコマンド生成回路。
- 請求項1乃至6のいずれかに記載のコマンド生成回路を備えたことを特徴とする半導体記憶装置。
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JP2006002436A JP2007184052A (ja) | 2006-01-10 | 2006-01-10 | コマンド生成回路及びこれらを備えた半導体記憶装置 |
US11/651,033 US7492661B2 (en) | 2006-01-10 | 2007-01-09 | Command generating circuit and semiconductor memory device having the same |
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JP2006002436A JP2007184052A (ja) | 2006-01-10 | 2006-01-10 | コマンド生成回路及びこれらを備えた半導体記憶装置 |
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KR101082106B1 (ko) * | 2009-09-30 | 2011-11-10 | 주식회사 하이닉스반도체 | 뱅크액티브신호생성회로 |
KR20110083859A (ko) * | 2010-01-15 | 2011-07-21 | 삼성전자주식회사 | 메모리 버퍼를 갖는 메모리 모듈 및 이를 포함하는 메모리 시스템 |
KR101735085B1 (ko) * | 2011-01-26 | 2017-05-15 | 에스케이하이닉스 주식회사 | 뱅크 선택 회로 및 이를 포함하는 메모리 장치 |
KR102405066B1 (ko) * | 2015-12-23 | 2022-06-07 | 에스케이하이닉스 주식회사 | 신호 쉬프팅 회로, 베이스 칩 및 이를 포함하는 반도체 시스템 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07141870A (ja) * | 1993-11-19 | 1995-06-02 | Hitachi Ltd | 半導体記憶装置 |
JPH0817182A (ja) * | 1994-06-27 | 1996-01-19 | Nec Corp | 論理データ入力ラッチ回路 |
JP2001006360A (ja) * | 1999-06-22 | 2001-01-12 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2003123478A (ja) * | 2001-10-03 | 2003-04-25 | Fujitsu Ltd | 半導体装置及び半導体記憶装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08124380A (ja) | 1994-10-20 | 1996-05-17 | Hitachi Ltd | 半導体メモリ及び半導体メモリアクセス方法 |
JP2904076B2 (ja) | 1995-11-10 | 1999-06-14 | 日本電気株式会社 | 半導体記憶装置 |
JP3152174B2 (ja) | 1997-07-29 | 2001-04-03 | 日本電気株式会社 | 半導体記憶装置 |
JPH11283395A (ja) * | 1998-03-30 | 1999-10-15 | Toshiba Microelectronics Corp | 半導体記憶装置 |
JP4011833B2 (ja) | 2000-06-30 | 2007-11-21 | 株式会社東芝 | 半導体メモリ |
US6965534B2 (en) * | 2003-12-16 | 2005-11-15 | Infineon Technologies Ag | Random access memory using precharge timers in test mode |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07141870A (ja) * | 1993-11-19 | 1995-06-02 | Hitachi Ltd | 半導体記憶装置 |
JPH0817182A (ja) * | 1994-06-27 | 1996-01-19 | Nec Corp | 論理データ入力ラッチ回路 |
JP2001006360A (ja) * | 1999-06-22 | 2001-01-12 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2003123478A (ja) * | 2001-10-03 | 2003-04-25 | Fujitsu Ltd | 半導体装置及び半導体記憶装置 |
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US20070159910A1 (en) | 2007-07-12 |
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