JP2007171736A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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JP2007171736A
JP2007171736A JP2005371551A JP2005371551A JP2007171736A JP 2007171736 A JP2007171736 A JP 2007171736A JP 2005371551 A JP2005371551 A JP 2005371551A JP 2005371551 A JP2005371551 A JP 2005371551A JP 2007171736 A JP2007171736 A JP 2007171736A
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JP4946042B2 (en
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Akio Ota
昭雄 太田
Osamu Kobayashi
修 小林
Sachiko Watanabe
佐智子 渡邉
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Epson Imaging Devices Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which hardly causes crosstalk or the like and has a low power consumption and is prevented from electrostatic discharge. <P>SOLUTION: The liquid crystal display device includes: a plurality of scan electrodes 8 and a plurality of signal electrodes 9 which are arranged in a matrix form on a first insulating substrate; a plurality of pixel electrodes 10 disposed near intersections between the scan electrodes 8 and the signal electrodes 9 on the first insulating substrate 2; switching elements 11 connected to the scan electrodes 8, the signal electrodes 9, and the pixel electrodes 10 respectively; a plurality of first common electrodes C1 to C220 disposed on the first insulating substrate; auxiliary capacitors 12 connected between the pixel electrodes 10 and the first common electrodes C1 to C220 respectively; and a second common electrode 13 connected to the first common electrodes C1 to C220. A first insulating layer and a second insulating layer are laminated between respective scan electrodes 8 and the second common electrode 13 at intersections between both of them. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は液晶表示装置に関する。   The present invention relates to a liquid crystal display device.

従来、この種の装置は例えば特許文献１に示されている。特許文献１において、複数の走査電極１および複数の信号電極２と、その交点近傍に位置する複数の画素電極１０が配置されている。各走査電極１と各信号電極２と各画素電極１０に接続されたＴＦＴ５が設けられている。そして、複数の共通電極６と、各画素電極６との間に接続された各補助コンデンサ１３が設けられている。
特開２００３−１６２２６５号公報 Conventionally, this kind of apparatus is shown by patent document 1, for example. In Patent Document 1, a plurality of scanning electrodes 1 and a plurality of signal electrodes 2 and a plurality of pixel electrodes 10 located in the vicinity of the intersections are arranged. A TFT 5 connected to each scanning electrode 1, each signal electrode 2, and each pixel electrode 10 is provided. Each auxiliary capacitor 13 connected between the plurality of common electrodes 6 and each pixel electrode 6 is provided.
JP 2003-162265 A

上記装置では、クロストークやフリッカが生じ易い、第１の欠点がある。本発明者がその原因を究明したところ、各共通電極６に接続された各補助コンデンサ１３に印加される電圧が一定でなく、ばらついているからである事がわかった。その結果、各走査電極１に印加されるゲートパルスが立ち上がった後に、各画素電極に印加される電圧の特性がばらつくので、クロストークやフリッカが起こり易い事が分かった。   The above apparatus has a first drawback that crosstalk and flicker are likely to occur. As a result of investigation by the inventor of the present invention, it was found that the voltage applied to each auxiliary capacitor 13 connected to each common electrode 6 is not constant and varies. As a result, it was found that the characteristics of the voltage applied to each pixel electrode after the gate pulse applied to each scan electrode 1 rises, so that crosstalk and flicker are likely to occur.

そもそもの原因は、高精細とするためには、各画素３０同士の隙間を大きくできないため、共通電極６の幅を１０〜２０μｍと、狭くせざるを得ない。そのため、共通電極６の先端近傍での電圧降下が大きいためである。   In the first place, in order to achieve high definition, the gap between the pixels 30 cannot be increased, so the width of the common electrode 6 must be narrowed to 10 to 20 μm. Therefore, the voltage drop in the vicinity of the tip of the common electrode 6 is large.

この欠点を解消するために、本発明者は、各電極１，２，１０の周囲に位置し、各共通電極６に接続された幅広の第２共通電極を設けた。そして、各走査電極１と、第２共通電極の交点においては、両電極の間に、ＳｉＮＸからなる絶縁層を設けた。しかし、この交点におけるコンデンサ容量が大きく、電力消費量が大きい、第２の欠点がある。 In order to eliminate this drawback, the present inventor provided a wide second common electrode that is located around each electrode 1, 2, 10 and connected to each common electrode 6. An insulating layer made of SiN X was provided between the electrodes at the intersection of each scanning electrode 1 and the second common electrode. However, there is a second drawback that the capacitor capacity at this intersection is large and the power consumption is large.

更に、上記装置では、静電破壊の対策がなされていない、第３の欠点がある。そこで、本発明はこの様な従来の欠点を考慮して、クロストーク等が生じにくい、電力消費量が小さい、静電破壊を防止した、液晶表示装置を提供する。   Further, the above apparatus has a third drawback in which no countermeasure against electrostatic breakdown is taken. In view of the above-described conventional drawbacks, the present invention provides a liquid crystal display device in which crosstalk or the like is unlikely to occur, power consumption is small, and electrostatic breakdown is prevented.

上記課題を解決するために、請求項１の本発明では、第１絶縁基板と、第２絶縁基板と、両基板間に設けられた液晶とを備え、前記第１絶縁基板上において、行列状に配置された複数の走査電極および複数の信号電極と、前記走査電極と前記信号電極との交点近傍に配置された複数の画素電極と、各走査電極と各信号電極と各画素電極に接続された各スイッチング素子と、前記第１絶縁基板上に配置された複数の第１共通電極と、各画素電極と各第１共通電極の間に接続された各補助コンデンサと、各第１共通電極に接続された第２共通電極とを備え、各走査電極と前記第２共通電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された。   In order to solve the above-mentioned problem, the present invention of claim 1 includes a first insulating substrate, a second insulating substrate, and a liquid crystal provided between the two substrates, and the matrix is formed on the first insulating substrate. A plurality of scanning electrodes and a plurality of signal electrodes disposed in the plurality of pixel electrodes, a plurality of pixel electrodes disposed near intersections of the scanning electrodes and the signal electrodes, and each scanning electrode, each signal electrode, and each pixel electrode. Switching elements, a plurality of first common electrodes disposed on the first insulating substrate, auxiliary capacitors connected between the pixel electrodes and the first common electrodes, and the first common electrodes. The first insulating layer and the second insulating layer are stacked between the electrodes at the intersection of each scanning electrode and the second common electrode.

請求項２の本発明では、前記信号電極と前記第２共通電極との間に位置し、前記第２共通電極の近傍に、列電極が設けられ、前記列電極と各走査電極との間に各静電破壊防止素子が設けられ、各走査電極と前記列電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された。   In the present invention of claim 2, a column electrode is provided between the signal electrode and the second common electrode, and is provided in the vicinity of the second common electrode, and between the column electrode and each scanning electrode. Each electrostatic breakdown preventing element was provided, and a first insulating layer and a second insulating layer were laminated between the two electrodes at the intersection of each scanning electrode and the column electrode.

請求項３の本発明では、前記信号電極と前記第２共通電極との間に位置し、前記第２共通電極の近傍に、列電極が設けられ、前記列電極と各走査電極との間に各静電破壊防止素子が設けられ、各第１共通電極と前記列電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された。   In the present invention of claim 3, a column electrode is provided between the signal electrode and the second common electrode, and is provided in the vicinity of the second common electrode, and between the column electrode and each scanning electrode. Each electrostatic breakdown preventing element was provided, and a first insulating layer and a second insulating layer were laminated between the electrodes at the intersection of each first common electrode and the column electrode.

請求項４の本発明では、前記第２共通電極に共通電極が印加され、前記第２共通電極は閉回路とされた。   In a fourth aspect of the present invention, a common electrode is applied to the second common electrode, and the second common electrode is a closed circuit.

請求項５の本発明では、前記第１絶縁層はＳｉＮＸからなり、前記第２絶縁層は、ａ−Ｓｉ層およびｎ＋ａ−Ｓｉ層が積層されている。 In the present invention of claim 5, the first insulating layer is made of SiN X , and the second insulating layer is formed by laminating an a-Si layer and an n + a-Si layer.

請求項１の様に、各走査電極と第２共通電極の交点において、第１絶縁層および第２絶縁層を積層することにより、上記交点近傍でのコンデンサ容量は、従来に比べ、極めて小さくなる。その結果として、上記交点部分における電力ロス（電力消費量）は極めて小さくなる。   As described in claim 1, by stacking the first insulating layer and the second insulating layer at the intersection of each scanning electrode and the second common electrode, the capacitance of the capacitor in the vicinity of the intersection is extremely small as compared with the prior art. . As a result, the power loss (power consumption) at the intersection is extremely small.

請求項２の様に、各走査電極と列電極の交点において、第１絶縁層および第２絶縁層を積層することにより、上記交点近傍でのコンデンサ容量は、従来に比べ、極めて小さくなる。その結果として、上記交点部分における電力ロス（電力消費量）は極めて小さくなる。また、請求項２の構成により、静電破壊を防止できる。   As described in claim 2, by stacking the first insulating layer and the second insulating layer at the intersection of each scanning electrode and the column electrode, the capacitor capacity in the vicinity of the intersection becomes extremely small as compared with the conventional case. As a result, the power loss (power consumption) at the intersection is extremely small. Further, according to the configuration of claim 2, electrostatic breakdown can be prevented.

請求項３の様に、各第１共通電極と列電極の交点において、第１絶縁層および第２絶縁層を積層することにより、上記交点近傍でのコンデンサ容量は、従来に比べ、極めて小さくなる。その結果として、上記交点部分における電力ロス（電力消費量）は極めて小さくなる。また、請求項３の構成により、静電破壊を防止できる。   According to the third aspect, by stacking the first insulating layer and the second insulating layer at the intersection of each first common electrode and the column electrode, the capacitor capacity in the vicinity of the intersection is extremely small as compared with the prior art. . As a result, the power loss (power consumption) at the intersection is extremely small. Further, according to the configuration of claim 3, electrostatic breakdown can be prevented.

請求項４の様に、各第１共通電極に接続され、共通電圧が供給され、閉回路とされた第２共通電極を設ける事により、各第１共通電極の各部分における電圧降下が小さくなる。その結果、各第１共通電極に接続された各補助コンデンサの印加電圧が略一定となり、クロストークやフリッカの発生を防止できる。   As in claim 4, by providing a second common electrode connected to each first common electrode, supplied with a common voltage, and having a closed circuit, a voltage drop at each portion of each first common electrode is reduced. . As a result, the applied voltage of each auxiliary capacitor connected to each first common electrode becomes substantially constant, and the occurrence of crosstalk and flicker can be prevented.

請求項５の様に、各交点部分における第１絶縁層および第２絶縁層の具体的構成は、スイッチング素子の構成と同一になる。故に、スイッチング素子と各交点部分は、同一の製造プロセスにて成膜されるので、製造コストが安い。   As in claim 5, the specific configuration of the first insulating layer and the second insulating layer at each intersection is the same as the configuration of the switching element. Therefore, since the switching element and each intersection portion are formed by the same manufacturing process, the manufacturing cost is low.

以下に、本発明を実施するための最良の形態を、実施例及び図面を用いて詳細に説明する。以下の実施例は、本発明の技術思想を具体化するための液晶表示装置の一例を例示するものである。本発明は、特許請求の範囲に示した技術思想を逸脱することなく、種々の変更を行ったものにも、均しく適用し得る。   Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples and drawings. The following embodiments exemplify an example of a liquid crystal display device for embodying the technical idea of the present invention. The present invention can be equally applied to various modifications without departing from the technical idea shown in the claims.

以下、図１ないし図３に従い、本実施例に係る液晶表示装置１を説明する。図１は液晶表示装置１の部分断面図である。図２は液晶表示装置１の電気回路図である。図３は図２のＡ部詳細図である。   Hereinafter, the liquid crystal display device 1 according to the present embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a partial cross-sectional view of the liquid crystal display device 1. FIG. 2 is an electric circuit diagram of the liquid crystal display device 1. FIG. 3 is a detailed view of part A in FIG.

図１において、液晶表示装置１は、第１絶縁基板２と、第２絶縁基板３と、両基板２，３間に設けられた液晶４等を有している。第１絶縁基板２および第２絶縁基板３は例えばガラス板等からなる。第１絶縁基板２上において、配線２ａと、ドレイン２ｂ等が形成され、その上に第１絶縁層２ｃが形成されている。ドレイン２ｂと導通して、第１絶縁層２ｃ上に画素電極１０が形成され、その上に配向膜７が形成されている。   In FIG. 1, the liquid crystal display device 1 includes a first insulating substrate 2, a second insulating substrate 3, and a liquid crystal 4 provided between both the substrates 2 and 3. The first insulating substrate 2 and the second insulating substrate 3 are made of, for example, a glass plate. On the first insulating substrate 2, wirings 2a, drains 2b and the like are formed, and a first insulating layer 2c is formed thereon. The pixel electrode 10 is formed on the first insulating layer 2c in conduction with the drain 2b, and the alignment film 7 is formed thereon.

第２絶縁基板３の背面には、カラーフィルタ層５と、ブラックマトリクス５ａと、共通電極６と、配向膜７等が形成されている。カラーフィルタ層５は例えば、Ｒ，Ｇ，Ｂの各フィルタがストライプ状に順に、繰り返し、配置されたものである。液晶４はシール剤４ａにより封止されている。   On the back surface of the second insulating substrate 3, a color filter layer 5, a black matrix 5a, a common electrode 6, an alignment film 7 and the like are formed. The color filter layer 5 is, for example, one in which R, G, B filters are repeatedly arranged in order in a stripe shape. The liquid crystal 4 is sealed with a sealant 4a.

図２において、第１絶縁基板２上において、行列状に、複数の走査電極８と、複数の信号電極９が形成されている。   In FIG. 2, a plurality of scanning electrodes 8 and a plurality of signal electrodes 9 are formed in a matrix on the first insulating substrate 2.

信号電極９は、図１の上から順に、ｓ１，ｓ２，…ｓ５２７，ｓ５２８で示されたものである。走査電極８は、図１の右から順に、ｇ１，…ｇ１１０，ｇ２２０，…ｇ１１１で示したものである。   The signal electrodes 9 are indicated by s1, s2,... S527, s528 in order from the top of FIG. The scanning electrodes 8 are indicated by g1,... G110, g220,.

複数の画素電極１０は、各走査電極８と、各信号電極９の交点近傍に配置されている。各スイッチング素子１１は、各走査電極８と、各信号電極９と、各画素電極１０に接続されている。   The plurality of pixel electrodes 10 are arranged in the vicinity of the intersections of the scanning electrodes 8 and the signal electrodes 9. Each switching element 11 is connected to each scanning electrode 8, each signal electrode 9, and each pixel electrode 10.

各スイッチング素子１１は例えば、ＴＦＴ（薄膜トランジスタ）等からなる。各スイッチング素子１１のソースは各信号電極９に接続されている。各スイッチング素子１１のゲートは各走査電極８に接続されている。各スイッチング素子１１のドレインは、各画素電極１０に接続されている。   Each switching element 11 includes, for example, a TFT (Thin Film Transistor). The source of each switching element 11 is connected to each signal electrode 9. The gate of each switching element 11 is connected to each scanning electrode 8. The drain of each switching element 11 is connected to each pixel electrode 10.

複数の第１共通電極Ｃ１，…Ｃ１１０，Ｃ２２０，…Ｃ１１１は、第１絶縁基板２上に配置されている。各第１共通電極Ｃ１，…Ｃ１１０，Ｃ２２０，…Ｃ１１１は、走査電極
ｇ１，…ｇ１１０，ｇ２２０，…ｇ１１１に隣接して配置されている。 The plurality of first common electrodes C1, ... C110, C220, ... C111 are arranged on the first insulating substrate 2. Each of the first common electrodes C1,... C110, C220,... C111 is disposed adjacent to the scanning electrodes g1,.

各補助コンデンサ１２は、各画素電極１０と、各第１共通電極Ｃ１〜Ｃ２２０との間に接続されている。   Each auxiliary capacitor 12 is connected between each pixel electrode 10 and each first common electrode C1 to C220.

即ち、図３に示す様に、第１絶縁基板２上に第１共通電極Ｃ１１１〜１１４が形成されている。第１共通電極Ｃ１１１〜１１４上に、第１絶縁層２ｃが形成されている。   That is, as shown in FIG. 3, the first common electrodes C111 to 114 are formed on the first insulating substrate 2. A first insulating layer 2c is formed on the first common electrodes C111 to C114.

画素電極１０は、第１絶縁層２ｃ上に形成されている。これらの第１共通電極Ｃ１１１〜１１４と、第１絶縁層２ｃと、画素電極１０とにより、各補助コンデンサ１２が形成されている。   The pixel electrode 10 is formed on the first insulating layer 2c. Each auxiliary capacitor 12 is formed by the first common electrodes C111 to 114, the first insulating layer 2c, and the pixel electrode 10.

第２共通電極１３は、第１絶縁基板２上の、第１絶縁層２ｃ上に形成され、各第１共通電極Ｃ１〜Ｃ２２０に接続され、閉回路として構成されている。   The second common electrode 13 is formed on the first insulating layer 2c on the first insulating substrate 2, is connected to each of the first common electrodes C1 to C220, and is configured as a closed circuit.

第２共通電極１３は、入力端子１８を介して、共通電圧（例えば、直流５ボルト）が供給される。   The second common electrode 13 is supplied with a common voltage (for example, DC 5 volts) via the input terminal 18.

第２共通電極１３は例えばアルミニュウム等からなる。第２共通電極１３は、第１絶縁基板２上の、第１絶縁層２ｃの上に、例えば、厚さが２０００オングストローム、幅が１００μｍないし５００μｍにて形成されている。   The second common electrode 13 is made of, for example, aluminum. The second common electrode 13 is formed on the first insulating substrate 2 and on the first insulating layer 2c, for example, with a thickness of 2000 angstroms and a width of 100 μm to 500 μm.

第２共通電極１３は、幅が１００μｍ以上になると、第１共通電極Ｃ１〜Ｃ２２０における電圧降下が減ることにより、実用上、差し支えない程度に、クロストークやフリッカの発生を防止できる。   When the width of the second common electrode 13 is 100 μm or more, the voltage drop in the first common electrodes C1 to C220 is reduced, so that the occurrence of crosstalk and flicker can be prevented to the extent that there is no practical problem.

また、第２共通電極１３は、幅が５００μｍを越えても、幅が５００μｍの時と、上記電圧降下値は変わらない。従って、第２共通電極１３は、幅が１００μｍないし５００μｍが望ましい。   Further, even if the width of the second common electrode 13 exceeds 500 μm, the voltage drop value does not change from that when the width is 500 μm. Accordingly, the second common electrode 13 preferably has a width of 100 μm to 500 μm.

第３共通電極１７は第１絶縁基板２上の、第１絶縁層２ｃの上に、第２共通電極１３と離れて配置されている。例えば、第２共通電極１３は、第１絶縁基板２の１辺近傍に配置されている。第３共通電極１７は、上記１辺に対向する位置にある第１絶縁基板２の他辺近傍に配置されている。   The third common electrode 17 is disposed on the first insulating substrate 2 and on the first insulating layer 2 c so as to be separated from the second common electrode 13. For example, the second common electrode 13 is disposed near one side of the first insulating substrate 2. The third common electrode 17 is disposed in the vicinity of the other side of the first insulating substrate 2 at a position facing the one side.

第３共通電極１７は、各第１共通電極Ｃ１〜Ｃ２２０に接続され、閉回路として構成されている。   The third common electrode 17 is connected to each of the first common electrodes C1 to C220 and is configured as a closed circuit.

第３共通電極１７は、入力端子１４，１５，１６を介して、共通電圧（例えば、直流５ボルト）が供給されている。   The third common electrode 17 is supplied with a common voltage (for example, DC 5 volts) via the input terminals 14, 15, and 16.

第３共通電極１７は、例えばアルミニュウム等からなる。第３共通電極１７は、第１絶縁層２ｃ上に、例えば、厚さが２０００オングストローム、幅が１００μｍないし５００μｍにて形成されている。   The third common electrode 17 is made of, for example, aluminum. The third common electrode 17 is formed on the first insulating layer 2c, for example, with a thickness of 2000 angstroms and a width of 100 μm to 500 μm.

第３共通電極１７の幅は、１００μｍないし５００μｍが望ましい理由は、第２共通電極１３と同じである。   The reason why the width of the third common electrode 17 is preferably 100 μm to 500 μm is the same as that of the second common electrode 13.

接続線１９は、第２共通電極１３と、第３共通電極１７とを電気的接続させるものである。接続線１９は、ＩＣ２０内の絶縁基板（図示せず）上に、厚さが２０００オングストローム、幅が１００μｍないし５００μｍのアルミニュウムにて形成されている。   The connection line 19 electrically connects the second common electrode 13 and the third common electrode 17. The connection line 19 is formed of aluminum having a thickness of 2000 angstroms and a width of 100 μm to 500 μm on an insulating substrate (not shown) in the IC 20.

第１共通電極Ｃ１〜Ｃ２２０及び／又は第２共通電極１３及び／又は第３共通電極１７は、第２絶縁基板３の背面に設けられた共通電極６に電気的接続されている。   The first common electrodes C1 to C220 and / or the second common electrode 13 and / or the third common electrode 17 are electrically connected to the common electrode 6 provided on the back surface of the second insulating substrate 3.

ＩＣ２０を構成する走査駆動部４３の各出力端子ＧＤ１〜Ｇ１１０は行電極２３、走査電極ｇ１〜ｇ１１０に接続され、各々、電極２３，ｇ１〜ｇ１１０を駆動する。   The output terminals GD1 to G110 of the scan driving unit 43 constituting the IC 20 are connected to the row electrode 23 and the scan electrodes g1 to g110, and drive the electrodes 23 and g1 to g110, respectively.

ＩＣ２０を構成する走査駆動部４４の各出力端子ＧＤ３〜Ｇ２２０は行電極２２、走査電極ｇ１１１〜ｇ２２０に接続され、各々、電極２２，ｇ１１１〜ｇ２２０を駆動する。   The output terminals GD3 to G220 of the scan driver 44 constituting the IC 20 are connected to the row electrode 22 and the scan electrodes g111 to g220, and drive the electrodes 22, g111 to g220, respectively.

ＩＣ２０を構成する信号駆動部４５の各出力端子Ｓ１〜Ｓ５２８は，信号電極ｓ１〜ｓ５２８に接続され、各々、信号電極ｓ１〜ｓ５２８を駆動する。   The output terminals S1 to S528 of the signal driver 45 constituting the IC 20 are connected to the signal electrodes s1 to s528, and drive the signal electrodes s1 to s528, respectively.

以下に、本発明の特徴をまとめる。第１の特徴は、第１絶縁基板２と、第２絶縁基板３と、両基板間に設けられた液晶４とを備え、第１絶縁基板上２において、行列状に配置された複数の走査電極８および複数の信号電極９と、走査電極８と信号電極９との交点近傍に配置された複数の画素電極１０が設けられている。そして、各走査電極８と各信号電極９と各画素電極１０に接続された各スイッチング素子１１と、第１絶縁基板２上に配置された複数の第１共通電極Ｃ１〜Ｃ２２０と、各画素電極１０と各第１共通電極Ｃ１〜Ｃ２２０との間に接続された各補助コンデンサ１２が設けられている。そして、各第１共通電極Ｃ１〜Ｃ２２０に接続され、共通電圧が供給され、閉回路とされた第２共通電極１３とが設けられている。   The features of the present invention are summarized below. The first feature includes a first insulating substrate 2, a second insulating substrate 3, and a liquid crystal 4 provided between the two substrates, and a plurality of scans arranged in a matrix on the first insulating substrate 2. An electrode 8 and a plurality of signal electrodes 9 and a plurality of pixel electrodes 10 disposed in the vicinity of the intersections of the scanning electrodes 8 and the signal electrodes 9 are provided. Each scanning electrode 8, each signal electrode 9, each switching element 11 connected to each pixel electrode 10, a plurality of first common electrodes C1 to C220 disposed on the first insulating substrate 2, and each pixel electrode 10 and the auxiliary capacitors 12 connected between the first common electrodes C1 to C220. And the 2nd common electrode 13 connected to each 1st common electrode C1-C220, a common voltage is supplied, and was used as the closed circuit is provided.

第２の特徴は、第１絶縁基板２上に、第２共通電極１３と離れて配置され、各第１共通電極Ｃ１〜Ｃ２２０に接続され、共通電圧が供給され、閉回路とされた第３共通電極１７が設けられている。   The second feature is that a third circuit is arranged on the first insulating substrate 2 apart from the second common electrode 13 and connected to each of the first common electrodes C1 to C220, supplied with a common voltage, and a closed circuit. A common electrode 17 is provided.

第３の特徴は、第２共通電極１３と、第３共通電極１７とを電気的接続させた構成である。   The third feature is a configuration in which the second common electrode 13 and the third common electrode 17 are electrically connected.

第４の特徴は、第２絶縁基板３の背面に共通電極７が配置され、第１共通電極Ｃ１〜Ｃ２２０及び／又は第２共通電極１３及び／又は第３共通電極１７が、共通電極７に電気的接続された構成である。   A fourth feature is that the common electrode 7 is disposed on the back surface of the second insulating substrate 3, and the first common electrodes C <b> 1 to C <b> 220 and / or the second common electrode 13 and / or the third common electrode 17 are formed on the common electrode 7. It is an electrically connected configuration.

第５の特徴は、第２共通電極１３および第３共通電極１７の各幅が、１００μｍないし５００μｍである事である。以上で、本発明の特徴の説明を終わる。   A fifth feature is that each width of the second common electrode 13 and the third common electrode 17 is 100 μm to 500 μm. This completes the description of the features of the present invention.

共通線２１は、走査電極ｇ１１１の左側に形成されている。行電極２２は共通線２１の左側に形成されている。   The common line 21 is formed on the left side of the scanning electrode g111. The row electrode 22 is formed on the left side of the common line 21.

第１共通電極Ｃ１の右側には順に、行電極２３、共通線２４，２５，２６，２７が形成されている。共通線２４〜２７は、第２共通電極１３と、第３共通電極１７との間に接続されている。   A row electrode 23 and common lines 24, 25, 26, and 27 are formed in order on the right side of the first common electrode C1. The common lines 24 to 27 are connected between the second common electrode 13 and the third common electrode 17.

信号電極ｓ１の上側には順に、列電極２８，２９，３０が形成されている。信号電極ｓ５２８の下側には順に、列電極３１，３２，３３が形成されている。   Column electrodes 28, 29, and 30 are sequentially formed on the upper side of the signal electrode s1. Column electrodes 31, 32, and 33 are sequentially formed below the signal electrode s528.

スイッチング素子１１は、各電極２２、ｇ１１１，…ｇ１，２３と、各列電極２９，２８と、各画素電極１０とに接続されている。   The switching element 11 is connected to each electrode 22, g 111,... G 1, 23, each column electrode 29, 28, and each pixel electrode 10.

各補助コンデンサ１２は、各画素電極１０と、共通線２１と、第１共通電極Ｃ１１１，…Ｃ１と、共通線２４との間に形成されている。   Each auxiliary capacitor 12 is formed between each pixel electrode 10, the common line 21, the first common electrodes C 111,... C 1, and the common line 24.

同様に、スイッチング素子１１は、各電極２２、ｇ１１１，…ｇ１，２３と、列電極３１と、各画素電極１０とに接続されている。各補助コンデンサ１２は、各画素電極１０と、共通線２１と、第１共通電極Ｃ１１１，…Ｃ１と、共通線２４との間に形成されている。   Similarly, the switching element 11 is connected to each electrode 22, g 111,... G 1, 23, the column electrode 31, and each pixel electrode 10. Each auxiliary capacitor 12 is formed between each pixel electrode 10, the common line 21, the first common electrodes C 111,... C 1, and the common line 24.

この様に、走査電極ｇ１〜ｇ２２０と、信号電極ｓ１〜ｓ２２０と、画素電極１０に接続された各ＴＦＴを有する画素３４は、有効表示領域である。   In this manner, the scanning electrodes g1 to g220, the signal electrodes s1 to s220, and the pixel 34 having each TFT connected to the pixel electrode 10 are effective display areas.

また、上記画素３４を外れた、各ＴＦＴを有する画素３５は、非表示領域である。この非表示領域は、表示領域が、入力された画像データを正確に表示するために必要である。   Further, the pixel 35 having each TFT outside the pixel 34 is a non-display area. This non-display area is necessary for the display area to accurately display the input image data.

静電破壊防止素子３６は、行電極２３および走査電極ｇ１〜ｇ１１０と、列電極３０との間に接続されている。静電破壊防止素子３６は、走査電極ｇ１〜ｇ１１０から列電極３０を介して、第２共通電極１３へ、静電気で生じた電流を流すものである。また、上記流れとは、逆の流れ方もある。   The electrostatic breakdown preventing element 36 is connected between the row electrode 23 and the scan electrodes g 1 to g 110 and the column electrode 30. The electrostatic breakdown preventing element 36 allows a current generated by static electricity to flow from the scan electrodes g1 to g110 to the second common electrode 13 via the column electrode 30. Moreover, there is also a flow reverse to the above flow.

静電破壊防止素子３７は、行電極２２および走査電極ｇ１１１〜ｇ２２０と、列電極３３との間に接続されている。静電破壊防止素子３７は、走査電極ｇ１１１〜ｇ２２０から列電極３３を介して、第３共通電極１７へ、静電気で生じた電流を流すものである。また、上記流れとは、逆の流れ方もある。   The electrostatic breakdown preventing element 37 is connected between the row electrode 22 and the scan electrodes g111 to g220 and the column electrode 33. The electrostatic breakdown preventing element 37 allows a current generated by static electricity to flow from the scanning electrodes g111 to g220 to the third common electrode 17 via the column electrode 33. Moreover, there is also a flow reverse to the above flow.

保護ダイオード３８は、列電極２９，２８および信号電極ｓ１〜ｓ５２８および列電極３１，３２と、共通線２６との間に接続されている。保護ダイオード３８は、信号電極ｓ１〜ｓ５２８から共通線２６を介して、第２共通電極１３および第３共通電極１７へ、静電気で生じた電流を流すものである。また、上記流れとは、逆の流れ方もある。   The protection diode 38 is connected between the column electrodes 29 and 28, the signal electrodes s 1 to s 528 and the column electrodes 31 and 32, and the common line 26. The protection diode 38 allows a current generated by static electricity to flow from the signal electrodes s1 to s528 to the second common electrode 13 and the third common electrode 17 via the common line 26. Moreover, there is also a flow reverse to the above flow.

上記内容をまとめる。第２共通電極１３と、信号電極ｓ１〜ｓ５２８との間に位置し、第２共通電極１３の近傍に、列電極３３が設けられている。列電極３３と、各走査電極ｇ１１１〜ｇ２２０との間に、各静電破壊防止素子３７が設けられている。   Summarize the above contents. A column electrode 33 is provided between the second common electrode 13 and the signal electrodes s <b> 1 to s <b> 528 and in the vicinity of the second common electrode 13. Each electrostatic breakdown preventing element 37 is provided between the column electrode 33 and each of the scanning electrodes g111 to g220.

また、第３共通電極１７と、信号電極ｓ１〜ｓ５２８との間に位置し、第３共通電極１７の近傍に、列電極３０が設けられている。列電極３０と、各走査電極ｇ１〜ｇ１１０との間に、各静電破壊防止素子３６が設けられている。   A column electrode 30 is provided between the third common electrode 17 and the signal electrodes s <b> 1 to s <b> 528 and in the vicinity of the third common electrode 17. Each electrostatic breakdown preventing element 36 is provided between the column electrode 30 and each of the scanning electrodes g1 to g110.

次に、図１ないし図４に従い、本液晶表示装置１の第６の特徴を説明する。図４は図３のＢ−Ｂ断面図である。図３に示す様に、各走査電極ｇ１１１〜ｇ１１４と、第２共通電極１３との交点において、各走査電極ｇ１１１〜ｇ１１４と、第２共通電極１３との間に第１絶縁層２ｃおよび第２絶縁層４６が積層されている点が特徴である。   Next, a sixth feature of the liquid crystal display device 1 will be described with reference to FIGS. 4 is a cross-sectional view taken along line BB in FIG. As shown in FIG. 3, the first insulating layer 2 c and the second insulating layer 2 c and the second common electrode 13 are arranged between the scan electrodes g 111 to g 114 and the second common electrode 13 at the intersections of the scan electrodes g 111 to g 114 and the second common electrode 13. The feature is that the insulating layer 46 is laminated.

図４に示す様に、第１絶縁層２ｃはＳｉＮＸからなり、層厚は約２０００オングストロームである。第２絶縁層４６は、ａ−Ｓｉ層４７（層厚が約２０００オングストローム）と、ｎ＋ａ−Ｓｉ層４８（層厚が約５００オングストローム）が積層されたものである。 As shown in FIG. 4, the first insulating layer 2c is made of SiN x and has a thickness of about 2000 angstroms. The second insulating layer 46 is formed by laminating an a-Si layer 47 (having a thickness of about 2000 angstroms) and an n + a-Si layer 48 (having a thickness of about 500 angstroms).

スイッチング素子１１は例えば、ａ−ＴＦＴ（アモルファスシリコン、薄膜トランジスタ）からなる。スイッチング素子１１は、第１絶縁層２ｃの上に、ａ−Ｓｉ層と、ｎ＋ａ−Ｓｉ層が積層されている。それ故、上記ａ−Ｓｉ層４７と、ｎ＋ａ−Ｓｉ層４８は、このスイッチング素子１１を製造する時に、同一のプロセスにて成膜することができ、製造コストが安くなる。 The switching element 11 is made of, for example, an a-TFT (amorphous silicon, thin film transistor). In the switching element 11, an a-Si layer and an n + a-Si layer are stacked on the first insulating layer 2c. Therefore, the a-Si layer 47 and the n + a-Si layer 48 can be formed by the same process when the switching element 11 is manufactured, and the manufacturing cost is reduced.

次に、図１、図２、図３、図５に従い、本液晶表示装置１の第７の特徴を説明する。図５は図３のＣ−Ｃ断面図である。図３に示す様に、各走査電極ｇ１１１〜ｇ１１４と、列電極３３との交点において、各走査電極ｇ１１１〜ｇ１１４と、列電極３３との間に第１絶縁層２ｃおよび第２絶縁層４６ａが積層されている点が特徴である。   Next, the seventh feature of the present liquid crystal display device 1 will be described with reference to FIGS. 1, 2, 3, and 5. 5 is a cross-sectional view taken along the line CC of FIG. As shown in FIG. 3, the first insulating layer 2 c and the second insulating layer 46 a are provided between the scan electrodes g 111 to g 114 and the column electrode 33 at the intersections of the scan electrodes g 111 to g 114 and the column electrode 33. It is characterized by being laminated.

図５に示す様に、第１絶縁層２ｃはＳｉＮＸからなり、層厚は約２０００オングストロームである。第２絶縁層４６ａは、ａ−Ｓｉ層４７ａ（層厚が約２０００オングストローム）と、ｎ＋ａ−Ｓｉ層４８ａ（層厚が約５００オングストローム）が積層されたものである。 As shown in FIG. 5, the first insulating layer 2c is made of SiN X and has a thickness of about 2000 angstroms. The second insulating layer 46a is formed by laminating an a-Si layer 47a (layer thickness is about 2000 angstroms) and an n + a-Si layer 48a (layer thickness is about 500 angstroms).

スイッチング素子１１は例えば、ａ−ＴＦＴ（アモルファスシリコン、薄膜トランジスタ）からなる。スイッチング素子１１は、第１絶縁層２ｃの上に、ａ−Ｓｉ層と、ｎ＋ａ−Ｓｉ層が積層されている。それ故、上記ａ−Ｓｉ層４７ａと、ｎ＋ａ−Ｓｉ層４８ａは、このスイッチング素子１１を製造する時に、同一のプロセスにて成膜することができ、製造コストが安くなる。 The switching element 11 is made of, for example, an a-TFT (amorphous silicon, thin film transistor). In the switching element 11, an a-Si layer and an n + a-Si layer are stacked on the first insulating layer 2c. Therefore, the a-Si layer 47a and the n + a-Si layer 48a can be formed by the same process when the switching element 11 is manufactured, and the manufacturing cost is reduced.

次に、図１、図２、図３、図６に従い、本液晶表示装置１の第８の特徴を説明する。図６は図３のＤ−Ｄ断面図である。図３に示す様に、各第１共通電極Ｃ１１１〜Ｃ１１４と、列電極３３との交点において、各第１共通電極Ｃ１１１〜Ｃ１１４と、列電極３３との間に第１絶縁層２ｃおよび第２絶縁層４６ｂが積層されている点が特徴である。   Next, an eighth feature of the liquid crystal display device 1 will be described with reference to FIGS. 1, 2, 3, and 6. FIG. 6 is a cross-sectional view taken along the line DD of FIG. As shown in FIG. 3, at the intersections of the first common electrodes C111 to C114 and the column electrode 33, the first insulating layer 2c and the second insulating layer 2c are formed between the first common electrodes C111 to C114 and the column electrode 33. It is characterized in that the insulating layer 46b is laminated.

図６に示す様に、第１絶縁層２ｃはＳｉＮＸからなり、層厚は約２０００オングストロームである。第２絶縁層４６ｂは、ａ−Ｓｉ層４７ｂ（層厚が約２０００オングストローム）と、ｎ＋ａ−Ｓｉ層４８ｂ（層厚が約５００オングストローム）が積層されたものである。 As shown in FIG. 6, the first insulating layer 2c is made of SiN X and has a thickness of about 2000 angstroms. The second insulating layer 46b is formed by laminating an a-Si layer 47b (layer thickness is about 2000 angstroms) and an n + a-Si layer 48b (layer thickness is about 500 angstroms).

スイッチング素子１１は例えば、ａ−ＴＦＴ（アモルファスシリコン、薄膜トランジスタ）からなる。スイッチング素子１１は、第１絶縁層２ｃの上に、ａ−Ｓｉ層と、ｎ＋ａ−Ｓｉ層が積層されている。それ故、上記ａ−Ｓｉ層４７ｂと、ｎ＋ａ−Ｓｉ層４８ｂは、このスイッチング素子１１を製造する時に、同一のプロセスにて成膜することができ、製造コストが安くなる。 The switching element 11 is made of, for example, an a-TFT (amorphous silicon, thin film transistor). In the switching element 11, an a-Si layer and an n + a-Si layer are stacked on the first insulating layer 2c. Therefore, the a-Si layer 47b and the n + a-Si layer 48b can be formed by the same process when the switching element 11 is manufactured, and the manufacturing cost is reduced.

次に、図１、図２、図３、図７に従い、本液晶表示装置１に用いられるスイッチング素子１１を説明する。図７は図３のＥ−Ｅ断面図である。図７に示す様に、第１絶縁基板２上に、ゲート４９（アルミニュウム等からなり、層厚は約２０００オングストローム）から形成されている。   Next, the switching element 11 used in the present liquid crystal display device 1 will be described with reference to FIGS. 1, 2, 3, and 7. 7 is a cross-sectional view taken along line EE in FIG. As shown in FIG. 7, a gate 49 (made of aluminum or the like, having a layer thickness of about 2000 angstroms) is formed on the first insulating substrate 2.

ゲート４９上に、第１絶縁層２ｃ（ＳｉＮＸからなり、層厚が約２０００オングストローム）が形成されている。第１絶縁層２ｃ上に、ａ−Ｓｉ層４７ｃ（左、右の層厚が約２０００オングストローム）が形成されている。 On the gate 49, a first insulating layer 2c (made of SiN X and having a layer thickness of about 2000 angstroms) is formed. An a-Si layer 47c (left and right layer thicknesses are about 2000 angstroms) is formed on the first insulating layer 2c.

左右のａ−Ｓｉ層４７ｃ上に各々、ｎ＋ａ−Ｓｉ層４８ｃ，４８ｄが形成されている。ｎ＋ａ−Ｓｉ層４８ｃ上に、ソース５０が形成されている。ｎ＋ａ−Ｓｉ層４８ｄ上に、ドレイン５１が形成されている。これらのソース５０と、ａ−Ｓｉ層４７ｃと、ドレイン５１を覆う様に、保護層５２が形成されている。 On the left and right a-Si layers 47c, n + a-Si layers 48c and 48d are formed, respectively. A source 50 is formed on the n + a-Si layer 48c. A drain 51 is formed on the n + a-Si layer 48d. A protective layer 52 is formed so as to cover the source 50, the a-Si layer 47 c, and the drain 51.

ゲート４９は走査電極ｇ１１２に接続されている。ソース５０は信号電極ｓ５２８に接続されている。ドレイン５１は画素電極１０に接続されている。以上の部品により、この液晶表示装置１は構成されている。   The gate 49 is connected to the scan electrode g112. The source 50 is connected to the signal electrode s528. The drain 51 is connected to the pixel electrode 10. The liquid crystal display device 1 is constituted by the above components.

本発明の実施例に係る液晶表示装置１の部分断面図である。It is a fragmentary sectional view of the liquid crystal display device 1 which concerns on the Example of this invention. 液晶表示装置１の電気回路図である。3 is an electric circuit diagram of the liquid crystal display device 1. FIG. 図２のＡ部詳細図である。FIG. 3 is a detailed view of part A in FIG. 2. 図３のＢ−Ｂ断面図である。It is BB sectional drawing of FIG. 図３のＣ−Ｃ断面図である。It is CC sectional drawing of FIG. 図３のＤ−Ｄ断面図である。It is DD sectional drawing of FIG. 図３のＥ−Ｅ断面図である。It is EE sectional drawing of FIG.

符号の説明Explanation of symbols

２ 第１絶縁基板
３ 第２絶縁基板
４ 液晶
８ 走査電極
９ 信号電極
１０ 画素電極
１１ スイッチング素子
１２ 補助コンデンサ
１３ 第２共通電極
Ｃ１〜Ｃ２２０ 第１共通電極 2 First insulating substrate 3 Second insulating substrate 4 Liquid crystal 8 Scan electrode 9 Signal electrode 10 Pixel electrode 11 Switching element 12 Auxiliary capacitor 13 Second common electrode C1 to C220 First common electrode

Claims (5)

第１絶縁基板と、第２絶縁基板と、両基板間に設けられた液晶とを備え、前記第１絶縁基板上において、行列状に配置された複数の走査電極および複数の信号電極と、前記走査電極と前記信号電極との交点近傍に配置された複数の画素電極と、各走査電極と各信号電極と各画素電極に接続された各スイッチング素子と、前記第１絶縁基板上に配置された複数の第１共通電極と、各画素電極と各第１共通電極の間に接続された各補助コンデンサと、各第１共通電極に接続された第２共通電極とを備え、各走査電極と前記第２共通電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された事を特徴とする液晶表示装置。 A plurality of scanning electrodes and a plurality of signal electrodes arranged in a matrix on the first insulating substrate, the first insulating substrate; a second insulating substrate; and a liquid crystal provided between the substrates. A plurality of pixel electrodes arranged in the vicinity of the intersection of the scanning electrode and the signal electrode, each scanning electrode, each signal electrode, each switching element connected to each pixel electrode, and each arranged on the first insulating substrate A plurality of first common electrodes; each auxiliary capacitor connected between each pixel electrode and each first common electrode; and a second common electrode connected to each first common electrode; A liquid crystal display device, wherein a first insulating layer and a second insulating layer are laminated between two electrodes at an intersection with a second common electrode. 前記信号電極と前記第２共通電極との間に位置し、前記第２共通電極の近傍に、列電極が設けられ、前記列電極と各走査電極との間に各静電破壊防止素子が設けられ、各走査電極と前記列電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された事を特徴とする請求項１の液晶表示装置。 A column electrode is provided between the signal electrode and the second common electrode, in the vicinity of the second common electrode, and each electrostatic breakdown preventing element is provided between the column electrode and each scan electrode. The liquid crystal display device according to claim 1, wherein a first insulating layer and a second insulating layer are laminated between the electrodes at the intersection of each scanning electrode and the column electrode. 前記信号電極と前記第２共通電極との間に位置し、前記第２共通電極の近傍に、列電極が設けられ、前記列電極と各走査電極との間に各静電破壊防止素子が設けられ、各第１共通電極と前記列電極との交点において、両電極との間に、第１絶縁層および第２絶縁層が積層された事を特徴とする請求項１の液晶表示装置。 A column electrode is provided between the signal electrode and the second common electrode, in the vicinity of the second common electrode, and each electrostatic breakdown preventing element is provided between the column electrode and each scan electrode. 2. The liquid crystal display device according to claim 1, wherein a first insulating layer and a second insulating layer are laminated between the electrodes at the intersection of each first common electrode and the column electrode. 前記第２共通電極に共通電極が印加され、前記第２共通電極は閉回路とされた事を特徴とする請求項１の液晶表示装置。 2. The liquid crystal display device according to claim 1, wherein a common electrode is applied to the second common electrode, and the second common electrode is a closed circuit. 前記第１絶縁層はＳｉＮＸからなり、前記第２絶縁層は、ａ−Ｓｉ層およびｎ＋ａ−Ｓｉ層が積層されている事を特徴とする請求項１ないし請求項４のいずれか一つに記載された液晶表示装置。 The first insulating layer is made of SiN X , and the second insulating layer is formed by laminating an a-Si layer and an n + a-Si layer. Liquid crystal display device described in one.
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