JP2007134458A - 配線基板の製造方法および半導体装置の製造方法 - Google Patents
配線基板の製造方法および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 93
- 238000009713 electroplating Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 5
- 239000011295 pitch Substances 0.000 abstract 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 20
- 239000013256 coordination polymer Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 238000012360 testing method Methods 0.000 description 10
- 239000000654 additive Substances 0.000 description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 6
- 239000002253 acid Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000035515 penetration Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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Abstract
【解決手段】半導体チップに接続される接続部と、前記接続部を介して前記半導体チップに接続されるパターン配線と、を有する、半導体チップを実装する配線基板の製造方法であって、前記パターン配線上に、前記接続部を電解メッキ法により形成するための給電層を形成する給電層形成工程と、前記給電層上にマスクパターンを形成するマスク工程と、前記マスクパターンから露出する前記給電層をエッチングするエッチング工程と、前記マスクパターンから露出する前記パターン配線上に電解メッキ法により前記接続部を形成する電解メッキ工程と、を有することを特徴とする配線基板の製造方法。
【選択図】図1K
Description
101 給電層
102 マスクパターン
102A 開口部
103 第1の層
104 第2の層
105 第3の層
201 半導体チップ
202 半田バンプ
206 アンダーフィル
V1,V2,V3,v2,v3 ビアプラグ
L1,L3,L3,l1,l2,l3 パターン配線
S コア基板
SR1,sr1 ソルダーレジスト層
D1,D2,d1,d2 絶縁層
CP 接続部
M マスク
Claims (10)
- 半導体チップに接続される接続部と、前記接続部を介して前記半導体チップに接続されるパターン配線と、を有する、半導体チップを実装する配線基板の製造方法であって、
前記パターン配線上に、前記接続部を電解メッキ法により形成するための給電層を形成する給電層形成工程と、
前記給電層上にマスクパターンを形成するマスク工程と、
前記マスクパターンから露出する前記給電層をエッチングするエッチング工程と、
前記マスクパターンから露出する前記パターン配線上に電解メッキ法により前記接続部を形成する電解メッキ工程と、を有することを特徴とする配線基板の製造方法。 - 前記接続部は、複数の層が電解メッキ法により積層されることで形成されることを特徴とする請求項1記載の配線基板の製造方法。
- 前記接続部は、前記パターン配線を構成する材料と同じ材料よりなる最下層を含み、当該最下層が前記パターン配線と接するように形成されることを特徴とする請求項2記載の配線基板の製造方法。
- 前記接続部は、前記パターン配線上に起立するように形成されることを特徴とする請求項1乃至3のうち、いずれか1項記載の配線基板の製造方法。
- 前記接続部の高さが前記接続部の径より大きいことを特徴とする請求項4記載の配線基板の製造方法。
- 前記給電層は、前記パターン配線上とともに該パターン配線の一部を覆う絶縁層上に形成されることを特徴とする請求項1乃至5のうち、いずれか1項記載の配線基板の製造方法。
- 前記電解メッキ工程の後で、前記マスクパターンを除去するとともに、当該マスクパターンを除去することで露出した前記給電層をエッチングする工程をさらに有することを特徴とする請求項1乃至6のうち、いずれか1項記載の配線基板の製造方法。
- 半導体チップと、前記半導体チップに接続される接続部と、前記接続部を介して前記半導体チップに接続されるパターン配線と、を有する、配線基板に半導体チップが実装されてなる半導体装置の製造方法であって、
前記パターン配線上に、前記接続部を電解メッキ法により形成するための給電層を形成する給電層形成工程と、
前記給電層上にマスクパターンを形成するマスク工程と、
前記マスクパターンから露出する前記給電層をエッチングするエッチング工程と、
前記マスクパターンから露出する前記パターン配線上に電解メッキ法により前記接続部を形成する電解メッキ工程と、
前記接続部に半導体チップが接続される実装工程と、を有することを特徴とする半導体装置の製造方法。 - 前記接続部は、前記パターン配線上に起立するように形成されることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記接続部は、複数の層が電解メッキ法により積層されることで形成され、前記半導体チップに接続される層と前記パターン配線に接続される層を構成する材料が異なることを特徴とする請求項8または9記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005325090A JP4718305B2 (ja) | 2005-11-09 | 2005-11-09 | 配線基板の製造方法および半導体装置の製造方法 |
KR1020060104331A KR101195886B1 (ko) | 2005-11-09 | 2006-10-26 | 배선 기판의 제조 방법 및 반도체 장치의 제조 방법 |
US11/594,074 US20070111387A1 (en) | 2005-11-09 | 2006-11-08 | Manufacturing method of wiring board and manufacturing method of semiconductor device |
TW095141468A TW200731436A (en) | 2005-11-09 | 2006-11-09 | Manufacturing method of wiring board and manufacturing method of semiconductor device |
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JP2005325090A JP4718305B2 (ja) | 2005-11-09 | 2005-11-09 | 配線基板の製造方法および半導体装置の製造方法 |
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JP2007134458A true JP2007134458A (ja) | 2007-05-31 |
JP2007134458A5 JP2007134458A5 (ja) | 2008-08-07 |
JP4718305B2 JP4718305B2 (ja) | 2011-07-06 |
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JP (1) | JP4718305B2 (ja) |
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TW (1) | TW200731436A (ja) |
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TWI434405B (zh) * | 2011-06-07 | 2014-04-11 | Univ Nat Chiao Tung | 具有積體電路與發光二極體之異質整合結構及其製作方法 |
US20150195912A1 (en) * | 2014-01-08 | 2015-07-09 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Substrates With Ultra Fine Pitch Flip Chip Bumps |
US9642261B2 (en) * | 2014-01-24 | 2017-05-02 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Composite electronic structure with partially exposed and protruding copper termination posts |
JP6502814B2 (ja) * | 2015-09-25 | 2019-04-17 | 京セラ株式会社 | 指紋センサー用配線基板 |
JP2017063163A (ja) * | 2015-09-25 | 2017-03-30 | 京セラ株式会社 | 指紋センサー用配線基板 |
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JPH0245996A (ja) * | 1988-08-05 | 1990-02-15 | Nec Corp | 混成集積回路の製造方法 |
JPH02162734A (ja) * | 1988-12-16 | 1990-06-22 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH03129831A (ja) * | 1989-10-16 | 1991-06-03 | Nec Corp | 半導体装置の製造方法 |
JPH03139851A (ja) * | 1989-10-25 | 1991-06-14 | Aoi Denshi Kk | 半導体装置 |
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JP2002009203A (ja) * | 2000-06-23 | 2002-01-11 | Dainippon Printing Co Ltd | 配線形成方法と配線基板 |
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JP2002141437A (ja) * | 2000-11-06 | 2002-05-17 | Dainippon Printing Co Ltd | Cspタイプの半導体装置及びその作製方法 |
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US6890829B2 (en) * | 2000-10-24 | 2005-05-10 | Intel Corporation | Fabrication of on-package and on-chip structure using build-up layer process |
US6660633B1 (en) * | 2002-02-26 | 2003-12-09 | Advanced Micro Devices, Inc. | Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed |
DE10355953B4 (de) * | 2003-11-29 | 2005-10-20 | Infineon Technologies Ag | Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung |
KR100597993B1 (ko) * | 2004-04-08 | 2006-07-10 | 주식회사 네패스 | 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법 |
JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US7179738B2 (en) * | 2004-06-17 | 2007-02-20 | Texas Instruments Incorporated | Semiconductor assembly having substrate with electroplated contact pads |
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2005
- 2005-11-09 JP JP2005325090A patent/JP4718305B2/ja not_active Expired - Fee Related
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2006
- 2006-10-26 KR KR1020060104331A patent/KR101195886B1/ko active IP Right Grant
- 2006-11-08 US US11/594,074 patent/US20070111387A1/en not_active Abandoned
- 2006-11-09 TW TW095141468A patent/TW200731436A/zh unknown
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JPH03129831A (ja) * | 1989-10-16 | 1991-06-03 | Nec Corp | 半導体装置の製造方法 |
JPH03139851A (ja) * | 1989-10-25 | 1991-06-14 | Aoi Denshi Kk | 半導体装置 |
JPH0613385A (ja) * | 1992-06-24 | 1994-01-21 | Matsushita Electric Ind Co Ltd | 突起電極の製造方法 |
JPH0964493A (ja) * | 1995-08-29 | 1997-03-07 | Nippon Mektron Ltd | 回路基板の配線構造及びその形成法 |
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JP2002009203A (ja) * | 2000-06-23 | 2002-01-11 | Dainippon Printing Co Ltd | 配線形成方法と配線基板 |
JP2002050851A (ja) * | 2000-08-02 | 2002-02-15 | Dainippon Printing Co Ltd | 配線形成方法および配線部材 |
JP2002141437A (ja) * | 2000-11-06 | 2002-05-17 | Dainippon Printing Co Ltd | Cspタイプの半導体装置及びその作製方法 |
JP2002170845A (ja) * | 2000-12-04 | 2002-06-14 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2002246744A (ja) * | 2001-02-20 | 2002-08-30 | Nec Corp | 導体形成方法およびこれを用いた多層配線基板製造方法 |
Also Published As
Publication number | Publication date |
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US20070111387A1 (en) | 2007-05-17 |
TW200731436A (en) | 2007-08-16 |
KR101195886B1 (ko) | 2012-10-30 |
JP4718305B2 (ja) | 2011-07-06 |
KR20070049957A (ko) | 2007-05-14 |
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