JP2007123515A - Method for preventing warpage in jig for manufacturing capacitor - Google Patents
Method for preventing warpage in jig for manufacturing capacitor Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims description 30
- 239000007787 solid Substances 0.000 claims description 12
- 230000002265 prevention Effects 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 28
- 238000000465 moulding Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 125000004432 carbon atom Chemical group C* 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229920001940 conductive polymer Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 125000000217 alkyl group Chemical group 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- -1 Ta 2 O 5 Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- YADSGOSSYOOKMP-UHFFFAOYSA-N dioxolead Chemical compound O=[Pb]=O YADSGOSSYOOKMP-UHFFFAOYSA-N 0.000 description 2
- QXYJCZRRLLQGCR-UHFFFAOYSA-N dioxomolybdenum Chemical compound O=[Mo]=O QXYJCZRRLLQGCR-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical compound O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BFRGSJVXBIWTCF-UHFFFAOYSA-N niobium monoxide Chemical compound [Nb]=O BFRGSJVXBIWTCF-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920000128 polypyrrole Polymers 0.000 description 2
- 229920000123 polythiophene Polymers 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- DZKDPOPGYFUOGI-UHFFFAOYSA-N tungsten(iv) oxide Chemical compound O=[W]=O DZKDPOPGYFUOGI-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- SIKJAQJRHWYJAI-UHFFFAOYSA-N Indole Chemical compound C1=CC=C2NC=CC2=C1 SIKJAQJRHWYJAI-UHFFFAOYSA-N 0.000 description 1
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 125000003545 alkoxy group Chemical group 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 125000000843 phenylene group Chemical group C1(=C(C=CC=C1)*)* 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229920000414 polyfuran Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229930195734 saturated hydrocarbon Natural products 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 125000001424 substituent group Chemical group 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- UGNWTBMOAKPKBL-UHFFFAOYSA-N tetrachloro-1,4-benzoquinone Chemical compound ClC1=C(Cl)C(=O)C(Cl)=C(Cl)C1=O UGNWTBMOAKPKBL-UHFFFAOYSA-N 0.000 description 1
- PCCVSPMFGIFTHU-UHFFFAOYSA-N tetracyanoquinodimethane Chemical compound N#CC(C#N)=C1C=CC(=C(C#N)C#N)C=C1 PCCVSPMFGIFTHU-UHFFFAOYSA-N 0.000 description 1
- 125000004417 unsaturated alkyl group Chemical group 0.000 description 1
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Abstract
Description
本発明は、コンデンサ製造用冶具の反り防止方法に関する。 The present invention relates to a method for preventing warpage of a jig for manufacturing a capacitor.
パソコン等に使用されるＣＰＵ（中央演算処理装置）周りのコンデンサは、電圧変動を抑え、高リップル（ripple）通過時の発熱を低くするために、高容量かつ低ＥＳＲ（等価直列抵抗）であることが求められている。 Capacitors around CPU (Central Processing Unit) used in personal computers have high capacity and low ESR (Equivalent Series Resistance) to suppress voltage fluctuation and reduce heat generation when passing through high ripple. It is demanded.
一般には、アルミニウム固体電解コンデンサや、タンタル固体電解コンデンサが複数個使用されている。
このような固体電解コンデンサは、表面層に微細な細孔を有するアルミニウム箔や、内部に微小な細孔を有するタンタル粉の焼結体を一方の電極（導電体）とし、該電極の表層に形成した誘電体層と該誘電体層上に設けられた他方の電極（通常は、半導体層）とから構成されている。
In general, a plurality of aluminum solid electrolytic capacitors and tantalum solid electrolytic capacitors are used.
Such a solid electrolytic capacitor uses a sintered body of aluminum foil having fine pores in the surface layer or tantalum powder having fine pores inside as one electrode (conductor), and on the surface layer of the electrode. The dielectric layer is formed and the other electrode (usually a semiconductor layer) provided on the dielectric layer.
半導体層を他方の電極とするコンデンサの該半導体層の形成方法としては、例えば、特許第１８６８７２２号公報（特許文献１）、特許第１９８５０５６号公報（特許文献２）や特許第２０５４５０６号公報（特許文献３）に記載された通電手法により形成する方法がある。各々、表面に誘電体層を設けた導電体を半導体層形成溶液に漬け、導電体側を陽極にして半導体層形成溶液中に用意した外部電極（陰極）との間に電圧を印加する（電流を流す）ことにより半導体層を形成する方法である。 As a method for forming the semiconductor layer of the capacitor having the semiconductor layer as the other electrode, for example, Japanese Patent No. 1868722 (Patent Document 1), Japanese Patent No. 1985056 (Patent Document 2) and Japanese Patent No. 2054506 (Patent Patent) There is a method of forming by an energization method described in the literature 3). In each case, a conductor provided with a dielectric layer on the surface is dipped in a semiconductor layer forming solution, and a voltage is applied between the external electrode (cathode) prepared in the semiconductor layer forming solution with the conductor side as an anode (current is applied). This is a method of forming a semiconductor layer by flowing.
このように、いずれの製造方法でも導電体（陽極基体）を各種溶液に浸漬し通電し引き上げる操作を含むため、浸漬、通電及び引き上げ操作を効率的に行なう必要がある。このため、通常、固体電解コンデンサ素子の製造においては長尺の基板（コンデンサ製造用冶具）に複数のソケットを設け、各ソケットに導電体を取り付けて同時に処理している。
しかしこのようなコンデンサ製造用冶具に対して高温乾燥・室温冷却する操作を繰り返すと冶具が反り、機械装置により自動的に導電体を冶具の連結ソケット部に挿入する場合、反った冶具に挿入することが困難となる。
As described above, since any of the manufacturing methods includes an operation of immersing the conductor (anode base) in various solutions, energizing and pulling up, it is necessary to efficiently perform the dipping, energizing and lifting operations. For this reason, normally, in the manufacture of a solid electrolytic capacitor element, a plurality of sockets are provided on a long substrate (capacitor manufacturing jig), and a conductor is attached to each socket for simultaneous processing.
However, when such a capacitor manufacturing jig is repeatedly subjected to high temperature drying and room temperature cooling, the jig warps, and when a mechanical device automatically inserts a conductor into the connecting socket portion of the jig, the jig is inserted into the warped jig. It becomes difficult.
コンデンサ製造用冶具の反りについては、一般に冶具の片面のみに部品を搭載した場合には、冶具の長手方向に反りを生じ、両面に搭載した場合には幅方向に反りを生ずる。
冶具は基板が厚いと反りにくくなるが、コンデンサ製造冶具は複数枚規定間隔を空けてフレームに並列に装着した後に、冶具の連結ソケットに挿入された導電体に誘電体層、導電体層（電極層）を形成するので、冶具の厚さが所定以上厚くなるとフレームに装着される冶具数が少なくなり、一度に製造されるコンデンサ素子の数が減少するので好ましくない。
Regarding the warpage of a capacitor manufacturing jig, in general, when a component is mounted on only one side of the jig, warpage occurs in the longitudinal direction of the jig, and when mounted on both sides, warpage occurs in the width direction.
The jig is hard to warp when the substrate is thick, but after the capacitor manufacturing jig is mounted in parallel to the frame with a specified interval, a dielectric layer, a conductor layer (electrode) are attached to the conductor inserted in the connection socket of the jig. Therefore, if the thickness of the jig is larger than a predetermined thickness, the number of jigs attached to the frame is reduced, and the number of capacitor elements manufactured at one time is reduced, which is not preferable.
したがって、本発明の課題は、表面及び裏面に各種部品を搭載したコンデンサ製造用冶具の反り防止方法を提供することにある。 Therefore, the subject of this invention is providing the curvature prevention method of the jig for capacitor | condenser manufacture which mounted various components on the surface and the back surface.
本発明者らは、上記背景技術で説明した、例えば図１の構成のコンデンサ製造用冶具に搭載したガラス混入エポキシ基板（１）上の各部品の搭載位置を種々変更して詳細に検討し、部品の配置を特定の範囲に規定すれば、反応液に浸漬後これを取りだし高温（約１５０℃）で乾燥し、室温に戻す操作を繰り返しても反りを生じないことを確認し、冶具の反りを防止することができることを見出した。 The inventors of the present invention have studied in detail by variously changing the mounting position of each component on the glass-mixed epoxy substrate (1) mounted on the capacitor manufacturing jig having the configuration shown in FIG. If the arrangement of the parts is defined within a specific range, it is confirmed that no warpage will occur even if the operation is repeated after being immersed in the reaction solution, taken out at high temperature (about 150 ° C), and returned to room temperature. It was found that can be prevented.
すなわち、本発明は以下のコンデンサ製造用冶具の反り防止方法及びコンデンサ製造用冶具を提供する。
１．複数個の導電体の表面に通電手法により誘電体層または半導体層を形成するための長尺状の基板（１）の片方の長辺にコンデンサ素子接続部（２）を有し、前記基板上の幅方向の片面（表面）に、チップ部品１（３ａ）、反対面（裏面）にチップ部品５（５ｂ）、チップ部品６（４ｂ）の各部品を搭載し、それらチップ部品が前記基板の長手方向に複数回繰り返し配置されたコンデンサ製造用冶具の反り防止方法であって、前記基板の幅Ｗに対して、コンデンサ素子接続部を有する側の長辺からのチップ部品１中央部までの距離をＬ１、チップ部品５中央部までの距離をＬ４、チップ部品６中央部までの距離をＬ５としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載することを特徴とするコンデンサ製造用冶具の反り防止方法：
Ｌ１＝０．９９Ｗ〜０．６６Ｗ、
Ｌ４＝０〜０．５Ｗ、
Ｌ５＝０．５Ｗ±０．１５Ｗ、
２．複数個の導電体の表面に通電手法により誘電体層または半導体層を形成するための長尺状の基板（１）の片方の長辺にコンデンサ素子接続部（２）を有し、前記基板上の幅方向の片面（表面）に、チップ部品２（３ｂ）、反対面（裏面）にチップ部品３（５ａ）、チップ部品４（４ａ）の各部品を搭載し、それらチップ部品が前記基板の長手方向に複数回繰り返し配置されたコンデンサ製造用冶具の反り防止方法であって、前記基板の幅Ｗに対して、コンデンサ素子接続部を有する側の長辺からのチップ部品２中央部までの一方の長辺からの距離をＬ２、チップ部品３中央部までの距離をＬ６、チップ部品４中央部までの距離をＬ７としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載することを特徴とするコンデンサ製造用冶具の反り防止方法：
Ｌ２＝０．５Ｗ±０．１５Ｗ、
Ｌ６＝０〜０．９Ｗ、
Ｌ７＝０．９９Ｗ〜０．６６Ｗ。
３．複数個の導電体の表面に通電手法により誘電体層または半導体層を形成するための長尺状の基板（１）の片方の長辺にコンデンサ素子接続部（２）を有し、前記基板上の幅方向の片面（表面）に、チップ部品１（３ａ）、チップ部品２（３ｂ）、反対面（裏面）にチップ部品３（５ａ）、チップ部品４（４ａ）、チップ部品５（５ｂ）、チップ部品６（４ｂ）の各部品を搭載し、それらチップ部品が前記基板の長手方向に複数回繰り返し配置されたコンデンサ製造用冶具の反り防止方法であって、前記基板の幅Ｗに対して、
［１］コンデンサ素子接続部を有する側の長辺からのチップ部品１中央部までの距離をＬ１、チップ部品５中央部までの距離をＬ４、チップ部品６中央部までの距離をＬ５としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載することを特徴とするパターン、および
［２］コンデンサ素子接続部を有する側の長辺からのチップ部品２中央部までの一方の長辺からの距離をＬ２、チップ部品３中央部までの距離をＬ６、チップ部品４中央部までの距離をＬ７としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載するパターン
を導電体１つおきに組み合わせたことを特徴とする前記１または２に記載の固体電解コンデンサ製造用冶具の反り防止方法：
Ｌ１＝０．９９Ｗ〜０．６６Ｗ、
Ｌ２＝０．５Ｗ±０．１５Ｗ、
Ｌ４＝０〜０．５Ｗ、
Ｌ５＝０．５Ｗ±０．１５Ｗ、
Ｌ６＝０〜０．９Ｗ、
Ｌ７＝０．９９Ｗ〜０．６６Ｗ。
４．基板がガラス混入エポキシ基板である前記１〜３のいずれかに記載の固体電解コンデンサ製造用冶具の反り防止方法。
５．前記１〜４のいずれかに記載の反り防止方法の施されている固体電解コンデンサ製造用冶具。
６．前記５に記載のコンデンサ製造用冶具を用いて得られた固体電解コンデンサ群。
That is, the present invention provides the following method for preventing warpage of a capacitor manufacturing jig and a capacitor manufacturing jig.
1. A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, The chip component 1 (3a) is mounted on one side (front surface) of the width direction, and the chip component 5 (5b) and chip component 6 (4b) are mounted on the opposite surface (back surface), and these chip components are mounted on the substrate. A method for preventing warpage of a jig for manufacturing a capacitor that is repeatedly arranged a plurality of times in the longitudinal direction, the distance from the long side having the capacitor element connection portion to the center of the chip component 1 with respect to the width W of the substrate L1 is the distance to the center of the chip component 5 and L5 is the distance to the center of the chip component 5, and the distance to the center of the
L1 = 0.99W to 0.66W,
L4 = 0 to 0.5W,
L5 = 0.5W ± 0.15W,
2. A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, The chip component 2 (3b) is mounted on one side (front surface) of the width direction, and the chip component 3 (5a) and chip component 4 (4a) are mounted on the opposite surface (back surface). A method for preventing warpage of a jig for manufacturing a capacitor that is repeatedly arranged a plurality of times in the longitudinal direction, wherein one side from the long side on the side having the capacitor element connection portion to the center portion of the chip component 2 with respect to the width W of the substrate When the distance from the long side is L2, the distance to the center part of the chip part 3 is L6, and the distance to the center part of the chip part 4 is L7, the following conditions are satisfied and the parts are mounted so as not to contact each other. Capacitor manufacturing characterized by Jig of warp prevention method:
L2 = 0.5W ± 0.15W,
L6 = 0-0.9W,
L7 = 0.99W to 0.66W.
3. A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, Chip part 1 (3a), chip part 2 (3b) on one side (front surface) of the width direction, chip part 3 (5a), chip part 4 (4a), chip part 5 (5b) on the opposite side (back side) A method for preventing warping of a capacitor manufacturing jig in which each component of the chip component 6 (4b) is mounted and the chip component is repeatedly arranged in the longitudinal direction of the substrate, and is relative to the width W of the substrate. ,
[1] When the distance from the long side having the capacitor element connecting portion to the center of the chip component 1 is L1, the distance to the center of the chip component 5 is L4, and the distance to the center of the
L1 = 0.99W to 0.66W,
L2 = 0.5W ± 0.15W,
L4 = 0 to 0.5W,
L5 = 0.5W ± 0.15W,
L6 = 0-0.9W,
L7 = 0.99W to 0.66W.
4). 4. The method for preventing warpage of a jig for manufacturing a solid electrolytic capacitor according to any one of 1 to 3, wherein the substrate is a glass-mixed epoxy substrate.
5. A jig for manufacturing a solid electrolytic capacitor, wherein the warpage preventing method according to any one of 1 to 4 is applied.
6). 6. A solid electrolytic capacitor group obtained using the capacitor manufacturing jig according to 5 above.
搭載部品の配置場所を規定した本発明のコンデンサ製造冶具によれば、高温乾燥及び例冷却（室温）の加熱サイクルを繰り返す際の反りが発生しない。 According to the capacitor manufacturing jig of the present invention in which the placement location of the mounted parts is specified, no warpage occurs when the heating cycle of high temperature drying and example cooling (room temperature) is repeated.
本発明によるコンデンサ製造用冶具は、複数の導電体を支持するとともに通電手法によって導電体表面に誘電体層または半導体層を形成するための長尺の部材であり、通電制御を可能とするための電気回路を搭載した基板を含む。
本発明では、前記基板上の部品搭載の位置を上記のように規定することにより、コンデンサ製造用冶具全体の反りを抑制する。
なお、具体的な部品は回路の目的に応じて設計されるが、例えば、定電流回路を構成する場合、チップ部品１、２として整流ダイオード、チップ部品３、５として抵抗、また、チップ部品４、６として電界効果トランジスタを用いた例が挙げられる。
The jig for manufacturing a capacitor according to the present invention is a long member for supporting a plurality of conductors and forming a dielectric layer or a semiconductor layer on the surface of the conductor by an energization method, and enabling energization control. Includes a board with an electrical circuit.
In the present invention, the warpage of the entire capacitor manufacturing jig is suppressed by defining the component mounting position on the substrate as described above.
Specific components are designed according to the purpose of the circuit. For example, when configuring a constant current circuit, rectifier diodes as chip components 1 and 2, resistors as chip components 3 and 5, and
本発明の導電体としては、タンタル、アルミニウム、ニオブ或いはこれらを主成分とする合金等の弁作用金属または、一酸化ニオブ等の金属酸化物が使用できる。
導電体の形状は特に限定されず、箔状、板状、棒状、導電体自身を粉状にして成形または成形後焼結した形状等として用いてもよい。導電体表面をエッチング等で処理して、微細な細孔を有するようにしてもよい。導電体を粉状にして成形体形状または成形後焼結した形状とする場合には、成形時の圧力を適当に選択することにより、成形または焼結後の内部に微小な細孔を設けることができる。また、導電体を粉状にして成形体形状または成形後焼結した形状とする場合は、成形時に別途用意した引き出しリード線の一部を導電体と共に成形し、引き出しリード線の成形外部の箇所を、コンデンサの一方の電極の引き出しリードとすることもできる。勿論、導電体に引き出しリードを直接接続することも可能である。箔状または棒状の場合、後に記述する連結ソケットに挿入可能なリード線を接続しておく。
As the conductor of the present invention, a valve action metal such as tantalum, aluminum, niobium or an alloy containing these as a main component, or a metal oxide such as niobium monoxide can be used.
The shape of the conductor is not particularly limited, and may be used as a foil shape, a plate shape, a rod shape, a shape in which the conductor itself is powdered, molded, or sintered after molding. The conductor surface may be processed by etching or the like to have fine pores. When the conductor is powdered to form a molded body or a sintered shape after molding, fine pores should be provided in the interior after molding or sintering by appropriately selecting the pressure during molding. Can do. If the conductor is powdered to form a molded body or a sintered shape after molding, a part of the lead wire prepared separately at the time of molding is molded together with the conductor, and the outside of the lead wire is molded. Can be used as a lead lead for one electrode of the capacitor. Of course, it is also possible to connect the lead lead directly to the conductor. In the case of a foil shape or a rod shape, a lead wire that can be inserted is connected to a connecting socket described later.
本発明の導電体表面に形成される誘電体層としては、Ｔａ2Ｏ5、Ａｌ2Ｏ3、Ｚｒ2Ｏ3、Ｎｂ2Ｏ5等の金属酸化物から選ばれる少なくとも１つを主成分とする誘電体層が挙げられる。 The dielectric layer formed on the surface of the conductor of the present invention contains at least one selected from metal oxides such as Ta 2 O 5 , Al 2 O 3 , Zr 2 O 3 , and Nb 2 O 5 as a main component. And a dielectric layer.
一方、本発明のコンデンサの他方の電極としては、有機半導体および無機半導体から選ばれる少なくとも１種の化合物が挙げられるが、ここで前記の化合物を後述する通電手法により形成することが肝要である。 On the other hand, the other electrode of the capacitor of the present invention includes at least one compound selected from an organic semiconductor and an inorganic semiconductor, but it is important to form the compound by an energization method described later.
有機半導体の具体例としては、ベンゾピロリン４量体とクロラニルからなる有機半導体、テトラチオテトラセンを主成分とする有機半導体、テトラシアノキノジメタンを主成分とする有機半導体、下記一般式（１）または（２）で示される繰り返し単位を含む高分子にドーパントをドープした導電性高分子を主成分とした有機半導体が挙げられる。 Specific examples of the organic semiconductor include an organic semiconductor composed of benzopyrroline tetramer and chloranil, an organic semiconductor mainly composed of tetrathiotetracene, an organic semiconductor mainly composed of tetracyanoquinodimethane, and the following general formula (1) Or the organic semiconductor which has as a main component the conductive polymer which doped the dopant to the polymer containing the repeating unit shown by (2) is mentioned.
さらに、本発明においては、前記一般式（１）で示される繰り返し単位を含む導電性高分子として、好ましくは下記一般式（３）で示される構造単位を繰り返し単位として含む導電性高分子が挙げられる。 Furthermore, in the present invention, the conductive polymer containing a repeating unit represented by the general formula (1) is preferably a conductive polymer containing a structural unit represented by the following general formula (3) as a repeating unit. It is done.
このような化学構造を含む導電性高分子は、荷電されており、ドーパントがドープされる。ドーパントは特に限定されず公知のドーパントが使用できる。
式（１）乃至（３）で示される繰り返し単位を含む高分子としては、例えば、ポリアニリン、ポリオキシフェニレン、ポリフェニレンサルファイド、ポリチオフェン、ポリフラン、ポリピロール、ポリメチルピロール、およびこれらの置換誘導体や共重合体などが挙げられる。中でも、ポリピロール、ポリチオフェン及びこれらの置換誘導体（例えば、ポリ（３，４−エチレンジオキシチオフェン）等）が好ましい。
A conductive polymer containing such a chemical structure is charged and doped with a dopant. A dopant is not specifically limited, A well-known dopant can be used.
Examples of the polymer containing the repeating unit represented by the formulas (1) to (3) include polyaniline, polyoxyphenylene, polyphenylene sulfide, polythiophene, polyfuran, polypyrrole, polymethylpyrrole, and substituted derivatives and copolymers thereof. Etc. Among these, polypyrrole, polythiophene, and substituted derivatives thereof (for example, poly (3,4-ethylenedioxythiophene)) are preferable.
無機半導体の具体例としては、二酸化モリブデン、二酸化タングステン、二酸化鉛、二酸化マンガン等から選ばれる少なくとも１種の化合物が挙げられる。
上記有機半導体および無機半導体として、電導度１０-2〜１０3Ｓ／ｃｍの範囲のものを使用すると、作製したコンデンサのＥＳＲ値が小さくなり好ましい。
Specific examples of the inorganic semiconductor include at least one compound selected from molybdenum dioxide, tungsten dioxide, lead dioxide, manganese dioxide and the like.
When the organic semiconductor and the inorganic semiconductor have an electric conductivity in the range of 10 −2 to 10 3 S / cm, the ESR value of the manufactured capacitor is preferably reduced.
前述した半導体層は、通電操作を行わない純粋な化学反応（溶液反応、気相反応、固液反応およびそれらの組み合わせ）によって形成したり、通電手法によって形成したり、あるいはこれらの方法を組み合わせて形成するが、本発明では、半導体層形成工程で少なくとも１回は通電手法を採用する。また、通電手法により半導体層を形成する場合に、少なくとも１回の通電を、通電時に定電流源により行うことにより本発明の目的が達成される。 The semiconductor layer described above is formed by a pure chemical reaction (solution reaction, gas phase reaction, solid-liquid reaction, and a combination thereof) without conducting an energization operation, formed by an energization method, or a combination of these methods. In the present invention, the energization method is adopted at least once in the semiconductor layer forming step. Further, when the semiconductor layer is formed by an energization method, the object of the present invention is achieved by performing energization at least once by a constant current source during energization.
コンデンサ素子接続部には市販の連結ソケットを用いてもよい。連結ソケットのピッチ間隔としては、市販されている１ｍｍ、１．２７ｍｍ、１．７７８ｍｍ、２．０ｍｍ、２．５４ｍｍのうち任意のものを導電体の形状に応じて使用可能である。連結ソケットの連結数は６４個のものが市販されているので、６４個のものを最大５個基板に実装しても使用可能である。長さ２．５４ｍｍ×６４×５＝８１２．８ｍｍの長さ（基板の左右に設けられる電極部分を含まない）の基板でも適応できる。一般には基板の長さが長くなると反りが発生しやすくなるが、本方法を適応すれば、この長さの基板でも反りの発生はごく僅かとなる。また、連結数を６４個以下にして使用することも可能であるが、基板の長さを５０ｍｍ以下で使用すると、反りの発生は少ないが、一度に作成できるコンデンサ数が減少する。
本発明に使用される基板の幅は、通常１０〜６０ｍｍである。１０ｍｍ以下であると大きい部品の実装をしにくくなり、また、６０ｍｍを超えると基板の材料費が高くなる。基板としては、ガラス混入エポキシ基板が好ましく使用される。
A commercially available connection socket may be used for the capacitor element connection portion. As a pitch interval of the connection socket, any one of commercially available 1 mm, 1.27 mm, 1.778 mm, 2.0 mm, and 2.54 mm can be used according to the shape of the conductor. Since 64 sockets with 64 connection sockets are commercially available, even if 64 sockets are mounted on a maximum of 5 boards, they can be used. A substrate having a length of 2.54 mm × 64 × 5 = 812.8 mm (not including electrode portions provided on the left and right sides of the substrate) is also applicable. In general, warping tends to occur when the length of the substrate becomes long. However, if this method is applied, the warping is very small even with this length of substrate. Although it is possible to use with the number of connections being 64 or less, when the substrate is used with a length of 50 mm or less, the number of capacitors that can be formed at one time is reduced, although the occurrence of warpage is small.
The width of the substrate used in the present invention is usually 10 to 60 mm. If it is 10 mm or less, it will be difficult to mount a large component, and if it exceeds 60 mm, the material cost of the substrate will be high. As the substrate, a glass-mixed epoxy substrate is preferably used.
以下、本発明の具体例についてさらに詳細に説明するが、以下の例により本発明は限定されるものではない。 Hereinafter, specific examples of the present invention will be described in more detail, but the present invention is not limited to the following examples.
実施例１〜３９及び比較例１〜２１
図１に示す搭載部品構成で基板の厚さ１．６ｍｍ，幅Ｗ３３ｍｍのコンデンサ製造冶具に対して、第一の整流ダイオード（チップ部品１）中央部までの距離をＬ１、第二の整流ダイオード（チップ部品２）中央部までの距離をＬ２、第二の抵抗（チップ部品５）中央部までの距離をＬ４、第二の電界効果トランジスタ（ＦＥＴ：チップ部品６）中央部までの距離をＬ５、第一の抵抗（チップ部品３）中央部までの距離をＬ６、第一の電界効果トランジスタ（ＦＥＴ：チップ部品４）中央部までの距離Ｌ７を表１に示す値に設定した、各コンデンサ製造冶具をヒ−トサイクル装置で、１５０℃３０分放置と２５℃３０分放置を連続して５００回繰り返した後に冶具を側面から見た最大反り（ｄ（ｍｍ））（図２参照）を測定した結果を表１〜３に合わせて示す。
Examples 1-39 and Comparative Examples 1-21
For the capacitor manufacturing jig having a substrate thickness of 1.6 mm and a width W of 33 mm in the mounting component configuration shown in FIG. 1, the distance to the center of the first rectifier diode (chip component 1) is L1, and the second rectifier diode ( Chip component 2) L2 is the distance to the center, L4 is the distance to the center of the second resistor (chip component 5), L5 is the distance to the center of the second field effect transistor (FET: chip component 6), Each capacitor manufacturing jig in which the distance to the central portion of the first resistor (chip component 3) is set to L6, and the distance L7 to the central portion of the first field effect transistor (FET: chip component 4) is set to the values shown in Table 1. In a heat cycle device, the maximum warpage (d (mm)) of the jig viewed from the side surface (see FIG. 2) was measured after 500 times of standing at 150 ° C. for 30 minutes and 25 ° C. for 30 minutes. Tables 1-3 Together shown.
基板の厚さが、１．０ｍｍ及び１．９ｍｍの場合も同様な実験を行い、同様の結果を得た。すなわち、厚さ１．０ｍｍの場合は実施例の条件では、ｄは０．１ｍｍ未満、比較例の条件では、厚さ１．６ｍｍの基板に比較して各５倍の反りを認めた。また厚さ１．９ｍｍの基板の場合、実施例の条件ではｄは０．１ｍｍ未満、比較例の条件では、厚さ１．６ｍｍの基板と同様な反りを認めた。なお、チップ部品と同様に、連結ソケットについても図１で示す位置Ｌ３（ソケット最端部までの距離）が−１、０、２ｍｍの場合及び連結ソケットが無い場合について同様な実験を行ったが、反りへの影響は認められなかった。 Similar experiments were performed when the substrate thickness was 1.0 mm and 1.9 mm, and similar results were obtained. That is, when the thickness was 1.0 mm, d was less than 0.1 mm under the conditions of the example, and under the conditions of the comparative example, 5 times each warp was recognized as compared with the 1.6 mm thick substrate. In the case of a substrate having a thickness of 1.9 mm, d was less than 0.1 mm under the conditions of the example, and warping similar to that of the substrate having a thickness of 1.6 mm was recognized under the conditions of the comparative example. Similar to the chip component, the same experiment was performed for the connection socket when the position L3 (distance to the socket end) shown in FIG. 1 is -1, 0, 2 mm and when there is no connection socket. No effect on warping was observed.
上記実施例及び比較例の結果から明らかなように、表面に誘電体層を形成した複数個の導電体に通電手法により半導体層を形成するための、各種部品（導電体ピン連結ソケット、整流ダイオード、抵抗、電界効果トランジスタ（ＦＥＴ））を搭載した長尺状の基板上の部品の配置を特定の範囲（特許請求の範囲に規定した範囲）として本発明によれば基板の反りが認められず、長期間に亘って安定して使用できる。 As is apparent from the results of the above-described examples and comparative examples, various components (conductor pin connection socket, rectifier diode) for forming a semiconductor layer on a plurality of conductors having a dielectric layer formed on the surface by a current application method In accordance with the present invention, no warpage of the substrate is recognized with the arrangement of the components on the long substrate mounted with a resistor, a field effect transistor (FET) as a specific range (range defined in the claims). Can be used stably over a long period of time.
１ 基板
２ ６４丸ピン連結ソケット（コンデンサ素子接続部）
３ 整流ダイオード
４ 電界効果トランジスタ（ＦＥＴ）
５ 抵抗
６ 電極（誘電体層形成用）
７ 電極（半導体層形成用）
８ 電気回路
ｄ 最大反り
1 Substrate 2 64 round pin connection socket (capacitor element connection part)
3 Rectifier diode 4 Field effect transistor (FET)
5
7 Electrode (for semiconductor layer formation)
8 Electric circuit d Maximum warpage
Claims (6)
Ｌ１＝０．９９Ｗ〜０．６６Ｗ、
Ｌ４＝０〜０．５Ｗ、
Ｌ５＝０．５Ｗ±０．１５Ｗ、 A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, The chip component 1 (3a) is mounted on one side (front surface) of the width direction, and the chip component 5 (5b) and chip component 6 (4b) are mounted on the opposite surface (back surface), and these chip components are mounted on the substrate. A method for preventing warpage of a jig for manufacturing a capacitor that is repeatedly arranged a plurality of times in the longitudinal direction, the distance from the long side having the capacitor element connection portion to the center of the chip component 1 with respect to the width W of the substrate L1 is the distance to the center of the chip component 5 and L5 is the distance to the center of the chip component 5, and the distance to the center of the chip component 6 is L5. Warpage prevention of manufacturing jigs Law:
L1 = 0.99W to 0.66W,
L4 = 0 to 0.5W,
L5 = 0.5W ± 0.15W,
Ｌ２＝０．５Ｗ±０．１５Ｗ、
Ｌ６＝０〜０．９Ｗ、
Ｌ７＝０．９９Ｗ〜０．６６Ｗ。 A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, The chip component 2 (3b) is mounted on one side (front surface) of the width direction, and the chip component 3 (5a) and chip component 4 (4a) are mounted on the opposite surface (back surface). A method for preventing warpage of a jig for manufacturing a capacitor that is repeatedly arranged a plurality of times in the longitudinal direction, wherein one side from the long side on the side having the capacitor element connection portion to the center portion of the chip component 2 with respect to the width W of the substrate When the distance from the long side is L2, the distance to the center part of the chip part 3 is L6, and the distance to the center part of the chip part 4 is L7, the following conditions are satisfied and the parts are mounted so as not to contact each other. Capacitor manufacturing characterized by Jig of warp prevention method:
L2 = 0.5W ± 0.15W,
L6 = 0-0.9W,
L7 = 0.99W to 0.66W.
［１］コンデンサ素子接続部を有する側の長辺からのチップ部品１中央部までの距離をＬ１、チップ部品５中央部までの距離をＬ４、チップ部品６中央部までの距離をＬ５としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載することを特徴とするパターン、および
［２］コンデンサ素子接続部を有する側の長辺からのチップ部品２中央部までの一方の長辺からの距離をＬ２、チップ部品３中央部までの距離をＬ６、チップ部品４中央部までの距離をＬ７としたとき、下記の条件を満たし、かつ各部品が接触しないように搭載するパターン
を導電体１つおきに組み合わせたことを特徴とする請求項１または２に記載の固体電解コンデンサ製造用冶具の反り防止方法：
Ｌ１＝０．９９Ｗ〜０．６６Ｗ、
Ｌ２＝０．５Ｗ±０．１５Ｗ、
Ｌ４＝０〜０．５Ｗ、
Ｌ５＝０．５Ｗ±０．１５Ｗ、
Ｌ６＝０〜０．９Ｗ、
Ｌ７＝０．９９Ｗ〜０．６６Ｗ。 A capacitor element connection portion (2) is provided on one long side of a long substrate (1) for forming a dielectric layer or a semiconductor layer on a surface of a plurality of conductors by an energization method, Chip part 1 (3a), chip part 2 (3b) on one side (front surface) of the width direction, chip part 3 (5a), chip part 4 (4a), chip part 5 (5b) on the opposite side (back side) A method for preventing warping of a capacitor manufacturing jig in which each component of the chip component 6 (4b) is mounted and the chip component is repeatedly arranged in the longitudinal direction of the substrate, and is relative to the width W of the substrate. ,
[1] When the distance from the long side having the capacitor element connecting portion to the center of the chip component 1 is L1, the distance to the center of the chip component 5 is L4, and the distance to the center of the chip component 6 is L5 A pattern satisfying the following conditions and mounted so as not to contact each component, and [2] one length from the long side on the side having the capacitor element connection portion to the center of the chip component 2 When the distance from the side is L2, the distance to the center part of the chip part 3 is L6, and the distance to the center part of the chip part 4 is L7, the pattern that is mounted so that the following conditions are satisfied and each part does not contact The method for preventing warpage of a jig for manufacturing a solid electrolytic capacitor according to claim 1 or 2, wherein every other conductor is combined.
L1 = 0.99W to 0.66W,
L2 = 0.5W ± 0.15W,
L4 = 0 to 0.5W,
L5 = 0.5W ± 0.15W,
L6 = 0-0.9W,
L7 = 0.99W to 0.66W.
A solid electrolytic capacitor group obtained using the capacitor manufacturing jig according to claim 5.
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| JPH0883968A (en) * | 1994-09-13 | 1996-03-26 | Toshiba Corp | Base for electronic component |
| JPH08102569A (en) * | 1994-09-30 | 1996-04-16 | Sony Corp | Electronic device mounting structure on wiring board |
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