JP2007123430A - Semiconductor wafer and semiconductor inspecting method - Google Patents

Semiconductor wafer and semiconductor inspecting method Download PDF

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JP2007123430A
JP2007123430A JP2005311521A JP2005311521A JP2007123430A JP 2007123430 A JP2007123430 A JP 2007123430A JP 2005311521 A JP2005311521 A JP 2005311521A JP 2005311521 A JP2005311521 A JP 2005311521A JP 2007123430 A JP2007123430 A JP 2007123430A
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back surface
semiconductor wafer
wafer
semiconductor
chip
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Kazunori Kimura
和則 木村
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Tokyo Seimitsu Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer and a semiconductor inspecting method for realizing Kelvin connection to the rear surface of wafer with a simplified structure without complication of an inspection apparatus for the inspection of electrical characteristics of a chip formed on a semiconductor wafer. <P>SOLUTION: A rear surface potential measuring electrode 5 to be connected electrically to the rear surface of wafer for measurement of potential at the rear surface is provided on the front surface of a semiconductor wafer 2, and this rear surface potential measuring electrode 5 and the rear surface are electrically connected through the semiconductor wafer 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体ウエハに形成されたチップの電気的特性の検査に関し、特に半導体ウエハに形成されたチップ等の表面電極とウエハ裏面との間に検査電流を流してこのとき現れる表面電極とウエハ裏面の間の電圧を測定する電気的特性の検査に関する。   The present invention relates to inspection of electrical characteristics of chips formed on a semiconductor wafer, and in particular, the surface electrode and wafer appearing at this time by passing an inspection current between the surface electrode of the chip or the like formed on the semiconductor wafer and the back surface of the wafer. The present invention relates to an inspection of electrical characteristics for measuring a voltage between back surfaces.

半導体装置の製造工程においては、半導体ウエハ上に形成された半導体チップを検査して不良チップを発見し、不良チップについては後の組立工程を行なわないようにすることで製造効率を向上させている。このような検査には各半導体チップの電気的な特性の検査が含まれており、この電気的特性の検査では半導体チップの表面電極とウエハ裏面との間に検査電流を流してこのとき現れる表面電極とウエハ裏面との間の電圧も測定される（このように測定される電圧を、本明細書における以下の説明で「被測定電圧」と記す）。このような被測定電圧としては、例えば、表面に電界効果型トランジスタのゲート及びソースが形成され、他方の面に対応するドレインが形成された半導体ウエハでは、ウエハ表面に形成されたゲート電極とウエハ裏面との間の順方向電圧（オン抵抗）が測定される。   In the manufacturing process of a semiconductor device, a semiconductor chip formed on a semiconductor wafer is inspected to find a defective chip, and the defective chip is not subjected to a subsequent assembly process, thereby improving manufacturing efficiency. . Such inspection includes inspection of electrical characteristics of each semiconductor chip. In the inspection of electrical characteristics, an inspection current is passed between the front surface electrode of the semiconductor chip and the back surface of the wafer, and the surface that appears at this time. The voltage between the electrode and the back surface of the wafer is also measured (the voltage measured in this way is referred to as “measured voltage” in the following description of the present specification). As such a voltage to be measured, for example, in a semiconductor wafer in which a gate and a source of a field effect transistor are formed on the surface and a drain corresponding to the other surface is formed, a gate electrode and a wafer formed on the wafer surface The forward voltage (ON resistance) between the back surface is measured.

図１の（Ａ）は上記被測定電圧測定を行う従来の半導体検査方法の説明図である。図１の（Ａ）に示すとおり、半導体検査装置１は、ウエハ２を保持するウエハチャック（試料台）１０と、ウエハ２上に形成されたチップ（図示せず）に設けられたパッド（電極）３に接触してパッド３に検査電流を流し電圧測定を行うためのプローブ（針）３１ｆ及び３１ｓを備えたプローブカード３０と、チップのパッド３から裏面へ検査電流を流してそのときの電圧を測定するテスタ回路４０と、を備えている。なお、半導体検査装置１としては、プローブカード３０を備えないプローブヘッド形式のものも使用される。   FIG. 1A is an explanatory diagram of a conventional semiconductor inspection method for measuring the measured voltage. As shown in FIG. 1A, a semiconductor inspection apparatus 1 includes a wafer chuck (sample stage) 10 that holds a wafer 2 and pads (electrodes) provided on a chip (not shown) formed on the wafer 2. ) A probe card 30 provided with probes (needles) 31f and 31s for making a voltage measurement by applying an inspection current to the pad 3 in contact with 3 and a voltage at the time when an inspection current is supplied from the pad 3 of the chip to the back surface. And a tester circuit 40 for measuring. As the semiconductor inspection apparatus 1, a probe head type that does not include the probe card 30 is also used.

プローブカード３０に設けられるプローブ３１ｆ及び３１ｓは、これらプローブとパッドとの間の接触抵抗に起因する電圧降下分が測定電圧に影響しないように、フォース用プローブ３１ｆとセンス用プローブ３１ｓとに別個に設けられ、下記特許文献１等に開示されようにケルビン接続が採用されている。
テスタ回路４０は、電源４２によってフォース用プローブ３１ｆを介してパッド３からウエハ２の裏面へと検査電流を流す一方で、そのときにパッド３とウエハ２の裏面との間に生じる電圧を、センス用プローブ３１ｓを介して電圧計４１で測定することにより、半導体チップの表面電極と裏面電極との間に現れる上記被測定電圧を得る。
テスタ４０内の電圧計４１には、電圧計自身の抵抗値による電圧降下を防ぐためにハイインピーダンスの内部抵抗Ｒｉが直列に接続されており、検査電流は殆ど電圧計４１を通らない。このためにセンス用プローブ３１ｓとパッド３との間の接触抵抗の影響を被ることなく測定値を得ることが可能である。 The probes 31f and 31s provided on the probe card 30 are separately provided for the force probe 31f and the sense probe 31s so that the voltage drop caused by the contact resistance between the probe and the pad does not affect the measurement voltage. Kelvin connection is employed as disclosed in Patent Document 1 below.
The tester circuit 40 causes an inspection current to flow from the pad 3 to the back surface of the wafer 2 via the force probe 31f by the power source 42, and senses a voltage generated between the pad 3 and the back surface of the wafer 2 at that time. By measuring with the voltmeter 41 through the probe 31s, the measured voltage appearing between the front surface electrode and the back surface electrode of the semiconductor chip is obtained.
The voltmeter 41 in the tester 40 is connected in series with a high impedance internal resistance Ri in order to prevent a voltage drop due to the resistance value of the voltmeter itself, and the inspection current hardly passes through the voltmeter 41. Therefore, it is possible to obtain a measurement value without being affected by the contact resistance between the sensing probe 31s and the pad 3.

図１の（Ｂ）は図１（Ａ）の半導体検査装置１による検査回路の等価回路図である。図１の（Ｂ）において、Ｒ１ｆはフォース用プローブ３１ｆとパッド３との間の接触抵抗を示し、Ｒ１ｓはセンス用プローブ３１ｓとパッド３との間の接触抵抗を示し、Ｒ２はウエハ２の裏面側の接触抵抗を示す。
図１の（Ｂ）から分かるとおり、従来の半導体検査装置１の構成では、電圧計４１とパッド３及びウエハ２とを接続する直列回路には、検査電流が流れるウエハ２の裏面側の接触抵抗Ｒ２が含まれる。このために接触抵抗Ｒ２により生じる電圧降下分が測定結果に含まれることにより測定精度が劣化する問題があった。 FIG. 1B is an equivalent circuit diagram of an inspection circuit by the semiconductor inspection apparatus 1 of FIG. In FIG. 1B, R1f represents the contact resistance between the force probe 31f and the pad 3, R1s represents the contact resistance between the sense probe 31s and the pad 3, and R2 represents the back surface of the wafer 2. Side contact resistance.
As can be seen from FIG. 1B, in the configuration of the conventional semiconductor inspection apparatus 1, the series circuit connecting the voltmeter 41, the pad 3 and the wafer 2 has a contact resistance on the back side of the wafer 2 through which an inspection current flows. R2 is included. For this reason, there is a problem that the measurement accuracy is deteriorated because the voltage drop caused by the contact resistance R2 is included in the measurement result.

この問題を解決するため、下記特許文献２に開示する半導体検査装置では、ウエハを保持するウエハステージに複数の貫通穴を設けて、そのそれぞれにコンタクトピンを配置し背面側からの押圧によってピンの先端がステージ表面からわずかに突出してウエハ裏面に当接するように構成する。一方でステージ裏側にはコンタクトピンを押し上げるためのフォース用コンタクト片及びセンス用コンタクト片を設け、これらコンタクト片が検査対象のチップの直下に移動してそれぞれ別個にコンタクトピンを押圧し、フォース用コンタクト片に接触するピンとセンス用コンタクト片に接触するピンとを別々にウエハ裏面に当接させることにより、ウエハ裏面においてもケルビン接続を実現する。   In order to solve this problem, in the semiconductor inspection apparatus disclosed in Patent Document 2 below, a plurality of through holes are provided in a wafer stage for holding a wafer, contact pins are arranged in each of the holes, and the pins are pressed by pressing from the back side. The tip is slightly protruded from the surface of the stage and is in contact with the back surface of the wafer. On the other hand, a force contact piece and a sense contact piece for pushing up the contact pin are provided on the back side of the stage, and these contact pieces move directly under the chip to be inspected to press the contact pin separately to force contact. Kelvin connection is realized also on the back surface of the wafer by separately bringing the pins in contact with the pins and the pins in contact with the sensing contact pieces into contact with the back surface of the wafer.

特開平１１−６４３８５号公報JP-A-11-64385 特開２００４−３１１７９９号公報JP 2004-311799 A 特開平２００３−３２２３９５号公報Japanese Patent Laid-Open No. 2003-322395

しかしながら、上記特許文献２の構成ではウエハに配置される各チップの裏面に、フォース用及びセンス用のピンが少なくとも１つずつ当接することが望まれるため、細かなピッチで多数のコンタクトピンを、背面から押圧された場合にステージ表面に突出しつつ背面から脱落しないように配置する必要がある。また、コンタクトピンを押し上げるコンタクト片を各チップのそれぞれの直下まで移動させる駆動機構をステージに組み込む必要がある。このため、上記特許文献２の構成ではステージ機構が非常に複雑となる問題があった。   However, in the configuration of Patent Document 2, it is desired that at least one force pin and a sense pin abut on the back surface of each chip disposed on the wafer. Therefore, a large number of contact pins are arranged at a fine pitch. When pressed from the back side, it is necessary to arrange it so as not to fall out from the back side while protruding to the stage surface. In addition, it is necessary to incorporate a drive mechanism in the stage that moves the contact piece that pushes up the contact pin to directly below each chip. For this reason, the configuration of Patent Document 2 has a problem that the stage mechanism becomes very complicated.

上記問題に鑑み、本発明は半導体ウエハに形成されたチップの電気的特性の検査において、検査装置を複雑化させることなく、簡易な構成でウエハ裏面に対するケルビン接続を実現することが可能な半導体ウエハ及び半導体検査方法を提供することを目的とする。   In view of the above problems, the present invention provides a semiconductor wafer capable of realizing Kelvin connection to the back surface of the wafer with a simple configuration without complicating the inspection apparatus in the inspection of the electrical characteristics of the chip formed on the semiconductor wafer. It is another object of the present invention to provide a semiconductor inspection method.

上記目的を達成するために、本発明では、半導体ウエハの表面に、ウエハ裏面に電気的に接続されて裏面の電位測定に供される裏面電位測定用電極を設ける。裏面電位測定用電極と裏面とは半導体ウエハを貫通して導通される。
そして、この半導体ウエハの表面に形成されたチップの電気的特性を検査する際には、チップ上の測定部位に第１のフォース端子を、半導体ウエハの裏面に第２のフォース端子を接触させる。一方で上記測定部位に第１のセンス端子を接触させ、上記裏面電位測定用電極に第２のセンス端子を接触させる。このようにフォース端子及びセンス端子を測定部位、裏面及び裏面電位測定用電極に接触させることにより、これらフォース端子及びセンス端子を測定部位及び裏面にケルビン接続する。 In order to achieve the above object, in the present invention, a back surface potential measurement electrode is provided on the surface of a semiconductor wafer and is electrically connected to the back surface of the wafer and used for potential measurement of the back surface. The back surface potential measurement electrode and the back surface are conducted through the semiconductor wafer.
When inspecting the electrical characteristics of the chip formed on the surface of the semiconductor wafer, the first force terminal is brought into contact with the measurement site on the chip and the second force terminal is brought into contact with the back surface of the semiconductor wafer. On the other hand, a first sense terminal is brought into contact with the measurement site, and a second sense terminal is brought into contact with the back surface potential measurement electrode. In this way, the force terminal and the sense terminal are brought into contact with the measurement site, the back surface, and the back surface potential measurement electrode, whereby the force terminal and the sense terminal are Kelvin connected to the measurement site and the back surface.

なお、裏面電位測定用電極は、裏面電位測定用電極自身が半導体ウエハを貫通してその裏面に至るように設けてよい。
さらに、裏面電位測定用電極は、半導体ウエハの表面に形成されるチップ領域内に形成してよく、チップ領域外に形成してもよく、複数のチップ領域間のストリート領域に形成してもよい。 The back surface potential measurement electrode may be provided so that the back surface potential measurement electrode itself penetrates the semiconductor wafer and reaches the back surface thereof.
Furthermore, the back surface potential measurement electrode may be formed in a chip region formed on the surface of the semiconductor wafer, may be formed outside the chip region, or may be formed in a street region between a plurality of chip regions. .

本発明によって、簡易な構成でウエハ裏面に対するケルビン接続を実現する半導体ウエハ及び半導体検査方法が実現される。これによって安価な構成によってチップの電気的特性の検査の精度向上を図ることが可能となる。   According to the present invention, a semiconductor wafer and a semiconductor inspection method that realize Kelvin connection to the back surface of the wafer with a simple configuration are realized. This makes it possible to improve the accuracy of the inspection of the electrical characteristics of the chip with an inexpensive configuration.

以下、添付する図面を参照して本発明の実施例を説明する。図２は、本発明の実施例に係る半導体ウエハの電気的特性の検査の様子を示す図である。図２に示すとおり、半導体検査装置１には、ＸＹ可動テーブル２０と、テーブル２０上に設けられ半導体ウエハ２を保持する真空チャックなどのウエハチャック（試料台）１０が設けられる。
チャック１０の上方には、チャック１０上に保持されるウエハ２表面に形成されたチップ４上のパッド３に接触してパッド３をテスタ回路４０に電気的に接続するためのプローブ３１ｆ及び３１ｓを備えたプローブカード３０が設けられる。なお、半導体検査装置１を、プローブカード３０を備えないプローブヘッド形式としてもよい。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 2 is a view showing a state of inspection of electrical characteristics of the semiconductor wafer according to the embodiment of the present invention. As shown in FIG. 2, the semiconductor inspection apparatus 1 is provided with an XY movable table 20 and a wafer chuck (sample stage) 10 such as a vacuum chuck that is provided on the table 20 and holds the semiconductor wafer 2.
Above the chuck 10, probes 31f and 31s for contacting the pad 3 on the chip 4 formed on the surface of the wafer 2 held on the chuck 10 and electrically connecting the pad 3 to the tester circuit 40 are provided. A provided probe card 30 is provided. The semiconductor inspection apparatus 1 may be a probe head type that does not include the probe card 30.

プローブカード３０に設けられたプローブ３１ｆは、パッド３からウエハ２の裏面へ検査電流を流すために、テスタ回路４０内の電源４２に電気的に接続されパッド３に電圧を印加するためのフォース用プローブであり、プローブ３１ｓは、パッド３とウエハ２の裏面との間の電圧（チップ４に関する上記被測定電圧）を測定するために電圧計４１の一方の端子にパッド３を接続する第１センス用プローブである。テスタ回路４０内の電圧計４１にはハイインピーダンスの内部抵抗Ｒｉが直列に接続されており、半導体検査装置１は、これらフォース用プローブ３１ｆ及び第１センス用プローブ３１ｓとパッド３との間をケルビン接続する。
ここに、プローブカード３０に設けられたフォース用プローブ３１ｆは本願の特許請求の範囲に係る第１のフォース端子を成し、プローブカード３０に設けられた第１センス用プローブ３１ｓは本願の特許請求の範囲に係る第１のセンス端子を成す。 The probe 31 f provided on the probe card 30 is for a force for applying a voltage to the pad 3 that is electrically connected to the power source 42 in the tester circuit 40 in order to flow an inspection current from the pad 3 to the back surface of the wafer 2. The probe 31 s is a first sense that connects the pad 3 to one terminal of a voltmeter 41 in order to measure a voltage between the pad 3 and the back surface of the wafer 2 (the voltage to be measured with respect to the chip 4). Probe. A high impedance internal resistance Ri is connected in series to the voltmeter 41 in the tester circuit 40, and the semiconductor inspection apparatus 1 provides Kelvin between the force probe 31 f and the first sense probe 31 s and the pad 3. Connecting.
Here, the force probe 31f provided in the probe card 30 constitutes a first force terminal according to the claims of the present application, and the first sense probe 31s provided in the probe card 30 is claimed in the present application. The first sense terminal according to the range is formed.

一方でウエハチャック１０の表面は、ウエハ２の裏面に接触してウエハ２の裏面をテスタ回路４０の電源４２に接続されることによってフォース用端子をなす。ウエハチャック１０の表面は、フォース用プローブ３１ｆと共にパッド３とウエハ２の裏面との間に電圧を印加することにより、パッド３とウエハ２の裏面との間に検査電流を流す。したがってウエハチャック１０の表面は、本願の特許請求の範囲に係る第２のフォース端子を成す。   On the other hand, the front surface of the wafer chuck 10 is in contact with the back surface of the wafer 2 and the back surface of the wafer 2 is connected to the power source 42 of the tester circuit 40 to form a force terminal. The front surface of the wafer chuck 10 applies an inspection current between the pad 3 and the back surface of the wafer 2 by applying a voltage between the pad 3 and the back surface of the wafer 2 together with the force probe 31f. Therefore, the surface of the wafer chuck 10 forms a second force terminal according to the claims of the present application.

さらに、ウエハ２の表面には、ウエハ２の裏面の電気的に接続される裏面電位測定用電極５が設けられる。裏面電位測定用電極５については以下に詳述する。一方でプローブカード３０には、裏面電位測定用電極５に接触する第２センス用プローブ３２ｓが設けられる。第２センス用プローブ３２ｓは、テスタ回路４０内の電圧計４１の他方の端子に接続される。上記第１センス用プローブ３１ｓによってパッド３が電圧計４１の一方の端子に電気的に接続され、第２センス用プローブ３２ｓによってウエハ２の裏面が電圧計４１の他方の端子に電気的に接続されることにより、パッド３とウエハ２の裏面との間の電位差が測定される。ここに、第２センス用プローブ３２ｓは本願の特許請求の範囲に係る第２のセンス端子を成す。   Furthermore, a back surface potential measuring electrode 5 electrically connected to the back surface of the wafer 2 is provided on the front surface of the wafer 2. The back surface potential measurement electrode 5 will be described in detail below. On the other hand, the probe card 30 is provided with a second sense probe 32 s that contacts the back surface potential measurement electrode 5. The second sense probe 32 s is connected to the other terminal of the voltmeter 41 in the tester circuit 40. The pad 3 is electrically connected to one terminal of the voltmeter 41 by the first sensing probe 31s, and the back surface of the wafer 2 is electrically connected to the other terminal of the voltmeter 41 by the second sensing probe 32s. Thus, the potential difference between the pad 3 and the back surface of the wafer 2 is measured. Here, the second sense probe 32s forms a second sense terminal according to the claims of the present application.

図３の（Ａ）は、本発明の実施例に係る半導体検査方法の基本的な原理を説明する図である。裏面電位測定用電極５は、半導体ウエハ２を貫通する接続部５１によってウエハ２の裏面に導通されウエハ２の裏面と同一電位となる。このような接続部５１は、ウエハ２の当該部分にドナーやアクセプタをドーピングしてこの部分の導電率を高めることによって形成してもよく、またはウエハ２を穿孔した後に良導体を埋め込んで形成してもよい。
一方、フォース用プローブ３１ｆからパッド３に流れ込む検査電流Ｉｆの大部分は、ウエハチャック１０の表面で集電されて電源４２に帰還する。したがって第２センス用プローブ３２ｓへは検査電流Ｉｆの流入が無くなるため、ウエハ２の裏面に対してもフォース用電極１１ｆ及びセンス用電極１１ｓによるケルビン接続が実現する。 FIG. 3A is a view for explaining the basic principle of the semiconductor inspection method according to the embodiment of the present invention. The back surface potential measuring electrode 5 is electrically connected to the back surface of the wafer 2 by the connecting portion 51 penetrating the semiconductor wafer 2 and has the same potential as the back surface of the wafer 2. Such a connection part 51 may be formed by doping a corresponding part of the wafer 2 with a donor or an acceptor to increase the conductivity of this part, or by burying a good conductor after the wafer 2 is drilled. Also good.
On the other hand, most of the inspection current If flowing into the pad 3 from the force probe 31 f is collected on the surface of the wafer chuck 10 and returned to the power source 42. Accordingly, since the inspection current If does not flow into the second sensing probe 32s, the Kelvin connection by the force electrode 11f and the sensing electrode 11s is also realized on the back surface of the wafer 2.

図３の（Ｂ）は図３の（Ａ）の等価回路図である。図１の（Ｂ）に示した従来の等価回路図との対比によって理解されるように、ウエハチャック１０の表面及び第２センス用プローブ３２ｓによるウエハ２の裏面に対するケルビン接続が実現することによって、電源４２によってパッド３からウエハ２の裏面に電流を流すフォース用回路Ｃｆと、電圧計４１によってパッド３とウエハ２の裏面との間の電圧を測定するセンス用回路Ｃｓとが分離される。ここに、図３に示す抵抗Ｒ２はウエハ２裏面とウエハチャック１０の表面の間の接触抵抗であり、抵抗Ｒ２ｓは第２センス用プローブ３２ｓとウエハ２裏面との間の接触抵抗である。
このため、図１の（Ｂ）に示す等価回路を参照して上述した、従来生じていたウエハ裏面の接触抵抗Ｒ２に起因する電圧降下分の測定電圧への重畳が防止され、測定精度を向上することが可能となる。 FIG. 3B is an equivalent circuit diagram of FIG. As understood from comparison with the conventional equivalent circuit diagram shown in FIG. 1B, by realizing the Kelvin connection to the front surface of the wafer chuck 10 and the back surface of the wafer 2 by the second sensing probe 32s, A force circuit Cf that allows current to flow from the pad 3 to the back surface of the wafer 2 by the power source 42 is separated from a sense circuit Cs that measures a voltage between the pad 3 and the back surface of the wafer 2 by the voltmeter 41. Here, the resistor R2 shown in FIG. 3 is a contact resistance between the back surface of the wafer 2 and the surface of the wafer chuck 10, and the resistor R2s is a contact resistance between the second sensing probe 32s and the back surface of the wafer 2.
For this reason, the superposition of the voltage drop caused by the contact resistance R2 on the back surface of the wafer described above with reference to the equivalent circuit shown in FIG. 1B is prevented from being superimposed on the measurement voltage, and the measurement accuracy is improved. It becomes possible to do.

図３の（Ａ）に示すように、裏面電位測定用電極５の電位が、半導体ウエハ２の表面の電位や、半導体ウエハ２の表面から裏面へ貫通する貫通孔の裏面に至る途中部分の内壁の電位に影響されることを防ぐために、裏面電位測定用電極５と半導体ウエハ２の表面との間や、裏面電位測定用電極５及び接続部５１と上記貫通口の途中部分の内壁との間を絶縁する絶縁膜などの絶縁手段５２を設けてもよい。
なお、裏面電位測定用電極５がパッド３から遠くに設けられている場合には、裏面電位測定用電極５が導通するウエハ２の裏面部分とパッド３との間の電圧降下分が測定値に影響を及ぼすことになるが、ウエハ２の裏面は抵抗の低い半導体であり、また、検査電流Ｉｆはウエハチャック１０の表面に集電されていて、裏面電位測定用電極５が導通するウエハ２の裏面部分とパッド３との間には殆ど電流が流れないために、影響は軽微で問題とならない。
さらに図３の（Ａ）において、裏面電位測定用電極５は、半導体ウエハ２を貫通する接続部５１によってウエハ２の裏面に導通されることとしたが、裏面電位測定用電極５自身を、半導体ウエハ２を貫通してその裏面に至るように設けてもよい。 As shown in FIG. 3A, the inner wall of the intermediate portion where the potential of the back surface potential measuring electrode 5 reaches the back surface of the through hole penetrating from the front surface of the semiconductor wafer 2 to the back surface. In order to prevent the potential from being influenced by the potential of the back surface potential measuring electrode 5 and the surface of the semiconductor wafer 2, or between the back surface potential measuring electrode 5 and the connection portion 51 and the inner wall in the middle of the through hole. An insulating means 52 such as an insulating film may be provided.
When the back surface potential measuring electrode 5 is provided far from the pad 3, the voltage drop between the back surface portion of the wafer 2 through which the back surface potential measuring electrode 5 is conducted and the pad 3 becomes the measured value. The back surface of the wafer 2 is a low-resistance semiconductor, and the inspection current If is collected on the surface of the wafer chuck 10 so that the back surface potential measuring electrode 5 is conductive. Since almost no current flows between the back surface portion and the pad 3, the influence is slight and does not cause a problem.
Further, in FIG. 3A, the back surface potential measuring electrode 5 is electrically connected to the back surface of the wafer 2 by the connecting portion 51 penetrating the semiconductor wafer 2, but the back surface potential measuring electrode 5 itself is connected to the semiconductor. You may provide so that the wafer 2 may be penetrated and it may reach the back surface.

図４の（Ａ）及び（Ｂ）は、裏面電位測定用電極５の様々な配置例を示す図である。図４の（Ａ）に示す例では、半導体ウエハ２の表面に形成される各チップ４毎に、各チップ領域内に裏面電位測定用電極５が形成される。
図４の（Ｂ）に示す例では、半導体ウエハ２の表面に形成される各チップ４毎に、各チップ領域外に裏面電位測定用電極５が形成される。このとき裏面電位測定用電極５を、チップ領域４の間のストリート領域に設けてもよい。 4A and 4B are diagrams showing various arrangement examples of the back surface potential measuring electrode 5. FIG. In the example shown in FIG. 4A, the back surface potential measuring electrode 5 is formed in each chip region for each chip 4 formed on the surface of the semiconductor wafer 2.
In the example shown in FIG. 4B, a back surface potential measuring electrode 5 is formed outside each chip region for each chip 4 formed on the surface of the semiconductor wafer 2. At this time, the back surface potential measuring electrode 5 may be provided in a street region between the chip regions 4.

図４の（Ａ）及び図４の（Ｂ）に示すように、各チップ４毎に、そのチップ領域内及びチップ領域付近に裏面電位測定用電極５を設けることにより、検査対象のチップ４に近い裏面電位を測定することが可能となり、より精度の高い測定が可能となる。
なお、複数のチップに対してそのうちの１つのチップのみに裏面電位測定用電極５を設けてもよい。またチップ間のストリート領域に設けられる裏面電位測定用電極５を、そのストリートを挟む２つのチップで共用してもよい。 As shown in FIG. 4A and FIG. 4B, by providing the back surface potential measuring electrode 5 in and near the chip area for each chip 4, the chip 4 to be inspected is provided. It is possible to measure the near back surface potential, and more accurate measurement is possible.
Note that the back surface potential measuring electrode 5 may be provided on only one of the plurality of chips. Further, the back surface potential measuring electrode 5 provided in the street region between the chips may be shared by two chips sandwiching the street.

本発明は、半導体ウエハに形成されたチップの電気的特性の検査に利用可能であり、特に半導体ウエハに形成されたチップ等の表面電極とウエハ裏面との間に検査電流を流してこのとき現れるチップ等の表面電極とウエハ裏面の間の電圧を測定する電気的特性の検査に利用可能である。   INDUSTRIAL APPLICABILITY The present invention can be used for inspection of electrical characteristics of chips formed on a semiconductor wafer, and particularly appears when an inspection current is passed between a surface electrode such as a chip formed on a semiconductor wafer and the back surface of the wafer. It can be used for inspection of electrical characteristics for measuring a voltage between a surface electrode such as a chip and the back surface of the wafer.

（Ａ）は半導体ウエハに形成されたチップ等の表面電極とウエハ裏面との間に検査電流を流してこのとき現れる電圧の測定を行う従来の半導体検査方法の説明図であり、（Ｂ）は（Ａ）に示す半導体検査装置による検査回路の等価回路図である。(A) is explanatory drawing of the conventional semiconductor test | inspection method which measures the voltage which flows an inspection electric current between surface electrodes, such as a chip | tip formed in the semiconductor wafer, and a wafer back surface, and (B). It is the equivalent circuit schematic of the test | inspection circuit by the semiconductor test | inspection apparatus shown to (A). 本発明の実施例に係る半導体ウエハの電気的特性の検査の様子を示す図である。It is a figure which shows the mode of the test | inspection of the electrical property of the semiconductor wafer which concerns on the Example of this invention. （Ａ）は本発明の実施例に係る半導体検査方法の基本的な原理を説明する図であり、（Ｂ）は（Ａ）の等価回路図である。(A) is a figure explaining the basic principle of the semiconductor inspection method based on the Example of this invention, (B) is an equivalent circuit schematic of (A). 裏面電位測定用電極の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the electrode for back surface potential measurement.

符号の説明Explanation of symbols

１ 半導体検査装置
２ ウエハ
４ チップ
５ 裏面電位測定用電極
１０ ウエハチャック
２０ ステージ
３０ プローブカード
３１ｆ フォース用プローブ
３１ｓ、３２ｓ センス用プローブ
４０ テスタ回路 DESCRIPTION OF SYMBOLS 1 Semiconductor inspection apparatus 2 Wafer 4 Chip 5 Back surface potential measurement electrode 10 Wafer chuck 20 Stage 30 Probe card 31f Force probe 31s, 32s Sense probe 40 Tester circuit

Claims (6)

表面に半導体回路が形成される半導体ウエハであって、
その裏面に電気的に接続されて裏面の電位測定に供される裏面電位測定用電極を、その表面に備え、
前記裏面電位測定用電極と前記裏面とが、前記半導体ウエハを貫通して導通されることを特徴とする半導体ウエハ。 A semiconductor wafer having a semiconductor circuit formed on a surface thereof;
A back surface potential measuring electrode that is electrically connected to the back surface and used for back surface potential measurement is provided on the surface,
A semiconductor wafer, wherein the back surface potential measuring electrode and the back surface are conducted through the semiconductor wafer. 前記裏面電位測定用電極が、前記半導体ウエハを貫通してその裏面に至ることを特徴とする請求項２に記載の半導体ウエハ。   The semiconductor wafer according to claim 2, wherein the back surface potential measurement electrode penetrates the semiconductor wafer and reaches the back surface thereof. 前記裏面電位測定用電極が、前記半導体ウエハの表面に形成されるチップ領域内に形成されることを特徴とする請求項１又は２に記載の半導体ウエハ。   The semiconductor wafer according to claim 1, wherein the back surface potential measurement electrode is formed in a chip region formed on a surface of the semiconductor wafer. 前記裏面電位測定用電極が、前記半導体ウエハの表面に形成されるチップ領域外に形成されることを特徴とする請求項１又は２に記載の半導体ウエハ。   The semiconductor wafer according to claim 1, wherein the back surface potential measuring electrode is formed outside a chip region formed on a surface of the semiconductor wafer. 前記裏面電位測定用電極が、前記半導体ウエハの表面に形成される複数のチップ領域間のストリート領域に形成されることを特徴とする請求項４に記載の半導体ウエハ。   The semiconductor wafer according to claim 4, wherein the back surface potential measuring electrode is formed in a street region between a plurality of chip regions formed on the surface of the semiconductor wafer. 半導体ウエハの表面に形成されたチップの電気的特性を検査する半導体検査方法において、
前記チップ上の測定部位に第１のフォース端子を、前記半導体ウエハの裏面に第２のフォース端子を接触させ、
前記測定部位に第１のセンス端子を接触させ、
前記半導体ウエハの表面に設けられた該ウエハの裏面に電気的に接続される裏面電位測定用電極であって、この裏面電位測定用電極と前記半導体ウエハの裏面とが前記半導体ウエハを貫通して導通する裏面電位測定用電極に第２のセンス端子を接触させて、
前記フォース端子及び前記センス端子を前記測定部位及び前記裏面にケルビン接続することを特徴とする半導体検査方法。 In a semiconductor inspection method for inspecting electrical characteristics of chips formed on the surface of a semiconductor wafer,
The first force terminal is brought into contact with the measurement site on the chip, and the second force terminal is brought into contact with the back surface of the semiconductor wafer,
Bringing the first sense terminal into contact with the measurement site;
A back surface potential measuring electrode electrically connected to the back surface of the wafer provided on the front surface of the semiconductor wafer, the back surface potential measuring electrode and the back surface of the semiconductor wafer penetrating the semiconductor wafer. The second sense terminal is brought into contact with the conductive back surface potential measurement electrode,
A semiconductor inspection method, wherein the force terminal and the sense terminal are Kelvin connected to the measurement site and the back surface.
JP2005311521A 2005-10-26 2005-10-26 Semiconductor wafer and semiconductor inspecting method Pending JP2007123430A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012058225A (en) * 2010-03-12 2012-03-22 Tokyo Electron Ltd Probe apparatus
CN103703381A (en) * 2011-08-01 2014-04-02 东京毅力科创株式会社 Probe card for power device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012058225A (en) * 2010-03-12 2012-03-22 Tokyo Electron Ltd Probe apparatus
CN102713650A (en) * 2010-03-12 2012-10-03 东京毅力科创株式会社 Probe apparatus
KR101389251B1 (en) 2010-03-12 2014-04-25 도쿄엘렉트론가부시키가이샤 Probe apparatus
US9658285B2 (en) 2010-03-12 2017-05-23 Tokyo Electron Limited Probe apparatus
CN103703381A (en) * 2011-08-01 2014-04-02 东京毅力科创株式会社 Probe card for power device

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