JP2007095927A - Wiring board and its production method - Google Patents

Wiring board and its production method Download PDF

Info

Publication number
JP2007095927A
JP2007095927A JP2005282152A JP2005282152A JP2007095927A JP 2007095927 A JP2007095927 A JP 2007095927A JP 2005282152 A JP2005282152 A JP 2005282152A JP 2005282152 A JP2005282152 A JP 2005282152A JP 2007095927 A JP2007095927 A JP 2007095927A
Authority
JP
Japan
Prior art keywords
conductor
dividing
hole
castellation
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005282152A
Other languages
Japanese (ja)
Other versions
JP4703342B2 (en
Inventor
Keiichi Morikane
圭一 森兼
Masashi Nagao
賢史 長尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP2005282152A priority Critical patent/JP4703342B2/en
Publication of JP2007095927A publication Critical patent/JP2007095927A/en
Application granted granted Critical
Publication of JP4703342B2 publication Critical patent/JP4703342B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board and its production method wherein under the state of a multi-piece large-sized board, an overall surface of a castellation conductor can be subjected to plating processing and division properties are also good. <P>SOLUTION: On each of multiple wiring boards 11 to be taken by division of a large-sized board 27, a castellation conductor 15 is provided in notches 13, 14 on the side of a ceramic substrate 12 thereof. A plating layer 17 is coated on the entire surface of the castellation conductor 15, but cutting parts 16 are provided between both ends in a widthwise direction of the notches 13, 14 and the side, respectively. Therefore, the side is separate from the castellation conductor 15. In other words, a segmentation hole 26 which segments a cylindrical conductor 25 in a through-hole 23 is provided in a production process of the wiring board 11, whereby the end 15a of the castellation conductor 15 is located inside of division lines 21, 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、大判基板から多数個取りされる配線基板とその製造方法とに係り、特に、配線基板の側面に設けられるキャスタレーション導体（側面導体）の改良に関する。   The present invention relates to a wiring board obtained from a large number of large-sized boards and a manufacturing method thereof, and more particularly, to an improvement in a castellation conductor (side conductor) provided on a side surface of the wiring board.

一般的に、半導体素子等の電子部品が搭載される配線基板は、グリーンシートの積層体を焼成してなるセラミック製の大判基板を縦横の分割ラインに沿って分割して多数個取りされるようになっている。この大判基板には多数個分の配線基板領域が分割ラインによって区画されており、各配線基板領域に配線パターンやキャスタレーション導体が設けられている。ここで、キャスタレーション導体は、大判基板においては分割ラインに穿設されたスルーホールの内壁に設けられているが、この分割ラインに沿う分割面が各配線基板の側面となるため、多数個取りされた配線基板の側面の凹溝内の壁面にキャスタレーション導体が形成されている。このキャスタレーション導体と配線パターンは適宜個所で接続されており、配線基板の上面に搭載された電子回路素子がワイヤボンディング等によって配線パターンと接続されると共に、配線基板が実装される母基板の半田ランド上でキャスタレーション導体が半田付けされるようになっている。これにより、配線基板上の電子回路素子がキャスタレーション導体を介して外部回路と電気的に接続されることとなる。   In general, a wiring board on which electronic components such as semiconductor elements are mounted is obtained by dividing a large ceramic substrate formed by firing a green sheet laminate along vertical and horizontal dividing lines. It has become. In this large substrate, a large number of wiring board regions are partitioned by dividing lines, and wiring patterns and castellation conductors are provided in each wiring board region. Here, the caster conductor is provided on the inner wall of the through-hole formed in the dividing line in the large-sized substrate. Since the dividing surface along the dividing line is the side surface of each wiring substrate, a large number of caster conductors are obtained. A castellation conductor is formed on the wall surface in the concave groove on the side surface of the printed wiring board. The caster conductor and the wiring pattern are connected at appropriate places, and the electronic circuit element mounted on the upper surface of the wiring board is connected to the wiring pattern by wire bonding or the like, and the mother board solder on which the wiring board is mounted The castellation conductor is soldered on the land. As a result, the electronic circuit element on the wiring board is electrically connected to the external circuit via the castellation conductor.

図６は従来の配線基板のキャスタレーション導体を示す斜視図である。同図に示す配線基板１には、セラミック基板２の側面に凹溝状の切欠き３，４が設けられており、これら切欠き３，４内の壁面に銀等の良導電性材料からなる所定の厚みのキャスタレーション導体５が形成されている。また、図示はしていないが、この配線基板１の内層や外層にはキャスタレーション導体５と接続された配線パターンが設けられていると共に、配線基板１の上面に電子回路素子が搭載されており、これら電子回路素子と配線パターンとがワイヤボンディング等によって接続されている。なお、通常、キャスタレーション導体５の表面には半田濡れ性の向上や銀の半田喰われ防止を図るために、ニッケル層等の図示せぬメッキ層が被着されている（例えば、特許文献１参照）。   FIG. 6 is a perspective view showing a castor conductor of a conventional wiring board. The wiring board 1 shown in the figure is provided with notched grooves 3 and 4 on the side surface of the ceramic substrate 2, and the wall surfaces in the notches 3 and 4 are made of a highly conductive material such as silver. A castellation conductor 5 having a predetermined thickness is formed. Although not shown, a wiring pattern connected to the castellation conductor 5 is provided on the inner layer and the outer layer of the wiring substrate 1, and an electronic circuit element is mounted on the upper surface of the wiring substrate 1. These electronic circuit elements and the wiring pattern are connected by wire bonding or the like. In general, the surface of the castellation conductor 5 is coated with a plating layer (not shown) such as a nickel layer in order to improve solder wettability and prevent silver solder erosion (for example, Patent Document 1). reference).

図７は図６に示す従来の配線基板の製造過程を示す説明図である。図７に示す大判基板６は、所要の導電部を形成したグリーンシートの積層体を焼成したものであり、縦横の分割ライン７，８によって区画されている小領域９が各配線基板１に対応しているため、この大判基板６を分割ライン７，８に沿って分割することにより配線基板１が多数個取りされる。また、大判基板６には分割ライン７，８と重なり合う所定位置に多数のスルーホール１０が穿設されており、各スルーホール１０の内壁に所定の厚みの未分割なキャスタレーション導体５が設けられている。つまり、この大判基板６は分割ライン７，８に沿う分割面が各配線基板１の側面となるため、多数個取りされた配線基板１の側面には、スルーホール１０を２分割してなる切欠き３の内壁と４分割してなる切欠き４の内壁にそれぞれキャスタレーション導体５が設けられた状態となる。なお、スルーホール１０の内壁にキャスタレーション導体５を形成する際には、スルーホール１０内に銀ペースト等の導電材料を充填した後、このスルーホール１０の中央部に貫通孔１０ａを穿設して該導電材料の一部を取り除くことにより、残存する導電材料によって所定の厚みの未分割なキャスタレーション導体５を形成できる。
特開２００３−１７９１７６号公報（第３−５頁、図３） FIG. 7 is an explanatory view showing a manufacturing process of the conventional wiring board shown in FIG. A large-sized substrate 6 shown in FIG. 7 is obtained by firing a laminate of green sheets on which required conductive portions are formed. A small region 9 defined by vertical and horizontal dividing lines 7 and 8 corresponds to each wiring substrate 1. Therefore, a large number of wiring boards 1 are taken by dividing the large-sized board 6 along the dividing lines 7 and 8. The large-sized substrate 6 has a large number of through holes 10 at predetermined positions overlapping the dividing lines 7 and 8, and an undivided castellation conductor 5 having a predetermined thickness is provided on the inner wall of each through hole 10. ing. In other words, since the large-sized substrate 6 has a dividing surface along the dividing lines 7 and 8 as the side surface of each wiring substrate 1, the through-hole 10 is divided into two on the side surface of the wiring substrate 1 taken in large numbers. The caster conductor 5 is provided on each of the inner wall of the notch 4 divided into four with the inner wall of the notch 3. When forming the castellation conductor 5 on the inner wall of the through hole 10, after filling the through hole 10 with a conductive material such as silver paste, a through hole 10 a is formed in the center of the through hole 10. By removing a part of the conductive material, an undivided castellation conductor 5 having a predetermined thickness can be formed by the remaining conductive material.
JP 2003-179176 A (page 3-5, FIG. 3)

前述したように、大判基板６から多数個取りされる配線基板１のキャスタレーション導体５は、分割ライン７，８と重なり合うスルーホール１０の内壁に形成されたものなので、大判基板６を分割する前にメッキ処理を施してキャスタレーション導体５にメッキ層を被着させたとしても、分割ライン７や分割ライン８に合致するキャスタレーション導体５の端面（分割面）はメッキ層の存しない無メッキ領域になってしまう。そして、キャスタレーション導体５の該端面が無メッキのまま配線基板１が母基板上に実装されると、キャスタレーション導体５中の銀成分が該端面で半田喰われを起こしてしまうので、信頼性は著しく低下する。   As described above, the castellation conductors 5 of the wiring board 1 taken from the large-sized substrate 6 are formed on the inner wall of the through hole 10 overlapping the dividing lines 7 and 8. Therefore, before the large-sized substrate 6 is divided. Even if the plating layer is applied to the castellation conductor 5, the end face (split surface) of the castellation conductor 5 that matches the dividing line 7 or the dividing line 8 is not plated. Become. When the wiring board 1 is mounted on the mother board with the end face of the castellation conductor 5 being unplated, the silver component in the castellation conductor 5 causes solder biting on the end face. Is significantly reduced.

そこで、キャスタレーション導体５中の銀成分の半田喰われを防止するためには大判基板６を分割して得た個片（配線基板１）にメッキ処理を施す必要があるが、このようにすると、大判基板６の状態で行うメッキ処理と比べて作業効率が低下するのみならず、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も大判基板６の状態では実施できなくなってしまうので、生産性が低下して製造コストの上昇を余儀なくされてしまう。   Therefore, in order to prevent the silver component in the castellation conductor 5 from being eroded by solder, it is necessary to perform plating on the piece (wiring board 1) obtained by dividing the large-sized board 6, but if this is done, In addition to the reduction in work efficiency compared to the plating process performed in the state of the large substrate 6, the post-plating process of mounting an electronic circuit element and conducting a continuity test or the like cannot be performed in the state of the large substrate 6. As a result, productivity is reduced and manufacturing costs are inevitably increased.

また、従来の製造方法では、分割ライン７，８とキャスタレーション導体５とが重なり合った状態のまま、ハーフカットやダイシング等の手法で大判基板６の分割作業を行うことになるが、セラミックと金属が混在する部位が分割面となるため分割性に難があり、分割面にバリや欠け、汚れ等が生じやすいという問題があった。   In the conventional manufacturing method, the large-sized substrate 6 is divided by a technique such as half-cutting or dicing while the dividing lines 7 and 8 and the castellation conductor 5 are overlapped. There is a problem that splitting is difficult because the part where the mixture is mixed becomes a split surface, and burrs, chips, dirt, etc. are likely to occur on the split surface.

本発明は、このような従来技術の実情に鑑みてなされたもので、その第１の目的は、多数個取り用の大判基板の状態でキャスタレーション導体の全表面にメッキ処理を施すことができて分割性も良好な配線基板を提供することにある。また、本発明の第２の目的は、かかる配線基板の製造方法を提供することにある。   The present invention has been made in view of such a state of the art, and a first object thereof is to perform plating on the entire surface of the castellation conductor in the state of a large-sized substrate for taking a large number of pieces. Another object of the present invention is to provide a wiring board with good separation. A second object of the present invention is to provide a method for manufacturing such a wiring board.

上記第１の目的を達成するために、本発明では、上下両面に至る凹溝状の切欠きが側面に設けられたセラミック基板と、前記切欠き内の壁面に設けられてメッキ層が被着されたキャスタレーション導体とを備え、前記セラミックは大判基板を分割ラインに沿って分割することにより多数個取りされる配線基板において、前記セラミック基板の前記切欠きが臨出する側面と該切欠きの幅方向両端との間に、該セラミック基板の上下両面に至る凹溝状の切除部を設け、この切除部によって該側面と前記キャスタレーション導体とを離隔させた。   In order to achieve the first object, in the present invention, a notched groove-shaped notch extending to both upper and lower surfaces is provided on a side surface, and a plating layer is provided on a wall surface in the notch. In a wiring board in which a large number of large-size substrates are taken by dividing a large-sized substrate along a dividing line, a side surface of the ceramic substrate from which the notches protrude and a notch of the notches are provided. Concave groove-shaped cut portions reaching both the upper and lower surfaces of the ceramic substrate were provided between both ends in the width direction, and the side surfaces and the castellation conductor were separated by the cut portions.

このように構成された配線基板は、セラミック基板の側面と該側面に臨出するキャスタレーション導体とが切除部を介して離隔しているため、多数個取り用の大判基板の状態でキャスタレーション導体の幅方向の端面が分割ラインよりも内側に位置することになり、該端面を含むキャスタレーション導体の全表面にメッキ層を被着させることができる。すなわち、この配線基板は、大判基板の状態でキャスタレーション導体の全表面にメッキ処理を施すことができるため、メッキ工程の作業効率が向上すると共に、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も大判基板の状態で実施できるようになり、信頼性を損なうことなく生産性を大幅に高めることが可能となる。また、大判基板の分割ラインとキャスタレーション導体とが重なり合わないことから、分割性が良好となり、よって分割面にバリや欠け、汚れ等が生じにくくなる。   In the wiring board configured as described above, since the side surface of the ceramic substrate and the castellation conductor that protrudes from the side surface are separated through the cut portion, the castoration conductor is in the state of a large-sized substrate for taking multiple pieces. The end surface in the width direction is positioned inside the dividing line, and the plating layer can be deposited on the entire surface of the castellation conductor including the end surface. In other words, since this wiring board can be plated on the entire surface of the castellation conductor in the state of a large-sized board, the work efficiency of the plating process is improved, and electrical circuit elements are mounted to conduct continuity inspection and the like. Thus, the post-plating process can be performed in the state of a large-sized substrate, and the productivity can be greatly increased without impairing the reliability. Further, since the dividing line of the large-sized substrate and the castellation conductor do not overlap each other, the dividing property is improved, so that burrs, chips, dirt, etc. are hardly generated on the dividing surface.

上記構成の配線基板において、セラミック基板は単層であってもよいが、セラミック基板が多層基板であれば、一般的な配線基板に適用できるため好ましい。   In the wiring substrate having the above-described configuration, the ceramic substrate may be a single layer, but if the ceramic substrate is a multilayer substrate, it is preferable because it can be applied to a general wiring substrate.

また、上記第２の目的を達成するために、本発明による配線基板の製造方法では、多数個取り用のグリーンシートの分割ラインと重なり合う所定位置に多数のキャスタレーション導体用スルーホールを穿設した後、これらスルーホールに導電材料を充填する導電材料充填工程と、この導電材料充填工程後に前記キャスタレーション導体用スルーホールを貫通する貫通孔を穿設して、該スルーホール内の前記導電材料の一部を前記分割ラインに沿って切除することにより、該分割ラインから離隔した所定の厚みのキャスタレーション導体を該スルーホールの内壁に複数形成するキャスタレーション導体形成工程と、このキャスタレーション導体形成工程後に前記グリーンシートを焼成して多数個取り用の大判基板を得る焼成工程と、前記焼成工程後に前記キャスタレーション導体の全表面にメッキ層を被着させるメッキ工程と、前記メッキ工程後に前記大判基板を前記分割ラインに沿って個片に分割する分割工程とを含み、前記分割工程によって前記キャスタレーション導体を有する配線基板が多数個取りされるようにした。   In order to achieve the second object, in the method for manufacturing a wiring board according to the present invention, a number of through holes for castellation conductors are formed at predetermined positions overlapping with the dividing lines of a multi-sheet green sheet. Thereafter, a conductive material filling step for filling the through holes with a conductive material, and a through hole penetrating the through hole for castellation conductors is formed after the conductive material filling step, and the conductive material in the through holes is formed. A castellation conductor forming step of forming a plurality of castellation conductors having a predetermined thickness separated from the split line on the inner wall of the through hole by cutting a part along the split line, and the castellation conductor forming step A firing step of firing the green sheet later to obtain a large-sized substrate for taking a large number of pieces; A plating step of depositing a plating layer on the entire surface of the castellation conductor later; and a dividing step of dividing the large-sized substrate into pieces along the dividing line after the plating step. A large number of wiring boards having a connection conductor are taken.

このような配線基板の製造方法では、キャスタレーション導体形成工程において、キャスタレーション導体の幅方向の端面を分割ラインよりも内側に位置させるため、多数個取り用の大判基板を個片に分割する前にキャスタレーション導体の全表面にメッキ層を被着させることができて、メッキ工程の作業効率が向上すると共に、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も大判基板の状態で実施できるようになり、信頼性を損なうことなく生産性を大幅に高めることが可能となる。また、大判基板の分割ラインとキャスタレーション導体とが重なり合わないことから、分割性が良好となり、よって分割面にバリや欠け、汚れ等が生じにくくなる。   In such a method for manufacturing a wiring board, since the end face in the width direction of the castellation conductor is positioned on the inner side of the dividing line in the castoration conductor forming step, before the large-sized board for multi-piece production is divided into pieces, The plating layer can be applied to the entire surface of the castellation conductor to improve the work efficiency of the plating process, and the post-plating process of mounting electronic circuit elements and conducting continuity inspection etc. Thus, the productivity can be greatly increased without impairing the reliability. Further, since the dividing line of the large-sized substrate and the castellation conductor do not overlap each other, the dividing property is improved, so that burrs, chips, dirt, etc. are hardly generated on the dividing surface.

上記の製造方法において、キャスタレーション導体形成工程は、キャスタレーション導体用スルーホールの中央部に該スルーホールよりも小径な中央孔を穿設することによって、該スルーホールの内壁に所定の厚みの導電材料を残存させる導体厚設定工程と、この導体厚設定工程後にグリーンシートの分割ラインと導電材料とが重なり合う個所にそれぞれスルーホールよりも小径で該導電材料を分断する分断孔を穿設することによって、該スルーホールの内壁に該分断孔を介して端面どうしが対向する複数のキャスタレーション導体を形成する導体分断工程とを含むことが好ましい。すなわち、導体厚設定工程でキャスタレーション導体を所定の厚みに設定した後に、導体分断工程で分断孔を穿設してキャスタレーション導体を分割ラインから離隔させれば、これら各工程を通常のパンチングマシン等で容易かつ正確に行うことができる。   In the manufacturing method described above, the castellation conductor forming step includes forming a central hole having a smaller diameter than the through hole in the central portion of the through hole for the castellation conductor, so that the inner wall of the through hole has a predetermined thickness. By forming a conductor thickness setting step that leaves the material, and after the conductor thickness setting step, a dividing hole that divides the conductive material with a smaller diameter than the through hole is formed at each of the locations where the dividing line of the green sheet and the conductive material overlap. And a conductor dividing step of forming a plurality of castellation conductors whose end faces face each other through the dividing hole on the inner wall of the through hole. In other words, after setting the castellation conductor to a predetermined thickness in the conductor thickness setting step, if a hole is formed in the conductor dividing step to separate the castellation conductor from the dividing line, each of these steps is performed by a normal punching machine. Etc. can be carried out easily and accurately.

また、上記の製造方法において、キャスタレーション導体形成工程後にグリーンシートを複数枚積層して加熱圧着する積層体形成工程を行い、この積層体形成工程後に焼成工程を行うことにより大判基板を多層基板となしておけば、一般的な配線基板の製造に適用できるため好ましい。   Further, in the above manufacturing method, after the caster conductor formation process, a multilayer body forming process is performed in which a plurality of green sheets are stacked and thermocompression bonded, and a large-size substrate is formed as a multilayer board by performing a firing process after the multilayer body forming process. If it is made, it is preferable because it can be applied to the production of a general wiring board.

本発明の配線基板は、セラミック基板の側面と該側面に臨出するキャスタレーション導体とが切除部を介して離隔しているため、多数個取り用の大判基板の状態でキャスタレーション導体の幅方向の端面が分割ラインよりも内側に位置することになり、該端面を含むキャスタレーション導体の全表面にメッキ層を被着させることができる。それゆえ、メッキ工程の作業効率が向上すると共に、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も大判基板の状態で実施できるようになり、信頼性を損なうことなく生産性を大幅に高めることが可能となる。また、大判基板の分割ラインとキャスタレーション導体とが重なり合わないことから、分割性が良好となって、分割面にバリや欠け、汚れ等が生じにくくなる。   In the wiring board according to the present invention, since the side surface of the ceramic substrate and the castellation conductor that protrudes from the side surface are separated through the cut portion, the width direction of the castellation conductor in the state of a large-sized substrate for multi-piece production Thus, the plating layer can be deposited on the entire surface of the castellation conductor including the end surface. Therefore, the work efficiency of the plating process is improved, and the post-plating process of mounting electronic circuit elements and conducting continuity inspections can be performed in the state of a large substrate, producing without sacrificing reliability. It is possible to greatly improve the performance. Further, since the dividing line of the large-sized substrate and the castellation conductor do not overlap each other, the dividing property is improved, and burrs, chips, dirt, etc. are hardly generated on the dividing surface.

また、本発明による配線基板の製造方法は、キャスタレーション導体形成工程において、キャスタレーション導体の幅方向の端面を分割ラインよりも内側に位置させるため、多数個取り用の大判基板を個片に分割する前に、該端面を含むキャスタレーション導体の全表面にメッキ層を被着させることができて、メッキ工程の作業効率が向上すると共に、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も大判基板の状態で実施できるようになって、信頼性を損なうことなく生産性を大幅に高めることが可能となる。また、大判基板の分割ラインとキャスタレーション導体とが重なり合わないことから、分割性が良好となって、分割面にバリや欠け、汚れ等が生じにくくなる。   In addition, in the method for manufacturing a wiring board according to the present invention, in the castellation conductor forming step, the end face in the width direction of the castellation conductor is positioned on the inner side of the dividing line. Plating can be applied to the entire surface of the castellation conductor including the end face before the plating process, and the working efficiency of the plating process is improved, and an electronic circuit element is mounted to conduct continuity inspection and the like. The post-treatment process can also be performed in the state of a large-sized substrate, and the productivity can be significantly increased without impairing the reliability. Further, since the dividing line of the large-sized substrate and the castellation conductor do not overlap each other, the dividing property is improved, and burrs, chips, dirt, etc. are hardly generated on the dividing surface.

発明の実施の形態を図面を参照して説明すると、図１は本発明の実施形態例に係る配線基板のキャスタレーション導体を示す斜視図、図２は該キャスタレーション導体の断面図、図３〜図５は該配線基板の製造工程図である。   1 is a perspective view showing a caster conductor of a wiring board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the caster conductor, and FIG. FIG. 5 is a manufacturing process diagram of the wiring board.

図１および図２に示す配線基板１１は、図示せぬ電子回路素子が上面に搭載される多層構造のセラミック基板１２と、このセラミック基板１２の内層や外層に設けられた図示せぬ配線パターンと、セラミック基板１２の側面の切欠き１３，１４内の壁面に設けられたキャスタレーション導体１５とを備えた構成になっており、セラミック基板１２の側面に切欠き１３，１４に隣接する小径な切除部１６を設けることによって、該側面とキャスタレーション導体１５とを離隔させてある。この配線基板１１の配線パターンは適宜個所でキャスタレーション導体１５と接続されており、この配線パターンと電子回路素子とがワイヤボンディング等によって接続されるようになっている。また、キャスタレーション導体１５は、この配線基板１１が実装される図示せぬ母基板の半田ランド上で半田付けされるため、配線基板１１上の電子回路素子がキャスタレーション導体１５を介して外部回路と電気的に接続されることとなる。なお、このキャスタレーション導体１５の全表面には、半田濡れ性の向上や銀の半田喰われ防止を図るためにニッケルや金等からなるメッキ層１７が被着させてある。   A wiring board 11 shown in FIGS. 1 and 2 includes a multilayer ceramic substrate 12 on which an electronic circuit element (not shown) is mounted, and a wiring pattern (not shown) provided on an inner layer or an outer layer of the ceramic substrate 12. And a caster conductor 15 provided on the wall surface in the notches 13 and 14 on the side surface of the ceramic substrate 12, and a small-diameter cut adjacent to the notches 13 and 14 on the side surface of the ceramic substrate 12. By providing the portion 16, the side surface and the castellation conductor 15 are separated from each other. The wiring pattern of the wiring board 11 is connected to the castellation conductor 15 at an appropriate location, and the wiring pattern and the electronic circuit element are connected by wire bonding or the like. Further, since the castellation conductor 15 is soldered on a solder land of a mother board (not shown) on which the wiring board 11 is mounted, an electronic circuit element on the wiring board 11 is connected to an external circuit via the castation conductor 15. Will be electrically connected. Note that a plating layer 17 made of nickel, gold, or the like is deposited on the entire surface of the castellation conductor 15 in order to improve solder wettability and prevent silver solder erosion.

キャスタレーション導体１５の構造について詳しく説明すると、セラミック基板１２の側面には、後述するスルーホール２３を２分割してなる切欠き１３と４分割してなる切欠き１４が複数個所に設けられていると共に、各切欠き１３の幅方向両端と該側面との間、および各切欠き１４の幅方向両端と該側面との間にそれぞれ、後述する分断孔２６を２分割してなる切除部１６が設けられている。これら切欠き１３，１４や切除部１６は、いずれもセラミック基板１２の上下両面に至る凹溝状に形成されている。そして、切欠き１３，１４内の壁面に銀等の良導電性材料からなる所定の厚みのキャスタレーション導体１５が設けられているが、後述するように切除部１６はキャスタレーション導体１５の一部を切除するようにして形成されるため、キャスタレーション導体１５の幅方向の端面１５ａは切除部１６の深さ相当分だけセラミック基板１２の側面よりも内側に位置している。つまり、図５に示す大判基板２７から配線基板１１を多数個取りする製造過程で、この大判基板２７の分割ライン２１，２２と各配線基板１１のキャスタレーション導体１５とは重なり合わない。そのため、この配線基板１１は大判基板２７の状態でキャスタレーション導体１５の全表面にメッキ層１７が被着できるようになっている。   The structure of the castellation conductor 15 will be described in detail. On the side surface of the ceramic substrate 12, a notch 13 formed by dividing a through hole 23 described later into two and a notch formed by dividing into four are provided at a plurality of locations. At the same time, there are cut portions 16 formed by dividing a dividing hole 26, which will be described later, into two portions, between the widthwise ends of each notch 13 and the side surfaces, and between the widthwise ends of each notch 14 and the side surfaces. Is provided. The notches 13 and 14 and the cut portion 16 are each formed in a concave groove shape extending to both the upper and lower surfaces of the ceramic substrate 12. A caster conductor 15 having a predetermined thickness made of a highly conductive material such as silver is provided on the wall surfaces in the notches 13 and 14, but the cut portion 16 is a part of the caster conductor 15 as described later. Therefore, the end face 15a in the width direction of the castellation conductor 15 is positioned on the inner side of the side surface of the ceramic substrate 12 by an amount corresponding to the depth of the cut portion 16. That is, in the manufacturing process of removing a large number of wiring boards 11 from the large board 27 shown in FIG. 5, the dividing lines 21 and 22 of the large board 27 and the castellation conductor 15 of each wiring board 11 do not overlap. For this reason, the wiring board 11 can be applied to the entire surface of the castellation conductor 15 in the state of the large-sized board 27.

この配線基板１１の製造方法を詳しく説明すると、まず、図３（ａ）に示すように、多数個取り用のグリーンシート２０の縦横の分割ライン２１，２２と重なり合う所定位置に、パンチングマシン等によってキャスタレーション導体１５用の多数のスルーホール２３を穿設する。このとき、図示せぬ配線パターン用のスルーホールも穿設しておく。そして、図３（ｂ）に示すように、これらスルーホール２３や配線パターン用スルーホールに銀ペースト２４を充填した後、図３（ｃ）に示すように、各スルーホール２３の中央部を貫通する中央孔２３ａを穿設して、各スルーホール２３の内壁に銀を主成分とする所定の厚みの円筒状導体２５を形成する。このとき、中央孔２３ａの直径をスルーホール２３の直径よりも例えば２００μｍ小さく設定しておくことにより、膜厚が約１００μｍの円筒状導体２５を形成することができる。なお、本実施形態例では、スルーホール２３が平面視円形であるが、平面視楕円形や平面視方形等のスルーホールであってもよい。   The manufacturing method of the wiring board 11 will be described in detail. First, as shown in FIG. 3A, a punching machine or the like is used to place the wiring board 11 at a predetermined position overlapping the vertical and horizontal dividing lines 21 and 22 of the multi-sheet green sheet 20. A number of through holes 23 for the castoration conductor 15 are formed. At this time, a through hole for a wiring pattern (not shown) is also formed. Then, as shown in FIG. 3B, these through holes 23 and wiring pattern through holes are filled with a silver paste 24, and then, as shown in FIG. A central hole 23 a is formed, and a cylindrical conductor 25 having a predetermined thickness mainly composed of silver is formed on the inner wall of each through-hole 23. At this time, by setting the diameter of the central hole 23a smaller than the diameter of the through hole 23 by, for example, 200 μm, the cylindrical conductor 25 having a film thickness of about 100 μm can be formed. In the present embodiment, the through hole 23 has a circular shape in plan view, but may be a through hole such as an elliptical shape in plan view or a square shape in plan view.

次に、図４に示すように、グリーンシート２０の分割ライン２１，２２と円筒状導体２５とが重なり合う個所にそれぞれ、同一スルーホール２３内の円筒状導体２５を分断する例えば直径が２００μｍの分断孔２６を穿設して、分断された円筒状導体２５をキャスタレーション導体１５となす。すなわち、分割ライン２１のみ、または分割ライン２２のみと重なり合うスルーホール２３内の円筒状導体２５は、２個所の分断孔２６により二分されるため、この分断孔２６を介して端面１５ａどうしが対向する２個のキャスタレーション導体１５が得られる。また、分割ライン２１，２２の交差部と重なり合うスルーホール２３内の円筒状導体２５は４個所の分断孔２６により四分されるため、この分断孔２６を介して端面１５ａどうしが対向する４個のキャスタレーション導体１５が得られる。なお、分断孔２６の大きさや形状は、同一スルーホール２３内の円筒状導体２５が確実に分断でき、かつキャスタレーション導体１５の導体量が不足しなければ、任意に選択可能である。   Next, as shown in FIG. 4, the cylindrical conductor 25 in the same through hole 23 is divided at the portion where the dividing lines 21 and 22 of the green sheet 20 and the cylindrical conductor 25 overlap, for example, a division having a diameter of 200 μm. The hole 26 is formed and the divided cylindrical conductor 25 is used as the castellation conductor 15. That is, only the dividing line 21 or the cylindrical conductor 25 in the through hole 23 that overlaps only the dividing line 22 is divided into two by the dividing holes 26, so that the end faces 15 a face each other through the dividing holes 26. Two castellation conductors 15 are obtained. Further, the cylindrical conductor 25 in the through hole 23 that overlaps the intersection of the dividing lines 21 and 22 is divided into four by the four dividing holes 26, so that the four end faces 15 a face each other through the dividing holes 26. The castellation conductor 15 is obtained. The size and shape of the dividing hole 26 can be arbitrarily selected as long as the cylindrical conductor 25 in the same through hole 23 can be reliably divided and the amount of the caster conductor 15 is not short.

この後、グリーンシート２０に図示せぬ配線パターン等を印刷し、次いで、所定枚数のグリーンシート２０を図示せぬ積層治具に積層して、これを真空パック状態で図示せぬ静水圧プレス装置に入れて加熱圧着することにより積層体となす。そして、この積層体を焼成することにより、図５に示すような多数個取り用の大判基板２７を得る。この大判基板２７は、縦横の分割ライン２１，２２によって区画されている小領域２８が各配線基板１１に対応している。   Thereafter, a wiring pattern or the like (not shown) is printed on the green sheet 20, and then a predetermined number of green sheets 20 are laminated on a lamination jig (not shown), and this is hydrostatic pressure press apparatus (not shown) in a vacuum pack state. It is made into a laminate by thermocompression bonding. And the large-sized board | substrate 27 for many pieces as shown in FIG. 5 is obtained by baking this laminated body. In this large-sized substrate 27, a small area 28 defined by vertical and horizontal dividing lines 21 and 22 corresponds to each wiring substrate 11.

次に、大判基板２７の表面に露出する導体部分にニッケルメッキや金メッキを施し、各キャスタレーション導体５にメッキ層１７を被着させる。このとき、各小領域２８のキャスタレーション導体１５は、分断孔２６の深さ相当分だけ分割ライン２１，２２よりも内側に位置しているため、大判基板２７の状態で各キャスタレーション導体１５の全表面にメッキ層１７を被着させることができる。しかる後、この大判基板２７を分割ライン２１，２２に沿って分割することにより、図１および図２に示すような配線基板１１を多数個取りできる。なお、この分割工程で、分割ライン２１，２２に沿う大判基板２７の分割面は各配線基板１１の側面となり、この側面の切欠き１３，１４はスルーホール２３を分割して形成されたものである。つまり、分割ライン２１のみ、または分割ライン２２のみと重なり合うスルーホール２３は、二分割されて配線基板１１の切欠き１３となり、分割ライン２１，２２の交差部と重なり合うスルーホール２３は四分割されて配線基板１１の切欠き１４となる。同様に、分割ライン２１や分割ライン２２と重なり合う分断孔２６は二分割されて配線基板１１の切除部１６となる。   Next, the conductor portion exposed on the surface of the large-sized substrate 27 is subjected to nickel plating or gold plating, and the plating layer 17 is adhered to each castellation conductor 5. At this time, since the castellation conductor 15 in each small region 28 is located on the inner side of the dividing lines 21 and 22 by an amount corresponding to the depth of the dividing hole 26, each castellation conductor 15 is in the state of the large substrate 27. The plating layer 17 can be deposited on the entire surface. Thereafter, a large number of wiring boards 11 as shown in FIGS. 1 and 2 can be obtained by dividing the large substrate 27 along the dividing lines 21 and 22. In this dividing step, the dividing surface of the large substrate 27 along the dividing lines 21 and 22 becomes the side surface of each wiring substrate 11, and the notches 13 and 14 on the side surfaces are formed by dividing the through holes 23. is there. That is, only the dividing line 21 or the through hole 23 that overlaps only the dividing line 22 is divided into two to form the notch 13 of the wiring board 11, and the through hole 23 that overlaps the intersection of the dividing lines 21 and 22 is divided into four. It becomes the notch 14 of the wiring board 11. Similarly, the dividing hole 26 that overlaps the dividing line 21 and the dividing line 22 is divided into two to form the cut portion 16 of the wiring board 11.

このように本実施形態例にあっては、配線基板１１の製造過程で、キャスタレーション導体１５の幅方向の端面１５ａを分割ライン２１，２２よりも内側に位置させるため、多数個取り用の大判基板２７を個片に分割する前に、該端面１５ａを含むキャスタレーション導体１５の全表面にメッキ層１７を被着させることができて、メッキ工程の作業効率が向上する。また、電子回路素子を搭載して導通検査等を行うというメッキ処理後の工程も、大判基板２７の状態で実施することができる。したがって、キャスタレーション導体１５中の銀成分の半田喰われを防止して信頼性を確保しつつ、生産性を大幅に高めることができる。しかも、分割ライン２１，２２とキャスタレーション導体１５とが重なり合わないので、大判基板２７の分割性は良好であり、それゆえ分割面にバリや欠け、汚れ等が生じにくくなって良品率の向上が期待できる。   As described above, in the present embodiment, the end face 15a in the width direction of the castellation conductor 15 is positioned on the inner side of the dividing lines 21 and 22 in the manufacturing process of the wiring board 11, so Before the substrate 27 is divided into individual pieces, the plating layer 17 can be deposited on the entire surface of the castellation conductor 15 including the end face 15a, thereby improving the working efficiency of the plating process. In addition, the post-plating process of mounting an electronic circuit element and conducting a continuity test or the like can be performed in the state of the large substrate 27. Therefore, it is possible to significantly increase productivity while ensuring reliability by preventing the silver component in the castellation conductor 15 from being eroded by solder. In addition, since the dividing lines 21 and 22 and the castoration conductor 15 do not overlap each other, the dividing property of the large-sized substrate 27 is good, so that burrs, chips, dirt, etc. are hardly generated on the dividing surface, and the yield rate is improved. Can be expected.

また、本実施形態例では、キャスタレーション導体１５を形成する際に、まずスルーホール２３に中央孔２３ａを穿設して所定の厚みの円筒状導体２５を形成した後、分断孔２６を穿設して円筒状導体２５から複数のキャスタレーション導体１５を得ているため、通常のパンチングマシン等で容易かつ正確に所望のキャスタレーション導体１５を形成できる。ただし、中央孔２３ａと分断孔２６を一括して穿設することも可能である。   In this embodiment, when the castoration conductor 15 is formed, the central hole 23a is first formed in the through hole 23 to form the cylindrical conductor 25 having a predetermined thickness, and then the dividing hole 26 is formed. Since a plurality of castellation conductors 15 are obtained from the cylindrical conductor 25, the desired castellation conductors 15 can be formed easily and accurately with a normal punching machine or the like. However, it is also possible to make the central hole 23a and the dividing hole 26 at once.

なお、上記の実施形態例では、セラミック基板１２が多層基板である配線基板１１とその製造方法について説明したが、セラミック基板が単層の配線基板であっても本発明を適用できることは言うまでもない。   In the above embodiment, the wiring substrate 11 in which the ceramic substrate 12 is a multilayer substrate and the manufacturing method thereof have been described. However, it goes without saying that the present invention can be applied even if the ceramic substrate is a single-layer wiring substrate.

本発明の実施形態例に係る配線基板のキャスタレーション導体を示す斜視図である。It is a perspective view which shows the castellation conductor of the wiring board which concerns on the example of embodiment of this invention. 該キャスタレーション導体の断面図である。It is sectional drawing of this castellation conductor. 該配線基板の製造工程図である。It is a manufacturing process figure of this wiring board. 該配線基板の製造工程図である。It is a manufacturing process figure of this wiring board. 該配線基板の製造工程図である。It is a manufacturing process figure of this wiring board. 従来の配線基板のキャスタレーション導体を示す斜視図である。It is a perspective view which shows the castellation conductor of the conventional wiring board. 図６に示す従来の配線基板の製造過程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the conventional wiring board shown in FIG.

符号の説明Explanation of symbols

１１ 配線基板
１２ セラミック基板
１３，１４ 切欠き
１５ キャスタレーション導体
１５ａ 端面
１６ 切除部
１７ メッキ層
２０ セラミックグリーンシート
２１，２２ 分割ライン
２３ スルーホール
２３ａ 中央孔
２４ 銀ペースト
２５ 円筒状導体
２６ 分断孔
２７ 大判基板 DESCRIPTION OF SYMBOLS 11 Wiring board 12 Ceramic board 13,14 Notch 15 Castoration conductor 15a End face 16 Cut part 17 Plating layer 20 Ceramic green sheet 21, 22 Dividing line 23 Through hole 23a Central hole 24 Silver paste 25 Cylindrical conductor 26 Dividing hole 27 Large size substrate

Claims (5)

上下両面に至る凹溝状の切欠きが側面に設けられたセラミック基板と、前記切欠き内の壁面に設けられてメッキ層が被着されたキャスタレーション導体とを備え、前記セラミックは大判基板を分割ラインに沿って分割することにより多数個取りされる配線基板において、
前記セラミック基板の前記切欠きが臨出する側面と該切欠きの幅方向両端との間に、該セラミック基板の上下両面に至る凹溝状の切除部を設け、この切除部によって該側面と前記キャスタレーション導体とを離隔させたことを特徴とする配線基板。 A ceramic substrate provided with a concave groove-shaped notch extending on both sides of the upper and lower sides, and a castellation conductor provided on a wall surface in the notch and having a plating layer deposited thereon, the ceramic comprising a large substrate In the wiring board that is taken many by dividing along the dividing line,
Between the side surface where the cutout of the ceramic substrate protrudes and both ends of the cutout in the width direction, there are provided groove-shaped cut portions extending to the upper and lower surfaces of the ceramic substrate, and the cut portion cuts the side surface and the side surface. A wiring board characterized by separating a castellation conductor. 請求項１の記載において、前記セラミック基板が多層基板であることを特徴とする配線基板。   2. The wiring board according to claim 1, wherein the ceramic substrate is a multilayer substrate. 多数個取り用のグリーンシートの分割ラインと重なり合う所定位置に多数のキャスタレーション導体用スルーホールを穿設した後、これらスルーホールに導電材料を充填する導電材料充填工程と、
この導電材料充填工程後に前記キャスタレーション導体用スルーホールを貫通する貫通孔を穿設して、該スルーホール内の前記導電材料の一部を前記分割ラインに沿って切除することにより、該分割ラインから離隔した所定の厚みのキャスタレーション導体を該スルーホールの内壁に複数形成するキャスタレーション導体形成工程と、
このキャスタレーション導体形成工程後に前記グリーンシートを焼成して多数個取り用の大判基板を得る焼成工程と、
前記焼成工程後に前記キャスタレーション導体の全表面にメッキ層を被着させるメッキ工程と、
前記メッキ工程後に前記大判基板を前記分割ラインに沿って個片に分割する分割工程とを含み、
前記分割工程によって前記キャスタレーション導体を有する配線基板が多数個取りされるようにしたことを特徴とする配線基板の製造方法。 A conductive material filling step of filling a plurality of through holes for castellation conductors at predetermined positions overlapping with dividing lines of a multi-sheet green sheet, and filling the through holes with a conductive material;
By forming a through hole penetrating the through hole for castellation conductor after the conductive material filling step, and cutting off a part of the conductive material in the through hole along the division line, the division line A castellation conductor forming step of forming a plurality of castellation conductors of a predetermined thickness separated from the inner wall of the through hole;
A firing step of firing the green sheet after the castellation conductor forming step to obtain a large-sized substrate for taking a large number of pieces;
A plating step of depositing a plating layer on the entire surface of the castellation conductor after the firing step;
A dividing step of dividing the large substrate into pieces along the dividing line after the plating step,
A method of manufacturing a wiring board, wherein a large number of wiring boards having the castellation conductors are removed by the dividing step. 請求項３の記載において、前記キャスタレーション導体形成工程は、
前記キャスタレーション導体用スルーホールの中央部に該スルーホールよりも小径な中央孔を穿設することによって、該スルーホールの内壁に所定の厚みの前記導電材料を残存させる導体厚設定工程と、
この導体厚設定工程後に前記グリーンシートの分割ラインと前記導電材料とが重なり合う個所にそれぞれ前記スルーホールよりも小径で該導電材料を分断する分断孔を穿設することによって、該スルーホールの内壁に該分断孔を介して端面どうしが対向する複数の前記キャスタレーション導体を形成する導体分断工程とを含むことを特徴とする配線基板の製造方法。 The castellation conductor forming step according to claim 3,
Conductor thickness setting step of leaving the conductive material of a predetermined thickness on the inner wall of the through hole by drilling a central hole having a smaller diameter than the through hole at the center of the through hole for the castor conductor,
After the conductor thickness setting step, by forming a dividing hole that divides the conductive material with a smaller diameter than the through hole at a portion where the dividing line of the green sheet and the conductive material overlap each other, an inner wall of the through hole is formed. And a conductor dividing step of forming a plurality of the castellation conductors whose end faces are opposed to each other through the dividing hole. 請求項３または４の記載において、前記キャスタレーション導体形成工程後に前記グリーンシートを複数枚積層して加熱圧着する積層体形成工程を行い、この積層体形成工程後に前記焼成工程を行うことにより前記大判基板を多層基板となしたことを特徴とする配線基板の製造方法。   5. The large format according to claim 3, wherein after the castellation conductor formation step, a plurality of the green sheets are laminated and subjected to thermocompression bonding, and the firing step is performed after the laminate formation step. A method of manufacturing a wiring board, wherein the board is a multilayer board.
JP2005282152A 2005-09-28 2005-09-28 Wiring board manufacturing method Expired - Fee Related JP4703342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005282152A JP4703342B2 (en) 2005-09-28 2005-09-28 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005282152A JP4703342B2 (en) 2005-09-28 2005-09-28 Wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP2007095927A true JP2007095927A (en) 2007-04-12
JP4703342B2 JP4703342B2 (en) 2011-06-15

Family

ID=37981267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005282152A Expired - Fee Related JP4703342B2 (en) 2005-09-28 2005-09-28 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP4703342B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294246A (en) * 2007-05-25 2008-12-04 Koa Corp End electrode forming method of low-temperature baked ceramic multilayer substrate
JP2009158892A (en) * 2007-12-28 2009-07-16 Nec Corp Multilayer wiring board and method of manufacturing the same
US20100244166A1 (en) * 2009-03-30 2010-09-30 Sony Corporation Multilayer wiring substrate, stack structure sensor package, and method of manufacturing stack structure sensor package
KR101001352B1 (en) * 2008-09-04 2010-12-14 삼성전기주식회사 board for package
JP2012174713A (en) * 2011-02-17 2012-09-10 Kyocera Corp Electronic component housing package, and electronic equipment including the same
JP2013026277A (en) * 2011-07-15 2013-02-04 Kyocera Corp Base plate with built-in coil and electronic module
JP2013239559A (en) * 2012-05-15 2013-11-28 Denso Corp Method for manufacturing multilayer circuit board
JP2015060976A (en) * 2013-09-19 2015-03-30 京セラ株式会社 Multi-piece wiring board
TWI651030B (en) * 2017-11-27 2019-02-11 健鼎科技股份有限公司 Circuit board and manufacturing method thereof
CN109803494A (en) * 2017-11-17 2019-05-24 健鼎（无锡）电子有限公司 Circuit board and its manufacturing method
CN115767882A (en) * 2023-01-09 2023-03-07 苏州浪潮智能科技有限公司 Differential signal transmission circuit, circuit board, electronic device, and circuit manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10126024A (en) * 1996-10-24 1998-05-15 Hitachi Aic Inc Wiring board having end-face through hole
JP2001077507A (en) * 1999-09-02 2001-03-23 Sumitomo Metal Electronics Devices Inc Manufacture of castellation structure of multi-circuit board
JP2003178928A (en) * 2001-10-05 2003-06-27 Murata Mfg Co Ltd Monolithic ceramic electronic part, manufacturing method therefor and aggregate electronic part

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10126024A (en) * 1996-10-24 1998-05-15 Hitachi Aic Inc Wiring board having end-face through hole
JP2001077507A (en) * 1999-09-02 2001-03-23 Sumitomo Metal Electronics Devices Inc Manufacture of castellation structure of multi-circuit board
JP2003178928A (en) * 2001-10-05 2003-06-27 Murata Mfg Co Ltd Monolithic ceramic electronic part, manufacturing method therefor and aggregate electronic part

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294246A (en) * 2007-05-25 2008-12-04 Koa Corp End electrode forming method of low-temperature baked ceramic multilayer substrate
JP2009158892A (en) * 2007-12-28 2009-07-16 Nec Corp Multilayer wiring board and method of manufacturing the same
KR101001352B1 (en) * 2008-09-04 2010-12-14 삼성전기주식회사 board for package
US20100244166A1 (en) * 2009-03-30 2010-09-30 Sony Corporation Multilayer wiring substrate, stack structure sensor package, and method of manufacturing stack structure sensor package
US8446002B2 (en) * 2009-03-30 2013-05-21 Sony Corporation Multilayer wiring substrate having a castellation structure
JP2012174713A (en) * 2011-02-17 2012-09-10 Kyocera Corp Electronic component housing package, and electronic equipment including the same
JP2013026277A (en) * 2011-07-15 2013-02-04 Kyocera Corp Base plate with built-in coil and electronic module
JP2013239559A (en) * 2012-05-15 2013-11-28 Denso Corp Method for manufacturing multilayer circuit board
JP2015060976A (en) * 2013-09-19 2015-03-30 京セラ株式会社 Multi-piece wiring board
CN109803494A (en) * 2017-11-17 2019-05-24 健鼎（无锡）电子有限公司 Circuit board and its manufacturing method
TWI651030B (en) * 2017-11-27 2019-02-11 健鼎科技股份有限公司 Circuit board and manufacturing method thereof
CN115767882A (en) * 2023-01-09 2023-03-07 苏州浪潮智能科技有限公司 Differential signal transmission circuit, circuit board, electronic device, and circuit manufacturing method

Also Published As

Publication number Publication date
JP4703342B2 (en) 2011-06-15

Similar Documents

Publication Publication Date Title
JP4703342B2 (en) Wiring board manufacturing method
JP5763962B2 (en) Ceramic wiring board, multi-cavity ceramic wiring board, and manufacturing method thereof
JP2012230945A (en) Wiring substrate, multi-piece wiring substrate, and manufacturing method thereof
WO2006112337A1 (en) Semiconductor device and semiconductor device manufacturing method
JP2008153441A (en) Wiring substrate, and manufacturing method thereof
US10123413B2 (en) Package substrate and manufacturing method thereof
JP2009170561A (en) Wiring substrate and its manufacturing method
JP5235627B2 (en) Multiple wiring board
JP2007234749A (en) Manufacturing method of chip-shape solid electrolytic capacitor
JP5738109B2 (en) Multiple wiring board
JP2011071368A (en) Multiple-pattern wiring board
JP6258810B2 (en) Wiring board manufacturing method
JP2010283074A (en) Method for manufacturing substrate, substrate and ceramic substrate
JP2008187198A (en) Multi-piece wiring substrate and wiring substrate, and manufacturing method therefor
JPH1126913A (en) Manufacture of wiring substrate
JP4723275B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP4728032B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2019047005A (en) Multi-cavity ceramic substrate and manufacturing method thereof
JP2009194000A (en) Multiple wiring board
JP6506132B2 (en) Multi-cavity wiring board and wiring board
JP2005340538A (en) Multiple patterning wiring board
JP2006041310A (en) Multi-pattern wiring board
JP6374279B2 (en) Multi-cavity wiring board, wiring board, and manufacturing method of multi-cavity wiring board
JP2014192471A (en) Method of manufacturing wiring board and wiring board
JP2008053444A (en) Production process of ceramic substrate, and electronic circuit module employing it

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080627

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101208

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101214

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110203

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110222

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110308

R150 Certificate of patent or registration of utility model

Ref document number: 4703342

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees