JP2007088232A - Method of manufacturing printed wiring board - Google Patents

Method of manufacturing printed wiring board Download PDF

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JP2007088232A
JP2007088232A JP2005275474A JP2005275474A JP2007088232A JP 2007088232 A JP2007088232 A JP 2007088232A JP 2005275474 A JP2005275474 A JP 2005275474A JP 2005275474 A JP2005275474 A JP 2005275474A JP 2007088232 A JP2007088232 A JP 2007088232A
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resist
pattern
substrate material
groove
product
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Mitsuru Koyama
充 小山
Nobutaka Tanaka
宣孝 田中
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Daisho Denshi Co Ltd
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Daisho Denshi Co Ltd
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  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a printed wiring board which ensures the surface flatness and reduces adverse influences to a minimum such as mounting failures due to the board refuse. <P>SOLUTION: The method comprises a step of forming a pattern 3 on a product 2 of a board material 1, coating the surface of the board material 1 with a first resist 6, applying the exposure and developing processes to remove suitably parts of the first resist 6, feeding the pattern 3 with power from a power feed line connected to the pattern 3 through lead wires 7 to form a plating layer 13 on the pattern 3, forming trenches 4 piercing the front side to the backside around the product part 2 except a plurality of thin-width connecting parts 5, coating the surface of the trenches 4 with a second resist 9 after cleaning, and cutting off the connectors to separate spaces outside the trenches 4 from the products 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、表面にめっき層を形成したパターンを有するプリント基板の製造方法に関する。   The present invention relates to a method for manufacturing a printed circuit board having a pattern in which a plating layer is formed on the surface.

プリント基板を製造するには、製品の外側にツーリング・ホール、レジストレーション・マーク、テスト・クーポン等のためのスペースが必要なので、従来は、大きい基板材の一部を製品部分とし、その表面にパターンを基板材周縁との間に間隔を開けて形成した後、ソルダー・レジスト等の保護レジストをコーティングし、最後に、製品部分の周囲をプレス加工又はルータ加工により切り取ってプリント基板を得ていた。   In order to manufacture printed circuit boards, space for tooling holes, registration marks, test coupons, etc. is required outside the product. Conventionally, a part of a large board material is used as a product part on the surface. After the pattern was formed with a gap between the substrate and the periphery, a protective resist such as solder resist was coated, and finally, the printed circuit board was obtained by cutting the periphery of the product part by pressing or router processing. .

ところで、近年、デバイス実装等、極小電子部品の搭載が増加する傾向にあり、外形加工時に発生する切削屑が飛び散ってパターンに付着すると、実装不良となってしまう。また、プリント基板製造の最終工程では、切削屑等を除去するために純水洗浄を行っているが、外形加工後の切断端面から発生する数十ミクロンのカスは後を絶たず、これによる悪影響も無視できない。   By the way, in recent years, there has been a tendency for mounting of very small electronic components such as device mounting, and if cutting waste generated during outer shape processing is scattered and adhered to a pattern, mounting failure occurs. Also, in the final process of printed circuit board manufacturing, pure water cleaning is performed to remove cutting debris, etc., but tens of microns of debris generated from the cut end face after the outer shape processing is continually being affected. Cannot be ignored.

この対策として、例えば、特許文献１には、基板材１の製品部分２の表面にパターン３を形成した後、製品部分２の周囲に、複数の細幅の接続部を除いて表裏面に貫通する溝４を形成し、さらに、洗浄してから、基板材１及び溝４の表面にレジスト６を塗布し、次いで、露光及び現像処理を施してレジスト６の適宜箇所を除去し、次に、前記接続部を切断して製品部分２と溝４より外側のスペースとを分離する工程より成る技術が提案されている（例えば、図１０〜図１２参照）。
特開平１１−１４５５８０号公報 As a countermeasure, for example, in Patent Document 1, a pattern 3 is formed on the surface of the product portion 2 of the substrate material 1 and then penetrates the front and back surfaces around the product portion 2 except for a plurality of narrow connection portions. The groove 4 to be formed is further formed, and after washing, a resist 6 is applied to the surface of the substrate material 1 and the groove 4, and then exposed and developed to remove appropriate portions of the resist 6. There has been proposed a technique comprising a step of cutting the connecting portion to separate the product portion 2 and the space outside the groove 4 (see, for example, FIGS. 10 to 12).
Japanese Patent Laid-Open No. 11-145580

しかしながら、従来の技術においては、以下のような問題がある。
すなわち、基板材の表面に比して溝の表面にはレジスト６を塗布し難いため、溝の表面に形成されるレジストの厚さは基板材の表面に形成されるレジスト６の厚さよりも薄くなってしまう。一方、外形加工時に発生する切削屑を防止するためには、溝の表面（換言すれば、製品部分２の端面）に一定以上の厚さでレジスト６を形成する必要がある。従って、従来においては、図１１に示すように、製品部分２の端面近傍の表面に塗布されるレジストに膨らみ１１が生じ易く、そのため、製品部分２の表面の平坦度を確保し難くなってしまう。その結果、プリント配線板に電子部品を搭載する際に作業負担を引き起こす虞があるという問題がある。 However, the conventional techniques have the following problems.
That is, since it is difficult to apply the resist 6 to the surface of the groove compared to the surface of the substrate material, the thickness of the resist formed on the surface of the groove is thinner than the thickness of the resist 6 formed on the surface of the substrate material. turn into. On the other hand, in order to prevent cutting waste generated during the outer shape processing, it is necessary to form the resist 6 with a certain thickness or more on the surface of the groove (in other words, the end surface of the product portion 2). Therefore, in the prior art, as shown in FIG. 11, the swell 11 is likely to occur in the resist applied to the surface near the end face of the product part 2, so that it is difficult to ensure the flatness of the surface of the product part 2. . As a result, there is a problem that there is a risk of causing a work burden when electronic components are mounted on the printed wiring board.

また、基板材表面のパターン３には、耐食性の確保等のためにニッケル金等からなるめっき層を形成する場合が多い。しかしながら、めっき層を形成するためには、図１２に示すように、製品部分２の外側の給電線８を介して給電を行う必要がある。このため、給電線８とパターン３とを接続するリード線７が形成される領域には溝４を形成できず、この領域の切断端面をレジスト６で覆って基板材カスの発生を防ぐことができないという問題がある。   Further, a plating layer made of nickel gold or the like is often formed on the pattern 3 on the surface of the substrate material in order to ensure corrosion resistance. However, in order to form the plating layer, it is necessary to supply power via the power supply line 8 outside the product portion 2 as shown in FIG. For this reason, the groove 4 cannot be formed in the region where the lead wire 7 connecting the power supply line 8 and the pattern 3 is formed, and the cut end surface of this region is covered with the resist 6 to prevent the generation of substrate material residue. There is a problem that you can not.

従って、本発明は、上記事情に鑑みてなされたものであり、その目的は、表面の平坦度を確保するとともに、基板材カスによる実装不良等の悪影響を最小限に抑えることができるプリント配線板の製造方法を提供することにある。   Accordingly, the present invention has been made in view of the above circumstances, and its purpose is to ensure a flat surface and to minimize adverse effects such as mounting defects due to substrate material residue. It is in providing the manufacturing method of.

基板材の製品部分の表面にパターンを形成し、前記基板材の表面に第１レジストを塗布し、次いで、露光及び現像処理を施して前記第１レジストの適宜箇所を除去し、前記パターンにリード線を介して接続された給電線により前記パターンに給電して、前記パターンにめっき層を形成し、前記製品部分の周囲に、複数の細幅の接続部を除いて表裏面に貫通する溝を形成し、さらに、洗浄してから、前記溝の表面に第２レジストを塗布し、次に、前記接続部を切断して製品部分と溝より外側のスペースとを分離することを特徴とする。   A pattern is formed on the surface of the product portion of the substrate material, a first resist is applied to the surface of the substrate material, then exposure and development are performed to remove appropriate portions of the first resist, and lead to the pattern Power is supplied to the pattern by a power supply line connected via a wire, a plating layer is formed on the pattern, and a groove penetrating the front and back surfaces around the product portion excluding a plurality of narrow connection portions. After forming and further cleaning, a second resist is applied to the surface of the groove, and then the connecting portion is cut to separate a product portion and a space outside the groove.

この発明によれば、前記基板材の表面には第１レジストが、前記溝の表面には第２レジストが、それぞれ独立に塗布されるので、それぞれのレジスト厚さを任意に制御することが可能となる。従って、前記溝の表面に第２レジストを必要厚さ分塗布して基板材カスの発生を防ぐとともに、前記基板材の表面に塗布される第１レジストの厚さを略一定にして、前記基板材の表面の平坦度を確保することが可能となる。加えて、前記パターンの表面にめっき層を形成した後に前記溝を形成するので、リード線が形成される領域であっても溝を形成することができ、この領域の切断端面を前記第２レジストで覆って基板材カスの発生を防ぐことができるので、基板材カスによる実装不良等の悪影響を最小限に抑えることができる。   According to the present invention, since the first resist is applied to the surface of the substrate material and the second resist is applied to the surface of the groove, the resist thickness can be arbitrarily controlled. It becomes. Accordingly, the second resist is applied to the surface of the groove by a necessary thickness to prevent generation of substrate material debris, and the thickness of the first resist applied to the surface of the substrate material is substantially constant, It becomes possible to ensure the flatness of the surface of the plate material. In addition, since the groove is formed after the plating layer is formed on the surface of the pattern, the groove can be formed even in the region where the lead wire is formed, and the cut end surface of this region is formed on the second resist. Since the generation of substrate material residue can be prevented by covering the substrate, adverse effects such as defective mounting due to the substrate material residue can be minimized.

この場合において、前記接続部を製品部分のコーナーに形成するようにしてもよい。
このようにすると、製品部分と溝より外側のスペースとの分離も容易に行うことができる。 In this case, the connecting portion may be formed at a corner of the product portion.
If it does in this way, isolation | separation with the space outside a product part and a groove | channel can also be performed easily.

本発明のプリント基板の製造方法によれば、表面の平坦度を確保するとともに、基板材カスによる実装不良等の悪影響を最小限に抑えることができる。   According to the method for manufacturing a printed circuit board of the present invention, it is possible to secure the flatness of the surface and minimize adverse effects such as mounting defects caused by the substrate material residue.

以下、本発明を実施するための最良の形態について、図１〜図１０を参照して説明する。
プリント基板を製造するには、まず、図１、図２（ａ）に示すように、電気絶縁板の表面に銅箔等の導電層を形成して成る基板材１上に、プリント基板となる製品部分２のスペースを決め、製品部分２の表面にパターン３を形成する。基板材１の電気絶縁板は、プリント基板の用途や必要とする精度に応じて、ポリイミド樹脂、エポキシ系樹脂をガラス・合成繊維等に含浸させた素材、コンポジット材等から適宜選択する。 The best mode for carrying out the present invention will be described below with reference to FIGS.
To manufacture a printed circuit board, first, as shown in FIGS. 1 and 2A, a printed circuit board is formed on a substrate material 1 formed by forming a conductive layer such as a copper foil on the surface of an electrical insulating plate. A space for the product portion 2 is determined, and a pattern 3 is formed on the surface of the product portion 2. The electrical insulating plate of the substrate material 1 is appropriately selected from a material obtained by impregnating glass / synthetic fibers with a polyimide resin or an epoxy resin, a composite material, or the like, depending on the use of the printed circuit board and the required accuracy.

また、基板材１の大きさは、メーカーが何種類かの標準サイズのものを用意しており、一枚の基板材から一枚のプリント基板をとるのは効率が悪いため、大きい基板材１の表面に、その周縁と製品部分２との間に１５〜３０mm程度の間隔があくと共に、製品部分２の間に若干の間隔があくように、多面付けを行ってパターン３を形成すると良い。   Also, the size of the substrate material 1 is prepared by several manufacturers of standard sizes, and it is inefficient to take one printed circuit board from one substrate material. The pattern 3 may be formed by performing multi-sided attachment so that a space of about 15 to 30 mm is provided between the peripheral edge of the surface and the product portion 2 and a slight space is provided between the product portions 2.

パターン３を形成するには、基板材１の表面に液状タイプ又はドライ・フィルム・タイプのレジスト層を形成し、さらにその表面にフォト・マスクを重ねてから露光し、その後、現像処理を行って露光されていないパターン部のレジスト層を除去し、次いで、導電層のレジスト層で保護されていない部分を塩化第二鉄等のエッチング液で取り除く、いわゆるフォト・エッチング法を採用するのが一般的である。また、多層のプリント基板の場合は、内層パターンの上にプリプレグを介して片面銅張積層板を貼着し、上記パターン形成工程を繰り返せば良い。   In order to form the pattern 3, a liquid type or dry film type resist layer is formed on the surface of the substrate material 1, and a photo mask is placed on the surface, followed by exposure, and then development processing is performed. It is common to use a so-called photo-etching method that removes the resist layer of the pattern portion that is not exposed and then removes the portion of the conductive layer that is not protected by the resist layer with an etching solution such as ferric chloride. It is. Moreover, in the case of a multilayer printed circuit board, a single-sided copper-clad laminate is stuck on the inner layer pattern via a prepreg, and the pattern formation process is repeated.

図２（ｂ）に示すように、基板材１の表面に形成されたパターン３は、製品部分２よりも外側に位置する給電線８にリード線７を介して接続されている。
そして、図３に示すように、基板材１に第１レジスト６を塗布して、基板材１の表面および端面を第１レジスト６で被覆する。
さらに、レジスト６の表面にフォト・マスクを重ねて露光した後、現像処理を行い、図４に示すように、レジスト６の適宜箇所、例えば表面実装部品を接続するためにパターン３を露出させる箇所や給電線８を露出させる箇所等を除去する。 As shown in FIG. 2B, the pattern 3 formed on the surface of the substrate material 1 is connected via a lead wire 7 to a power supply line 8 located outside the product portion 2.
Then, as shown in FIG. 3, the first resist 6 is applied to the substrate material 1, and the surface and the end surface of the substrate material 1 are covered with the first resist 6.
Further, after exposing the surface of the resist 6 with a photo mask, development processing is performed, and as shown in FIG. 4, an appropriate portion of the resist 6, for example, a portion where the pattern 3 is exposed to connect the surface mounting components And a portion where the feeder 8 is exposed is removed.

次に、図５に示すように、給電線８からリード線７を介してパターン３の表面に給電して、パターン３の表面に例えばニッケル金からなるめっき層１３を形成する。
次に、図６に示すように、製品部分２の周囲に、基板材１の表裏面に貫通する溝４をプレス又はルータにより形成する。この溝４は、製品部分２のコーナーに配置される細幅の接続部５を除いて形成され、これらの接続部５によって製品部分２と基板材１の他のスペースとが接続される。その後、基板材１を純水等で洗浄して、溝４を形成する際に発生した切削屑等のゴミを除去する。 Next, as shown in FIG. 5, power is supplied from the power supply line 8 to the surface of the pattern 3 via the lead wire 7, and a plating layer 13 made of, for example, nickel gold is formed on the surface of the pattern 3.
Next, as shown in FIG. 6, a groove 4 penetrating the front and back surfaces of the substrate material 1 is formed around the product portion 2 by a press or a router. The groove 4 is formed except for a narrow connection portion 5 arranged at a corner of the product portion 2, and the product portion 2 and another space of the substrate material 1 are connected by these connection portions 5. Thereafter, the substrate material 1 is washed with pure water or the like to remove dust such as cutting waste generated when the grooves 4 are formed.

次いで、図７に示すように、基板材１の表面に再度レジスト１０を塗布する。再度レジスト１０を塗布することにより、溝４の表面に第２レジスト９が形成される。すると、製品部分２の外形端面が、接続部５を除いて第２レジスト９で被覆されるため、この部分から基板材１のカスが発生することはない。さらに、図８に示すように、基板材１の表面に塗布したレジスト１０を溝４の表面のみ露光・硬化させ、その他は現像処理により除去する。次に、接続部５をプレス又はＮＣルータにより切断して、図９に示すように、製品部分２と溝４より外側のスペースとを分離する。   Next, as shown in FIG. 7, a resist 10 is applied again on the surface of the substrate material 1. By applying the resist 10 again, the second resist 9 is formed on the surface of the groove 4. Then, since the outer end face of the product portion 2 is covered with the second resist 9 except for the connection portion 5, no residue of the substrate material 1 is generated from this portion. Further, as shown in FIG. 8, the resist 10 applied to the surface of the substrate material 1 is exposed and cured only on the surface of the groove 4, and the others are removed by development processing. Next, the connecting portion 5 is cut by a press or an NC router to separate the product portion 2 and the space outside the groove 4 as shown in FIG.

以上説明したように、本実施例によれば、基板材１の表面には第１レジスト６が、溝４の表面には第２レジスト９が、それぞれ独立に塗布されるので、それぞれのレジスト６、９の厚さを任意に制御することが可能となる。従って、溝４の表面に第２レジスト９を必要厚さ分塗布して基板材カスの発生を防ぐとともに、基板材１の表面に塗布される第１レジスト６の厚さを略一定にして、基板材１の表面の平坦度を確保することが可能となる。 加えて、パターン３の表面にめっき層１３を形成した後に溝４を形成するので、リード線７が形成される領域であっても溝４を形成することができ、この領域の切断端面を第２レジスト９で覆って基板材カスの発生を防ぐことができるので、基板材カスによる実装不良等の悪影響を最小限に抑えることができる。   As described above, according to the present embodiment, the first resist 6 is applied to the surface of the substrate material 1 and the second resist 9 is applied to the surface of the groove 4 independently. , 9 can be arbitrarily controlled. Accordingly, the second resist 9 is applied to the surface of the groove 4 by a necessary thickness to prevent the generation of the substrate material residue, and the thickness of the first resist 6 applied to the surface of the substrate material 1 is made substantially constant, It becomes possible to ensure the flatness of the surface of the substrate material 1. In addition, since the groove 4 is formed after the plating layer 13 is formed on the surface of the pattern 3, the groove 4 can be formed even in the region where the lead wire 7 is formed. Since it is possible to prevent the generation of the substrate material residue by covering with the two resists 9, it is possible to minimize adverse effects such as mounting defects caused by the substrate material residue.

なお、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々の設計変更が可能である。例えば、実施例では、接続部５を製品部分２のコーナーに形成しているので、製品部分２と溝４より外側のスペースとの分離を容易に行うことができる点で好ましいが、コーナー以外に接続部５を形成してもよい。   In addition, this invention is not limited to the said Example, A various design change is possible in the range which does not deviate from the summary. For example, in the embodiment, since the connecting portion 5 is formed at the corner of the product portion 2, it is preferable in that the product portion 2 and the space outside the groove 4 can be easily separated. The connecting portion 5 may be formed.

本発明の一実施例によるプリント配線板の要部平面図である。It is a principal part top view of the printed wiring board by one Example of this invention. 本発明の一実施例によるプリント配線板の基板材を示す断面図である。It is sectional drawing which shows the board | substrate material of the printed wiring board by one Example of this invention. 図２に示す基板材に第１レジストを形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the 1st resist in the board | substrate material shown in FIG. 図３に続いて、第１レジストの所定領域を除去した状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state where a predetermined region of the first resist is removed following FIG. 3. 図４に続いて、第１レジスト層下の銅箔を給電部として、露出した基板材のパターン表面にニッケル金めっき層を形成した状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which a nickel gold plating layer is formed on the exposed pattern surface of the substrate material, with the copper foil under the first resist layer as a power feeding portion, following FIG. 4. 図５に続いて、基板材に溝を形成した状態を示す断面図である。FIG. 6 is a cross-sectional view illustrating a state where grooves are formed in the substrate material, following FIG. 5. 図６に続いて、基板材にマスクパターンを形成した状態を示す断面図である。FIG. 7 is a cross-sectional view illustrating a state in which a mask pattern is formed on the substrate material following FIG. 6. 図７に続いて、基板材の溝表面に第２レジストを形成した状態を示す断面図である。FIG. 8 is a cross-sectional view illustrating a state in which a second resist is formed on the groove surface of the substrate material following FIG. 7. 図８に続いて、マスクパターンを除去した状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state where the mask pattern is removed following FIG. 8. 従来におけるプリント配線板の要部平面図である。It is a principal part top view of the conventional printed wiring board. 従来におけるプリント配線板の問題点を示す要部断面図である。It is principal part sectional drawing which shows the problem of the conventional printed wiring board. 従来におけるプリント配線板の問題点を示す要部平面図である。It is a principal part top view which shows the problem of the printed wiring board in the past.

符号の説明Explanation of symbols

１…基板材
２…製品部分
３…パターン
４…溝
５…接続部
６…第１レジスト
７…リード線
８…給電線
９…第２レジスト
１０…マスクパターン
１３…めっき層
DESCRIPTION OF SYMBOLS 1 ... Board | substrate material 2 ... Product part 3 ... Pattern 4 ... Groove 5 ... Connection part 6 ... 1st resist 7 ... Lead wire 8 ... Feeding wire 9 ... 2nd resist 10 ... Mask pattern 13 ... Plating layer

Claims (2)

基板材の製品部分の表面にパターンを形成し、
前記基板材の表面に第１レジストを塗布し、次いで、露光及び現像処理を施して前記第１レジストの適宜箇所を除去し、
前記パターンにリード線を介して接続された給電線により前記パターンに給電して、前記パターンにめっき層を形成し、
前記製品部分の周囲に、複数の細幅の接続部を除いて表裏面に貫通する溝を形成し、
さらに、洗浄してから、前記溝の表面に第２レジストを塗布し、次に、前記接続部を切断して製品部分と溝より外側のスペースとを分離することを特徴とするプリント基板の製造方法。 A pattern is formed on the surface of the product part of the substrate material,
A first resist is applied to the surface of the substrate material, and then exposed and developed to remove appropriate portions of the first resist,
Power is supplied to the pattern by a power supply line connected to the pattern via a lead wire, and a plating layer is formed on the pattern.
Around the product part, forming a groove penetrating the front and back surfaces excluding a plurality of narrow connection portions,
Further, after cleaning, a second resist is applied to the surface of the groove, and then the connection portion is cut to separate a product portion and a space outside the groove, thereby producing a printed circuit board Method. 前記接続部を製品部分のコーナーに形成することを特徴とする請求項１に記載のプリント基板の製造方法。

The method for manufacturing a printed circuit board according to claim 1, wherein the connection portion is formed at a corner of the product portion.

JP2005275474A 2005-09-22 2005-09-22 Method of manufacturing printed wiring board Pending JP2007088232A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026923A (en) * 2007-07-19 2009-02-05 Cmk Corp Printed circuit boards, and manufacturing method therefor
US9939753B2 (en) 2014-12-08 2018-04-10 Canon Kabushiki Kaisha Printed circuit board, exposure device having printed circuit board, and image forming apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10173320A (en) * 1996-12-13 1998-06-26 Teikoku Tsushin Kogyo Co Ltd Coating method of press-torn surface provided on printed board
JPH11145580A (en) * 1997-11-10 1999-05-28 Daisho Denshi:Kk Manufacture of printed board
JP2005197648A (en) * 2003-12-09 2005-07-21 Shinko Electric Ind Co Ltd Method for manufacturing a circuit board wired by electroplating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10173320A (en) * 1996-12-13 1998-06-26 Teikoku Tsushin Kogyo Co Ltd Coating method of press-torn surface provided on printed board
JPH11145580A (en) * 1997-11-10 1999-05-28 Daisho Denshi:Kk Manufacture of printed board
JP2005197648A (en) * 2003-12-09 2005-07-21 Shinko Electric Ind Co Ltd Method for manufacturing a circuit board wired by electroplating

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026923A (en) * 2007-07-19 2009-02-05 Cmk Corp Printed circuit boards, and manufacturing method therefor
US9939753B2 (en) 2014-12-08 2018-04-10 Canon Kabushiki Kaisha Printed circuit board, exposure device having printed circuit board, and image forming apparatus

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