JP2007066997A - Thin-film capacitor and its manufacturing method, and wiring board - Google Patents

Thin-film capacitor and its manufacturing method, and wiring board Download PDF

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JP2007066997A
JP2007066997A JP2005248114A JP2005248114A JP2007066997A JP 2007066997 A JP2007066997 A JP 2007066997A JP 2005248114 A JP2005248114 A JP 2005248114A JP 2005248114 A JP2005248114 A JP 2005248114A JP 2007066997 A JP2007066997 A JP 2007066997A
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protective layer
film capacitor
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electrode layer
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JP4711781B2 (en
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Fumio Fukumaru
文雄 福丸
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Kyocera Corp
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<P>PROBLEM TO BE SOLVED: To provide a thin-film capacitor which can keep residual stress inside a protection layer within an appropriate range while at the same time securing a long-time reliability by achieving a high adhesiveness with a layer immediately below, and also to provide its manufacturing method and a wiring board having a high reliability using the thin-film capacitor. <P>SOLUTION: The thin-film capacitor comprises a bottom electrode layer 2, a dielectric layer 3, and a top electrode layer 4, which are formed in order on a support substrate 1 to form an electrostatic capacity region. In the thin-film capacitor, an external terminal 5a electrically connected to the bottom electrode layer 2 and another external terminal 5b electrically connected to the top electrode layer 4 are formed and the protection layer 7 which is formed with openings 6a and 6b to expose these external terminals 5a and 5b within is so formed as to cover the electrostatic capacity region. The protection layer 7 is mainly formed of silica, and the compressed residual stress thereof is within a range not less than 100 MPa nor more than 210 MPa. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、長期信頼性に優れた薄膜コンデンサとその製造方法、前記薄膜コンデンサを用いた配線基板に関するものである。   The present invention relates to a thin film capacitor having excellent long-term reliability, a method for manufacturing the same, and a wiring board using the thin film capacitor.

近年においては、電子機器の小型化、薄型化に伴い、電子機器内に設置される電子部品への小型化の要求が強い。コンデンサにおいても、積層セラミックコンデンサ等の小型化が進み、寸法が１ｍｍ未満の小型化が実現されている。   In recent years, with the downsizing and thinning of electronic devices, there is a strong demand for downsizing electronic components installed in electronic devices. Also in the capacitor, miniaturization of a multilayer ceramic capacitor or the like has progressed, and miniaturization with a dimension of less than 1 mm has been realized.

一方、電子機器の小型化にも、使いやすい大きさの観点からは下限に達しつつあり、今後は、軽量化、薄型化、高機能化の要求が強くなっている。   On the other hand, the downsizing of electronic devices is reaching the lower limit from the viewpoint of easy-to-use size, and in the future, demands for weight reduction, thinning, and high functionality are increasing.

電子部品の薄型化、高機能化に適したコンデンサとして、薄膜コンデンサがある。薄膜コンデンサの基本的な構成は、通常、素子を構成する薄膜に比べて十分に厚い支持基板と、その表面上に電極層と誘電体層を積層して成る容量素子と、その容量素子を外部環境から保護する保護層、及び外部との電気的な接続をとるための外部端子に大別することができる。このうち、支持基板は比較的外部からの衝撃や汚れ、高温、高湿環境等に対する耐久性に優れているが、容量素子はこれらの要因に対し耐久性に劣っているものが多い。そのため従来から、この容量素子を外部環境から保護するための保護層を形成することで容量素子を保護し、薄膜コンデンサとしての対環境耐性の向上を図ってきた。このように保護層を設けることが、電子部品としての信頼性を確保するためには必須である。保護層の材料としては、透湿性の低い無機物を用いることが望ましく、高機能を満たしながらも、長期信頼性を確保するという、高度な技術が要求されている（特許文献１〜４参照）。
特開２００４−３２７８６６号公報 特開２００３−２９８０２７号公報 特開２００２−３２９７８８号公報 特開２００１−２１７１４２号公報 As a capacitor suitable for thinning and high functionality of electronic components, there is a thin film capacitor. The basic configuration of a thin film capacitor is usually a support substrate that is sufficiently thicker than the thin film that constitutes the element, a capacitive element in which an electrode layer and a dielectric layer are laminated on the surface, and the capacitive element externally It can be roughly divided into a protective layer that protects from the environment and an external terminal for electrical connection with the outside. Among these, the support substrate is relatively excellent in durability against external impacts and dirt, high temperature, high humidity environment, and the like, but many capacitive elements are inferior in durability against these factors. For this reason, conventionally, a protective layer for protecting the capacitive element from the external environment is formed to protect the capacitive element and improve resistance to the environment as a thin film capacitor. Providing a protective layer in this way is essential to ensure the reliability as an electronic component. As a material for the protective layer, it is desirable to use an inorganic material having low moisture permeability, and there is a demand for advanced technology to ensure long-term reliability while satisfying high functions (see Patent Documents 1 to 4).
JP 2004-327866 A JP 2003-298027 A JP 2002-329788 A JP 2001-217142 A

薄膜コンデンサでは、高機能化を満足するために、電極層や誘電体層等の形状を複雑化し、それらを積層させる必要があるため、段差部の数が増え、且つその高さも様々である。そのような段差部を含めて、保護層によって薄膜コンデンサを必要な領域にわたって被覆する必要がある。総合的に見た保護層の応力は０に近いものが望ましいが、凹凸がある場合は、段差部での応力分布等を考慮しなければならなければならず、クラックの発生、進展を抑制するためには保護層内の平均的な応力としては圧縮側にあることが望ましい。化学蒸着法（プラズマＣＶＤ法）においては、放電電力、圧力、ガス流量比等の条件を変化させて、形成膜内に圧縮の残留応力を持たせることは可能であるが、直下の層との密着性が確保できないため、形成後に膜の変位（膨れ）が発生し、時間経過とともに形成膜がはじけ飛んでしまう問題があった。   In a thin film capacitor, in order to satisfy high performance, it is necessary to complicate the shapes of electrode layers, dielectric layers, and the like and to laminate them. Therefore, the number of step portions is increased and the heights thereof are various. Including such a stepped portion, it is necessary to cover the thin film capacitor over a necessary region with a protective layer. The overall stress of the protective layer is preferably close to 0. However, if there are irregularities, the stress distribution at the step must be taken into account, and crack generation and progress are suppressed. Therefore, the average stress in the protective layer is desirably on the compression side. In the chemical vapor deposition method (plasma CVD method), it is possible to change the conditions such as discharge power, pressure, gas flow rate ratio, etc. to give compressive residual stress in the formed film. Since the adhesion cannot be secured, there is a problem that the film is displaced (swelled) after the formation, and the formed film flies off over time.

本発明は、上述の課題に鑑みて案出されたものであり、その目的は、保護層の内部に残留する応力値を適正な圧縮応力範囲内にするとともに直下の層との密着性を確保させた長期信頼性を確保する薄膜コンデンサとその製造方法を提供するとともに、この薄膜コンデンサを用いた高信頼性の配線基板を提供することにある。   The present invention has been devised in view of the above-mentioned problems, and its purpose is to ensure that the stress value remaining in the protective layer is within an appropriate compressive stress range and to ensure adhesion with the layer immediately below. An object of the present invention is to provide a thin film capacitor that secures long-term reliability and a method of manufacturing the same, and to provide a highly reliable wiring board using the thin film capacitor.

本発明の薄膜コンデンサは、
支持基板と、
前記支持基板上に形成され、一方極性の電極層と他方極性の電極層と前記二つの極性の電極層間に挟持されて成る誘電体層とを備えた静電容量領域と、
前記一方極性の電極層と接続された一方外部端子と、
前記他方極性の電極層と接続された他方外部端子と、
前記一方外部端子及び前記他方外部端子の一部を露出させた状態で、前記静電容量領域を被覆する保護層と、を備えた薄膜コンデンサであって、
前記保護層は、シリカを主成分とするとともに、圧縮残留応力を１００ＭＰａ以上２１０ＭＰａ以下の範囲としたことを特徴とする。 The thin film capacitor of the present invention is
A support substrate;
A capacitance region formed on the support substrate and including a one-polarity electrode layer, a second-polarity electrode layer, and a dielectric layer sandwiched between the two-polarity electrode layers;
One external terminal connected to the one polarity electrode layer;
The other external terminal connected to the other polarity electrode layer;
A protective layer covering the capacitance region in a state in which a part of the one external terminal and the other external terminal is exposed, and a thin film capacitor comprising:
The protective layer has silica as a main component and has a compressive residual stress in a range of 100 MPa to 210 MPa.

本発明の薄膜コンデンサの保護層は、前記一方外部端子の一部を内部に露出させた一方開口部と、前記他方外部端子の一部を内部に露出させた他方開口部とを有することを特徴とする。   The protective layer of the thin film capacitor of the present invention has a first opening in which a part of the one external terminal is exposed inside, and a second opening in which a part of the other external terminal is exposed. And

本発明の薄膜コンデンサの製造方法は、上記記載の薄膜コンデンサの製造方法であって、前記保護層は、放電を伴う化学蒸着法により、３５０℃より高く４５０℃未満の温度範囲で形成されていることを特徴とする。   The manufacturing method of the thin film capacitor of the present invention is the manufacturing method of the thin film capacitor described above, wherein the protective layer is formed in a temperature range higher than 350 ° C. and lower than 450 ° C. by a chemical vapor deposition method with discharge. It is characterized by that.

本発明の配線基板は、基板の表面及び／又は内部に、上記記載の薄膜コンデンサを設けて成ることを特徴とする。   The wiring board of the present invention is characterized in that the thin film capacitor described above is provided on the surface and / or inside of the board.

本発明の薄膜コンデンサは、支持基板と、前記支持基板上に形成され、一方極性の電極層と他方極性の電極層と前記二つの極性の電極層間に挟持されて成る誘電体層とを備えた静電容量領域と、前記一方極性の電極層と接続された一方外部端子と、前記他方極性の電極層と接続された他方外部端子と、前記一方外部端子及び前記他方外部端子の一部を露出させた状態で、前記静電容量領域を被覆する保護層と、を備えた薄膜コンデンサであって、前記保護層は、シリカを主成分とするとともに、圧縮残留応力を１００ＭＰａ以上２１０ＭＰａ以下の範囲とした。これにより、電極層や誘電体層等が積層され、段差部を持った薄膜コンデンサ素子を保護層が被覆する際に、保護層が適正な圧縮応力と密着性とを持っているため、湿度等の外的要因から誘電体層を守ることができ、長期信頼性を確保することが可能となる。   The thin film capacitor of the present invention includes a support substrate, and a dielectric layer formed on the support substrate and sandwiched between the one polarity electrode layer, the other polarity electrode layer, and the two polarity electrode layers. Exposing a capacitance region, one external terminal connected to the one polarity electrode layer, the other external terminal connected to the other polarity electrode layer, and the one external terminal and a part of the other external terminal And a protective layer covering the capacitance region in a state where the protective layer is composed of silica as a main component and a compressive residual stress in a range of 100 MPa to 210 MPa. did. As a result, electrode layers, dielectric layers, etc. are laminated, and when the protective layer covers a thin film capacitor element having a stepped portion, the protective layer has appropriate compressive stress and adhesion, so that humidity etc. Thus, the dielectric layer can be protected from external factors, and long-term reliability can be ensured.

段差部での応力分布等を考慮すると、本発明の範囲外である、保護層の残留応力範囲が引張応力および圧縮応力の１００ＭＰａより小さい範囲においては、保護層は全体として下地に対して収縮する方向に力が働き、保護層の強度が耐えられないとクラックが発生、進展するという問題がある。本発明の範囲である保護層の残留応力範囲が１００ＭＰａ以上２１０ＭＰａ以下の範囲においては、保護層は全体として下地に対して膨張する方向に力が働く。つまり、保護層の中央部では保護層と下地との界面が引き離される方向に力が働き、密着性は低くなるが、保護層の端部では保護層と下地との界面が押し付けられる方向に力が働き、密着性は強くなる。したがって、湿度の進入経路の一つである保護層端部の密着性が強くなるため、長期信頼性が確保できると考えられる。一方、本発明の範囲外である、保護層の残留応力範囲が２１０ＭＰａより大きな範囲においては、保護層は全体として下地に対して膨張する方向に力が働くが、その大きさが強いため、下地の誘電体層に大きな引張応力を発生させクラックを発生させるとか、保護層の強度が耐えられず保護層がはじけ飛ぶ等の問題が生じる。   In consideration of the stress distribution at the stepped portion and the like, the protective layer shrinks as a whole with respect to the base in the range where the residual stress range of the protective layer is smaller than 100 MPa of tensile stress and compressive stress, which is outside the scope of the present invention. If the force acts in the direction and the strength of the protective layer cannot withstand, there is a problem that cracks are generated and progress. When the residual stress range of the protective layer, which is the scope of the present invention, is in the range of 100 MPa to 210 MPa, the protective layer acts as a whole in the direction of expansion with respect to the base. In other words, at the center of the protective layer, a force acts in the direction in which the interface between the protective layer and the base is pulled apart, and the adhesion decreases, but at the end of the protective layer, a force is applied in the direction in which the interface between the protective layer and the base is pressed. Works and adhesion becomes strong. Accordingly, it is considered that long-term reliability can be ensured because the adhesion of the end portion of the protective layer, which is one of the humidity entry paths, becomes strong. On the other hand, in the range where the residual stress range of the protective layer is larger than 210 MPa, which is outside the scope of the present invention, the protective layer exerts a force in the direction of expanding with respect to the base as a whole, but its size is strong. This causes problems such as generating a large tensile stress in the dielectric layer and generating cracks, or the strength of the protective layer cannot be withstood and the protective layer will pop off.

適正な圧縮応力とは、膜欠陥となるクラックの進展を抑制できる応力値範囲を指す。適正な密着性とは、保護層形成後の室温状態における保護層の変位（膨れ）や欠損（はずれ）が発生しないことを指す。   Appropriate compressive stress refers to a stress value range in which the development of cracks that are film defects can be suppressed. Appropriate adhesion refers to the absence of displacement (swelling) or loss (detachment) of the protective layer at room temperature after the formation of the protective layer.

また、保護層として、一方外部端子の一部を内部に露出させた一方開口部と、他方外部端子の一部を内部に露出させた他方開口部とを有するようにすれば、任意の位置に外部端子を形成することができ、設計の自由度が高くなる。   In addition, as a protective layer, it has one opening part of which one external terminal is exposed inside and the other opening part of which the other external terminal is exposed inside, so that it can be placed at any position. External terminals can be formed, and the degree of freedom in design is increased.

本発明の薄膜コンデンサの製造方法は、上記記載の薄膜コンデンサを製造するための方法であって、上述した適正な圧縮応力と密着性を兼ね備えた保護層は、プラズマＣＶＤ等の放電を伴う化学蒸着法により、３５０℃より高く４５０℃未満の温度範囲で形成することにより得ることができる。   The manufacturing method of the thin film capacitor of the present invention is a method for manufacturing the above-described thin film capacitor, and the protective layer having the appropriate compressive stress and adhesion described above is chemical vapor deposition accompanied by discharge such as plasma CVD. According to the method, it can be obtained by forming in a temperature range higher than 350 ° C. and lower than 450 ° C.

本発明の配線基板は、基板の表面及び／又は内部に、上記記載の薄膜コンデンサを設けて成るものであり、長期信頼性を有する本発明の薄膜コンデンサを用いていることから、高信頼性の配線基板を得ることができる。   The wiring board of the present invention is formed by providing the above-described thin film capacitor on the surface and / or inside of the substrate, and since the thin film capacitor of the present invention having long-term reliability is used, a highly reliable A wiring board can be obtained.

図１は、本発明の薄膜コンデンサの一例の断面構造図を示したものである。この図に示したものは、あくまでも本発明の一例示に過ぎず、これに限られるものではない。   FIG. 1 shows a cross-sectional structure diagram of an example of the thin film capacitor of the present invention. What is shown in this figure is merely an example of the present invention, and is not limited thereto.

支持基板１上に、一方極性の電極層である下部電極層２、誘電体層３、他方極性の電極層である上部電極層４が順次形成されている。なお、誘電体層３は、下部電極層２と上部電極層４との間に挟持されて静電容量領域が形成されている。そして、下部電極層２と電気的接続された一方外部端子５ａ、上部電極層４と電気的接続された他方外部端子５ｂが形成され、これらの一方外部端子５ａ、他方外部端子５ｂの一部がそれぞれ内部に露出するように、一方開口部６ａ、他方開口部６ｂを設けた保護層７が静電容量領域を被覆するように形成されている。   On the support substrate 1, a lower electrode layer 2, which is a one-polar electrode layer, a dielectric layer 3, and an upper electrode layer 4 which is the other-polar electrode layer are sequentially formed. The dielectric layer 3 is sandwiched between the lower electrode layer 2 and the upper electrode layer 4 to form a capacitance region. Then, one external terminal 5a electrically connected to the lower electrode layer 2 and the other external terminal 5b electrically connected to the upper electrode layer 4 are formed, and a part of the one external terminal 5a and the other external terminal 5b is formed. A protective layer 7 provided with one opening 6a and the other opening 6b is formed so as to cover the capacitance region so as to be exposed inside.

本発明に係る薄膜コンデンサでは、この保護層７は、シリカを主成分とするとともに、圧縮残留応力を１００ＭＰａ以上２１０ＭＰａ以下の範囲としたことを特徴とする。このような条件を満たすように形成された保護層７によれば、保護層７が段差部を被覆するだけでなく、保護層７の膜内平均応力値を適正な圧縮応力の範囲に制御することができ、膜内クラックの発生や進展を抑制することができる。さらに保護層７の下側と接する部位との密着性が良くなり、特に、保護層７端部の下側と接する、支持基板１、誘電体層３、外部端子５ａ、５ｂのそれぞれとの密着性がよくなり、保護層７の膨れ等の変位を食い止めることができる。   In the thin film capacitor according to the present invention, the protective layer 7 has silica as a main component and a compressive residual stress in a range of 100 MPa to 210 MPa. According to the protective layer 7 formed so as to satisfy such a condition, the protective layer 7 not only covers the step portion, but also controls the average stress value in the film of the protective layer 7 within a proper compressive stress range. It is possible to suppress the occurrence and progress of cracks in the film. Further, the adhesiveness with the portion in contact with the lower side of the protective layer 7 is improved, and in particular, the adhesiveness with each of the support substrate 1, the dielectric layer 3, and the external terminals 5a and 5b in contact with the lower side of the end of the protective layer 7. Therefore, it is possible to prevent displacement such as swelling of the protective layer 7.

残留した圧縮応力が、１００ＭＰａよりも小さいときには、保護層にクラックが発生するという問題があり、２１０ＭＰａを超えると、保護層７と誘電体層３の密着性が高いと、誘電体層３に大きな引張応力を発生させ、誘電体層３にクラックを発生させて信頼性を損なうという問題がある。一方、保護層７と誘電体層３の密着性が低いと、保護層７に膨れが生じたり、保護層７の強度に耐えられない場合は、はじけ飛んでしまうという問題がある。上記範囲内にすることによって、湿度等の外的要因による経時的劣化から薄膜素子を守ることができ、さらに誘電体への弊害を与えることなく、薄膜コンデンサの長期信頼性を確保することができる。また、この残留応力の範囲としたときには、保護層７内の残留応力のバランスがよくなり、保護層７の中央部では保護層と下地との界面が引き離される方向に力が働き、密着性は低くなるが、湿度等の外的要因の進入経路の一つである保護層端部の密着性が強くなるため、長期信頼性を確保できる。   When the residual compressive stress is smaller than 100 MPa, there is a problem that a crack occurs in the protective layer. When the compressive stress exceeds 210 MPa, if the adhesiveness between the protective layer 7 and the dielectric layer 3 is high, the dielectric layer 3 is large. There is a problem that a tensile stress is generated, and cracks are generated in the dielectric layer 3 to deteriorate the reliability. On the other hand, if the adhesiveness between the protective layer 7 and the dielectric layer 3 is low, there is a problem that the protective layer 7 swells or flies off when it cannot withstand the strength of the protective layer 7. By making it within the above range, the thin film element can be protected from deterioration over time due to external factors such as humidity, and the long-term reliability of the thin film capacitor can be ensured without causing any harmful effects on the dielectric. . In addition, when the residual stress is within the range, the balance of the residual stress in the protective layer 7 is improved, and a force acts in the direction in which the interface between the protective layer and the base is separated at the central portion of the protective layer 7, and the adhesion is Although it is low, long-term reliability can be ensured because the adhesion of the protective layer end, which is one of the entry paths for external factors such as humidity, becomes strong.

なお、膜の残留応力を評価する方法はいくつかあり、膜形成の工程途中に、膜形成前後の支持基板の反りを測定し、反りの変化量と材料定数から応力を算出する方法が一般的である。その具体的な方法については、実施例の欄において後述する。   There are several methods for evaluating the residual stress of the film, and it is common to measure the warpage of the support substrate before and after film formation and calculate the stress from the amount of change in warpage and the material constant during the film formation process. It is. The specific method will be described later in the example section.

その他、膜の残留応力を評価する方法として、ラマン分光法やカソードルミネッセンス法を用いて膜の残留応力を評価する方法があり、応力変化がピークシフト量に反映することを利用して、応力を算出することが可能である。この方法では、局所観察が可能であるので、製品サイズで応力を評価することができる。具体的な手順は、以下のとおりである。まず応力フリーの状態、例えば対象物質を粉末状にした状態、を測定し、応力ゼロの場合のピーク位置を求める。そして、応力未知のサンプルに既知の外部応力を印加した状態で測定し、ピーク位置を求める。既知の外部応力をいくつか変化させ、得られたピーク位置から算出するピークシフト量と既知の外部応力をプロットすることにより、応力変化とピークシフト量との相関係数が算出できる。そして、応力未知のサンプルを測定し、ピーク位置を求め、応力ゼロのピーク位置からのシフト量と相関係数から、応力を算出することができる。   In addition, as a method for evaluating the residual stress of the film, there is a method of evaluating the residual stress of the film using Raman spectroscopy or cathodoluminescence, and the stress is reflected by utilizing the fact that the stress change is reflected in the peak shift amount. It is possible to calculate. In this method, since local observation is possible, the stress can be evaluated by the product size. The specific procedure is as follows. First, a stress-free state, for example, a state in which the target substance is powdered is measured, and the peak position when the stress is zero is obtained. And it measures in the state which applied the known external stress to the sample with unknown stress, and calculates | requires a peak position. By changing some known external stresses and plotting the peak shift amount calculated from the obtained peak position and the known external stress, the correlation coefficient between the stress change and the peak shift amount can be calculated. Then, the stress unknown sample is measured, the peak position is obtained, and the stress can be calculated from the shift amount from the zero stress peak position and the correlation coefficient.

以下、本発明の薄膜コンデンサの製造方法について、さらに詳しく説明する。   Hereafter, the manufacturing method of the thin film capacitor of this invention is demonstrated in detail.

支持基板１としては、シリコン、アルミナ、サファイア等を用いることができる。その中でも、表面欠陥がなく、強度が高いという理由からサファイアを用いることが望ましい。支持基板１の材質としてサファイアを用いた場合、厚さの上限値は、基板のカットのしやすさや、基板の加工性を確保するため、０．４０ｍｍとすることが望ましく、厚さの下限値は、基板強度を維持するため、０．０５ｍｍとすることが望ましい。また、保護層７の密着性を向上させるために、支持基板１の表面状態は酸化物が形成されている状態としておくことが望ましい。   As the support substrate 1, silicon, alumina, sapphire, or the like can be used. Among them, it is desirable to use sapphire because it has no surface defects and high strength. When sapphire is used as the material of the support substrate 1, the upper limit value of the thickness is preferably 0.40 mm in order to ensure the ease of cutting the substrate and the workability of the substrate, and the lower limit value of the thickness Is preferably 0.05 mm in order to maintain the substrate strength. In order to improve the adhesion of the protective layer 7, it is desirable that the surface state of the support substrate 1 is a state in which an oxide is formed.

まず支持基板１上に、一方極性の電極層である下部電極層２を形成する。下部電極層２は、蒸着法、ＤＣスパッタ法、プラズマＣＶＤ法等の周知の薄膜形成法によって形成することができる。また、材質は、ＰｔやＡｕやＡｌやＮｉやＴｉ等を用いることができる。下部電極層２の膜厚の上限値は、生産効率を確保するため、２００ｎｍとすることが望ましい。さらに、膜厚の下限値は、コンデンサのＥＳＲ（等価直列抵抗）を確保するため、３０ｎｍとすることが望ましい。   First, the lower electrode layer 2 that is a one-polar electrode layer is formed on the support substrate 1. The lower electrode layer 2 can be formed by a known thin film forming method such as a vapor deposition method, a DC sputtering method, a plasma CVD method or the like. Moreover, Pt, Au, Al, Ni, Ti, etc. can be used for a material. The upper limit value of the film thickness of the lower electrode layer 2 is desirably 200 nm in order to ensure production efficiency. Furthermore, the lower limit of the film thickness is preferably 30 nm in order to ensure the ESR (equivalent series resistance) of the capacitor.

上述の方法によって、支持基板１上に下部電極層２を形成した後、周知のフォトリソグラフィ技術を用いて、所定形状にパターン加工する。   After the lower electrode layer 2 is formed on the support substrate 1 by the above-described method, it is patterned into a predetermined shape using a well-known photolithography technique.

次に、所定形状にパターン加工された下部電極層２に、誘電体層３を形成する。誘電体層３の材質としては、高誘電材料であるＢａＴｉＯ３、ＳｒＴｉＯ３、ＢａｘＳｒ１−ｘＴｉＯ３（０＜ｘ＜１）、ＰｂＺｒyＴｉ１−ｙＯ３（０＜ｙ＜１）等が好適に利用される。なお、このような誘電体層３は、ＲＦスパッタ法、プラズマＣＶＤ法、スプレードライ等の周知の薄膜形成法によって形成することができる。なお、誘電体層３として、Ｂａ０．５Ｓｒ０．５ＴｉＯ３を選択した場合、膜厚の上限値は、所定の容量を確保するため、０．５０μｍとすることが望ましく、膜厚の下限値は、長期信頼性を確保するため、０．１０μｍとすることが望ましい。 Next, the dielectric layer 3 is formed on the lower electrode layer 2 patterned into a predetermined shape. The material of the dielectric layer 3 is BaTiO 3 , SrTiO 3 , Ba x Sr 1-x TiO 3 (0 <x <1), PbZr y Ti 1-y O 3 (0 <y <1), which are high dielectric materials. ) Etc. are preferably used. Such a dielectric layer 3 can be formed by a well-known thin film forming method such as RF sputtering, plasma CVD, or spray drying. When Ba 0.5 Sr 0.5 TiO 3 is selected as the dielectric layer 3, the upper limit value of the film thickness is desirably 0.50 μm in order to secure a predetermined capacity. The lower limit is preferably 0.10 μm in order to ensure long-term reliability.

上述の方法によって、支持基板１及び下部電極層２上に誘電体層３を形成した後、周知のフォトリソグラフィ技術を用いて、所定形状にパターン加工する。   After the dielectric layer 3 is formed on the support substrate 1 and the lower electrode layer 2 by the above-described method, it is patterned into a predetermined shape using a well-known photolithography technique.

次に、誘電体層３の上面に、他方極性の電極層である上部電極層４を形成する。上部電極層４は、蒸着法、ＤＣスパッタ法、プラズマＣＶＤ法等の周知の薄膜形成法によって形成することができる。また、材質は、ＡｕやＰｔやＡｌやＮｉやＴｉやＣｕ等を用いることができる。上部電極層４の膜厚の上限値は、生産効率を確保し、残留応力を低減させるため、２．０μｍとすることが望ましい。さらに、膜厚の下限値は、コンデンサのＥＳＲを確保するため、２００ｎｍとすることが望ましい。   Next, the upper electrode layer 4 which is the other polarity electrode layer is formed on the upper surface of the dielectric layer 3. The upper electrode layer 4 can be formed by a well-known thin film forming method such as vapor deposition, DC sputtering, or plasma CVD. As the material, Au, Pt, Al, Ni, Ti, Cu, or the like can be used. The upper limit value of the film thickness of the upper electrode layer 4 is desirably 2.0 μm in order to ensure production efficiency and reduce residual stress. Furthermore, the lower limit of the film thickness is desirably 200 nm in order to ensure the ESR of the capacitor.

さらに、下部電極層２上の所定箇所に一方外部端子５ａ、上部電極層４の上の所定箇所に他方外部端子５ｂをそれぞれ形成する。例えば、後工程において、半田バンプを用いて配線基板等に表面実装する場合、一方外部端子５ａ、他方外部端子５ｂとして、Ｎｉ等からなる半田拡散防止層、Ａｕ等からなる半田密着層を順次ＤＣスパッタ法等により形成しておくと良い。これらの外部端子の層を形成した後、周知のフォトリソグラフィ技術を用いて、所定形状にパターン加工しておいても良い。   Further, one external terminal 5 a is formed at a predetermined location on the lower electrode layer 2, and the other external terminal 5 b is formed at a predetermined location on the upper electrode layer 4. For example, when surface mounting is performed on a wiring board or the like using solder bumps in a later process, a solder diffusion prevention layer made of Ni or the like and a solder adhesion layer made of Au or the like are sequentially DC-attached as one external terminal 5a and the other external terminal 5b. It may be formed by sputtering or the like. After these external terminal layers are formed, they may be patterned into a predetermined shape using a known photolithography technique.

この後、これらを覆うようにシリカを主成分とする保護層７を、放電を伴う化学蒸着法（プラズマＣＶＤ法）によって形成する。例えば、ＲＦ放電によるＲＦプラズマＣＶＤ法を好適に用いることができ、Ｓｉ源となるガスとＯ源となるガスを所定量供給してやればよい。Ｓｉ源のガスとしては、例えば、ＴＥＯＳ（テトラエトキシシラン）等を用いることができ、Ｏ源のガスとしては、酸素等を用いることができる。なお、上述したように、本発明に係る保護層７は成膜後の圧縮残留応力の範囲が１００ＭＰａ以上２１０ＭＰａとなるようにする必要がある。このためには、成膜時の保護層７を３５０℃より高く４５０℃より小さい温度範囲で、プラズマＣＶＤ法により成膜を行なってやればよい。この温度範囲は、支持基板１に熱電対を取り付け、支持基板１の温度が、支持基板１を保持するホルダの表示温度と±５℃の範囲で一致するように設定した後、プラズマＣＶＤ法の成膜により、決定すればよい。   Thereafter, a protective layer 7 mainly composed of silica is formed so as to cover them by a chemical vapor deposition method (plasma CVD method) involving discharge. For example, an RF plasma CVD method using RF discharge can be suitably used, and a predetermined amount of a gas serving as a Si source and a gas serving as an O source may be supplied. For example, TEOS (tetraethoxysilane) or the like can be used as the Si source gas, and oxygen or the like can be used as the O source gas. As described above, the protective layer 7 according to the present invention needs to have a compressive residual stress range of 100 MPa to 210 MPa after film formation. For this purpose, the protective layer 7 during film formation may be formed by plasma CVD in a temperature range higher than 350 ° C. and lower than 450 ° C. This temperature range is set such that a thermocouple is attached to the support substrate 1 and the temperature of the support substrate 1 is set within a range of ± 5 ° C. with the display temperature of the holder that holds the support substrate 1. What is necessary is just to determine by film-forming.

保護層７の膜厚の上限値は、生産効率を確保するため５．０μｍとすることが望ましい。さらに、膜厚の下限値は、膜の緻密性を確保するため０．５μｍとすることが望ましい。なお、Ｓｉ源のガスとしてＴＥＯＳ、Ｏ源のガスとして、酸素を選択した場合、ＴＥＯＳ：Ｏ２＝１：１１程度の混合比として、成膜を行なえばよい。 The upper limit value of the thickness of the protective layer 7 is desirably 5.0 μm in order to ensure production efficiency. Furthermore, the lower limit value of the film thickness is desirably 0.5 μm in order to ensure the denseness of the film. When TEOS is selected as the Si source gas and oxygen is selected as the O source gas, the film formation may be performed at a mixing ratio of about TEOS: O 2 = 1: 1.

上述の方法によって、保護層７を形成した後、周知のフォトリソグラフィ技術を用いて、所定形状にパターン加工し、下部電極層２と電気的に接続した一方外部端子５ａの一部が内部に露出した一方開口部６ａ、上部電極層４と電気的に接続した他方外部端子５ｂの一部が内部に露出した他方開口部６ｂをそれぞれ設ける。なお、一方外部端子５ａ、他方外部端子５ｂを電極パッド形状とした場合、例えば、スクリーン印刷を用いて、半田ペーストを転写、リフローを行って半田バンプを形成し、配線基板等に表面実装することができる。あるいは、ワイヤボンディングによって、実装するようにしても良い。   After the protective layer 7 is formed by the above-described method, it is patterned into a predetermined shape using a well-known photolithography technique, and a part of the external terminal 5a electrically connected to the lower electrode layer 2 is exposed inside. One opening 6b and the other opening 6b in which a part of the other external terminal 5b electrically connected to the upper electrode layer 4 is exposed are provided. When one of the external terminals 5a and the other external terminal 5b has an electrode pad shape, for example, by using screen printing, solder paste is transferred and reflowed to form solder bumps, which are surface-mounted on a wiring board or the like. Can do. Or you may make it mount by wire bonding.

以上のようにして、図１に記載された本発明の薄膜コンデンサを形成することができる。以上説明した本発明の薄膜コンデンサの製造方法を用いて作製された本発明の薄膜コンデンサは、保護層が適正な圧縮応力と密着性とを有し、湿度等の外的要因から誘電体層を守ることができ、長期信頼性を確保することが可能となる。   As described above, the thin film capacitor of the present invention shown in FIG. 1 can be formed. In the thin film capacitor of the present invention manufactured using the method of manufacturing a thin film capacitor of the present invention described above, the protective layer has appropriate compressive stress and adhesion, and the dielectric layer is removed from external factors such as humidity. It can be protected and long-term reliability can be ensured.

図２に本発明の薄膜コンデンサを表面に実装した本発明の配線基板の概断面図を示す。本発明の薄膜コンデンサ２２は、一方外部端子５ａ、他方外部端子５ｂにそれぞれ半田バンプ２３ａ、２３ｂが設けられている。そして、配線基板２０の表面に形成された表面電極２１ａ、２１ｂに、半田バンプ２３ａ、２３ｂを位置決めした後、リフローによって表面電極２１ａ、２１ｂと接合し、配線基板２０に実装される。このように配線基板２０の表面に、長期信頼性を有する本発明の薄膜コンデンサを用いていることから、高信頼性の配線基板２０となる。   FIG. 2 is a schematic cross-sectional view of the wiring board of the present invention on which the thin film capacitor of the present invention is mounted. In the thin film capacitor 22 of the present invention, solder bumps 23a and 23b are provided on one external terminal 5a and the other external terminal 5b, respectively. Then, after positioning the solder bumps 23 a and 23 b on the surface electrodes 21 a and 21 b formed on the surface of the wiring substrate 20, the solder bumps 23 a and 23 b are joined to the surface electrodes 21 a and 21 b by reflow and mounted on the wiring substrate 20. Since the thin film capacitor of the present invention having long-term reliability is used on the surface of the wiring board 20 in this way, the wiring board 20 is highly reliable.

なお、本発明の実施形態は上述の例にのみ限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々変更を加え得ることはもちろんである。   It should be noted that the embodiment of the present invention is not limited to the above-described example, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

例えば、上述の説明では、保護層７として、一方外部端子５ａの一部を内部に露出させた一方開口部６ａと、他方外部端子５ｂの一部を内部に露出させた他方開口部６ｂとを有する例によって説明した。このような構成にすれば、任意の位置に外部端子を形成することができ、設計の自由度が高くなるため望ましいが、これに限るものではなく、保護層７の端部から、一方外部端子５ａの一部と他方外部端子５ｂの一部を露出させた状態としても良い。   For example, in the above description, as the protective layer 7, one opening 6a in which a part of one external terminal 5a is exposed inside, and the other opening 6b in which a part of the other external terminal 5b is exposed inside. Explained by example. With such a configuration, an external terminal can be formed at an arbitrary position, which is desirable because the degree of freedom in design is high, but this is not restrictive. A part of 5a and a part of the other external terminal 5b may be exposed.

また、例えば、図１では、保護層７の下側と接する領域を持つ部位として、下部電極層２、誘電体層３、上部電極層４、外部端子５ａ、５ｂがあるが、これに限定されるものではなく、例えば、下部電極層２が保護層７と接する領域が無い場合も、全く同様にして本発明を適用することができる。   Further, for example, in FIG. 1, there are a lower electrode layer 2, a dielectric layer 3, an upper electrode layer 4, and external terminals 5 a and 5 b as a portion having a region in contact with the lower side of the protective layer 7. For example, even when there is no region where the lower electrode layer 2 is in contact with the protective layer 7, the present invention can be applied in exactly the same manner.

また、一方外部端子５ａ、他方外部端子５ｂに対して、半田バンプ２３ａ、２３ｂを形成して配線基板に実装する例について説明したが、これに限るものではなく、外部端子が上面になるように配線基板に対してダイボンディングし、それぞれの外部端子から配線基板にワイヤボンディングしても良いし、外部端子と配線基板とを電気的に接続する接続配線を半田付け等によって形成しても良い。   Moreover, although the example which forms solder bump 23a, 23b and mounts it on a wiring board with respect to the one external terminal 5a and the other external terminal 5b was demonstrated, it does not restrict to this but an external terminal becomes an upper surface Die bonding may be performed on the wiring board and wire bonding may be performed from each external terminal to the wiring board, or a connection wiring that electrically connects the external terminal and the wiring board may be formed by soldering or the like.

また、上述の説明では、支持基板１上に形成され、一方極性の下部電極層２と他方極性の上部電極層４との二つの極性の電極層間に挟持されて成る誘電体層３とを備えた静電容量領域が一つの場合について述べたが、支持基板１上に複数の静電容量領域が形成され、互いに直列／並列に接続されているものに対しても、本発明に係る保護層７を好適に適用することが可能である。   In the above description, the dielectric layer 3 is formed on the support substrate 1 and is sandwiched between two polar electrode layers, ie, one polar lower electrode layer 2 and the other polar upper electrode layer 4. However, the protective layer according to the present invention is also applied to a case where a plurality of capacitance areas are formed on the support substrate 1 and connected in series / parallel to each other. 7 can be preferably applied.

以下、本発明の実施例について説明する。なお、ここで挙げる例は、本発明の一例示に過ぎず、これに限定されるものではない。   Examples of the present invention will be described below. In addition, the example given here is only an example of the present invention, and is not limited thereto.

図３に実施した薄膜コンデンサの断面構造図を示す。一方極性の電極層である下部電極層、他方極性の電極層である上部電極層、半田拡散防止層及び半田密着層の形成はＤＣスパッタ法を用い、誘電体層はＲＦスパッタ法を用いて作製した。   FIG. 3 shows a cross-sectional structure diagram of the thin film capacitor implemented. DC sputtering method is used to form the lower electrode layer, which is one polarity electrode layer, upper electrode layer, which is the other polarity electrode layer, solder diffusion prevention layer, and solder adhesion layer, and the dielectric layer is produced using RF sputtering method. did.

先ず、サファイアからなる支持基板３１上に、膜厚６０ｎｍのＰｔを形成し、下部電極層３２とした。その後、フォトリソグラフィ技術を用いて、下部電極層３２を所定形状にパターン加工した。   First, Pt with a film thickness of 60 nm was formed on the support substrate 31 made of sapphire to form the lower electrode layer 32. Thereafter, the lower electrode layer 32 was patterned into a predetermined shape using a photolithography technique.

所定形状に加工された下部電極層３２に、ＲＦスパッタ法によって膜厚０．３μｍのＢａ０．５Ｓｒ０．５ＴｉＯ３からなる誘電体層３３を形成した。その後、フォトリソグラフィ技術を用いて、誘電体層３３に下部電極層３２が内面に露出した一方開口部３８ａに連通させる誘電体層側一方開口部３３ａと、後で形成する上部電極層３４を内面に露出させた他方開口部３８ｂに連通させる誘電体層側他方開口部３３ｂを形成した。 A dielectric layer 33 made of Ba 0.5 Sr 0.5 TiO 3 having a thickness of 0.3 μm was formed on the lower electrode layer 32 processed into a predetermined shape by RF sputtering. Thereafter, by using a photolithography technique, the dielectric layer 33 has one opening 33a on the dielectric layer side communicating with the one opening 38a where the lower electrode layer 32 is exposed on the inner surface, and an upper electrode layer 34 to be formed later on the inner surface. The other opening 33b on the dielectric layer side that communicates with the other opening 38b exposed to the surface was formed.

次に、誘電体層３３の上面及び誘電体層側他方開口部３３ｂの内面に、膜厚３００ｎｍのＡｕを形成した後、フォトリソグラフィ技術を用いて所定形状にパターン加工を行い、上部電極層３４を得た。図３に示すように、上部電極層３４は誘電体層３３の上面から誘電体層側他方開口部３３ｂの内部に連続して設けられている。   Next, Au having a film thickness of 300 nm is formed on the upper surface of the dielectric layer 33 and the inner surface of the other opening 33b on the dielectric layer side, and then patterned into a predetermined shape using a photolithography technique, so that the upper electrode layer 34 is formed. Got. As shown in FIG. 3, the upper electrode layer 34 is provided continuously from the upper surface of the dielectric layer 33 to the inside of the other opening 33 b on the dielectric layer side.

次に、誘電体層側一方開口部３３ａ及び誘電体層側他方開口部３３ｂの内部に露出した下部電極層３２及び上部電極層３４の上に、一方外部端子及び他方外部端子として、膜厚１．０μｍのＮｉからなる半田拡散防止層３５ａ、３５ｂと、膜厚０．１ｕｍのＡｕからなる半田密着層３６ａ、３６ｂを順次形成した。その後、フォトリソグラフィ技術を用いて、先ず、半田密着層３６ａ、３６ｂを直径１００μｍの形状に加工し、その後、半田拡散防止層３５ａ、３５ｂを直径２００μｍの形状に加工した。   Next, on the lower electrode layer 32 and the upper electrode layer 34 exposed inside the dielectric layer side one opening 33a and the dielectric layer side other opening 33b, a film thickness of 1 is formed as one external terminal and the other external terminal. Solder diffusion preventing layers 35a and 35b made of 0.0 μm Ni and solder adhesion layers 36a and 36b made of Au having a thickness of 0.1 μm were formed in order. Thereafter, using the photolithography technique, first, the solder adhesion layers 36a and 36b were processed into a shape having a diameter of 100 μm, and then the solder diffusion preventing layers 35a and 35b were processed into a shape having a diameter of 200 μm.

この後、支持基板３１を平行平板型のプラズマＣＶＤ装置の反応槽に設置し、反応槽内を真空引きした後、基板温度をヒータ加熱により３８０℃に保持し、ＴＥＯＳ（テトラエトキシシラン）ガス２０ｓｃｃｍと酸素ガス２３４ｓｃｃｍとを導入し、圧力を８０Ｐａに維持して、ＲＦ放電電力２００Ｗで、０．２μｍ／分のレートで厚さ１．５μｍのＳｉＯ２（シリカ）を主成分とする保護層３７を形成した。 Thereafter, the support substrate 31 is placed in a reaction vessel of a parallel plate type plasma CVD apparatus, the inside of the reaction vessel is evacuated, the substrate temperature is maintained at 380 ° C. by heating with a heater, and TEOS (tetraethoxysilane) gas 20 sccm. And oxygen gas 234 sccm are introduced, the pressure is maintained at 80 Pa, a protective layer 37 containing SiO 2 (silica) as a main component with a thickness of 1.5 μm at a rate of 0.2 μm / min at an RF discharge power of 200 W. Formed.

保護層３７形成後の支持基板３１には、支持基板３１の片面に保護層３７が形成されたため、大気中、室温において反りが発生した。この反り量を曲率半径ｒとして測定したところ、保護層３７の形成面側に凸形状で、ｒ＝２９ｍであった。この曲率半径より、残留応力値を算出できることが一般に知られている。応力値σは、支持基板３１のヤング率Ｅ、支持基板３１の厚さｂ、支持基板３１のポアソン比ν、保護層３７の厚さｄ、及び曲率半径ｒにより、σ＝Ｅ×ｂ＾２／（６×（１−ν）×ｒ×ｄ）で算出できる。サファイアからなる支持基板３１の物性値より、Ｅ＝４３１ＧＰａ、ν＝０．２９、支持基板３１の厚さｂ＝０．２５ｍｍ、及び保護層３７の厚さｄ＝１．５μｍから応力値σを求めたところ、保護層３７内にσ＝−１４５ＭＰａの平均圧縮応力が残留していることが分かった。   Since the protective layer 37 was formed on one side of the support substrate 31 on the support substrate 31 after the protective layer 37 was formed, warping occurred in the atmosphere at room temperature. When the amount of warpage was measured as the radius of curvature r, it was a convex shape on the surface where the protective layer 37 was formed, and r = 29 m. It is generally known that the residual stress value can be calculated from this radius of curvature. The stress value σ depends on the Young's modulus E of the support substrate 31, the thickness b of the support substrate 31, the Poisson's ratio ν of the support substrate 31, the thickness d of the protective layer 37, and the radius of curvature r, σ = E × b ^ 2 / (6 × (1−ν) × r × d). From the physical property values of the support substrate 31 made of sapphire, the stress value σ is calculated from E = 431 GPa, ν = 0.29, the thickness b = 0.25 mm of the support substrate 31, and the thickness d = 1.5 μm of the protective layer 37. As a result, it was found that an average compressive stress of σ = −145 MPa remains in the protective layer 37.

得られた保護層３７は、Ａｕからなる半田密着層３６ａ、３６ｂが露出するように、フォトリソグラフィ技術を用いて、直径１２０μｍ、深さ１．５μｍの一方開口部３８ａ、他方開口部３８ｂを形成した。   The obtained protective layer 37 is formed with one opening 38a and the other opening 38b having a diameter of 120 μm and a depth of 1.5 μm by using a photolithography technique so that the solder adhesion layers 36a and 36b made of Au are exposed. did.

最後に、スクリーン印刷を用いて、一方開口部３８ａ、他方開口部３８ｂ内の外部端子を構成している半田密着層３６ａ、３６ｂの上に、Ｓｎが９６．５質量％、Ａｇが３．０質量％、Ｃｕが０．５質量％からなる鉛フリー半田ペーストを転写し、リフローを行い、半田バンプ３９ａ、３９ｂを形成し、図３に示す薄膜コンデンサを得た。   Finally, Sn is 96.5% by mass and Ag is 3.0 on the solder adhesion layers 36a and 36b constituting the external terminals in the one opening 38a and the other opening 38b by screen printing. A lead-free solder paste containing 0.5% by mass of Cu and 0.5% by mass of Cu was transferred and reflowed to form solder bumps 39a and 39b. Thus, the thin film capacitor shown in FIG. 3 was obtained.

即ち、半田バンプ３９ａは、半田密着層３６ａと半田拡散防止層３５ａを介して、下部電極層３２と電気的接続されていて、また、半田バンプ３９ｂは、半田密着層３６ｂと半田拡散防止層３５ｂを介して、上部電極層３４と電気的接続されているようにした。   That is, the solder bump 39a is electrically connected to the lower electrode layer 32 via the solder adhesion layer 36a and the solder diffusion prevention layer 35a, and the solder bump 39b is connected to the solder adhesion layer 36b and the solder diffusion prevention layer 35b. It was made to be electrically connected to the upper electrode layer 34 via.

得られた薄膜コンデンサの有効電極面積は１．８９ｍｍ２であり、周波数１ｋＨｚでの静電容量は３３ｎＦであった。 The effective electrode area of the obtained thin film capacitor was 1.89 mm 2 , and the capacitance at a frequency of 1 kHz was 33 nF.

また、保護層３７の形成温度条件と、長期信頼性の関係を調べるために、保護層３７を形成するときのプラズマＣＶＤ法の支持基板３１の温度を変更することで、それ以外は上述と同じ方法によって、比較用薄膜コンデンサを作製した。本発明の薄膜コンデンサ及び比較用薄膜コンデンサのシリカ形成温度条件として、３００℃から４８０℃までのものを作製した。   Further, in order to investigate the relationship between the formation temperature condition of the protective layer 37 and the long-term reliability, the temperature of the support substrate 31 of the plasma CVD method when the protective layer 37 is formed is changed, and the rest is the same as above. A thin film capacitor for comparison was produced by the method. As the silica forming temperature conditions of the thin film capacitor of the present invention and the comparative thin film capacitor, those having a temperature of 300 ° C. to 480 ° C. were produced.

これら、本発明の薄膜コンデンサ及び比較用薄膜コンデンサを外観検査した後、高温高湿負荷試験を行った。高温高湿負荷試験は、槽内温度８５℃、槽内相対湿度８５％Ｒ．Ｈ．の試験槽内において、直流電圧２．５Ｖを連続的に負荷し、絶縁抵抗値の時間変化を比較観測した。   These thin film capacitors of the present invention and comparative thin film capacitors were inspected for appearance and then subjected to a high temperature and high humidity load test. The high-temperature and high-humidity load test was conducted at 85 ° C. in the tank and 85% relative humidity in the tank. H. In the test tank, a DC voltage of 2.5 V was continuously loaded, and the temporal change of the insulation resistance value was comparatively observed.

図４に示す線図は、上述のようにして作製した本発明の薄膜コンデンサ及び比較用薄膜コンデンサに対して、高温高湿負荷試験を行ったときの初期値に対する絶縁抵抗値の時間変化を示すものである。図４の縦軸には、試験投入前の絶縁抵抗値を１としての時間変化を示した。なお、シリカからなる保護層３７の形成温度条件の代表的なものとして３００℃、４００℃、４８０℃の３種類を選択して記載している。図４によれば、保護層３７の形成温度条件の違いにより、絶縁抵抗値の劣化率が異なるのが明らかである。具体的には、形成温度が３００℃、４８０℃の場合は、劣化率が大きく、４００℃の場合が最も良好な結果が得られており、保護層３７の形成温度条件は、高ければよい、低ければよいという傾向ではなく、ある範囲のものが良いことを示している。   The diagram shown in FIG. 4 shows the time variation of the insulation resistance value with respect to the initial value when the high-temperature and high-humidity load test is performed on the thin film capacitor of the present invention and the comparative thin film capacitor manufactured as described above. Is. The vertical axis in FIG. 4 shows the time change with the insulation resistance value before the test being taken as 1. It should be noted that three types of temperatures of 300 ° C., 400 ° C., and 480 ° C. are selected and described as typical conditions for forming the protective layer 37 made of silica. According to FIG. 4, it is clear that the deterioration rate of the insulation resistance value varies depending on the formation temperature condition of the protective layer 37. Specifically, when the formation temperature is 300 ° C. and 480 ° C., the deterioration rate is large, and the best result is obtained when the formation temperature is 400 ° C. The formation temperature condition of the protective layer 37 only needs to be high. It is not a tendency to be low, but a certain range is good.

保護層３７の形成温度条件と、長期信頼性の関係をより明確にするために、図４に示す絶縁抵抗値が初期値に対して１０％になった時点を薄膜コンデンサの故障発生時間と定義し、故障発生時間と保護層３７の形成温度条件との関係を、外観検査、及び保護層３７形成後の室温における支持基板反り量からの応力の結果と併せて表１に示す。また、故障発生時間と保護層３７の形成温度条件との関係を図５の線図に示す。

Figure 2007066997
In order to clarify the relationship between the formation temperature condition of the protective layer 37 and the long-term reliability, the time when the insulation resistance value shown in FIG. 4 becomes 10% of the initial value is defined as the failure occurrence time of the thin film capacitor. The relationship between the failure occurrence time and the formation temperature condition of the protective layer 37 is shown in Table 1 together with the results of the appearance inspection and the stress from the amount of warping of the support substrate at room temperature after the formation of the protective layer 37. The relationship between the failure occurrence time and the formation temperature condition of the protective layer 37 is shown in the diagram of FIG.
Figure 2007066997

図５より、保護層３７の形成温度が本発明で規定された３５０℃から４５０℃の範囲のときには、故障は１０００時間を越えてからしか発生しておらず、良好な長期信頼性が得られている。それに対して、形成温度が３５０℃から４５０℃の本発明の範囲外のときには、故障時間が１０００時間を下回っていることがわかる。   From FIG. 5, when the formation temperature of the protective layer 37 is in the range of 350 ° C. to 450 ° C. defined in the present invention, the failure occurs only after 1000 hours, and good long-term reliability is obtained. ing. On the other hand, when the forming temperature is outside the range of the present invention of 350 ° C. to 450 ° C., it can be seen that the failure time is less than 1000 hours.

また、表１によれば、保護層３７の形成温度条件Ｔが、本発明で規定された上限値を超えて高過ぎる、即ちＴ≧４５０℃の範囲にある場合、外観検査の結果から、保護層３７の下に形成されている誘電体層３３にクラックの発生が認められた。また、保護層３７形成後の室温における残留応力の測定結果も、２１１ＭＰａを超える圧縮応力値を示している。この結果より、保護層形成工程で応力がかかり過ぎて、誘電体層３３に過度の引張応力がかかることによってダメージが与えられているものと推測される。   Further, according to Table 1, when the formation temperature condition T of the protective layer 37 is too high exceeding the upper limit defined in the present invention, that is, in the range of T ≧ 450 ° C. Cracks were observed in the dielectric layer 33 formed under the layer 37. Moreover, the measurement result of the residual stress at room temperature after the formation of the protective layer 37 also shows a compressive stress value exceeding 211 MPa. From this result, it is presumed that the stress is excessively applied in the protective layer forming step, and the dielectric layer 33 is damaged by applying an excessive tensile stress.

また、保護層３７の形成温度条件Ｔが、本発明で規定された下限値を超えて低過ぎる、即ちＴ≦３５０℃の範囲にある場合、保護層３７内のクラックの発生や、保護層３７の一部欠損が認められた。この温度条件下では、室温における残留応力値が圧縮応力で１００ＭＰａを下回っている。この結果より、誘電体層３３へのダメージは少ないものの、保護層３７内のクラック進展を抑制するに必要な平均圧縮応力が不足しているものと推測される。つまり、段差部等の構造的に引張応力となり易い部位で圧縮応力が相殺されてしまいクラックの進展を止められない状態の保護層３７が形成されていると考えられる。また、一部欠損が認められていることより、保護層３７と下層との密着性が十分に確保できていないこともわかった。   When the formation temperature condition T of the protective layer 37 is too low exceeding the lower limit defined in the present invention, that is, in the range of T ≦ 350 ° C., generation of cracks in the protective layer 37 or the protective layer 37 A partial deficiency was observed. Under this temperature condition, the residual stress value at room temperature is less than 100 MPa in compressive stress. From this result, although the damage to the dielectric layer 33 is small, it is presumed that the average compressive stress necessary for suppressing the crack progress in the protective layer 37 is insufficient. That is, it is considered that the protective layer 37 is formed in a state in which the compressive stress is canceled out at a site where structurally prone to tensile stress such as a stepped portion and the progress of cracks cannot be stopped. Moreover, it was also found that the adhesiveness between the protective layer 37 and the lower layer could not be sufficiently secured because some defects were observed.

以上のように、本発明の効果を確認することができた。   As described above, the effect of the present invention could be confirmed.

本発明の薄膜コンデンサの断面構造図である。It is a cross-section figure of the thin film capacitor of this invention. 本発明の配線基板の断面構造図である。It is a cross-section figure of the wiring board of the present invention. 本発明の薄膜コンデンサの実施形態の一例を示す断面構造図である。It is a sectional structure figure showing an example of an embodiment of a thin film capacitor of the present invention. 本発明及び比較用の薄膜コンデンサに対して、高温高湿負荷試験を行ったときの初期値に対する絶縁抵抗値の時間変化を示した線図である。It is the diagram which showed the time change of the insulation resistance value with respect to the initial value when a high temperature, high humidity load test is done with respect to this invention and the thin film capacitor for a comparison. 保護層の形成温度条件と、高温高湿負荷試験における故障時間の関係を示す線図である。It is a diagram which shows the relationship between the formation temperature conditions of a protective layer, and the failure time in a high temperature, high humidity load test.

符号の説明Explanation of symbols

１：支持基板
２：一方極性の電極層である下部電極層
３：誘電体層
４：他方極性の電極層である上部電極層
５ａ：一方外部端子
５ｂ：他方外部端子
６ａ：一方開口部
６ｂ：他方開口部
７：保護層
２０：配線基板
２１ａ、２１ｂ：表面電極
２２：薄膜コンデンサ
２３ａ、２３ｂ：半田バンプ
３１：支持基板
３２：下部電極層
３３：誘電体層
３３ａ：誘電体層側一方開口部
３３ｂ：誘電体層側他方開口部
３４：上部電極層
３５ａ、３５ｂ：半田拡散防止層
３６ａ、３６ｂ：半田密着層
３７：保護層
３８ａ：一方開口部
３８ｂ：他方開口部
３９ａ、３９ｂ：半田バンプ 1: Support substrate 2: Lower electrode layer which is one polarity electrode layer 3: Dielectric layer 4: Upper electrode layer which is the other polarity electrode layer 5a: One external terminal 5b: Other external terminal 6a: One opening 6b: Other opening 7: Protective layer 20: Wiring substrate 21a, 21b: Surface electrode 22: Thin film capacitor 23a, 23b: Solder bump 31: Support substrate 32: Lower electrode layer 33: Dielectric layer 33a: One opening on the dielectric layer side 33b: Dielectric layer side other opening 34: Upper electrode layer 35a, 35b: Solder diffusion prevention layer 36a, 36b: Solder adhesion layer 37: Protective layer 38a: One opening 38b: Other opening 39a, 39b: Solder bump

Claims (4)

支持基板と、
前記支持基板上に形成され、一方極性の電極層と他方極性の電極層と前記二つの極性の電極層間に挟持されて成る誘電体層とを備えた静電容量領域と、
前記一方極性の電極層と接続された一方外部端子と、
前記他方極性の電極層と接続された他方外部端子と、
前記一方外部端子及び前記他方外部端子の一部を露出させた状態で、前記静電容量領域を被覆する保護層と、を備えた薄膜コンデンサであって、
前記保護層は、シリカを主成分とするとともに、圧縮残留応力を１００ＭＰａ以上２１０ＭＰａ以下の範囲としたことを特徴とする薄膜コンデンサ。 A support substrate;
A capacitance region formed on the support substrate and including a one-polarity electrode layer, a second-polarity electrode layer, and a dielectric layer sandwiched between the two-polarity electrode layers;
One external terminal connected to the one polarity electrode layer;
The other external terminal connected to the other polarity electrode layer;
A protective layer covering the capacitance region in a state in which a part of the one external terminal and the other external terminal is exposed, and a thin film capacitor comprising:
The protective layer is composed of silica as a main component and has a compressive residual stress in a range of 100 MPa to 210 MPa. 前記保護層は、前記一方外部端子の一部を内部に露出させた一方開口部と、前記他方外部端子の一部を内部に露出させた他方開口部とを有することを特徴とする請求項１に記載の薄膜コンデンサ。   The said protective layer has one opening part which exposed a part of said one external terminal inside, and the other opening part which exposed a part of said other external terminal inside. The thin film capacitor described in 1. 請求項１又は請求項２に記載の薄膜コンデンサの製造方法であって、
前記保護層は、放電を伴う化学蒸着法により、３５０℃より高く４５０℃未満の温度範囲で形成されていることを特徴とする薄膜コンデンサの製造方法。 A method of manufacturing a thin film capacitor according to claim 1 or 2,
The method for manufacturing a thin film capacitor, wherein the protective layer is formed in a temperature range higher than 350 ° C. and lower than 450 ° C. by a chemical vapor deposition method involving discharge. 表面及び／又は内部に、請求項１又は請求項２に記載の薄膜コンデンサを設けて成ることを特徴とする配線基板。

A wiring board comprising the thin film capacitor according to claim 1 or 2 provided on a surface and / or inside thereof.

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JP2018067566A (en) * 2016-10-17 2018-04-26 太陽誘電株式会社 Multilayer ceramic capacitor and method for manufacturing the same
JP2021097246A (en) * 2019-04-26 2021-06-24 太陽誘電株式会社 Multilayer ceramic capacitor

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JP2002329788A (en) * 2001-04-27 2002-11-15 Kyocera Corp Variable capacitor
JP2004259891A (en) * 2003-02-25 2004-09-16 Kyocera Corp Laminated thin-film capacitor

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JPH0547586A (en) * 1991-08-16 1993-02-26 Toshiba Corp Capacitor
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Publication number Priority date Publication date Assignee Title
JP2018067566A (en) * 2016-10-17 2018-04-26 太陽誘電株式会社 Multilayer ceramic capacitor and method for manufacturing the same
US10622152B2 (en) 2016-10-17 2020-04-14 Taiyo Yuden Co., Ltd. Multi-layer ceramic capacitor and method of producing the same
JP2021097246A (en) * 2019-04-26 2021-06-24 太陽誘電株式会社 Multilayer ceramic capacitor
JP7162690B2 (en) 2019-04-26 2022-10-28 太陽誘電株式会社 Multilayer ceramic capacitor

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