JP2007027308A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007027308A
JP2007027308A JP2005205471A JP2005205471A JP2007027308A JP 2007027308 A JP2007027308 A JP 2007027308A JP 2005205471 A JP2005205471 A JP 2005205471A JP 2005205471 A JP2005205471 A JP 2005205471A JP 2007027308 A JP2007027308 A JP 2007027308A
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area
semiconductor chip
electrode
solder
anode
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Takashi Fujii
岳志 藤井
Yoshinari Ikeda
良成 池田
Katsuhiko Yoshihara
克彦 吉原
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can radiate heat even from the periphery of a semiconductor chip. <P>SOLUTION: An anode area 4 is formed in the surface layer of a semiconductor substrate 3, an insulating film 6 is formed around the outer periphery of the semiconductor substrate 3, and then an anode electrode 7 having a hood 7a is formed on the anode area 4 and the insulating film 6. The anode electrode 7 including the hood 7a is joined with a metal 1 with a first solder layer 9 in-between. The area S3 of the metal 1 is made larger than that S1 of the anode area 4, and smaller than the anode electrode 7. Thus, heat can be radiated even from the outer periphery of the semiconductor chip, and an appropriate solder filet can be also made, resulting in enhancing joint strength by solder. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、ダイオードやＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）などの半導体装置に関する。   The present invention relates to a semiconductor device such as a diode or an IGBT (Insulated Gate Bipolar Transistor).

従来、半導体チップを収納したパッケージの外部取り出し電極（外部導出端子）と、半導体チップとの接続にはアルミ線や金線によるワイヤボンディングが多用されてきた。
パワー半導体モジュールにおいては、半導体チップの裏面側の主電極（裏面電極）は、はんだなどのろう材で支持基板に固着され、一方、半導体チップの表面側の主電極（表面電極）やゲート電極パッドは、アルミワイヤや金ワイヤによるワイヤボンディングでパッケージの外部取り出し電極と接続する。チップサイズが大きくなると半導体チップの表面側の主電極と接続するこのワイヤの本数が増加し、主電極とワイヤとの接続箇所での耐ヒートサイクル性や耐パワーサイクル性の低下が懸念される。また近年、より高温環境での使用などに耐えるように、半導体装置にはさらなる高い信頼性が要求されるようになってきた。 Conventionally, wire bonding using an aluminum wire or a gold wire has been frequently used for connection between an external extraction electrode (external lead-out terminal) of a package containing a semiconductor chip and the semiconductor chip.
In a power semiconductor module, a main electrode (back electrode) on the back side of a semiconductor chip is fixed to a support substrate with a brazing material such as solder, while a main electrode (surface electrode) or gate electrode pad on the front side of the semiconductor chip. Is connected to an external extraction electrode of the package by wire bonding using aluminum wire or gold wire. As the chip size increases, the number of wires connected to the main electrode on the surface side of the semiconductor chip increases, and there is a concern that heat cycle resistance and power cycle resistance may be reduced at the connection point between the main electrode and the wire. In recent years, semiconductor devices have been required to have higher reliability to withstand use in higher temperature environments.

パッケージとしての信頼性向上を考慮し、ワイヤボンディングに変わる方法として銅箔やアルミ箔などの金属箔が接続導体として用いられる。これにより半導体チップの主電極と接続導体の接合面積を増加させ、接合部での温度上昇を抑制して、耐ヒートサイクル性や耐パワーサイクル性の向上が図られ、さらに、この金属箔を用いることにより、抵抗やインダクタンスの低減などによる素子特性の向上も同時に図られている。
図５は、従来の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。また、図６は、図５（ｂ）のＣ部拡大図である。この半導体装置はダイオードである。
半導体チップ５２の裏面側からだけでなく、半導体チップ５２の表面側の主電極であるアノード電極５７に、この数μｍのアノード電極５７の厚さよりはるかに厚い数百μｍ〜数ｍｍのオーダの金属部品５１を固着することで、半導体チップ５２の表面側からも放熱できる場合を示している。 Considering improvement of reliability as a package, a metal foil such as a copper foil or an aluminum foil is used as a connection conductor as a method instead of wire bonding. This increases the bonding area between the main electrode of the semiconductor chip and the connection conductor, suppresses the temperature rise at the bonding portion, and improves heat cycle resistance and power cycle resistance, and further uses this metal foil. As a result, the device characteristics are improved at the same time by reducing resistance and inductance.
5A and 5B are configuration diagrams of a conventional semiconductor device, in which FIG. 5A is a plan view of the main part, and FIG. 5B is a cross-sectional view of the main part taken along line XX in FIG. . FIG. 6 is an enlarged view of a portion C in FIG. This semiconductor device is a diode.
Not only from the back surface side of the semiconductor chip 52 but also to the anode electrode 57 which is the main electrode on the front surface side of the semiconductor chip 52, a metal on the order of several hundred μm to several mm which is much thicker than the thickness of the anode electrode 57 of several μm. The case where heat can be radiated also from the surface side of the semiconductor chip 52 by fixing the component 51 is shown.

通常、表面側のアノード電極５７の周辺には、耐圧を維持するためのガードリング５５のような耐圧構造７２が配置される。アノード電極５７と金属部品５１との固着ははんだ材を供給して形成される第１はんだ層５９で行われる。また耐圧構造７２箇所は絶縁膜５６やポリイミド樹脂などの保護膜６１で覆われているので、この箇所でははんだの濡れ性がよくなく、はんだは広がらない。
半導体チップ５２は、通電するとエネルギー損失を発生し発熱する。この主な発熱箇所は活性領域７１であるアノード領域５４であり、パッケージはこの発熱を外部に効率よく放熱できるように設計される。
図６に示すように、アノード電極５７はアノード領域５４に接続され、アノード領域５４の周囲は耐圧構造７２で囲まれ、この耐圧構造７２の表面は絶縁膜５６で被覆されている。アノード領域５４上に形成されるアノード電極５７の端部はウエハプロセスや耐圧特性を考慮して、絶縁膜５６に乗り上げている。半導体チップ５２において、アノード領域５４が垂直投影された領域がダイオードの活性領域７１となり、主な発熱箇所となる。この半導体装置においては、金属部品１の面積Ｓ５は活性領域７１（アノード領域５４）の面積Ｓ４より小さい。勿論、アノード電極５７より小さい。 Usually, a breakdown voltage structure 72 such as a guard ring 55 for maintaining a breakdown voltage is disposed around the anode electrode 57 on the surface side. The anode electrode 57 and the metal part 51 are fixed to each other by a first solder layer 59 formed by supplying a solder material. In addition, since the 72 pressure-resistant structures are covered with a protective film 61 such as an insulating film 56 or a polyimide resin, solder wettability is not good at this location and the solder does not spread.
When energized, the semiconductor chip 52 generates energy loss and generates heat. This main heat generation location is the anode region 54 which is the active region 71, and the package is designed so that this heat generation can be efficiently radiated to the outside.
As shown in FIG. 6, the anode electrode 57 is connected to the anode region 54, the periphery of the anode region 54 is surrounded by a breakdown voltage structure 72, and the surface of the breakdown voltage structure 72 is covered with an insulating film 56. The end portion of the anode electrode 57 formed on the anode region 54 runs over the insulating film 56 in consideration of the wafer process and the breakdown voltage characteristics. In the semiconductor chip 52, a region in which the anode region 54 is vertically projected becomes an active region 71 of the diode, which is a main heat generation portion. In this semiconductor device, the area S5 of the metal component 1 is smaller than the area S4 of the active region 71 (anode region 54). Of course, it is smaller than the anode electrode 57.

尚、図中の５３は半導体基板、６０ははんだのフィレット、６５は支持基板、６６は支持基板６５と半導体チップ５２の裏面を固着する第２はんだ層である。
このように、半導体チップでの発熱を効率よく放散するため、半導体チップの裏面側からだけでなく、表面側からも放熱を図るため、半導体チップの表面側の主電極に、厚い導体（金属部品）を固着した半導体装置として、例えば特許文献１に記載のものがある。
また、ＩＧＢＴにおいて、耐圧構造およびゲート電極のそれぞれとエミッタ電極の間に絶縁シートを貼着し、絶縁シートで囲まれたエミッタ電極やゲート電極とはんだを介して銅配線を固着することで、耐圧構造と銅配線との絶縁性、エミッタ電極とゲート電極の間の絶縁性を良好に確保できることが開示されている（例えば、特許文献２）。
特開２００１−３３２６６４号公報 特開２００３−２１８３０６号公報 In the figure, 53 is a semiconductor substrate, 60 is a solder fillet, 65 is a support substrate, and 66 is a second solder layer for fixing the support substrate 65 and the back surface of the semiconductor chip 52.
In this way, in order to efficiently dissipate heat generated in the semiconductor chip, heat is dissipated not only from the back surface side of the semiconductor chip but also from the front surface side. For example, there is a semiconductor device described in Patent Document 1 as a semiconductor device to which is fixed.
Also, in an IGBT, an insulating sheet is bonded between each of the withstand voltage structure and the gate electrode and the emitter electrode, and the emitter electrode and gate electrode surrounded by the insulating sheet are bonded to the copper wiring via the solder, whereby the withstand voltage It is disclosed that the insulation between the structure and the copper wiring and the insulation between the emitter electrode and the gate electrode can be ensured satisfactorily (for example, Patent Document 2).
JP 2001-332664 A JP 2003-218306 A

しかし、図５および図６に示すように、半導体チップ５２の裏面側の放熱は、半導体チップ５２の裏面全面から第２はんだ層６６および支持基板６５を通して行われる。これに対し、表面側からの放熱は、金属部品５１を通して行われる。金属部品５１は半導体チップ５２の活性領域７１の面積より小さいため、金属部品５１から外れた半導体チップ５２の外周部で発生した熱は十分放散できない。
また、前記の特許文献１では、金属部品である導体とはんだを介して接続する主電極であるエミッタ電極が複数個ある場合であり、主電極が単一の場合についての説明はない。また、主電極の大きさと金属部品である導体の大きさの関係についても説明されていない。
また、前記の特許文献２では、エミッタ電極とゲート電極パッドの間に形成された絶縁シートでエミッタ電極とゲート電極パッドの間を絶縁することは記載されているが、放熱に関する説明がなく、また、エミッタ電極の大きさと銅配線の大きさの関係についても説明がない。 However, as shown in FIGS. 5 and 6, heat dissipation on the back surface side of the semiconductor chip 52 is performed from the entire back surface of the semiconductor chip 52 through the second solder layer 66 and the support substrate 65. On the other hand, heat dissipation from the surface side is performed through the metal component 51. Since the metal component 51 is smaller than the area of the active region 71 of the semiconductor chip 52, heat generated at the outer periphery of the semiconductor chip 52 that is out of the metal component 51 cannot be sufficiently dissipated.
Moreover, in the said patent document 1, it is a case where there are several emitter electrodes which are the main electrodes connected with the conductor which is a metal component via solder, and there is no description about the case where there is a single main electrode. Further, the relationship between the size of the main electrode and the size of the conductor which is a metal part is not described.
In addition, the above-mentioned Patent Document 2 describes that the insulating sheet formed between the emitter electrode and the gate electrode pad is insulated between the emitter electrode and the gate electrode pad, but there is no explanation about heat dissipation, There is no description about the relationship between the size of the emitter electrode and the size of the copper wiring.

この発明の目的は、前記の課題を解決して、半導体チップの外周部も含めて放熱できる半導体装置を提供することにある。   An object of the present invention is to solve the above-described problems and provide a semiconductor device that can dissipate heat including the outer periphery of a semiconductor chip.

前記の目的を達成するために、半導体チップと、該半導体チップの第１主面上に該半導体チップの活性領域を取り囲んで形成される絶縁膜と、前記活性領域上から前記第１絶縁膜上に延在するひさし部を有する第１主電極と、前記半導体チップの第２主面側に形成される第２主電極と、前記ひさし部を含む前記第１主電極とはんだを介して固着される導体（ヒートスプレッダーもしくはリードフレームの半導体チップ搭載台など）と、を有する半導体装置であって、前記はんだが接触する側の前記導体の平坦面の面積が、前記活性領域の面積より大きく前記ひさし部を含む第１主電極の面積より小さい構成とする。
また、前記半導体チップの前記第１主面上に該第１主電極と離して形成される制御電極を有する構成とする。
また、良好なはんだのフィレットを形成するために、前記ひさし部の幅を前記はんだの厚さより大きくするとよい。 To achieve the above object, a semiconductor chip, an insulating film formed on the first main surface of the semiconductor chip so as to surround the active region of the semiconductor chip, and the first insulating film from the active region to the first insulating film A first main electrode having an eaves portion extending to the second main electrode, a second main electrode formed on the second main surface side of the semiconductor chip, and the first main electrode including the eaves portion fixed to the first main electrode via solder. A conductor (a heat spreader or a semiconductor chip mounting table of a lead frame), wherein the area of the flat surface of the conductor on the side in contact with the solder is larger than the area of the active region. The configuration is smaller than the area of the first main electrode including the portion.
The semiconductor chip has a control electrode formed on the first main surface of the semiconductor chip so as to be separated from the first main electrode.
Moreover, in order to form a good solder fillet, the width of the eaves portion is preferably made larger than the thickness of the solder.

この発明によると、金属部品の面積を半導体チップの活性領域の面積より大きくし、半導体チップの主電極の面積より小さくすることで、はんだ層を介して金属部品と主電極を良好に固着でき、半導体チップの外周部も含めて効率よく放熱することができる。
半導体チップの外周部も含めて効率よく放熱することができることで、放熱効率の高い半導体装置を提供することができる。 According to the present invention, the area of the metal component is larger than the area of the active region of the semiconductor chip and smaller than the area of the main electrode of the semiconductor chip, so that the metal component and the main electrode can be satisfactorily fixed via the solder layer, Heat can be efficiently radiated including the outer periphery of the semiconductor chip.
Since heat can be efficiently radiated including the outer peripheral portion of the semiconductor chip, a semiconductor device with high heat dissipation efficiency can be provided.

実施の形態については、つぎの実施例で説明する。   Embodiments will be described in the following examples.

図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。この半導体装置はダイオードの場合である。
半導体基板３の表面層にアノード領域４を形成し、半導体基板３の外周部に耐圧構造２２を構成する絶縁膜６を形成し、アノード領域４上と絶縁膜６上にひさし部７ａを有するアノード電極７を形成する。ひさし部７ａは絶縁膜６上に張り出したアノード電極７である。アノード電極７と金属部品１を第１はんだ層９を介して固着する。第１はんだ層９の上部は金属部品１の裏面全面と固着し、第１はんだ層９の下部はアノード電極７のほぼ全面と固着する。半導体基板３の裏面側には図示しないカソード領域とこのカソード領域と接続するカソード電極が形成され、このカソード電極と、配線パターンが形成されたセラミックス基板などの支持基板１５は第２はんだ層１６を介して固着する。前記のアノード領域４を垂直投影した箇所が活性領域２１であり、この活性領域２１を取り囲む半導体基板２の外周部が耐圧構造２２である。前記の第１はんだ層９と前記の第２はんだ層１６による固着はリフロー炉を用いて同時に行われる。また、はんだの塗布方法としては、金属マスクを用いてはんだペーストを所定の範囲に塗布する方法や半導体チップ２の表面にディスペンサーを用いて部分的に塗布する方法がある。 FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along line XX in FIG. It is principal part sectional drawing. This semiconductor device is a diode.
An anode region 4 is formed on the surface layer of the semiconductor substrate 3, an insulating film 6 constituting the pressure-resistant structure 22 is formed on the outer periphery of the semiconductor substrate 3, and an anode having eaves 7 a on the anode region 4 and the insulating film 6. The electrode 7 is formed. The eaves portion 7 a is an anode electrode 7 that projects on the insulating film 6. The anode electrode 7 and the metal part 1 are fixed via the first solder layer 9. The upper part of the first solder layer 9 is fixed to the entire back surface of the metal part 1, and the lower part of the first solder layer 9 is fixed to almost the entire surface of the anode electrode 7. A cathode region (not shown) and a cathode electrode connected to the cathode region are formed on the back surface side of the semiconductor substrate 3, and this cathode electrode and a support substrate 15 such as a ceramic substrate on which a wiring pattern is formed have a second solder layer 16. It sticks through. A portion obtained by vertically projecting the anode region 4 is an active region 21, and an outer peripheral portion of the semiconductor substrate 2 surrounding the active region 21 is a breakdown voltage structure 22. The fixing by the first solder layer 9 and the second solder layer 16 is performed simultaneously using a reflow furnace. Also, as a solder application method, there are a method in which a solder paste is applied in a predetermined range using a metal mask, and a method in which the solder paste is partially applied to the surface of the semiconductor chip 2 using a dispenser.

前記の金属部品１は、熱を伝導・拡散するための四角形の厚い導電ブロックの冷却体であるヒートスプレッダーまたはチップと固着するリードフレームなどの導体である。この金属部品１とパッケージの外部引き出し導体との接続は図示しないワイヤや接続導体などで行う。
また、前記のアノード電極７は一般的なアルミ系電極の表面に、はんだの接合性（密着性や濡れ性）を考慮して、図示しないシード層としてニッケル膜や金膜が形成される。これらの膜は、主に無電解メッキで形成されるが、電解メッキ、スッパタリングまたは蒸着などで形成しても良い。
後述の図２で示すように、前記の金属部品１の面積Ｓ３（第１はんだ層９と接触する側の平坦面の面積）を、前記の活性領域２１（アノード領域４）の面積Ｓ１より大きく、前記のひさし部７ａを含むアノード電極７の面積Ｓ２より小さくする。 The metal component 1 is a conductor such as a heat spreader which is a cooling body of a rectangular thick conductive block for conducting and diffusing heat, or a lead frame fixed to a chip. The metal part 1 and the external lead conductor of the package are connected by a wire or a connection conductor (not shown).
The anode electrode 7 is formed with a nickel film or a gold film as a seed layer (not shown) on the surface of a general aluminum-based electrode in consideration of solder bonding (adhesion and wettability). These films are mainly formed by electroless plating, but may be formed by electrolytic plating, sputtering or vapor deposition.
As shown in FIG. 2 described later, the area S3 of the metal component 1 (the area of the flat surface on the side in contact with the first solder layer 9) is larger than the area S1 of the active region 21 (anode region 4). The area S2 of the anode electrode 7 including the eaves 7a is made smaller.

図２は、図１（ｂ）のＡ部拡大図である。耐圧構造２２の箇所では、半導体基板３の表面層にガードリング５が形成され、表面は絶縁膜６で被覆され、開口部を介してガードリング５と金属膜８が接続している。また、絶縁膜６上に保護膜としてポリイミド膜１１を被覆する場合もある。
前記したように、耐圧構造２２の絶縁層６の上に張り出すように、半導体チップ２のアノード電極７をひさし状（ひさし部７ａ）に形成し、このアノード電極７の面積Ｓ２を半導体チップ２の活性領域２１の面積Ｓ１より大きくする。金属部品１の面積Ｓ３（平坦部の面積）を半導体チップ２の活性領域２１の面積Ｓ１より大きくし、絶縁層６上に張り出すように形成されたアノード電極７の面積Ｓ２より小さくする。この金属部品１とアノード電極７をはんだ層９を介して固着する。 FIG. 2 is an enlarged view of a portion A in FIG. A guard ring 5 is formed on the surface layer of the semiconductor substrate 3 at the location of the breakdown voltage structure 22, the surface is covered with an insulating film 6, and the guard ring 5 and the metal film 8 are connected via an opening. Further, the polyimide film 11 may be coated on the insulating film 6 as a protective film.
As described above, the anode electrode 7 of the semiconductor chip 2 is formed in an elongate shape (elongation portion 7a) so as to overhang the insulating layer 6 of the pressure-resistant structure 22, and the area S2 of the anode electrode 7 is defined as the semiconductor chip 2. The area S1 of the active region 21 is made larger. The area S3 (area of the flat part) of the metal part 1 is made larger than the area S1 of the active region 21 of the semiconductor chip 2 and made smaller than the area S2 of the anode electrode 7 formed so as to protrude on the insulating layer 6. The metal part 1 and the anode electrode 7 are fixed through the solder layer 9.

このように、主な発熱箇所である活性領域２１（アノード領域４）の面積Ｓ１より広い面積（Ｓ３）の金属部品１が固着されることにより、半導体チップ２の外周部も含めて金属部品１を介して効率よく放熱することができる。
信頼性特性を考慮し金属部品１周辺にフィレット１０を形成する場合、例えば４５°の傾斜をもつ第１はんだ層９のフィレット１０を金属部品１の周辺に形成しようとすると、フィレット１０高さ程度の濡れ広がりの余裕をもった幅を、アノード電極７のひさし部７ａに持たせれば良好なフィレット１０を形成できる。これは、金属部品１の面積Ｓ３にひさし部７ａの面積を足した面積になるようにアノード電極７の面積Ｓ２を決めるとよい。つまり、金属部品１の面積Ｓ３よりアノード電極７の面積Ｓ２を大きくする。
例えば高さ２００μｍのフィレット１０を形成するような場合、金属部品１の端から２００μｍ以上の余裕をもたせ、アノード電極７のひさし部７ａの幅Ｗを決定すれば良好なフィレット１０が得られ、第１はんだ層９による固着が強化されて接合信頼性を向上させることができる。つまり、第１はんだ層９の厚さＴよりひさし部７ａの幅Ｗを大きくするとよい。 As described above, the metal component 1 having an area (S3) wider than the area S1 of the active region 21 (anode region 4), which is the main heat generation location, is fixed, so that the metal component 1 including the outer peripheral portion of the semiconductor chip 2 is also included. It is possible to efficiently dissipate heat through the.
When the fillet 10 is formed around the metal part 1 in consideration of reliability characteristics, for example, if the fillet 10 of the first solder layer 9 having an inclination of 45 ° is formed around the metal part 1, the height of the fillet 10 is about A good fillet 10 can be formed if the eaves 7a of the anode electrode 7 has a width with a margin for the spread of wetting. It is preferable that the area S2 of the anode electrode 7 is determined so as to be an area obtained by adding the area of the eaves portion 7a to the area S3 of the metal part 1. That is, the area S2 of the anode electrode 7 is made larger than the area S3 of the metal part 1.
For example, when forming a fillet 10 having a height of 200 μm, a good fillet 10 can be obtained by providing a margin of 200 μm or more from the end of the metal part 1 and determining the width W of the eaves portion 7 a of the anode electrode 7. Adhesion by one solder layer 9 is strengthened, and joint reliability can be improved. That is, the width W of the eaves part 7 a is preferably larger than the thickness T of the first solder layer 9.

逆に、フィレット１０形成をあまり考慮しないのであれば、ひさし状部７ａの幅Ｗは広く取る必要はない。この場合でも金属部品１の面積Ｓ３を、アノード領域４の面積Ｓ１より大きく、アノード電極７の面積Ｓ２より小さくする。
一般的に絶縁膜６は厚さが数μｍ程度であり、アノード電極７の表面はこれに対応した段差が形成される。しかし、固着部分の信頼性を確保するには、第１はんだ層９の厚さは５０μｍから１００μｍ以上を必要とするようになり、アノード電極７の表面の数μｍ程度の段差により第１はんだ層９の密着性が低下するなどの問題は発生しない。
アノード電極７のひさし部７ａの端付近から、絶縁膜６（耐圧構造２２）にかけてポリイミド膜１１などでコーティングすることにより、第１はんだ層９の絶縁膜６への濡れ広がりを抑制することができる。 On the contrary, if the fillet 10 formation is not considered much, the width W of the eaves-like portion 7a does not need to be wide. Even in this case, the area S3 of the metal component 1 is larger than the area S1 of the anode region 4 and smaller than the area S2 of the anode electrode 7.
In general, the insulating film 6 has a thickness of about several μm, and a step corresponding to this is formed on the surface of the anode electrode 7. However, in order to ensure the reliability of the fixed portion, the thickness of the first solder layer 9 needs to be 50 μm to 100 μm or more, and the first solder layer is formed by a step of about several μm on the surface of the anode electrode 7. No problems such as a decrease in the adhesion of 9 occur.
By coating with the polyimide film 11 or the like from the vicinity of the end of the eaves portion 7a of the anode electrode 7 to the insulating film 6 (withstand voltage structure 22), wetting and spreading of the first solder layer 9 to the insulating film 6 can be suppressed. .

このように、金属部品１の面積Ｓ３（平坦部の面積）を半導体チップ２の活性領域２１の面積Ｓ１より大きくし、ひさし部７ａを有するアノード電極７の面積Ｓ２より小さくすることで、第１はんだ層９を介して金属部品１とアノード電極７を良好に固着でき、半導体チップ２の外周部も含めて効率よく放熱することができる。例えば、第１はんだ層９の厚さが５０μｍ〜１００μｍの場合、ひさし部７ａの幅を５０μｍ〜１００μｍとすることで、第１はんだ層９のフィレット１０を良好にすることができる。フィレット１０を良好にすることで、金属部品１と半導体チップ２の接着強度が増強され、接合信頼性を向上させることができる。   As described above, the area S3 (the area of the flat portion) of the metal component 1 is made larger than the area S1 of the active region 21 of the semiconductor chip 2 and smaller than the area S2 of the anode electrode 7 having the eaves portion 7a. The metal component 1 and the anode electrode 7 can be satisfactorily fixed via the solder layer 9 and heat can be efficiently radiated including the outer peripheral portion of the semiconductor chip 2. For example, when the thickness of the first solder layer 9 is 50 μm to 100 μm, the fillet 10 of the first solder layer 9 can be improved by setting the width of the eaves part 7 a to 50 μm to 100 μm. By making the fillet 10 good, the adhesive strength between the metal component 1 and the semiconductor chip 2 is enhanced, and the bonding reliability can be improved.

図３は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。
また、図４は、図３（ｂ）のＢ部拡大図である。この半導体装置は、ゲート電極を有する半導体装置であり、ここではＩＧＢＴを例に挙げた。
金属部品３１にはゲート電極パッド４０を避けるように切り込みが形成されている。このゲート電極４０の周辺もフィレット１０が形成される程度、分離層６ａ上に乗り上げるエミッタ電極３のひさし部３７ｂを形成しておく。分離層６ａはウェル領域３４とゲート電極パッド４０の間の絶縁を確保するために形成した絶縁膜である。
第１実施例と同様に、フィレット１０の形成をあまり考慮しないのであれば、ひさし部３７ａの幅は広く取る必要はない。前記の金属部品３１の面積Ｓ３（平坦部の面積）を活性領域２１の面積Ｓ１より大きくエミッタ電極３７の面積Ｓ２より小さくする。 FIG. 3 is a block diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 3 (a) is a plan view of an essential part, and FIG. 3 (b) is cut along line XX in FIG. 3 (a). It is principal part sectional drawing.
FIG. 4 is an enlarged view of a portion B in FIG. This semiconductor device is a semiconductor device having a gate electrode, and an IGBT is taken as an example here.
A cut is formed in the metal part 31 so as to avoid the gate electrode pad 40. An eaves portion 37b of the emitter electrode 3 that runs on the separation layer 6a is formed to the extent that the fillet 10 is also formed around the gate electrode 40. The isolation layer 6 a is an insulating film formed to ensure insulation between the well region 34 and the gate electrode pad 40.
Similar to the first embodiment, if the formation of the fillet 10 is not considered much, the eaves portion 37a does not need to be wide. The area S3 (the area of the flat portion) of the metal part 31 is made larger than the area S1 of the active region 21 and smaller than the area S2 of the emitter electrode 37.

一般的に絶縁膜６と分離層６ａの厚さは数μｍ程度であり、エミッタ電極３７の表面にこれに対応した段差が形成される。しかし、固着部分の信頼性を確保するには、第１はんだ層９の厚さは５０μｍから１００μｍ以上を必要とするようになり、エミッタ電極３７の表面の数μｍの段差は前記したいように問題とならない。
エミッタ電極３７のひさし部３７ａ、３７ｂの端付近から、絶縁膜６および分離層６ａの露出部をポリイミド膜４２などでコーティングすることにより、はんだの濡れ広がりを抑制することができる。
このように、主発熱部分である活性領域２１（最外周のウェル領域３４で囲まれた領域）より広い面積で金属部品３１を固着するこにより、半導体チップ３２の外周部を含めて金属部品３１を介して効率よく放熱することができる。 In general, the thickness of the insulating film 6 and the separation layer 6 a is about several μm, and a step corresponding to the thickness is formed on the surface of the emitter electrode 37. However, in order to ensure the reliability of the fixed part, the thickness of the first solder layer 9 needs to be 50 μm to 100 μm or more, and the step of several μm on the surface of the emitter electrode 37 is a problem as described above. Not.
By coating the exposed portions of the insulating film 6 and the separation layer 6a from the vicinity of the ends of the eaves portions 37a and 37b of the emitter electrode 37 with the polyimide film 42 or the like, the spread of the solder can be suppressed.
In this way, the metal component 31 including the outer peripheral portion of the semiconductor chip 32 is fixed by fixing the metal component 31 in an area larger than the active region 21 (region surrounded by the outermost well region 34) which is the main heat generating portion. It is possible to efficiently dissipate heat through the.

尚、図中の３５はエミッタ領域、３６はゲート絶縁膜、４０ａはゲート電極、４１は層間絶縁膜である。ゲート電極４０ａとゲート電極パッド４０とは図示しないゲート配線により接続する。   In the figure, 35 is an emitter region, 36 is a gate insulating film, 40a is a gate electrode, and 41 is an interlayer insulating film. The gate electrode 40a and the gate electrode pad 40 are connected by a gate wiring (not shown).

この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). 図１（ｂ）のＡ部拡大図Part A enlarged view of FIG. この発明の第２実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). 図３（ｂ）のＢ部拡大図Part B enlarged view of FIG. 従来の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図FIG. 2 is a configuration diagram of a conventional semiconductor device, where (a) is a plan view of the main part, and (b) is a cross-sectional view of the main part taken along line XX of (a). 図５（ｂ）のＣ部拡大図C part enlarged view of FIG.5 (b)

符号の説明Explanation of symbols

１、３１ 金属部品
２、３２ 半導体チップ
３、３３ 半導体基板
４ アノード領域
５ ガードリング
６ 絶縁膜
６ａ 分離層
７ アノード電極
７ａ、３７ａ、３７ｂ ひさし部
８ 金属膜
９ 第１はんだ層
１０ フィレット
１１、４２ ポリイミド膜
１５ 支持基板
１６ 第２はんだ層
２１ 活性領域
２２ 耐圧構造
３４ ウェル領域
３５ エミッタ領域
３６ ゲート酸化膜
３７ エミッタ電極
４０ ゲート電極パッド
４０ａ ゲート電極
４１ 層間絶縁膜
DESCRIPTION OF SYMBOLS 1,31 Metal component 2,32 Semiconductor chip 3,33 Semiconductor substrate 4 Anode area | region 5 Guard ring 6 Insulating film 6a Separation layer 7 Anode electrode 7a, 37a, 37b Eaves part 8 Metal film 9 1st solder layer 10 Fillet 11, 42 Polyimide film 15 Support substrate 16 Second solder layer 21 Active region 22 Withstand voltage structure 34 Well region 35 Emitter region 36 Gate oxide film 37 Emitter electrode 40 Gate electrode pad 40a Gate electrode 41 Interlayer insulating film

Claims (3)

半導体チップと、該半導体チップの第１主面上に該半導体チップの活性領域を取り囲んで形成される絶縁膜と、前記活性領域上から前記第１絶縁膜上に延在するひさし部を有する第１主電極と、前記半導体チップの第２主面側に形成される第２主電極と、前記ひさし部を含む前記第１主電極とはんだを介して固着される導体と、を有する半導体装置であって、前記はんだが接触する側の前記導体の平坦面の面積が、前記活性領域の面積より大きく前記ひさし部を含む第１主電極の面積より小さいことを特徴とする半導体装置。 A semiconductor chip; an insulating film formed on the first main surface of the semiconductor chip so as to surround the active region of the semiconductor chip; and a protuberance extending from the active region to the first insulating film. A semiconductor device having one main electrode, a second main electrode formed on the second main surface side of the semiconductor chip, and a conductor fixed to the first main electrode including the eaves portion via solder. The area of the flat surface of the conductor on the side in contact with the solder is larger than the area of the active region and smaller than the area of the first main electrode including the eaves. 前記半導体チップの前記第１主面上に該第１主電極と離して形成される制御電極を有することを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, further comprising a control electrode formed on the first main surface of the semiconductor chip so as to be separated from the first main electrode. 前記ひさし部の幅が前記はんだの厚さより大きいことを特徴とする請求項１〜２のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein a width of the eaves portion is larger than a thickness of the solder.
JP2005205471A 2005-07-14 2005-07-14 Semiconductor device Withdrawn JP2007027308A (en)

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JP2011134998A (en) * 2009-12-25 2011-07-07 Toyota Motor Corp Semiconductor device
JP2014192500A (en) * 2013-03-28 2014-10-06 Shindengen Electric Mfg Co Ltd Method of manufacturing mesa type semiconductor device
JP2017147418A (en) * 2016-02-19 2017-08-24 トヨタ自動車株式会社 Semiconductor device

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