JP2005197435A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP2005197435A
JP2005197435A JP2004001848A JP2004001848A JP2005197435A JP 2005197435 A JP2005197435 A JP 2005197435A JP 2004001848 A JP2004001848 A JP 2004001848A JP 2004001848 A JP2004001848 A JP 2004001848A JP 2005197435 A JP2005197435 A JP 2005197435A
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substrate
semiconductor device
semiconductor element
power
power switching
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JP4491244B2 (en
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Makoto Kondo
信 近藤
Noriyoshi Arai
規由 新井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2004001848A priority Critical patent/JP4491244B2/en
Priority to DE200410060935 priority patent/DE102004060935B4/en
Priority to FR0413856A priority patent/FR2879021B1/en
Priority to US11/029,379 priority patent/US7535076B2/en
Priority to CNB2005100037238A priority patent/CN100435333C/en
Publication of JP2005197435A publication Critical patent/JP2005197435A/en
Priority to US12/427,151 priority patent/US7859079B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To control gate oscillation resulting from division of emitter cell by thermal dispersion on an element through reduction of circuit resistance with improvement of current capacity of the main circuit in the power semiconductor device. <P>SOLUTION: In the power semiconductor device, a power switching semiconductor element and a free wheel diode connected inversely in parallel to the power switching semiconductor element are provided, and the rear electrode of the power switching semiconductor element and the rear electrode of the free wheel diode are adhered and mounted on a circuit pattern formed on the principal surface of a first substrate. Moreover, a circuit pattern formed on the opposing main surface of a second substrate allocated opposing to the front electrode of the power switching semiconductor element and the front electrode of the free wheel diode is respectively connected to the front electrode of the power switching semiconductor element and the front electrode of the free wheel diode via the connecting conductor to be soldered. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電力用半導体装置に関する。   The present invention relates to a power semiconductor device.

従来の一般的な電力用半導体装置の構成を図１３に示す。   FIG. 13 shows a configuration of a conventional general power semiconductor device.

金属製のベース板２の上に、セラミックの表裏に回路パターンを金属メッキした絶縁基板４が配置され、その上にＩＧＢＴ／ＭＯＳＦＥＴ等の電力用スイッチング半導体素子６並びにフリーホイルダイオード８が搭載される。電力用スイッチング半導体素子６とフリーホイルダイオード８は、外部端子を内蔵したケース(インサートケース)１８と（外部端子を介して）接続する。ＩＧＢＴなどの電力用スイッチング半導体素子６は、上（表）がエミッタ面、下（裏）がコレクタ面になるように配置され、フリーホイルダイオード８は上（表）がアノード面、下（裏）がカソード面となるように配置されている。全体の回路は、絶縁基板４上のパターンとワイヤ２０を使って構成され、ケース１８に接続されている。これら素子並びに回路を保護するためケース１８内部はゲル（もしくは樹脂、ゲル及び樹脂）３６を注入し蓋で覆っている。   An insulating substrate 4 in which a circuit pattern is metal-plated on both sides of a ceramic is disposed on a metal base plate 2, and a power switching semiconductor element 6 such as an IGBT / MOSFET and a free foil diode 8 are mounted thereon. . The power switching semiconductor element 6 and the free wheel diode 8 are connected (via an external terminal) to a case (insert case) 18 having a built-in external terminal. The power switching semiconductor element 6 such as IGBT is arranged so that the upper (front) is the emitter surface and the lower (back) is the collector surface, and the freewheel diode 8 is the upper (front) is the anode surface and the lower (back). Is arranged to be the cathode surface. The entire circuit is configured by using the pattern on the insulating substrate 4 and the wire 20 and is connected to the case 18. In order to protect these elements and circuits, the inside of the case 18 is filled with a gel (or resin, gel and resin) 36 and covered with a lid.

このように、電力用半導体装置において電力用スイッチング半導体素子６のエミッタ面の接続は、ワイヤ２０でなされる。このため、以下のような問題点が生じている。   In this way, the connection of the emitter surface of the power switching semiconductor element 6 in the power semiconductor device is made by the wire 20. For this reason, the following problems have arisen.

第一に、このワイヤ２０が細いため電流（の量）に限界があることである。実務上は、ワイヤ２０を太くすることやワイヤ本数を増やすことで主回路に必要な電流容量を確保している。けれども、そのためのワイヤボンドのスペースが必要となる。よって素子並びに装置の小型化が進む中でこの方法には自ずと限界がある。第二に、ワイヤ２０が細いため回路抵抗が大きくなることである。この問題点もワイヤ２０を太くすることやワイヤ本数を増やすことで軽減できるが、上記と同様に自ずと限界がある。第三に、電力用スイッチング半導体素子６上のワイヤ接合面に電流が集中し、熱が局在化することである。素子上のワイヤ接合面を分散させることで熱の集中を軽減しているが、完全に発散させるには到っていない。第四に、半導体装置の短絡時のゲート発振が生じ得ることである。電力用半導体装置では、電力用スイッチング半導体素子６のエミッタセル毎にワイヤ２０を接合し、各セル同士はワイヤ２０の接合先の絶縁基板４上のパターンを介して接続されている。このことにより各セルでアンバランスが生じて、半導体装置の短絡時にゲート発振が起こり装置の破壊若しくは誤動作が起きことがある。各セル同士を直接ワイヤでステッチ接続することでこの問題は解決できる、とも言えそうであるが、ワイヤボンドの回数とそのための面積が増えるため、やはり上記の第一の問題点と同様の眼界がある。第五に、ワイヤの接合のための空間が必要となることである。   First, since the wire 20 is thin, the current (amount) is limited. In practice, the current capacity necessary for the main circuit is secured by making the wires 20 thicker or increasing the number of wires. However, this requires a wire bond space. Therefore, this method has its own limitations as the elements and devices become smaller. Second, since the wire 20 is thin, the circuit resistance is increased. This problem can be alleviated by making the wire 20 thicker or increasing the number of wires, but there is a limit in itself as described above. Third, current concentrates on the wire bonding surface on the power switching semiconductor element 6 and heat is localized. Although the concentration of heat is reduced by dispersing the wire bonding surface on the element, it has not yet completely diverged. Fourth, gate oscillation can occur when the semiconductor device is short-circuited. In the power semiconductor device, a wire 20 is bonded to each emitter cell of the power switching semiconductor element 6, and each cell is connected through a pattern on the insulating substrate 4 to which the wire 20 is bonded. As a result, imbalance occurs in each cell, and gate oscillation may occur when the semiconductor device is short-circuited, resulting in destruction or malfunction of the device. It can be said that this problem can be solved by stitching each cell directly with a wire, but since the number of wire bonds and the area for the wire bond increase, the same field of view as the first problem described above is obtained. is there. Fifth, a space for joining wires is required.

以上がワイヤ２０に関する主な問題点である。更に、放熱の問題もある。従来の半導体装置ではベース板裏にグリースを塗布し放熱フィンにネジ止めして放熱を行っている。この場合、片側のみしか放熱に利用できないという問題がある。   The above is the main problem regarding the wire 20. There is also a problem of heat dissipation. In a conventional semiconductor device, heat is radiated by applying grease to the back of the base plate and screwing it to the radiating fin. In this case, there is a problem that only one side can be used for heat dissipation.

なお、特許文献１では、上下に回路付パターンを有するＩＧＢＴモジュールにおいて、主電極の接続は多数のバンプを介して行う技術が開示される。特許文献２では、導電体小片類似の構成の技術の開示がある。特許文献３では、デバイスに多数のバンプを設ける例が示される。特許文献４では、２枚の基板をバネ接続する技術が示される。特許文献５では、パッケージマザーボードの接続において、バンプ中にポールや金属球を埋め込む技術が開示される。特許文献６や特許文献７では、上下２枚のリードフレーム使用のＩＰＭが示される。
特開平１０−５６１３１号公報 特開平８−８３９５号公報 特開平１０−２３３５０９号公報 特開平６−３０２７３４号公報 特開平８−１７９７２号公報 特開２００２−１６２１５公報 特開２００２−７６２５４公報 Patent Document 1 discloses a technique in which main electrodes are connected through a large number of bumps in an IGBT module having patterns with circuits on the top and bottom. Patent Document 2 discloses a technique having a configuration similar to a conductor piece. Patent Document 3 shows an example in which a large number of bumps are provided in a device. Patent Document 4 discloses a technique for connecting two substrates by springs. Patent Document 5 discloses a technique of embedding a pole or a metal ball in a bump when connecting a package mother board. Patent Document 6 and Patent Document 7 show an IPM using two upper and lower lead frames.
JP-A-10-56131 JP-A-8-8395 Japanese Patent Laid-Open No. 10-233509 JP-A-6-302734 JP-A-8-17972 JP 2002-16215 A JP 2002-76254 A

本発明は、電力用半導体装置において、主回路の電流容量を向上させ回路抵抗を低下し、また、素子上で熱分散させエミッタセル分割起因のゲート発振を抑制することを目的とする。   An object of the present invention is to improve the current capacity of a main circuit and reduce circuit resistance in a power semiconductor device, and to suppress gate oscillation caused by emitter cell division by heat dispersion on the element.

本発明は上記の目的を達成するためになされたものである。本発明の好適な実施の形態に係る電力用半導体装置は、
電力用スイッチング半導体素子と、該電力用スイッチング半導体素子と逆並列に接続されるフリーホイルダイオードとを備えた電力用半導体装置である。その電力用半導体装置において、
第１の基板の表主面に形成された回路パターン上に前記電力用スイッチング半導体素子の裏面電極および前記フリーホイルダイオードの裏面電極とを接着し搭載すると共に、前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極と対向するように配設された第２の基板の前記対向主面に形成された回路パターンを、半田付けされる接続導体を介し前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極の夫々に接続したことを特徴とする。 The present invention has been made to achieve the above object. A power semiconductor device according to a preferred embodiment of the present invention includes:
A power semiconductor device comprising a power switching semiconductor element and a free wheel diode connected in reverse parallel to the power switching semiconductor element. In the power semiconductor device,
A back electrode of the power switching semiconductor element and a back electrode of the free wheel diode are bonded and mounted on a circuit pattern formed on the front main surface of the first substrate, and a front electrode of the power switching semiconductor element And a surface of the switching semiconductor element for power via a connection conductor to which a circuit pattern formed on the opposing main surface of the second substrate disposed so as to face the surface electrode of the free wheel diode is soldered The electrode and the surface electrode of the free wheel diode are connected to each other.

本発明を利用することにより、主回路の電流容量を大幅に向上でき回路抵抗を低下できる。また、素子上での熱分散、エミッタセル分割起因のゲート発振の抑制に効果があり、装置全体を小型化できる。さらに、電力用半導体装置の上下両方の面から放熱することもできる。   By utilizing the present invention, the current capacity of the main circuit can be greatly improved and the circuit resistance can be lowered. In addition, it is effective in suppressing heat dispersion on the element and gate oscillation due to emitter cell division, and the entire apparatus can be miniaturized. Furthermore, heat can be radiated from both the upper and lower surfaces of the power semiconductor device.

以下、図面を参照して本発明に係る好適な実施の形態を説明する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings.

実施の形態１
図１は、本発明の実施の形態１に係る電力用半導体装置である。（１）は以下に説明する第１の基板の上面図、（２）は以下に説明する第２の基板の下面図、（３）は側断面図である。該電力用半導体装置では、第１の基板２４上に電力用スイッチング半導体素子６及びフリーホイルダイオード８が搭載される。ここで、電力用スイッチング半導体素子６のエミッタ面及びフリーホイルダイオード８のアノード面は、接続導体（図では球）２２を介して、回路パターン付絶縁基板である第２の基板２６と接続する。電力用スイッチング半導体素子６は、ＩＧＢＴ／ＭＯＳＦＥＴなどの半導体である Embodiment 1
FIG. 1 shows a power semiconductor device according to Embodiment 1 of the present invention. (1) is a top view of a first substrate described below, (2) is a bottom view of a second substrate described below, and (3) is a side sectional view. In the power semiconductor device, the power switching semiconductor element 6 and the free wheel diode 8 are mounted on the first substrate 24. Here, the emitter surface of the power switching semiconductor element 6 and the anode surface of the free wheel diode 8 are connected to a second substrate 26 which is an insulating substrate with a circuit pattern via a connection conductor (sphere in the figure) 22. The power switching semiconductor element 6 is a semiconductor such as an IGBT / MOSFET.

図１（３）に示されるように、第１の基板２４の下方に放熱部としてのヒートシンク３２が接着される。このヒートシンク３２は、第２の基板の上方面に接着することもできる。図１（３）のように直接絶縁基板が外部に露出することで強度に問題が生じるような場合には、下方面にベース板を取り付けたり、一部をコーティングしたり、ケースで覆うことをすればよい。   As shown in FIG. 1 (3), a heat sink 32 as a heat radiating portion is bonded below the first substrate 24. The heat sink 32 can be adhered to the upper surface of the second substrate. As shown in Fig. 1 (3), when the insulation substrate is directly exposed to the outside and there is a problem in strength, a base plate is attached to the lower surface, a part of it is coated, or it is covered with a case. do it.

接続導体２２を始め、其々の部品の接続は、半田付け、超音波接合、若しくは圧接などで行えばよい。実施の形態１では、其々の部品を第１の基板２４上に全て載せるようにしており、よって生産上の困難が避けられ生産性が向上する。また、接続導体２２は、組立後の状態において可撓性を有するようにしている。接続導体２２にかかる応力を吸収するためである。   Connection of each component including the connection conductor 22 may be performed by soldering, ultrasonic bonding, or pressure welding. In the first embodiment, all the components are placed on the first substrate 24, so that production difficulties are avoided and productivity is improved. Further, the connection conductor 22 has flexibility in the assembled state. This is because the stress applied to the connection conductor 22 is absorbed.

第１の基板２４と第２の基板２６との間には、ゲル状の絶縁耐熱性充填剤３６（わかりやすさのため、図ではハッチングを施していない）を充填する。この際、図６に示すように、３辺を接着剤や仕切り部材３４等で封鎖し、開口部から注入を行う。注入に際して、開口部からではなく、注射器等で３辺の底辺から行うこともできる。   Between the 1st board | substrate 24 and the 2nd board | substrate 26, it fills with the gel-like insulation heat resistant filler 36 (For the sake of clarity, it is not hatching in the figure.). At this time, as shown in FIG. 6, the three sides are sealed with an adhesive, a partition member 34, and the like, and injection is performed from the opening. The injection can be performed not from the opening but from the bottom of the three sides with a syringe or the like.

実施の形態１には次のような利点がある。一般に、伝導体の電流容量はその断面積に比例し電気抵抗は断面積に反比例する。回路の電流容量を増加させ電気抵抗を低下させるには伝導体の断面積を増やせばよい。しかし、電力用半導体装置においては、半導体素子のエミッタ面の面積は限られているため、ワイヤ全体の断面積（１本の断面積×本数）を増やすことには限界がある。しかも、ワイヤで接続する場合には、接続作業をするためのデッドスペースが不可欠である。ここで、実施の形態１のような接続導体２２を利用すると、かようなデッドスペースが不必要である。つまり、素材を同じとして、ワイヤで接続する場合と接続導体で接続する場合とを比較すると、後者のほうが実質的に２倍以上の断面積を持ち得ることとなる。   The first embodiment has the following advantages. In general, the current capacity of a conductor is proportional to its cross-sectional area, and the electrical resistance is inversely proportional to its cross-sectional area. In order to increase the current capacity of the circuit and reduce the electrical resistance, the cross-sectional area of the conductor may be increased. However, in the power semiconductor device, since the area of the emitter surface of the semiconductor element is limited, there is a limit to increasing the cross-sectional area of the entire wire (one cross-sectional area × number). In addition, when connecting with wires, a dead space for connection work is indispensable. Here, when the connection conductor 22 as in the first embodiment is used, such a dead space is unnecessary. That is, when the materials are the same and the case of connecting with wires and the case of connecting with connecting conductors are compared, the latter can have a cross-sectional area substantially twice or more.

さらに、対向する第１の基板２４と第２の基板２６は、短距離で接続しているためその分電気・熱抵抗が小さくなる。ここで、どの程度の短距離まで許容されるかは、２つの基板間の絶縁の必要性に依存するが、絶縁充填剤が入れられるから定格電圧３．３ｋＶ程であるなら２ｍｍ程度までは許容され得ると考えられる。   Furthermore, since the opposing first substrate 24 and second substrate 26 are connected at a short distance, the electrical / thermal resistance is reduced accordingly. Here, how much short distance is allowed depends on the necessity of insulation between the two substrates, but if the rated voltage is about 3.3 kV, it is acceptable up to about 2 mm because the insulating filler is inserted. It is thought that it can be done.

ワイヤには、通常、加工上の便宜からＡｌ（アルミニウム）が利用されている。一方、実施の形態１における接続導体２２では、そのような加工上の便宜を考慮する必要が無いから、（Ａｌより電気・熱伝導率がよい）Ｃｕを使うことができる。   For the wire, Al (aluminum) is usually used for processing convenience. On the other hand, in the connection conductor 22 in the first embodiment, it is not necessary to consider such processing convenience, so Cu (which has better electrical and thermal conductivity than Al) can be used.

以上のように、実施の形態１において、接続導体を介して回路パターン付絶縁基板を接続することにより、主回路の電気容量の大幅な向上並びに回路抵抗の低下を実現できる。さらに、エミッタセルと接続する実質的な面積が大きく、よって回路パターンに短距離で接続するから、半導体素子上での熱分散の向上や、エミッタセル分割起因のゲート発振の抑制を実現できる。加えて、回路パターン上にワイヤを接続するためのスペースを減らせ得るので、装置全体の平面面積を減らすことができる。高さに関しては、元来電力用半導体装置ではワイヤ高さが必要であるから、実施の形態１を利用したとしても大きく増えることはない。   As described above, in the first embodiment, by connecting the insulating substrate with a circuit pattern via the connection conductor, it is possible to realize a great improvement in the electric capacity of the main circuit and a reduction in the circuit resistance. Furthermore, since the substantial area connected to the emitter cell is large, and therefore, the circuit pattern is connected at a short distance, improvement of heat dispersion on the semiconductor element and suppression of gate oscillation due to emitter cell division can be realized. In addition, since the space for connecting the wires on the circuit pattern can be reduced, the plane area of the entire device can be reduced. Regarding the height, the power semiconductor device originally needs the wire height, so even if the first embodiment is used, it does not increase greatly.

更に、上下の両面にヒートシンクを取り付けることにより、放熱効果を向上させることが可能である。   Furthermore, it is possible to improve the heat dissipation effect by attaching heat sinks to the upper and lower surfaces.

実施の形態２
図２は、本発明の実施の形態２に係る電力用半導体装置である。実施の形態２に係る電力用半導体装置は、実施の形態１のものと略同様である。よって、同一部分には同一符号を付して説明を省略し、差異を中心に説明する。（１）が第１の基板の上面図、（２）が第２の基板の下面図、（３）が側断面図であることも、図１と同様である。 Embodiment 2
FIG. 2 shows a power semiconductor device according to the second embodiment of the present invention. The power semiconductor device according to the second embodiment is substantially the same as that of the first embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences will be mainly described. As in FIG. 1, (1) is a top view of the first substrate, (2) is a bottom view of the second substrate, and (3) is a side sectional view.

実施の形態２に係る電力用半導体装置では、接続導体を利用するのではなく、接続用の突出端３８を備える回路パターン付絶縁基板を第２の基板２６として用いる。接続用の突出端３８は、導電体で構成され、第１の基板２４上の電力用スイッチング半導体素子６のエミッタ面及びフリーホイルダイオード８のアノード面に接続する。   In the power semiconductor device according to the second embodiment, an insulating substrate with a circuit pattern including a protruding end 38 for connection is used as the second substrate 26 instead of using a connection conductor. The connecting protruding end 38 is made of a conductor and is connected to the emitter surface of the power switching semiconductor element 6 on the first substrate 24 and the anode surface of the freewheel diode 8.

実施の形態２には次のような利点がある。実施の形態１では、接続導体を半導体素子と回路パターン付絶縁基板との両方に接続する必要がある。このため、工程が多く、場合によっては多少の困難が生じることも予想される。実施の形態２では、突出端をそなえる回路パターン付絶縁基板を用いることにより、工程を簡略化できて装置の信頼性も向上させることができる。   The second embodiment has the following advantages. In the first embodiment, it is necessary to connect the connection conductor to both the semiconductor element and the insulating substrate with a circuit pattern. For this reason, there are many steps, and it is expected that some difficulties will occur in some cases. In the second embodiment, by using an insulating substrate with a circuit pattern having a protruding end, the process can be simplified and the reliability of the apparatus can be improved.

実施の形態３
図３は、本発明の実施の形態３に係る電力用半導体装置である。実施の形態３に係る電力用半導体装置も、実施の形態１及び実施の形態２のものと略同様である。よって、同一部分には同一符号を付して説明を省略し、差異を中心に説明する。（１）が第１の基板の上面図、（２）が第２の基板の下面図、（３）が側断面図であることも、図１、図２と同様である。 Embodiment 3
FIG. 3 shows a power semiconductor device according to the third embodiment of the present invention. The power semiconductor device according to the third embodiment is substantially the same as that of the first and second embodiments. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences will be mainly described. As in FIGS. 1 and 2, (1) is a top view of the first substrate, (2) is a bottom view of the second substrate, and (3) is a side sectional view.

図３の実施の形態３に係る電力用半導体装置は、実施の形態２に係る電力用半導体装置の接続用の突起を備えた回路パターン付き絶縁基板（第２の基板２６）を利用しつつ、更に、接続導体２２も利用する。つまり、第１の基板２４上の電力用スイッチング半導体素子６のエミッタ面及びフリーホイルダイオード８のアノード面と、第２の基板２６である回路パターン付絶縁基板の回路パターンとを、回路パターンの導電体の突出端３８と接続導体２２とにより、接続する。   The power semiconductor device according to the third embodiment of FIG. 3 uses an insulating substrate with a circuit pattern (second substrate 26) provided with a projection for connection of the power semiconductor device according to the second embodiment. Furthermore, a connection conductor 22 is also used. In other words, the emitter surface of the power switching semiconductor element 6 and the anode surface of the free wheel diode 8 on the first substrate 24 and the circuit pattern of the insulating substrate with a circuit pattern, which is the second substrate 26, are connected to each other. Connection is made by the protruding end 38 of the body and the connecting conductor 22.

実施の形態３のように、接続用の突出端と接続導体とを同時に利用することにより、対向する第１の導体２４と第２の導体２６の接続における、両者の距離と接続に要する面積とを、夫々独立に調整することができる。よって、電流量や熱量や応力などを考慮した最適な設計を行うことができる。   As in the third embodiment, by using the connecting protruding end and the connecting conductor at the same time, the distance between the first conductor 24 and the second conductor 26 facing each other, and the area required for the connection, Can be adjusted independently. Therefore, an optimal design can be performed in consideration of the amount of current, the amount of heat, and stress.

実施の形態４
図４は、本発明の実施の形態４に係る電力用半導体装置である。実施の形態４に係る電力用半導体装置は、実施の形態１乃至実施の形態３のものと略同様である。よって、同一部分には同一符号を付して説明を省略し、差異を中心に説明する。（１）が第１の基板の上面図、（２）が第２の基板の下面図、（３）が側断面図であることも、図１と同様である。 Embodiment 4
FIG. 4 shows a power semiconductor device according to Embodiment 4 of the present invention. The power semiconductor device according to the fourth embodiment is substantially the same as that of the first to third embodiments. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences will be mainly described. As in FIG. 1, (1) is a top view of the first substrate, (2) is a bottom view of the second substrate, and (3) is a side sectional view.

図４の実施の形態４に係る電力用半導体装置は、実施の形態１乃至実施の形態３に係る電力用半導体装置において、第２の基板２６の一部に表裏を導通させる部分と裏面（外側面）回路パターンを作るものである。この裏側主面に配設される回路パターンには、電力用スイッチング半導体素子６を駆動制御する制御用回路４０が搭載される。   The power semiconductor device according to the fourth embodiment of FIG. 4 is the same as the power semiconductor device according to the first to third embodiments. Side) Creates a circuit pattern. A control circuit 40 for driving and controlling the power switching semiconductor element 6 is mounted on the circuit pattern disposed on the back side main surface.

このようにすることにより、駆動制御部を別途プリント基板等で用意することなく直接搭載することができる。よって、部品点数を減らし、生産性を向上させることができる。更に、駆動制御部を電力用スイッチング半導体素子６の近傍に置くことで、インダクタンスを小さくでき、より適切な制御が可能となる。   By doing in this way, a drive control part can be directly mounted, without preparing separately with a printed circuit board etc. Therefore, the number of parts can be reduced and productivity can be improved. Furthermore, by placing the drive control unit in the vicinity of the power switching semiconductor element 6, the inductance can be reduced, and more appropriate control can be performed.

実施の形態５
図５は、本発明の実施の形態５に係る電力用半導体装置である。実施の形態５に係る電力用半導体装置は、実施の形態１乃至実施の形態４のものと略同様である。よって、同一部分には同一符号を付して説明を省略し、差異を中心に説明する。（１）が第１の基板の上面図、（２）が第２の基板の下面図、（３）が側断面図であることも、図１と同様である。 Embodiment 5
FIG. 5 shows a power semiconductor device according to the fifth embodiment of the present invention. The power semiconductor device according to the fifth embodiment is substantially the same as that of the first to fourth embodiments. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences will be mainly described. As in FIG. 1, (1) is a top view of the first substrate, (2) is a bottom view of the second substrate, and (3) is a side sectional view.

図５の実施の形態５に係る電力用半導体装置は、実施の形態１乃至実施の形態４に係る電力用半導体装置において、少なくとも第１の基板２４がセラミック絶縁基板であり、且つ該セラミック絶縁基板の裏面に複数に分割したヒートシンク３２を接着するものである。   The power semiconductor device according to the fifth embodiment of FIG. 5 is the power semiconductor device according to the first to fourth embodiments. At least the first substrate 24 is a ceramic insulating substrate, and the ceramic insulating substrate. The heat sink 32 divided into a plurality of parts is bonded to the back surface of the sheet.

このようにすることにより、放熱性の効率を高め得るだけでなく、ヒートシンクを複数に分割することから、応力を分散させてセラミック基板の熱割れを防止できる。   By doing in this way, not only can the efficiency of heat dissipation be improved, but the heat sink is divided into a plurality of parts, so that stress can be dispersed and thermal cracking of the ceramic substrate can be prevented.

また、分割したヒートシンクと第１の基板２４とを一体化させてもよい。このようにすると、生産性を向上させ、ボイド・クラック等による接続部の熱抵抗の上昇を避けることができる。   Further, the divided heat sink and the first substrate 24 may be integrated. In this way, productivity can be improved and an increase in the thermal resistance of the connection part due to voids, cracks, etc. can be avoided.

実施の形態６
図７及び図８は、本発明の実施の形態６に係る電力用半導体装置である。（１）が（以下で説明する）第１のリードフレームの上面図、（２）が（以下で説明する）第２のリードフレームの下面図、（３）が側断面図であることは、図１乃至図５と略同様である。 Embodiment 6
7 and 8 show a power semiconductor device according to the sixth embodiment of the present invention. (1) is a top view of the first lead frame (described below), (2) is a bottom view of the second lead frame (described below), and (3) is a side sectional view. This is substantially the same as FIGS.

該電力用半導体装置でも、電力用スイッチング半導体素子６と、該電力用スイッチング半導体素子６と逆並列に接続されるフリーホイルダイオード８とを備えるのであるが、両者は、絶縁基板ではなく、リードフレーム（第１のリードフレーム２８）上に搭載される。つまり、第１のリードフレーム２８の表主面に電力用スイッチング半導体素子６の裏面電極と、フリーボイルダイオード８の裏面電極とを接合する。同時に、電力用スイッチング半導体素子６の表面電極とフリーホイルダイオード８の表面電極とに対向する第２のリードフレーム３０の対向主面の一部を突出させ、その突出端３８を電力用スイッチング半導体素子６の表面電極とフリーホイルダイオード８の表面電極とに接続させている。この全体は樹脂にてトランスファーモールドされている。   The power semiconductor device also includes a power switching semiconductor element 6 and a freewheel diode 8 connected in reverse parallel to the power switching semiconductor element 6, both of which are not an insulating substrate but a lead frame. It is mounted on (first lead frame 28). That is, the back electrode of the power switching semiconductor element 6 and the back electrode of the free boil diode 8 are joined to the front main surface of the first lead frame 28. At the same time, a part of the opposing main surface of the second lead frame 30 facing the surface electrode of the power switching semiconductor element 6 and the surface electrode of the free wheel diode 8 is protruded, and the protruding end 38 is formed as the power switching semiconductor element. 6 and the surface electrode of the free wheel diode 8 are connected. The whole is transfer molded with resin.

実施の形態６に係る電力用半導体装置は、実施の形態１のそれと比べると、絶縁耐量は低くなるが、安価で加工のし易いリードフレームを用いるため、安価で生産性の高い電力用半導体装置を提供できる。さらに、外部端子をリードフレームで作ることで部品点数を減らせ生産性を向上できる。   The power semiconductor device according to the sixth embodiment has a lower dielectric strength than that of the first embodiment, but uses a lead frame that is inexpensive and easy to process. Therefore, the power semiconductor device is inexpensive and has high productivity. Can provide. Furthermore, by making the external terminal with a lead frame, the number of parts can be reduced and productivity can be improved.

図７の電力用半導体装置は、接続突出端３８を一つの素子に対して複数にして、素子表面のゲート配線を避けている。さらに複数に分けることで応力を緩和することを意図している。図８の電力用半導体装置は接、接続突出端３８をベタ板にして接続面積を増やしている。これにより、素子上での電流の集中を避け得る上に、放熱効率を向上できる。   The power semiconductor device of FIG. 7 avoids gate wiring on the surface of the element by providing a plurality of connection protruding ends 38 for one element. Furthermore, it is intended to relieve stress by dividing it into multiple parts. In the power semiconductor device of FIG. 8, the connection projecting end 38 is a solid plate to increase the connection area. As a result, current concentration on the element can be avoided and heat dissipation efficiency can be improved.

実施の形態７
図９は、本発明の実施の形態７に係る電力用半導体装置である。実施の形態７に係る電力用半導体装置は、実施の形態６のものと略同様である。よって、同一部分には同一符号を付して説明を省略し、差異を中心に説明する。（１）が第１のリードフレームの上面図、（２）が第２のリードフレームの下面図、（３）が側断面図であることも、図７及び図８と略同様である。 Embodiment 7
FIG. 9 shows a power semiconductor device according to Embodiment 7 of the present invention. The power semiconductor device according to the seventh embodiment is substantially the same as that of the sixth embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences will be mainly described. It is substantially the same as FIGS. 7 and 8 that (1) is a top view of the first lead frame, (2) is a bottom view of the second lead frame, and (3) is a side sectional view.

実施の形態７では、第１のリードフレーム２８と第２リードフレーム３０のいずれも平板状である。更に、第２のリードフレーム３０の対向主面の所定の位置に複数の接続導体２２を半田付けし、それら複数の接続導体を電力用スイッチング半導体素子６の表面電極とフリーホイルダイオード８の表面電極とに対応付けて半田付けしている。つまり、接続突出端ではなく接続導体２２が上下を繋ぐ。   In the seventh embodiment, both the first lead frame 28 and the second lead frame 30 are flat. Further, a plurality of connection conductors 22 are soldered to predetermined positions on the opposing main surface of the second lead frame 30, and the plurality of connection conductors are connected to the surface electrode of the power switching semiconductor element 6 and the surface electrode of the free foil diode 8. Soldering in association with. That is, the connection conductor 22 connects the upper and lower sides, not the connection protruding end.

実施の形態７に係る電力用半導体装置は、実施の形態６のそれと比べると、部品点数は多くなるが、接続部分の形状・材質の選択を増すことができるため、回路抵抗の低減と信頼性の向上が可能となる。   The power semiconductor device according to the seventh embodiment has a larger number of parts than that of the sixth embodiment, but can increase the selection of the shape and material of the connection portion, thereby reducing circuit resistance and reliability. Can be improved.

実施の形態７に係る電力用半導体装置において、図１０に示すように、第１のリードフレーム２８と対向する第２のリードフレーム３０の対向主面の裏側に配設される裏側主面にて、電力用スイッチング半導体素子６を駆動制御する制御用回路４０を搭載してもよい。   In the power semiconductor device according to the seventh embodiment, as shown in FIG. 10, the back side main surface disposed on the back side of the opposing main surface of the second lead frame 30 facing the first lead frame 28. A control circuit 40 for driving and controlling the power switching semiconductor element 6 may be mounted.

更に、第２のリードフレームの代わりに、多層プリント基板、又はスルーホール基板を用いて、そこに電力用スイッチング半導体素子６を駆動制御する制御用回路を搭載してもよい。   Furthermore, instead of the second lead frame, a multilayer printed board or a through-hole board may be used, and a control circuit for driving and controlling the power switching semiconductor element 6 may be mounted thereon.

このように制御用回路４０を搭載することにより、駆動制御部を別途プリント基板等で用意せずに直接搭載することができ、部品点数を滅らし、生産性を向上させることができる。更に駆動制御部を電力用スイッチング半導体素子の近傍に置くことで、インダクタンスを小さくできより適切な制御を可能となる。   By mounting the control circuit 40 in this way, it is possible to directly mount the drive control unit without preparing a separate printed circuit board or the like, thereby reducing the number of parts and improving productivity. Further, by placing the drive control unit in the vicinity of the power switching semiconductor element, the inductance can be reduced and more appropriate control can be performed.

実施の形態８
図１１及び図１２は、本発明の実施の形態８に係る電力用半導体素子である。図１１において、（１）は側断面図、（２）は第３のリードフレームの下面図、（３）は第２のリードフレームの上面図、（４）は第１のリードフレームの上面図である。図１２において、（１）は側断面図、（２）は第４のリードフレームの下面図、（３）は第３のリードフレームの上面図、（４）は第４のリードフレームの下面図、（５）は第１のリードフレームの上面図である。 Embodiment 8
11 and 12 show a power semiconductor element according to the eighth embodiment of the present invention. 11, (1) is a side sectional view, (2) is a bottom view of the third lead frame, (3) is a top view of the second lead frame, and (4) is a top view of the first lead frame. It is. In FIG. 12, (1) is a sectional side view, (2) is a bottom view of the fourth lead frame, (3) is a top view of the third lead frame, and (4) is a bottom view of the fourth lead frame. (5) is a top view of the first lead frame.

図１１、図１２の電力用半導体装置は、実施の形態１乃至実施の形態７を応用するものであり、リードフレーム（または絶縁基板）を２枚ではなく３枚以上としている。   The power semiconductor device of FIGS. 11 and 12 applies the first to seventh embodiments, and has three or more lead frames (or insulating substrates) instead of two.

通常の電力用半導体装置では、搭載する素子を増やすと平面方向に広がるしかないため、平面面積がその分大きくなる。本実施の形態では、立体方向に配置するため、平面面積を大幅に減らすことができる。その分高さが増えるとも考えられるが、従来技術ではワイヤ接続のために相当の高さが必要であるのだから、それと比較しても大きく増えることはない。   In a normal power semiconductor device, if the number of elements to be mounted is increased, the planar area can only be increased in the planar direction. In the present embodiment, the planar area can be significantly reduced because the three-dimensional direction is used. Although it is considered that the height will increase accordingly, the conventional technique requires a considerable height for wire connection, so it does not increase much compared to that.

更に、単に平面面積と回路抵抗を小さくするだけでなく、本実施の形態をインバータ使用する場合、３枚で１アームを形成することができ、共通電位部を別途設けずに済む。また、貼り合せによるインダクタンスの低減を図ることでサージ抑制の効果もある。   Furthermore, in addition to simply reducing the planar area and the circuit resistance, when the present embodiment is used with an inverter, one arm can be formed with three pieces, and a common potential portion need not be provided separately. Moreover, there is an effect of surge suppression by reducing the inductance by bonding.

特に図１１の装置では、主電流経路が対面になっているため、インダクタンスの低減を図ることができる。また、特に図１２の装置では、放熱部に素子が近く効果的に放熱することができる。   In particular, in the apparatus of FIG. 11, since the main current path is facing, the inductance can be reduced. In particular, in the apparatus of FIG. 12, the element is close to the heat radiating portion and can effectively radiate heat.

本発明の実施の形態１に係る電力用半導体装置である。1 is a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態２に係る電力用半導体装置である。3 is a power semiconductor device according to a second embodiment of the present invention. 本発明の実施の形態３に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る電力用半導体装置である。7 is a power semiconductor device according to a fifth embodiment of the present invention. 第１の基板と第２の基板との間にゲル状の絶縁耐熱性充填剤を充填する模式図である。It is a schematic diagram with which a gel-like insulating heat resistant filler is filled between the first substrate and the second substrate. 本発明の実施の形態６に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 6 of this invention. 本発明の実施の形態６に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 6 of this invention. 本発明の実施の形態７に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 7 of this invention. 本発明の実施の形態７に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 7 of this invention. 本発明の実施の形態８に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 8 of this invention. 本発明の実施の形態８に係る電力用半導体装置である。It is a power semiconductor device which concerns on Embodiment 8 of this invention. 従来の一般的な電力用半導体装置の構成である。This is a configuration of a conventional general power semiconductor device.

符号の説明Explanation of symbols

６ 電力用スイッチング半導体素子、 ８ フリーホイルダイオード、 ２４ 第１の基板、 ２６ 第２の基板、 ２８ 第１のリードフレーム、 ３０ 第２のリードフレーム、 ３２ ヒートシンク、 ３８ 接続（用）突出端。

6 power switching semiconductor element, 8 free foil diode, 24 first substrate, 26 second substrate, 28 first lead frame, 30 second lead frame, 32 heat sink, 38 connection (for) projecting end.

Claims (16)

電力用スイッチング半導体素子と、該電力用スイッチング半導体素子と逆並列に接続されるフリーホイルダイオードとを備えた電力用半導体装置において、
第１の基板の表主面に形成された回路パターン上に前記電力用スイッチング半導体素子の裏面電極および前記フリーホイルダイオードの裏面電極とを接着し搭載すると共に、前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極と対向するように配設された第２の基板の前記対向主面に形成された回路パターンを、半田付けされる接続導体を介し前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極の夫々に接続したことを特徴とする電力用半導体装置。 In a power semiconductor device comprising a power switching semiconductor element and a free wheel diode connected in antiparallel with the power switching semiconductor element,
A back electrode of the power switching semiconductor element and a back electrode of the free wheel diode are bonded and mounted on a circuit pattern formed on the front main surface of the first substrate, and a front electrode of the power switching semiconductor element And a surface of the switching semiconductor element for power via a connection conductor to which a circuit pattern formed on the opposing main surface of the second substrate disposed so as to face the surface electrode of the free wheel diode is soldered A power semiconductor device connected to each of an electrode and a surface electrode of the freewheel diode. 電力用スイッチング半導体素子と、該電力用スイッチング半導体素子と逆並列に接続されるフリーホイルダイオードとを備えた電力用半導体装置において、
第１の基板の表主面に形成された回路パターン上に前記電力用スイッチング半導体素子の裏面電極および前記フリーホイルダイオードの裏面電極とを接着し搭載すると共に、前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極と対向するように配設された第２の基板の前記対向主面に形成された回路パターンを部分的に突出させ、その突出端を前記電力用スイッチング半導体素子の表面電極および前記フリーホイルダイオードの表面電極の夫々に半田付け接続したことを特徴とする電力用半導体装置。 In a power semiconductor device comprising a power switching semiconductor element and a free wheel diode connected in antiparallel with the power switching semiconductor element,
A back electrode of the power switching semiconductor element and a back electrode of the free wheel diode are bonded and mounted on a circuit pattern formed on the front main surface of the first substrate, and a front electrode of the power switching semiconductor element And a circuit pattern formed on the opposing main surface of the second substrate disposed so as to face the surface electrode of the free wheel diode is partially projected, and the protruding end of the power switching semiconductor element A power semiconductor device, wherein the surface electrode and the surface electrode of the free wheel diode are connected by soldering. 第２の基板の第１の基板と対向する対向主面の裏側に配設される裏側主面に前記電力用スイッチング半導体素子を駆動制御する制御用ＩＣを搭載したことを特徴とする請求項１または請求項２に記載の電力用半導体装置。   2. A control IC for driving and controlling the power switching semiconductor element is mounted on the back side main surface disposed on the back side of the opposing main surface facing the first substrate of the second substrate. Alternatively, the power semiconductor device according to claim 2. 少なくとも第１の基板がセラミック絶縁基板であり、該セラミック基板の裏面に複数に分割したヒートシンクを接着したことを特徴とする請求項１乃至請求項３のうちのいずれか一つに記載の電力用半導体装置。   The power substrate according to any one of claims 1 to 3, wherein at least the first substrate is a ceramic insulating substrate, and a plurality of divided heat sinks are bonded to the back surface of the ceramic substrate. Semiconductor device. 少なくとも第１の基板がセラミック絶縁基板であり、該セラミック基板の裏面にヒートシンク機能を持つ形状を形成した請求項１乃至請求項３のうちのいずれか一つに記載の電力用半導体装置。   The power semiconductor device according to any one of claims 1 to 3, wherein at least the first substrate is a ceramic insulating substrate, and a shape having a heat sink function is formed on a back surface of the ceramic substrate. 外部導出リードの一端を基板に半田付けする場合に、それら半田付けの全てを第１の基板の表主面に形成された回路パターンに行なうことを特徴とする請求項１乃至請求項４のうちのいずれか一つに記載の電力用半導体装置。   5. When soldering one end of an external lead to a board, all of the soldering is performed on a circuit pattern formed on the front main surface of the first board. The power semiconductor device according to any one of the above. 第１の基板と、第２の基板間に絶縁耐熱性充填材を充填したことを特徴とする請求項１乃至請求項６のうちのいずれか一つに記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein an insulating heat resistant filler is filled between the first substrate and the second substrate. 絶縁耐熱性充填材は熱硬化性樹脂を圧入したことを特徴とする請求項７記載の電力用半導体装置。   8. The power semiconductor device according to claim 7, wherein the insulating heat-resistant filler is press-fitted with a thermosetting resin. 絶縁耐熱性充填材はゲル状としたことを特徴とする請求項７記載の電力用半導体装置。 The power semiconductor device according to claim 7, wherein the insulating heat-resistant filler is in a gel form. 第１の基板と第２の基板の外周縁の近傍において、該外周縁に沿って紐状の第１の仕切り部材をコ字状をなすように配設して前記第１の基板と前記第２の基板とに接着し、前記コ字状の開口部からゲル状の耐熱性充填材を充填し、その後、前記開口部に配設され前記第１の基板および第２の基板に接着される第２の仕切り部材で前記絶縁耐熱性充填材を密閉したことを特徴とする請求項７記載の電力用半導体装置。   In the vicinity of the outer peripheries of the first substrate and the second substrate, a string-like first partition member is disposed along the outer perimeter so as to form a U-shape, and the first substrate and the first substrate Is bonded to the second substrate, filled with a gel-like heat-resistant filler from the U-shaped opening, and then disposed in the opening and bonded to the first substrate and the second substrate. The power semiconductor device according to claim 7, wherein the insulating heat-resistant filler is sealed with a second partition member. 接続導体は組立状態において可撓性を有すことを特徴とする請求項１または請求項３に記載の電力用半導体装置。   4. The power semiconductor device according to claim 1, wherein the connection conductor has flexibility in an assembled state. 電力用スイッチング半導体素子と、該電力用スイッチング半導体素子と逆並列に接続されるフリーホイルダイオードとを備えた電力用半導体装置において、
第１のリードフレームの表主面に前記電力用スイッチング半導体素子の裏面電極と、前記フリーホイルダイオードの裏面電極とを接合すると共に、前記電力用スイッチング半導体素子の表面電極と前記フリーホイルダイオードの表面電極とに対向する第２のリードフレームの対向主面の一部を突出させ、その突出端を前記電力用スイッチング半導体素子の表面電極と前記フリーホイルダイオードの表面電極とに対応接続したことを特徴とする電力用半導体装置。 In a power semiconductor device comprising a power switching semiconductor element and a free wheel diode connected in antiparallel with the power switching semiconductor element,
The back electrode of the power switching semiconductor element and the back electrode of the free foil diode are joined to the front main surface of the first lead frame, and the front electrode of the power switching semiconductor element and the surface of the free foil diode are joined. A portion of the opposing main surface of the second lead frame that faces the electrode is protruded, and the protruding end is connected to the surface electrode of the power switching semiconductor element and the surface electrode of the freewheel diode. A power semiconductor device. 電力用スイッチング半導体素子と、該電力用スイッチング半導体素子と逆並列に接続されるフリーホイルダイオードとを備えた電力用半導体装置において、
平板状の第１のリードフレームの表主面に前記電力用スイッチング半導体素子の裏面電極と、前記フリーホイルダイオードの裏面電極とを接合すると共に、前記電力用スイッチング半導体素子の表面電極と前記フリーホイルダイオードの表面電極とに対向する平板状の第２のリードフレームの対向主面の所定の位置に半田付けされる複数の接続導体を前記電力用スイッチング半導体素子の表面電極と前記フリーホイルダイオードの表面電極とに対応し半田付け接続したことを特徴とする電力用半導体装置。 In a power semiconductor device comprising a power switching semiconductor element and a free wheel diode connected in antiparallel with the power switching semiconductor element,
The back electrode of the power switching semiconductor element and the back electrode of the free wheel diode are joined to the front main surface of the flat first lead frame, and the front electrode and the free foil of the power switching semiconductor element are joined. A plurality of connecting conductors soldered at predetermined positions on the opposing main surface of the flat plate-like second lead frame facing the surface electrode of the diode are connected to the surface electrode of the power switching semiconductor element and the surface of the free foil diode. A power semiconductor device characterized by being soldered and connected to an electrode. 第２のリードフレームの第１のリードフレームと対向する対向主面の裏側に配設される裏側主面に前記電力用スイッチング半導体素子を駆動制御する制御用ＩＣを搭載したことを特徴とする請求項１２または請求項１３に記載の電力用半導体装置。   5. A control IC for driving and controlling the power switching semiconductor element is mounted on a back side main surface disposed on the back side of the opposing main surface facing the first lead frame of the second lead frame. Item 14. The power semiconductor device according to Item 12 or Item 13. 第２のリードフレームの代わりに、多層プリント基板、又はスルーホール基板を用い駆動制御する制御用ＩＣを搭載したことを特徴とする請求項１４に記載の電力用半導体装置。   15. The power semiconductor device according to claim 14, further comprising a control IC for driving and controlling using a multilayer printed board or a through-hole board instead of the second lead frame. 基板またはリードフレームを３枚以上とすることを特徴とする、請求項１乃至請求項１３のうちのいずれか一つに記載の電力用半導体装置。

The power semiconductor device according to any one of claims 1 to 13, wherein the number of substrates or lead frames is three or more.

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US20050146027A1 (en) 2005-07-07
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