JP2007019104A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2007019104A
JP2007019104A JP2005196644A JP2005196644A JP2007019104A JP 2007019104 A JP2007019104 A JP 2007019104A JP 2005196644 A JP2005196644 A JP 2005196644A JP 2005196644 A JP2005196644 A JP 2005196644A JP 2007019104 A JP2007019104 A JP 2007019104A
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resin
semiconductor device
manufacturing
layer
surface treatment
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JP4853609B2 (en
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Hiroshi Obara
浩志 小原
Nobuaki Hashimoto
伸晃 橋元
Tatsuhiko Asakawa
達彦 淺川
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To improve the adhesiveness of a conductive layer and to prevent migration. <P>SOLUTION: The manufacturing method of the semiconductor device comprises processes of: (a) forming a resin layer 20 above a semiconductor substrate 10 having an electrode pad 16 and a passivation film 18; (b) forming a resin projection 40 by curing the resin layer 20; (c) forming the conductive layer 50 which is electrically connected to the electrode pad 16 and passes over the resin projection 40. Before at least the process (b), a surface treatment is applied to at least a peripheral region 32 of the resin layer 20 to improve the wettability of the resin layer 20 with the resin material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

電気的接続信頼性の向上を図るため、樹脂突起上に導電層が形成された樹脂コアバンプを外部端子とする半導体装置が開発されている。これによれば、半導体基板に樹脂突起が形成された後に、電極パッドから樹脂突起上に至る導電層が形成される。一般的に、導電層を形成する工程では、電極パッド上の酸化層を除去するため、Ａｒ逆スパッタが行われる。しかし、Ａｒ逆スパッタを行うと、それにより樹脂突起の表面の炭化が進行し、その結果、樹脂の絶縁抵抗が低下し、マイグレーションが引き起こされる可能性がある。また、上述した構造の場合、導電層は立体的形状をなす樹脂突起上を通るように形成されるので、導電層の剥離又は断線の防止を図ることが要求される。
特開平２−２７２７３７号公報 In order to improve electrical connection reliability, a semiconductor device using a resin core bump in which a conductive layer is formed on a resin protrusion as an external terminal has been developed. According to this, after the resin protrusion is formed on the semiconductor substrate, a conductive layer extending from the electrode pad to the resin protrusion is formed. In general, in the step of forming a conductive layer, Ar reverse sputtering is performed to remove an oxide layer on the electrode pad. However, when Ar reverse sputtering is performed, the carbonization of the surface of the resin protrusion proceeds, and as a result, the insulation resistance of the resin decreases and migration may occur. Further, in the case of the structure described above, the conductive layer is formed so as to pass over the resin protrusion having a three-dimensional shape, so that it is required to prevent peeling or disconnection of the conductive layer.
JP-A-2-272737

本発明の目的は、導電層の密着性の向上及びマイグレーションの防止を図ることにある。   An object of the present invention is to improve adhesion of a conductive layer and prevent migration.

（１）本発明に係る半導体装置の製造方法は、
（ａ）電極パッド及びパッシベーション膜を有する半導体基板の上方に樹脂層を形成する工程と、
（ｂ）前記樹脂層をキュアすることにより樹脂突起を形成する工程と、
（ｃ）前記電極パッドと電気的に接続する導電層を、少なくとも前記樹脂突起の上方に形成する工程と、
を含み、
少なくとも前記（ｂ）工程前において、少なくとも前記樹脂層の周辺領域に対して、前記樹脂層の樹脂材料との濡れ性を向上させる表面処理を行う。 (1) A method of manufacturing a semiconductor device according to the present invention includes:
(A) forming a resin layer above a semiconductor substrate having an electrode pad and a passivation film;
(B) a step of forming a resin protrusion by curing the resin layer;
(C) forming a conductive layer electrically connected to the electrode pad at least above the resin protrusion;
Including
At least before the step (b), at least the peripheral region of the resin layer is subjected to a surface treatment for improving wettability with the resin material of the resin layer.

本発明によれば、キュア工程において樹脂が周辺領域になじむように流れ、その後、硬化収縮反応が起こり、立ち上がり（接触角）が緩やかな樹脂突起を形成することができる。これにより、導電層の剥離及び断線の防止を図り、その密着性の向上を図ることができる。   According to the present invention, in the curing process, the resin flows so as to be adapted to the peripheral region, and thereafter, a curing shrinkage reaction occurs, and a resin protrusion having a gentle rise (contact angle) can be formed. Thereby, peeling of a conductive layer and prevention of a disconnection can be aimed at, and the improvement of the adhesiveness can be aimed at.

なお、本発明において、特定のＡの上方にＢが設けられているとは、Ａ上に直接Ｂが設けられている場合と、Ａ上に他を介してＢが設けられている場合と、を含むものとする。このことは、以下の発明においても同様である。   In the present invention, B is provided above a specific A when B is provided directly on A, and when B is provided on A via the other, Shall be included. The same applies to the following inventions.

（２）この半導体装置の製造方法において、
前記表面処理の工程を、前記（ａ）工程後であって前記（ｂ）工程前に行ってもよい。 (2) In this method of manufacturing a semiconductor device,
The surface treatment step may be performed after the step (a) and before the step (b).

（３）この半導体装置の製造方法において、
前記表面処理の工程を、前記（ａ）工程前であって、前記樹脂層の形成領域及び周辺領域に対して行ってもよい。 (3) In this method of manufacturing a semiconductor device,
The surface treatment step may be performed on the resin layer formation region and the peripheral region before the step (a).

（４）この半導体装置の製造方法において、
前記表面処理の工程は、表面処理剤を設けることにより行ってもよい。 (4) In this method of manufacturing a semiconductor device,
The surface treatment step may be performed by providing a surface treatment agent.

（５）この半導体装置の製造方法において、
前記表面処理の工程は、光エネルギーを照射することにより行ってもよい。 (5) In this method of manufacturing a semiconductor device,
The surface treatment step may be performed by irradiating light energy.

（６）この半導体装置の製造方法において、
前記表面処理の工程は、前記光エネルギーの照射量を調整することにより、前記樹脂層から離れるに従って前記濡れ性を向上させる割合を小さくすることを含んでもよい。 (6) In this method of manufacturing a semiconductor device,
The surface treatment step may include reducing the ratio of improving the wettability as the distance from the resin layer increases by adjusting the amount of irradiation of the light energy.

これによれば、樹脂が周辺領域に際限なく流出するのを防止することができる。   According to this, it is possible to prevent the resin from flowing into the peripheral region without limit.

（７）この半導体装置の製造方法において、
前記（ａ）工程前において、前記樹脂層の形成領域に対して、前記樹脂層の樹脂材料との濡れ性を低下させる他の表面処理を行う工程をさらに含んでもよい。 (7) In this method of manufacturing a semiconductor device,
Before the step (a), the surface of the resin layer may be further subjected to a surface treatment for reducing wettability with the resin material of the resin layer.

これによれば、樹脂層の形成領域は濡れ性が低いので、大量の樹脂がパターニング領域内に留まり、少量の樹脂のみが外側の周辺領域に流出する。そのため、確実に樹脂突起を形成することができる。   According to this, since the resin layer formation region has low wettability, a large amount of resin remains in the patterning region, and only a small amount of resin flows out to the outer peripheral region. Therefore, the resin protrusion can be reliably formed.

（８）この半導体装置の製造方法において、
前記（ｃ）工程において、
前記導電層を形成する前に、Ａｒガスにより、前記電極パッドの表面から酸化膜を除去するとともに、前記樹脂突起の表面の炭化を進行させ、
前記導電層を形成した後に、前記導電層をマスクとして前記樹脂突起を部分的に除去してもよい。 (8) In this method of manufacturing a semiconductor device,
In the step (c),
Before forming the conductive layer, with the Ar gas, the oxide film is removed from the surface of the electrode pad, and carbonization of the surface of the resin protrusion is advanced,
After forming the conductive layer, the resin protrusion may be partially removed using the conductive layer as a mask.

これによれば、Ａｒガスにより樹脂突起の炭化が進行し、炭化層（又はプラズマ重合層）が形成されたとしても、樹脂突起の立ち上がりが緩やかに形成されているので、これにより樹脂突起を炭化層等を残すことなく容易に除去することができる。特に、炭化層等は、樹脂突起の根元部に残存しやすいが、本発明によれば樹脂突起の根元部に残存する炭化層等を容易に除去することができる。   According to this, even if the carbonization of the resin protrusion proceeds by Ar gas and the carbonized layer (or plasma polymerization layer) is formed, the rising of the resin protrusion is gently formed, so that the resin protrusion is carbonized. It can be easily removed without leaving a layer or the like. In particular, the carbonized layer or the like tends to remain at the base portion of the resin protrusion, but according to the present invention, the carbonized layer or the like remaining at the base portion of the resin protrusion can be easily removed.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（半導体装置の製造方法）
図１〜図１２は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。 (Method for manufacturing semiconductor device)
1 to 12 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

（１）まず、図１及び図２に示すように、半導体基板１０を用意する。半導体基板１０は、例えば半導体ウエハである（図１参照）。その場合、半導体基板１０は、半導体チップとなる複数のチップ領域１２を有し、それぞれのチップ領域１２の内部に集積回路１４が形成されている。すなわち、半導体基板１０を複数の半導体チップに分割する場合、個々の半導体チップが個々の集積回路１４を有することになる。集積回路１４は、少なくともトランジスタ等の能動素子を含む。チップ領域１２は、例えば平面視が矩形形状（例えば長方形）をなしている。それぞれのチップ領域１２には、複数の電極パッド（例えばアルミパッド）１６が形成されている。複数の電極パッド１６は、チップ領域１２の対向する２辺（例えば長辺側の２辺）又は４辺に沿って配列されていてもよい。その場合、各辺に１列又は複数列の電極パッド１６が配列されている。電極パッド１６がチップ領域１２の端部に配列している場合、集積回路１４は、複数の電極パッド１６により囲まれた中央部に形成されていてもよい。あるいは、電極パッド１６は、集積回路１４と平面視において重なる領域に形成されていてもよい。電極パッド１６は、内部配線（図示しない）により集積回路１４と電気的に接続されている。   (1) First, as shown in FIGS. 1 and 2, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 is, for example, a semiconductor wafer (see FIG. 1). In that case, the semiconductor substrate 10 has a plurality of chip regions 12 to be semiconductor chips, and an integrated circuit 14 is formed in each chip region 12. That is, when the semiconductor substrate 10 is divided into a plurality of semiconductor chips, each semiconductor chip has an individual integrated circuit 14. The integrated circuit 14 includes at least an active element such as a transistor. The chip region 12 has, for example, a rectangular shape (for example, a rectangle) in plan view. A plurality of electrode pads (for example, aluminum pads) 16 are formed in each chip region 12. The plurality of electrode pads 16 may be arranged along two opposing sides (for example, two sides on the long side) or four sides of the chip region 12. In that case, one or more rows of electrode pads 16 are arranged on each side. When the electrode pads 16 are arranged at the end portions of the chip region 12, the integrated circuit 14 may be formed in a central portion surrounded by the plurality of electrode pads 16. Alternatively, the electrode pad 16 may be formed in a region overlapping the integrated circuit 14 in plan view. The electrode pad 16 is electrically connected to the integrated circuit 14 by internal wiring (not shown).

半導体基板１０の表面（集積回路１４の形成面）には、パッシベーション膜（保護膜）１８が形成されている。パッシベーション膜１８は、無機系又は有機系のいずれから形成してもよく、例えばシリコン酸化膜、シリコン窒化膜の少なくとも１層により形成することができる。パッシベーション膜１８には、電極パッド１６を開口する開口部１９が形成されている。開口部１９により、電極パッド１６の少なくとも一部（例えば中央部のみ）が露出している。なお、電極パッド１６上には、多くの場合、酸化層１７が形成されている。酸化層１７は、例えば自然酸化によるものであり、電極パッド１６の表面を被覆している。   A passivation film (protective film) 18 is formed on the surface of the semiconductor substrate 10 (formation surface of the integrated circuit 14). The passivation film 18 may be formed of either an inorganic system or an organic system. For example, the passivation film 18 may be formed of at least one layer of a silicon oxide film and a silicon nitride film. In the passivation film 18, an opening 19 that opens the electrode pad 16 is formed. At least a part (for example, only the central part) of the electrode pad 16 is exposed by the opening 19. In many cases, an oxide layer 17 is formed on the electrode pad 16. The oxide layer 17 is formed by natural oxidation, for example, and covers the surface of the electrode pad 16.

（２）次に、図３〜図５に示すように、樹脂層２０を形成する。   (2) Next, as shown in FIGS. 3 to 5, a resin layer 20 is formed.

樹脂層２０は、半導体基板１０上（詳しくはパッシベーション膜１８上）であって、平面視において電極パッド１６と異なる領域に形成することができる。樹脂層２０の形成領域は限定されるものではないが、例えば所定の幅を有する直線状に形成することができる（図６参照）。その場合、半導体基板１０のチップ領域１２の境界（例えば長辺方向）に沿って（例えば平行に）延出するように形成することができる。   The resin layer 20 can be formed on the semiconductor substrate 10 (specifically, on the passivation film 18) and in a region different from the electrode pad 16 in plan view. Although the formation area of the resin layer 20 is not limited, it can be formed in a straight line having a predetermined width, for example (see FIG. 6). In this case, the semiconductor substrate 10 can be formed so as to extend (for example, in parallel) along the boundary (for example, the long side direction) of the chip region 12 of the semiconductor substrate 10.

具体的には、まず、図３に示すように、感光性の樹脂材料２０ａを例えばスピンコート法により半導体基板１０上に塗布する。その後、図４に示すように、開口部２４を有するマスク２２を半導体基板１０上に配置し、光エネルギー２６を照射して露光を行う。樹脂材料２０ａとして、光エネルギー２６の照射部分において現像液の溶解性が減少するネガ型を使用した場合には、マスク２２の開口部２４から露出する領域のみに樹脂を残すことができる。あるいは、逆に、樹脂材料２０ａとして、光エネルギー２６の照射部分において現像液の溶解性が増加するポジ型を使用した場合には、マスク２２により覆われた領域のみに樹脂を残すことができる。その後、現像工程を行うことにより、図５に示すように、樹脂層２０を所定形状にパターニングすることができる。   Specifically, first, as shown in FIG. 3, a photosensitive resin material 20a is applied onto the semiconductor substrate 10 by, for example, a spin coating method. Thereafter, as shown in FIG. 4, a mask 22 having an opening 24 is disposed on the semiconductor substrate 10, and exposure is performed by irradiating light energy 26. In the case where a negative type in which the solubility of the developer is reduced in the irradiated portion of the light energy 26 is used as the resin material 20a, the resin can be left only in the region exposed from the opening 24 of the mask 22. Or, conversely, when a positive type in which the solubility of the developer increases in the irradiated portion of the light energy 26 is used as the resin material 20a, the resin can be left only in the region covered with the mask 22. Thereafter, by performing a development process, the resin layer 20 can be patterned into a predetermined shape as shown in FIG.

ここで、樹脂層２０の樹脂材料の一例としては、ポリイミド樹脂、アクリル樹脂、フェノール樹脂、エポキシ樹脂、シリコーン樹脂、変性ポリイミド樹脂等の弾性樹脂材料が挙げられる。また、樹脂層２０は、例えばベンゼン環及びそれが縮合した環をもつ有機化合物の芳香族化合物であるポリイミド、ポリベンゾオキサゾル、ベンゾシクロブテン又はエポキシ等であることができる。   Here, examples of the resin material of the resin layer 20 include elastic resin materials such as polyimide resin, acrylic resin, phenol resin, epoxy resin, silicone resin, and modified polyimide resin. The resin layer 20 can be made of, for example, polyimide, polybenzoxazole, benzocyclobutene, epoxy, or the like, which is an aromatic compound of an organic compound having a benzene ring and a condensed ring thereof.

上述した樹脂層２０のパターニング工程の変形例として、例えば液滴吐出法（例えばインクジェット法）を適用してもよい。これによれば、樹脂材料を必要な領域のみに直接吐出することができる。特に、インクジェット法によれば、インクジェットプリンタ用に実用化された技術を応用することによって、高速かつインク（樹脂材料）を無駄なく経済的に設けることができる。   As a modification of the patterning process of the resin layer 20 described above, for example, a droplet discharge method (for example, an ink jet method) may be applied. According to this, the resin material can be directly discharged only to a necessary region. In particular, according to the ink jet method, ink (resin material) can be provided economically without waste by applying a technique that has been put to practical use for an ink jet printer.

（３）次に、図６及び図７に示すように、樹脂層２０をキュアする工程前に、樹脂層２０の周辺領域３２（パッシベーション膜１８）に対して表面処理を行う。なお、図７は、図６のＶII−ＶII線断面図である。   (3) Next, as shown in FIGS. 6 and 7, surface treatment is performed on the peripheral region 32 (passivation film 18) of the resin layer 20 before the step of curing the resin layer 20. 7 is a cross-sectional view taken along line VII-VII in FIG.

ここで、表面処理とは、下地（パッシベーション膜１８）に対する樹脂層２０の樹脂材料との濡れ性を向上させる処理をいい、言い換えれば、パッシベーション膜１８と樹脂層２０との親和性（親液性（樹脂なので親油性））を向上させる処理をいう。また、表面処理は、化学的処理又は物理的処理のいずれであってもよい。表面処理は、樹脂層２０の形成領域の周縁から外側に広がる周辺領域３２に対して行う。その場合、図６に示すように、樹脂層２０よりもわずかに外側に広がる周辺領域３２のみに表面処理を行うことができる。これにより、樹脂が際限なく外側に広がるのを確実に防止することができる。また、周辺領域３２は、樹脂層２０の略全周を囲むことができる。あるいは、露出するパッシベーション膜１８の略全面に表面処理を行ってもよい。   Here, the surface treatment refers to a treatment for improving the wettability of the resin layer 20 with the resin material of the resin layer 20 with respect to the base (passivation film 18). In other words, the affinity between the passivation film 18 and the resin layer 20 (lyophilicity). (Resin is lipophilic because it is a resin)). Further, the surface treatment may be either chemical treatment or physical treatment. The surface treatment is performed on the peripheral region 32 that spreads outward from the periphery of the region where the resin layer 20 is formed. In that case, as shown in FIG. 6, the surface treatment can be performed only on the peripheral region 32 that extends slightly outward from the resin layer 20. Thereby, it can prevent reliably that resin spreads outside infinitely. Further, the peripheral region 32 can surround substantially the entire circumference of the resin layer 20. Alternatively, surface treatment may be performed on substantially the entire surface of the exposed passivation film 18.

具体的には、樹脂層２０をパターニングして形成した後、樹脂層２０の周辺領域３２に表面処理剤３０を設ける。表面処理剤３０としては、カップリング剤（シラン系カップリング剤）を使用することができる。カップリング剤は、樹脂層２０の樹脂材料と反応することができる反応性官能基を有する。表面処理剤３０は、例えば液状にして塗布することができる。塗布方法は、ディスペンサ法、インクジェット法などを適用することができる。表面処理剤３０を設けることにより、その領域において、樹脂層２０の樹脂材料の濡れ性、定着性を向上させることができる。   Specifically, after the resin layer 20 is formed by patterning, the surface treatment agent 30 is provided in the peripheral region 32 of the resin layer 20. As the surface treating agent 30, a coupling agent (silane coupling agent) can be used. The coupling agent has a reactive functional group that can react with the resin material of the resin layer 20. The surface treatment agent 30 can be applied in a liquid state, for example. As a coating method, a dispenser method, an inkjet method, or the like can be applied. By providing the surface treating agent 30, the wettability and the fixability of the resin material of the resin layer 20 can be improved in that region.

（４）その後、図８に示すように、樹脂層２０をキュアすることにより樹脂突起４０を形成する。   (4) Thereafter, as shown in FIG. 8, the resin protrusions 40 are formed by curing the resin layer 20.

詳しくは、樹脂層２０を加熱することにより、樹脂を溶融させ、その後に硬化収縮させる。溶融時の樹脂は、上述した樹脂層２０の周辺領域３２に至るように広がる。本実施の形態では、周辺領域３２の濡れ性が高くなっているので、樹脂がパッシベーション膜１８になじむように流れ、その後、硬化収縮反応が起こり、立ち上がり（接触角）が緩やかな樹脂突起４０を形成することができる。キュア後の樹脂突起４０は、表面が曲面となっている。樹脂突起４０の断面は、例えば略半円形状をなしている。樹脂突起４０の立ち上がり角度（立ち上がり近傍の傾斜面の接線とパッシベーション膜１８の表面のなす角度）θは、少なくともθ＜９０°（最適にはθ≒０°）である。また、樹脂突起４０の立ち上がりは、外方向（斜め上方向）に凹状をなすように湾曲して形成されている。上述したように、樹脂層２０の略全周の周辺領域３２に表面処理を行うことにより、樹脂突起４０の略全周において立ち上がりを緩やかな傾斜面をもって形成することができる。これにより、後述の導電層５０を高い密着性をもってあらゆる方向から樹脂突起４０上に延出させることができる。   Specifically, by heating the resin layer 20, the resin is melted and then cured and contracted. The resin at the time of melting spreads to reach the peripheral region 32 of the resin layer 20 described above. In the present embodiment, since the wettability of the peripheral region 32 is high, the resin flows so as to become familiar with the passivation film 18, and thereafter, a curing shrinkage reaction occurs, and the resin protrusion 40 having a gentle rise (contact angle) is formed. Can be formed. The cured resin protrusion 40 has a curved surface. The cross section of the resin protrusion 40 has, for example, a substantially semicircular shape. The rising angle of the resin protrusion 40 (the angle formed by the tangent to the inclined surface near the rising edge and the surface of the passivation film 18) θ is at least θ <90 ° (optimally θ≈0 °). In addition, the rising of the resin protrusion 40 is formed to be curved outwardly (obliquely upward) so as to form a concave shape. As described above, by performing surface treatment on the peripheral region 32 on substantially the entire circumference of the resin layer 20, the rising can be formed with a gentle inclined surface on the substantially entire circumference of the resin protrusion 40. Thereby, the below-mentioned conductive layer 50 can be extended on the resin protrusion 40 from every direction with high adhesiveness.

（５）次に、図９〜図１１に示すように、電極パッド１６と電気的に接続し、かつ樹脂突起４０上を通る導電層５０を形成する。なお、図９は導電層の形成工程後の部分平面図であり、図１０は図９のＸ−Ｘ線断面図であり、図１１は図９のＸＩ−ＸＩ線断面図である。   (5) Next, as shown in FIGS. 9 to 11, a conductive layer 50 that is electrically connected to the electrode pad 16 and passes over the resin protrusion 40 is formed. 9 is a partial plan view after the conductive layer forming step, FIG. 10 is a cross-sectional view taken along the line XX of FIG. 9, and FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG.

まず、導電層５０を形成する前に、電極パッド１６上の酸化層１７を除去する。酸化層１７は、例えば、自然酸化により成長したものや、上述した樹脂のキュア工程により成長したものである。酸化層１７の除去方法として、例えばＡｒガスの逆スパッタを適用することができる。Ａｒガスの逆スパッタを半導体基板１０の全面に行うと、これにより、樹脂突起４０の表面の炭化が進行する。すなわち、樹脂突起４０の表面に、炭化層又は炭化層に至る前の層（例えばプラズマ重合層）が形成される。なお、本実施の形態は、このように炭化層等が形成されてしまう場合に特に有益である。   First, before forming the conductive layer 50, the oxide layer 17 on the electrode pad 16 is removed. The oxide layer 17 is, for example, grown by natural oxidation or grown by the above-described resin curing process. As a method for removing the oxide layer 17, for example, reverse sputtering of Ar gas can be applied. When reverse sputtering of Ar gas is performed on the entire surface of the semiconductor substrate 10, carbonization of the surface of the resin protrusion 40 proceeds. That is, a carbonized layer or a layer before reaching the carbonized layer (for example, a plasma polymerization layer) is formed on the surface of the resin protrusion 40. This embodiment is particularly useful when a carbonized layer or the like is formed in this way.

導電層５０は、スパッタ法又は蒸着法により導電箔を成膜し、その後、導電箔をパターニングすることにより形成することができる。導電層５０は、例えば、下地となる第１の層（例えばＴｉＷ層）５２と、その上の第２の層（例えばＡｕ層）５４とからなる複数層により形成することができる。その場合、導電箔を第１及び第２の層５２，５４により形成し、レジストをマスクとしてドライエッチングにより第２の層５４をパターニングし、パターニング後の第２の層５４をマスクとして第１の層５２をパターニングしてもよい。下地となる第１の層５２は、金属拡散防止、密着性向上又はメッキ層として利用することができる。変形例として、下地となる第１の層５２をスパッタ法又は蒸着法により形成し、その上の第２の層５４を無電解メッキ又は電気メッキにより形成することもできる。これにより、第２の層５４を容易に厚く形成することができる。あるいは、導電層５０は、単一層（例えばＡｕ層）により形成することもできる。なお、導電層５０の材質は上述に限られず、例えば、Ｃｕ，Ｎｉ，Ｐｄ，Ａｌ，Ｃｒ等を使用することができる。   The conductive layer 50 can be formed by forming a conductive foil by sputtering or vapor deposition and then patterning the conductive foil. The conductive layer 50 can be formed of, for example, a plurality of layers including a first layer (for example, a TiW layer) 52 serving as a base and a second layer (for example, an Au layer) 54 thereon. In that case, a conductive foil is formed by the first and second layers 52 and 54, the second layer 54 is patterned by dry etching using the resist as a mask, and the first layer is patterned using the patterned second layer 54 as a mask. Layer 52 may be patterned. The first layer 52 serving as a base can be used as a metal diffusion prevention, adhesion improvement or plating layer. As a modification, the first layer 52 as a base can be formed by sputtering or vapor deposition, and the second layer 54 thereon can be formed by electroless plating or electroplating. Thereby, the second layer 54 can be easily formed thick. Alternatively, the conductive layer 50 can be formed of a single layer (for example, an Au layer). The material of the conductive layer 50 is not limited to the above, and for example, Cu, Ni, Pd, Al, Cr, or the like can be used.

導電層５０は、電極パッド１６と樹脂突起４０の間を電気的に接続する配線層である。導電層５０は、少なくとも、電極パッド１６上、パッシベーション膜１８上、及び樹脂突起４０上を通るように形成する。本実施の形態では、樹脂突起４０の立ち上がりが緩やかに形成されているので、導電層５０の密着性の向上を図ることができる。そのため、導電層５０の剥離及び断線の防止を図ることができる。図１０に示す例では、導電層５０を、樹脂突起４０上を超えて、電極パッド１６とは反対側のパッシベーション膜１８上に至るように形成する。言い換えれば、導電層５０を、樹脂突起４０から複数方向（例えば電極パッド１６側及びそれとは反対側）に分岐してパッシベーション膜１８上に至るように形成する。これにより、導電層５０の下地に対するさらなる密着性の向上を図ることができる。なお、導電層５０は、樹脂突起４０上に形成されている電気的接続部５６を有する。   The conductive layer 50 is a wiring layer that electrically connects the electrode pad 16 and the resin protrusion 40. The conductive layer 50 is formed so as to pass at least on the electrode pad 16, the passivation film 18, and the resin protrusion 40. In the present embodiment, since the rising of the resin protrusion 40 is gently formed, the adhesion of the conductive layer 50 can be improved. Therefore, peeling of the conductive layer 50 and disconnection can be prevented. In the example shown in FIG. 10, the conductive layer 50 is formed so as to extend over the resin protrusion 40 and onto the passivation film 18 on the side opposite to the electrode pad 16. In other words, the conductive layer 50 is formed so as to branch from the resin protrusion 40 in a plurality of directions (for example, the electrode pad 16 side and the opposite side thereof) and reach the passivation film 18. Thereby, the further adhesive improvement with respect to the foundation | substrate of the conductive layer 50 can be aimed at. The conductive layer 50 has an electrical connection portion 56 formed on the resin protrusion 40.

図１１及び図１２に示すように、導電層５０を形成した後に、導電層５０をマスクとして樹脂突起４０を部分的に除去してもよい。これにより、例えば実装時における接着剤の排出性の向上を図ることができる。例えば、樹脂突起４０が所定の幅を有する直線状に形成され、樹脂突起４０の長さ方向に複数の電気的接続部５６が所定間隔をあけて配列されている場合、隣接する電気的接続部５６同士の間から露出する部分を異方性のエッチャント（例えばＯ２プラズマ）５８によりエッチングして除去する。その場合、パッシベーション膜１８の損傷を防止するため、隣接する電気的接続部５６同士の間に樹脂の残渣４４を設けるようにエッチングすることができる。本実施の形態によれば、樹脂突起４０の立ち上がりが緩やかになっているため、樹脂突起４０の根元部に異方性のエッチャントが進入しやすくなり、これにより、樹脂突起４０の根元部に形成される炭化層等を従来に増して容易に除去することができる。したがって、炭化層等に起因するマイグレーションを防止し、信頼性の向上を図ることができる。 As shown in FIGS. 11 and 12, after forming the conductive layer 50, the resin protrusions 40 may be partially removed using the conductive layer 50 as a mask. Thereby, for example, it is possible to improve the dischargeability of the adhesive during mounting. For example, when the resin protrusions 40 are formed in a straight line having a predetermined width and a plurality of electrical connection portions 56 are arranged at predetermined intervals in the length direction of the resin protrusions 40, adjacent electrical connection portions The portion exposed between 56 is etched and removed by an anisotropic etchant (for example, O 2 plasma) 58. In that case, in order to prevent damage to the passivation film 18, etching can be performed so as to provide a resin residue 44 between the adjacent electrical connection portions 56. According to the present embodiment, since the rise of the resin protrusion 40 is gentle, an anisotropic etchant easily enters the base portion of the resin protrusion 40, thereby forming the base portion of the resin protrusion 40. The carbonized layer and the like can be easily removed as compared with the conventional case. Therefore, migration due to the carbonized layer or the like can be prevented, and reliability can be improved.

こうして、複数の樹脂コアバンプ６０を有する半導体装置１００を製造することができる。樹脂コアバンプ６０は、半導体基板１０の一方の面（集積回路１４の形成面）に形成され、樹脂突起４２と、樹脂突起４２上に形成された電気的接続部５６と、を含む。これによれば、樹脂突起４２がコアとなりそれ自体が弾力性を有するので、実装時における応力緩和機能や電気的接続信頼性の向上を図ることができる。なお、本実施の形態に係る半導体装置は、上述した半導体装置の製造方法の内容から導き出せる構成を有する。   In this way, the semiconductor device 100 having a plurality of resin core bumps 60 can be manufactured. The resin core bump 60 is formed on one surface of the semiconductor substrate 10 (the surface on which the integrated circuit 14 is formed), and includes a resin protrusion 42 and an electrical connection portion 56 formed on the resin protrusion 42. According to this, since the resin protrusion 42 becomes a core and itself has elasticity, it is possible to improve the stress relaxation function and electrical connection reliability at the time of mounting. Note that the semiconductor device according to the present embodiment has a configuration that can be derived from the contents of the above-described method for manufacturing a semiconductor device.

（電子機器）
図１３は、本発明の実施の形態に係る電子デバイスを示す図である。電子デバイス（例えば表示デバイス）１０００は、半導体装置１００を含む。図１３に示す例では、電子デバイス１０００は、半導体装置１００と、樹脂フィルム等からなる第１の基板２００と、ガラス等からなる第２の基板３００と、を含む。半導体装置１００は、例えば第１の基板２００にフェースダウン実装され、詳しくは、第１の基板２００に形成された配線パターンと、半導体装置１００の樹脂コアバンプ６０とが電気的に接続されている。半導体装置１００と第１の基板２００の間には、図示しない絶縁性接着剤（例えばＮＣＦ(Non Conductive Film)又はＮＣＰ(Non Conductive Paste)）が設けられている。あるいは、第１の基板２００を省略して、半導体装置１００を第２の基板３００にフェースダウン実装することもできる。電子デバイス１０００の例としては、例えば、液晶ディスプレイ、プラズマディスプレイ、ＥＬ（Electrical Luminescence）ディスプレイなどが挙げられる。なお、図１４には本発明の実施の形態に係る電子機器の一例としてノート型パーソナルコンピュータが示され、図１５には携帯電話が示されている。 (Electronics)
FIG. 13 is a diagram showing an electronic device according to an embodiment of the present invention. The electronic device (for example, display device) 1000 includes the semiconductor device 100. In the example illustrated in FIG. 13, the electronic device 1000 includes a semiconductor device 100, a first substrate 200 made of a resin film or the like, and a second substrate 300 made of glass or the like. The semiconductor device 100 is, for example, face-down mounted on the first substrate 200. Specifically, the wiring pattern formed on the first substrate 200 and the resin core bump 60 of the semiconductor device 100 are electrically connected. An insulating adhesive (not shown) (for example, NCF (Non Conductive Film) or NCP (Non Conductive Paste)) is provided between the semiconductor device 100 and the first substrate 200. Alternatively, the first substrate 200 can be omitted and the semiconductor device 100 can be mounted face down on the second substrate 300. Examples of the electronic device 1000 include a liquid crystal display, a plasma display, and an EL (Electrical Luminescence) display. Note that FIG. 14 shows a notebook personal computer as an example of the electronic apparatus according to the embodiment of the present invention, and FIG. 15 shows a mobile phone.

（変形例）
上述した例では、表面処理の工程を樹脂層２０をパターニングした後に行うが、変形例として、表面処理の工程を樹脂層２０の形成工程前に行うことも可能である。その場合、樹脂材料２０ａを半導体基板１０上に塗布する前に、樹脂層２０の形成領域及び周辺領域３２に対して表面処理の工程を行うことができる。あるいは、樹脂層２０の形成領域を避けて、その周辺領域３２に対して表面処理の工程を行ってもよい。 (Modification)
In the example described above, the surface treatment process is performed after patterning the resin layer 20. However, as a modification, the surface treatment process may be performed before the resin layer 20 formation process. In that case, a surface treatment process can be performed on the formation region of the resin layer 20 and the peripheral region 32 before applying the resin material 20a onto the semiconductor substrate 10. Alternatively, the surface treatment step may be performed on the peripheral region 32 while avoiding the region where the resin layer 20 is formed.

また、他の変形例として、樹脂層２０の形成工程前にその形成領域（のみ）に対して、樹脂層２０の樹脂材料との濡れ性を低下させる他の表面処理（化学的処理・物理的処理を含む）を行ってもよい。例えば、樹脂層２０の形成領域（パッシベーション膜１８）に対して撥液処理（樹脂は弾かない程度の撥液処理）を行ってもよい。これによれば、パターニングされた樹脂層２０の下地は濡れ性が低いので、大量の樹脂がパターニング領域内に留まり、少量の樹脂のみが外側の周辺領域３２に流出する。そのため、確実に樹脂突起４０を形成することができる。   As another modification, other surface treatment (chemical treatment / physical treatment) that reduces the wettability of the resin layer 20 with the resin material on the formation region (only) before the formation step of the resin layer 20 is performed. Processing). For example, a liquid repellent treatment (a liquid repellent treatment that does not repel the resin) may be performed on the formation region of the resin layer 20 (passivation film 18). According to this, since the base of the patterned resin layer 20 has low wettability, a large amount of resin stays in the patterning region, and only a small amount of resin flows out to the outer peripheral region 32. Therefore, the resin protrusion 40 can be reliably formed.

図１６及び図１７は、本発明の実施の形態の他の変形例に係る半導体装置の製造方法を説明する図である。本変形例では、樹脂突起１４０の形態が上述と異なる。   16 and 17 are diagrams illustrating a method for manufacturing a semiconductor device according to another modification of the embodiment of the present invention. In this modification, the form of the resin protrusion 140 is different from that described above.

樹脂層１２０の形成工程の詳細は上述した内容を適用することができる。ただし、本変形例では、導電層５０の形成工程前において、それぞれの電極パッド１６に対していずれかの樹脂突起１４０が対となるように、互いに離間させて複数の樹脂突起１４０を形成する。そのために、樹脂層１２０は、例えば個々が円柱状をなす複数にパターニングして形成することができる。その場合、表面処理を施す周辺領域１３２は、例えば個々の樹脂層１２０の周囲の領域であってもよいし、複数の樹脂層１２０の周囲の一体的な領域であってもよい。上述した表面処理の工程として表面処理剤３０を設けた後、キュア工程により個々の樹脂層１２０を略半球状に形成することができる。これにより、樹脂突起１４０を立ち上がりが緩やかな傾斜面をもって形成することができる。   The details described above can be applied to the details of the resin layer 120 forming process. However, in this modification, before the step of forming the conductive layer 50, the plurality of resin protrusions 140 are formed so as to be spaced apart from each other so that one of the resin protrusions 140 is paired with each electrode pad 16. Therefore, the resin layer 120 can be formed by patterning, for example, into a plurality of columns each having a cylindrical shape. In that case, the peripheral region 132 on which the surface treatment is performed may be, for example, a region around each resin layer 120 or may be an integrated region around the plurality of resin layers 120. After the surface treatment agent 30 is provided as the surface treatment step described above, the individual resin layers 120 can be formed into a substantially hemispherical shape by a curing step. Thereby, the resin protrusion 140 can be formed with an inclined surface with a gentle rise.

導電層５０は、例えば、いずれか１つの電極パッド１６といずれか１つの樹脂突起１４０の間を電気的に接続する。その場合、導電層５０は、１つの樹脂突起１４０の一部のみを覆うように形成してもよいし、その全部を覆うように形成してもよい。前者の場合、樹脂突起１４０の一部が露出することにより、外力が開放されるので、実装時の電気的接続部５６（導電層５０）のクラックを防止することができる。   The conductive layer 50 electrically connects, for example, any one electrode pad 16 and any one resin protrusion 140. In that case, the conductive layer 50 may be formed so as to cover only a part of one resin protrusion 140 or may be formed so as to cover the whole. In the former case, since the external force is released by exposing a part of the resin protrusion 140, it is possible to prevent cracks in the electrical connection portion 56 (conductive layer 50) during mounting.

なお、本変形例においては、樹脂突起１４０をあらかじめ個々に分離して形成するので、上述した例のように、導電層５０を形成した後の樹脂突起の部分的な除去工程を省略することができる。   In this modification, since the resin protrusions 140 are separately formed in advance, the step of partially removing the resin protrusions after forming the conductive layer 50 may be omitted as in the above-described example. it can.

図１８は、本発明の実施の形態の他の変形例に係る半導体装置の製造方法を説明する図である。本変形例では、表面処理の具体的方法が上述と異なる。   FIG. 18 is a diagram illustrating a method for manufacturing a semiconductor device according to another modification of the embodiment of the present invention. In this modification, the specific method of surface treatment is different from the above.

表面処理の具体的方法として、光エネルギー１７０を照射することにより、半導体基板１０（詳しくはパッシベーション膜１８）の表面を改質させる。光エネルギー１７０としては、例えば紫外線（ＵＶ）エネルギーを使用することができる。光エネルギー１７０の波長、照射量等は、表面処理後の樹脂材料の濡れ性の程度を考慮して適宜調整することができる。   As a specific method of the surface treatment, the surface of the semiconductor substrate 10 (specifically, the passivation film 18) is modified by irradiating light energy 170. As the light energy 170, for example, ultraviolet (UV) energy can be used. The wavelength, irradiation amount, and the like of the light energy 170 can be appropriately adjusted in consideration of the degree of wettability of the resin material after the surface treatment.

例えば、光エネルギー１７０の照射工程は、樹脂層の形成工程前に行うことができる。その場合、光エネルギー１７０は半導体基板１０の全面に照射してもよいし、図示しないマスクを介して所定領域（例えば上述した樹脂層の周辺領域）のみに照射してもよい。また、光エネルギー１７０の照射量を調整することにより、パターニング後の樹脂層から離れるに従って濡れ性を向上させる割合を小さくしてもよい。すなわち、パッシベーション膜１８の表面の濡れ性の度合いを段階的に変化させてもよい。具体的には、光の透過率が変更可能であるグレイマスクを介して光エネルギー１７０を照射すればよい。これによれば、樹脂が周辺領域に際限なく流出するのを防止することができる。なお、上述とは別に光エネルギー１７０の照射工程を樹脂層の形成工程後（キュア工程前）に行うことも可能である。   For example, the irradiation process of the light energy 170 can be performed before the resin layer formation process. In that case, the light energy 170 may be applied to the entire surface of the semiconductor substrate 10 or may be applied only to a predetermined region (for example, the peripheral region of the resin layer described above) through a mask (not shown). Further, by adjusting the irradiation amount of the light energy 170, the ratio of improving the wettability as the distance from the patterned resin layer increases may be reduced. That is, the degree of wettability of the surface of the passivation film 18 may be changed stepwise. Specifically, the light energy 170 may be irradiated through a gray mask whose light transmittance can be changed. According to this, it is possible to prevent the resin from flowing into the peripheral region without limit. In addition, the irradiation process of the light energy 170 can be performed after the resin layer formation process (before the curing process) separately from the above.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 図６のＶＩＩ−ＶＩＩ線断面図である。It is the VII-VII sectional view taken on the line of FIG. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 図９のＸ−Ｘ線断面図である。FIG. 10 is a sectional view taken along line XX in FIG. 9. 図９のＸＩ−ＸＩ線断面図である。It is the XI-XI sectional view taken on the line of FIG. 本実施の形態に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on this Embodiment. 本実施の形態に係る電子デバイスを示す図である。It is a figure which shows the electronic device which concerns on this Embodiment. 本実施の形態に係る電子機器を示す図である。It is a figure which shows the electronic device which concerns on this Embodiment. 本実施の形態に係る電子機器を示す図である。It is a figure which shows the electronic device which concerns on this Embodiment. 本実施の形態の変形例に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on the modification of this Embodiment. 本実施の形態の変形例に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on the modification of this Embodiment. 本実施の形態の変形例に係る半導体装置の製造方法を説明する図である。に係る半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device which concerns on the modification of this Embodiment. It is a figure explaining the manufacturing method of the semiconductor device concerning.

符号の説明Explanation of symbols

１０…半導体基板 １６…電極パッド １８…パッシベーション膜
２０…樹脂層 ３０…表面処理剤 ３２…周辺領域
４０，４２…樹脂突起 ５０…導電層 １００…半導体装置
１２０…樹脂層 １３２…周辺領域 １４０…樹脂突起 １７０…光エネルギー DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 16 ... Electrode pad 18 ... Passivation film 20 ... Resin layer 30 ... Surface treatment agent 32 ... Peripheral area | region 40,42 ... Resin protrusion 50 ... Conductive layer 100 ... Semiconductor device 120 ... Resin layer 132 ... Peripheral area 140 ... Resin Protrusion 170 ... Light energy

Claims (8)

（ａ）電極パッド及びパッシベーション膜を有する半導体基板の上方に樹脂層を形成する工程と、
（ｂ）前記樹脂層をキュアすることにより樹脂突起を形成する工程と、
（ｃ）前記電極パッドと電気的に接続する導電層を、少なくとも前記樹脂突起の上方に形成する工程と、
を含み、
少なくとも前記（ｂ）工程前において、少なくとも前記樹脂層の周辺領域に対して、前記樹脂層の樹脂材料との濡れ性を向上させる表面処理を行う半導体装置の製造方法。 (A) forming a resin layer above a semiconductor substrate having an electrode pad and a passivation film;
(B) a step of forming a resin protrusion by curing the resin layer;
(C) forming a conductive layer electrically connected to the electrode pad at least above the resin protrusion;
Including
A method for manufacturing a semiconductor device, wherein at least before the step (b), at least a peripheral region of the resin layer is subjected to a surface treatment for improving wettability with the resin material of the resin layer. 請求項１記載の半導体装置の製造方法において、
前記表面処理の工程を、前記（ａ）工程後であって前記（ｂ）工程前に行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the surface treatment step is performed after the step (a) and before the step (b). 請求項１記載の半導体装置の製造方法において、
前記表面処理の工程を、前記（ａ）工程前であって、前記樹脂層の形成領域及び周辺領域に対して行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the surface treatment step is performed before the step (a) and on the formation region and the peripheral region of the resin layer. 請求項１から請求項３のいずれかに記載の半導体装置の製造方法において、
前記表面処理の工程は、表面処理剤を設けることにより行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-3,
The surface treatment step is a method for manufacturing a semiconductor device by providing a surface treatment agent. 請求項１から請求項３のいずれかに記載の半導体装置の製造方法において、
前記表面処理の工程は、光エネルギーを照射することにより行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-3,
The surface treatment step is a method for manufacturing a semiconductor device performed by irradiating light energy. 請求項５記載の半導体装置の製造方法において、
前記表面処理の工程は、前記光エネルギーの照射量を調整することにより、前記樹脂層から離れるに従って前記濡れ性を向上させる割合を小さくすることを含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the surface treatment step includes reducing the rate of improving the wettability as the distance from the resin layer is adjusted by adjusting an irradiation amount of the light energy. 請求項１から請求項６のいずれかに記載の半導体装置の製造方法において、
前記（ａ）工程前において、前記樹脂層の形成領域に対して、前記樹脂層の樹脂材料との濡れ性を低下させる他の表面処理を行う工程をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-6,
A method of manufacturing a semiconductor device, further comprising a step of performing another surface treatment for reducing wettability with the resin material of the resin layer on the resin layer forming region before the step (a). 請求項１から請求項７のいずれかに記載の半導体装置の製造方法において、
前記（ｃ）工程において、
前記導電層を形成する前に、Ａｒガスにより、前記電極パッドの表面から酸化膜を除去するとともに、前記樹脂突起の表面の炭化を進行させ、
前記導電層を形成した後に、前記導電層をマスクとして前記樹脂突起を部分的に除去する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-7,
In the step (c),
Before forming the conductive layer, with the Ar gas, the oxide film is removed from the surface of the electrode pad, and carbonization of the surface of the resin protrusion is advanced,
A method of manufacturing a semiconductor device, wherein after forming the conductive layer, the resin protrusion is partially removed using the conductive layer as a mask.
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JP2011210939A (en) * 2010-03-30 2011-10-20 Casio Computer Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP7470836B2 (en) 2022-04-07 2024-04-18 ▲き▼邦科技股▲分▼有限公司 Thin Film Flip Chip Package

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JP2005101419A (en) * 2003-09-26 2005-04-14 Seiko Epson Corp Method and apparatus for manufacturing bump structure
JP2006351873A (en) * 2005-06-16 2006-12-28 Seiko Epson Corp Manufacturing method of semiconductor device
JP2007012678A (en) * 2005-06-28 2007-01-18 Seiko Epson Corp Method of manufacturing semiconductor device

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JPH0945771A (en) * 1995-07-31 1997-02-14 Sanyo Electric Co Ltd Manufacture of semiconductor integrated circuit
JP2005101419A (en) * 2003-09-26 2005-04-14 Seiko Epson Corp Method and apparatus for manufacturing bump structure
JP2006351873A (en) * 2005-06-16 2006-12-28 Seiko Epson Corp Manufacturing method of semiconductor device
JP2007012678A (en) * 2005-06-28 2007-01-18 Seiko Epson Corp Method of manufacturing semiconductor device

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Publication number Priority date Publication date Assignee Title
JP2011210939A (en) * 2010-03-30 2011-10-20 Casio Computer Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP7470836B2 (en) 2022-04-07 2024-04-18 ▲き▼邦科技股▲分▼有限公司 Thin Film Flip Chip Package

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