JP2007012786A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007012786A
JP2007012786A JP2005190048A JP2005190048A JP2007012786A JP 2007012786 A JP2007012786 A JP 2007012786A JP 2005190048 A JP2005190048 A JP 2005190048A JP 2005190048 A JP2005190048 A JP 2005190048A JP 2007012786 A JP2007012786 A JP 2007012786A
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semiconductor
semiconductor device
lifetime
trenches
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Tetsuya Takahashi
哲也 高橋
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Priority to PCT/JP2006/304629 priority patent/WO2007000838A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing recovery time (reverse recovery time) without increasing operation resistance upon operation of an element. <P>SOLUTION: The semiconductor device comprises first and second trenches 103, 104 formed to face each other on a first conductivity type semiconductor substrate 100 via a first conductivity type first semiconductor region 102 formed on the semiconductor substrate, a gate insulating film 105 formed on the side surfaces of the first and second trenches, a gate electrode 106 formed inside the first and second trenches, a second conductivity type second semiconductor region 107 formed to make contact with the first semiconductor region, a first conductivity type third semiconductor region 108 in contact with the second semiconductor region, and further a life time control region 110 formed in the first semiconductor region between the first and second trenches facing each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、チャネル部分をトレンチ構造の側壁に形成した絶縁ゲート型電界効果トランジスタ等の半導体装置に関する。   The present invention relates to a semiconductor device such as an insulated gate field effect transistor having a channel portion formed on a sidewall of a trench structure.

側壁にゲート絶縁膜を形成したトレンチの内部に、ポリシリコン等から成る導体膜を埋設したゲート構造、いわゆるトレンチゲートを有する絶縁ゲート型電界効果トランジスタは、例えば特許文献１に記載されている。
特許文献１に記載の絶縁ゲート型電界効果トランジスタは、図５に示すように、高濃度基板３０１と、高濃度基板３０１の上に形成された低濃度エピタキシャル成長層３０２と、低濃度エピタキシャル成長層３０２内に形成されたソース拡散領域３０４及びチャネル拡散領域（ベース領域）３０６とを有する半導体基板３００と、この半導体基板３００の一方の主面に形成されたソース電極３０７及びゲート電極３０８と、半導体基板３００の他方の主面に形成されたドレイン電極３０９とを備えている。 For example, Patent Document 1 discloses an insulated gate field effect transistor having a gate structure in which a conductor film made of polysilicon or the like is embedded in a trench having a gate insulating film formed on a side wall, that is, a so-called trench gate.
As shown in FIG. 5, the insulated gate field effect transistor described in Patent Document 1 includes a high concentration substrate 301, a low concentration epitaxial growth layer 302 formed on the high concentration substrate 301, and a low concentration epitaxial growth layer 302. A semiconductor substrate 300 having a source diffusion region 304 and a channel diffusion region (base region) 306 formed on the semiconductor substrate 300; a source electrode 307 and a gate electrode 308 formed on one main surface of the semiconductor substrate 300; And a drain electrode 309 formed on the other main surface.

半導体基板の一方の主面にはトレンチ（溝部）３１０、３１１が設けられており、トレンチ３１０、３１１の側壁にはゲート絶縁膜として機能するシリコン酸化膜３１３が形成されている。また、トレンチ３１０、３１１の内部には例えば、多結晶シリコン（ポリシリコン）から成る導体膜（ゲート電極）３１２が埋設されており、トレンチゲートが形成されている。
ゲート電極に閾値電圧以上の電位を印加すると、トレンチ３１０、３１１の側壁に沿って、すなわち、ゲート絶縁膜３１３に沿って、ソース拡散領域３０４から低濃度エピタキシャル成長層３０２に向かってベース領域３０６に縦方向に延伸するチャネルが生成される。この結果、ソース拡散領域３０４から低濃度エピタキシャル成長層３０２にチャネルを通じてキャリア（電子）が注入され、デバイスの縦方向に電流が流れる。
特開平１１−１７７０８６号公報 Trenches (grooves) 310 and 311 are provided on one main surface of the semiconductor substrate, and a silicon oxide film 313 functioning as a gate insulating film is formed on the side walls of the trenches 310 and 311. In addition, a conductor film (gate electrode) 312 made of, for example, polycrystalline silicon (polysilicon) is buried in the trenches 310 and 311 to form a trench gate.
When a potential equal to or higher than the threshold voltage is applied to the gate electrode, the base region 306 is vertically extended from the source diffusion region 304 toward the low concentration epitaxial growth layer 302 along the sidewalls of the trenches 310 and 311, that is, along the gate insulating film 313. A channel extending in the direction is generated. As a result, carriers (electrons) are injected from the source diffusion region 304 into the low-concentration epitaxial growth layer 302 through the channel, and a current flows in the vertical direction of the device.
JP-A-11-177086

ところで、この種の半導体装置において、ベース領域と低濃度エピタキシャル成長層との界面に形成されるＰＮ接合を利用して、これをダイオード素子とする場合がある。図６は、このような内蔵ダイオード４０１を備えた図５のＭＯＳＦＥＴ４００の等価回路を示すものである。
図示のように、ソース電極とドレイン電極との間に、ソース電極側をアノード、ドレイン電極側をカソードとするＰＮ接合ダイオードから成るダイオード４０１がＭＯＳＦＥＴ４００と一体的に形成されている。 By the way, in this type of semiconductor device, a PN junction formed at the interface between the base region and the low concentration epitaxial growth layer may be used to form a diode element. FIG. 6 shows an equivalent circuit of the MOSFET 400 of FIG. 5 having such a built-in diode 401.
As shown in the figure, a diode 401 composed of a PN junction diode having a source electrode side as an anode and a drain electrode side as a cathode is formed integrally with a MOSFET 400 between a source electrode and a drain electrode.

ここで、ＭＯＳＦＥＴ４００に内蔵されたダイオード４０１のリカバリータイム（逆回復時間）を短くするためには、電子線照射や重金属拡散等のライフタイム制御を行えば良い。しかし、単に、半導体基板の全面に一様に電子線照射や重金属拡散を行ったのでは、リカバリータイムを短くすることはできるが、オン抵抗、即ち素子（ＭＯＳＦＥＴ）動作時の動作抵抗が増加してしまうという問題がある。
このような問題は、高濃度基板３０１を反対導電型の半導体基板に置き換えた、周知の絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）等でも同様に生じる。 Here, in order to shorten the recovery time (reverse recovery time) of the diode 401 incorporated in the MOSFET 400, lifetime control such as electron beam irradiation or heavy metal diffusion may be performed. However, simply performing electron beam irradiation or heavy metal diffusion over the entire surface of the semiconductor substrate can reduce the recovery time, but increases the on-resistance, that is, the operating resistance during device (MOSFET) operation. There is a problem that it ends up.
Such a problem also occurs in a well-known insulated gate bipolar transistor (IGBT) or the like in which the high-concentration substrate 301 is replaced with a semiconductor substrate of opposite conductivity type.

本発明は、このような事情に鑑みてなされたものであり、素子動作時の動作抵抗を増加させることなく、内蔵ダイオードのリカバリータイム（逆回復時間）を短縮することができる半導体装置を提供することを目的とする。   The present invention has been made in view of such circumstances, and provides a semiconductor device capable of shortening the recovery time (reverse recovery time) of a built-in diode without increasing the operating resistance during device operation. For the purpose.

上記目的を達成するために請求項１に記載の発明は、半導体基板上に形成されたトレンチの側壁にチャネルが形成される絶縁ゲート構造を有する半導体装置において、隣り合うトレンチの側壁間にキャリアのライフタイムが他の領域におけるキャリアのライフタイムより比較して小さくしたライフタイム制御領域を形成したことを特徴とする。   To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device having an insulated gate structure in which a channel is formed on a sidewall of a trench formed on a semiconductor substrate. It is characterized in that a lifetime control region having a lifetime smaller than that of a carrier in another region is formed.

また、請求項２に記載の発明は、第１導電型の第１の半導体領域を備える半導体基板上に前記第１の半導体領域を介して互いに対向するように形成された第１及び第２のトレンチと、前記第１及び第２のトレンチの側面に形成されたゲート絶縁膜と、前記第１及び第２のトレンチの内部に形成されたゲート電極と、前記第１のトレンチと第２のトレンチの間に形成され、且つ前記第１の半導体領域に接触するように形成された第２導電型の第２の半導体領域と、前記第２の半導体領域に接触する、第１導電型の第３の半導体領域とを有し、互いに対向する前記第１のトレンチと第２のトレンチとの間の、前記第１の半導体領域内にライフタイム制御領域が形成されていることを特徴とする。   According to a second aspect of the present invention, there is provided a first and second semiconductor device formed on a semiconductor substrate having a first semiconductor region of a first conductivity type so as to face each other with the first semiconductor region interposed therebetween. A trench, a gate insulating film formed on side surfaces of the first and second trenches, a gate electrode formed inside the first and second trenches, the first trench and the second trench A second semiconductor region of a second conductivity type formed so as to be in contact with the first semiconductor region, and a third of the first conductivity type in contact with the second semiconductor region. A lifetime control region is formed in the first semiconductor region between the first trench and the second trench facing each other.

また、請求項３に記載の発明は、請求項１または２のいずれかに記載の半導体装置において、前記ライフタイム制御領域でのキャリアのライフタイムは、該ライフタイム制御領域以外の前記第1の半導体領域でのキャリアのライフタイム、及び前記第２の半導体領域でのキャリアのライフタイム、及び前記第３の半導体領域でのキャリアのライフタイムよりも小さいことを特徴とする。   According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the lifetime of the carrier in the lifetime control region is the first time other than the lifetime control region. It is smaller than the carrier lifetime in the semiconductor region, the carrier lifetime in the second semiconductor region, and the carrier lifetime in the third semiconductor region.

また、請求項４に記載の発明は、請求項２または３のいずれかに記載の半導体装置において、前記第１の半導体領域と前記第２の半導体領域とによってＰＮ接合ダイオードが形成されていることを特徴とする。   According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, a PN junction diode is formed by the first semiconductor region and the second semiconductor region. It is characterized by.

また、請求項５に記載の発明は、請求項２、３または４のいずれかに記載の半導体装置において、前記ライフタイム制御領域は、前記トレンチの底面よりも前記第３の半導体領域側に形成されていることを特徴とする。   According to a fifth aspect of the present invention, in the semiconductor device according to the second, third, or fourth aspect, the lifetime control region is formed closer to the third semiconductor region than the bottom surface of the trench. It is characterized by being.

また、請求項６に記載の発明は、請求項１乃至５のいずれかに記載の半導体装置において、前記ライフタイム制御領域は、軽イオンを注入して形成された領域であることを特徴とする。   According to a sixth aspect of the present invention, in the semiconductor device according to any of the first to fifth aspects, the lifetime control region is a region formed by implanting light ions. .

また、請求項７に記載の発明は、請求項１乃至５のいずれかに記載の半導体装置において、前記ライフタイム制御領域は、電子線を照射して形成された領域であることを特徴とする。   According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the lifetime control region is a region formed by irradiation with an electron beam. .

また、請求項８に記載の発明は、請求項１乃至５のいずれかに記載の半導体装置において、前記ライフタイム制御領域は、重金属を拡散して形成された領域であることを特徴とする。   According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the lifetime control region is a region formed by diffusing heavy metal.

以上説明したように、本発明によれば、半導体基板上に形成されたトレンチの側壁にチャネルが形成される絶縁ゲート構造を有する半導体装置において、隣り合うトレンチの側壁間にキャリアのライフタイムが他の領域におけるキャリアのライフタイムより比較して小さくしたライフタイム制御領域を形成したので、素子動作時の動作抵抗を増加させることなく、リカバリータイム（逆回復時間）を短縮することができる。   As described above, according to the present invention, in a semiconductor device having an insulated gate structure in which a channel is formed on the side wall of a trench formed on a semiconductor substrate, the lifetime of carriers is different between the side walls of adjacent trenches. Since the lifetime control region which is smaller than the carrier lifetime in this region is formed, the recovery time (reverse recovery time) can be shortened without increasing the operating resistance during device operation.

以下、本発明の実施形態を、図面を参照して詳細に説明する。
本発明の実施形態に係る半導体装置の構成を図１に示す。図１に示した半導体装置は、絶縁ゲート型電界効果トランジスタである。
本発明の実施形態に係る半導体装置１は、半導体基板上に形成されたトレンチの側壁にチャネルが形成される絶縁ゲート構造を有する半導体装置であって、隣り合うトレンチの側壁間にキャリアのライフタイムが他の領域におけるキャリアのライフタイムより比較して小さくしたライフタイム制御領域を形成したことを特徴としている。
軽イオンが照射されて形成されたライフタイム制御領域１１０が、ベース領域１０７とトレンチ１０３、１０４底部との間に位置する低濃度エピタキシャル成長層１０２に形成されていることを特徴としている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device shown in FIG. 1 is an insulated gate field effect transistor.
A semiconductor device 1 according to an embodiment of the present invention is a semiconductor device having an insulated gate structure in which a channel is formed on the side wall of a trench formed on a semiconductor substrate, and the lifetime of carriers between the side walls of adjacent trenches. Is characterized by the formation of a lifetime control region that is smaller than the lifetime of carriers in other regions.
The lifetime control region 110 formed by irradiating light ions is formed in the low-concentration epitaxial growth layer 102 located between the base region 107 and the bottoms of the trenches 103 and 104.

図１において、本発明の実施形態に係る半導体装置（絶縁ゲート型電界効果トランジスタ）は、高濃度基板（例えばｎ＋型半導体基板）１０１と、高濃度基板１０１上に形成された低濃度エピタキシャル成長層（例えばｎ−型エピタキシャル成長層）１０２と、低濃度エピタキシャル成長層１０２内に形成されたソース拡散領域（例えば、ｎ＋型拡散領域）１０８、ソース拡散領域１０８に接触するように、これらの上面に形成された電極層１０９及びチャネル拡散領域、すなわちベース領域（例えば、ｐ型拡散領域）１０７とを有する半導体基板１００と、この半導体基板１００の一方の主面に形成されたソース電極１１１及びゲート電極１１２と、半導体基板１００の他方の主面に形成されたドレイン電極１１３とを有している。 1, a semiconductor device (insulated gate field effect transistor) according to an embodiment of the present invention includes a high concentration substrate (for example, an n + type semiconductor substrate) 101 and a low concentration epitaxial growth layer formed on the high concentration substrate 101. (For example, an n − type epitaxial growth layer) 102, a source diffusion region (for example, an n + type diffusion region) 108 formed in the low-concentration epitaxial growth layer 102, and a source diffusion region 108 are formed on the upper surfaces thereof. The semiconductor substrate 100 having the electrode layer 109 and the channel diffusion region, that is, the base region (for example, p-type diffusion region) 107, and the source electrode 111 and the gate electrode 112 formed on one main surface of the semiconductor substrate 100 And a drain electrode 113 formed on the other main surface of the semiconductor substrate 100.

半導体基板１００の一方の主面には、図５に示した従来の半導体装置と同様に、トレンチ１０３、１０４が設けられており、トレンチ１０３、１０４の側壁にはゲート絶縁膜として機能するシリコン酸化膜１０５が形成されている。
トレンチ１０３、１０４の内部には、例えば多結晶シリコン（ポリシリコン）からなる導体膜（ゲート電極）１０６が埋設されており、トレンチゲートが形成されている。 Similar to the conventional semiconductor device shown in FIG. 5, trenches 103 and 104 are provided on one main surface of the semiconductor substrate 100, and silicon oxide that functions as a gate insulating film is formed on the sidewalls of the trenches 103 and 104. A film 105 is formed.
A conductor film (gate electrode) 106 made of, for example, polycrystalline silicon (polysilicon) is embedded in the trenches 103 and 104, and a trench gate is formed.

この導体膜１０６は、図示のように、シリコン酸化膜１０５を介して、低濃度エピタキシャル成長層１０２の上側領域、チャネル拡散領域すなわちベース領域１０７、及びソース拡散領域１０８の側面と接触している。
ライフタイム制御領域１１０は、この導体膜（ゲート電極）１０６と対向する低濃度エピタキシャル成長層１０２の上側領域に形成されており、隣り合うトレンチ１０３、１０４間を横切るように形成されている。
ここで、ライフタイム制御領域１１０とは、局所的に軽イオンを照射したり、局所的に電子線を照射したり、局所的に重金属（ライフタイムキラー）拡散をする等して、キャリアのライフタイムが他の領域におけるキャリアのライフタイムに比較して小さくされた領域をいう。本実施形態では、局所的に軽イオンを照射（導入）して、このライフタイム制御領域１１０を形成した。半導体基板１００は、本発明の半導体基板に、低濃度エピタキシャル成長層１０２は第１の半導体領域に、導体膜（ゲート電極）１０６は、本発明のゲート電極に、ベース領域（例えば、ｐ型拡散領域）１０７は、本発明の第２導電型の第２の半導体領域に、ソース拡散領域１０８は本発明の第１導電型（ｎ＋型）の第３の半導体領域に、それぞれ相当する。 As shown in the figure, the conductor film 106 is in contact with the upper region of the low-concentration epitaxial growth layer 102, the channel diffusion region, that is, the base region 107, and the side surfaces of the source diffusion region 108 through the silicon oxide film 105.
The lifetime control region 110 is formed in an upper region of the low-concentration epitaxial growth layer 102 facing the conductor film (gate electrode) 106 and is formed so as to cross between the adjacent trenches 103 and 104.
Here, the lifetime control region 110 refers to the life of the carrier by locally irradiating light ions, locally irradiating an electron beam, or locally diffusing heavy metal (lifetime killer). An area in which the time is made smaller than the carrier lifetime in other areas. In this embodiment, the lifetime control region 110 is formed by locally irradiating (introducing) light ions. The semiconductor substrate 100 is the semiconductor substrate of the present invention, the low-concentration epitaxial growth layer 102 is the first semiconductor region, the conductive film (gate electrode) 106 is the gate electrode of the present invention, and the base region (for example, p-type diffusion region). ) 107 corresponds to the second semiconductor region of the second conductivity type of the present invention, and the source diffusion region 108 corresponds to the third semiconductor region of the first conductivity type (n + type) of the present invention.

また、本実施形態では、ライフタイム制御領域１１０の上面は、べース領域１０７の下面よりも半導体基板１００の他方の主面側に位置し、ライフタイム制御領域１１０の上面とベース領域１０７の下面との間には、低濃度エピタキシャル成長層１０２の上側領域が薄く残存している。
また、ライフタイム制御領域１１０の下面は、トレンチ１０３、１０４の底面と半導体基板１００の一方の主面との間に位置し、ライフタイム制御領域１１０の下面とトレンチ１０３、１０４の底面の延長線との間には低濃度エピタキシャル成長層１０２の上側領域が薄く残存している。
なお、トレンチ１０３、１０４の間の低濃度エピタキシャル成長層１０２の全体にライムタイム制御領域１１０を形成してもよい。 In the present embodiment, the upper surface of the lifetime control region 110 is located on the other main surface side of the semiconductor substrate 100 with respect to the lower surface of the base region 107, and the upper surface of the lifetime control region 110 and the base region 107 are A thin upper region of the low concentration epitaxial growth layer 102 remains between the lower surface and the lower surface.
The lower surface of the lifetime control region 110 is located between the bottom surfaces of the trenches 103 and 104 and one main surface of the semiconductor substrate 100, and is an extension line between the lower surface of the lifetime control region 110 and the bottom surfaces of the trenches 103 and 104. The upper region of the low-concentration epitaxial growth layer 102 remains thin.
Note that the lime time control region 110 may be formed in the entire low concentration epitaxial growth layer 102 between the trenches 103 and 104.

しかし、ライフタイム制御領域１１０は、軽イオンの打ち込みによって形成された結晶欠陥領域として形成されたものである。このため、ライフタイム制御領域１１０の上面とその上の低濃度エビタキシャル成長層１０２との界面は明確に定まるものではない。同様に、ライフタイム制御領域１１０の下面とその下の低濃度エピタキシャル成長層１０２との界面も明確に定まるものではない。そこで便宜上、本願明細書では、その結晶欠陥の密度（再結合中心密度）がライフタイム制御領域１１０の中央側における再結合中心密度の１／３になった面を、それぞれライフタイム制御領域の上面及び下面としている。   However, the lifetime control region 110 is formed as a crystal defect region formed by light ion implantation. For this reason, the interface between the upper surface of the lifetime control region 110 and the low-concentration epitaxial growth layer 102 thereon is not clearly determined. Similarly, the interface between the lower surface of the lifetime control region 110 and the underlying low-concentration epitaxial growth layer 102 is not clearly determined. Therefore, for the sake of convenience, in the present specification, the surface where the density of crystal defects (recombination center density) is 1/3 of the recombination center density on the center side of the lifetime control region 110 is referred to as the upper surface of the lifetime control region. And the bottom surface.

このように、ライフタイム制御領域１１０を、対向するトレンチ１０３、１０４の間に形成することによって、比較的低いオン抵抗（素子動作時の動作抵抗）を維持しつつ、内蔵ダイオードのリカバリータイム（逆回復時間）を短くすることができる。
すなわち、図５に示す、トレンチゲート構造を有する従来の半導体装置では、軽イオンを照射してライフタイム制御を行うと、リカバリータイムは短くなるが、オン抵抗は増加した。しかし、本実施形態のトランジスタでは、オン抵抗も比較的小さい状態を維持する。この理由は、次のとおりである。 Thus, by forming the lifetime control region 110 between the opposing trenches 103 and 104, the recovery time (reverse of the built-in diode) is maintained while maintaining a relatively low on-resistance (operation resistance during device operation). (Recovery time) can be shortened.
That is, in the conventional semiconductor device having the trench gate structure shown in FIG. 5, when the lifetime control is performed by irradiating light ions, the recovery time is shortened but the on-resistance is increased. However, in the transistor of this embodiment, the on-resistance is also kept relatively small. The reason for this is as follows.

トランジスタの動作時（オン時）には、動作電流（電子電流）は、図２に示すように、チャネルを通じて流れるため、その電流通路はトレンチ１０３、１０４の側壁近傍の低濃度エピタキシャル成長層１０２とチャネル拡散領域に形成される。このため、電子電流はライフタイム制御領域１１０の一部のみを横切って流れることとなり、電子の捕獲断面積は小さく、ライフタイム制御領域１１０内での電子捕獲総量は比較的少なくなる。このため、オン抵抗は比較的低い状態を維持する。   When the transistor is operating (on), the operating current (electron current) flows through the channel, as shown in FIG. 2, so that the current path is the channel between the low-concentration epitaxial growth layer 102 near the sidewalls of the trenches 103 and 104 and the channel. It is formed in the diffusion region. For this reason, the electron current flows across only a part of the lifetime control region 110, the electron capture cross-sectional area is small, and the total amount of electron capture in the lifetime control region 110 is relatively small. For this reason, the on-resistance is kept relatively low.

一方、内蔵ダイオードの動作時、即ち、ソース電極１１１とドレイン電極１１３との間にソース電極１１１側の電位を高くする電圧を印加したときには、図３に示すように、ホール電流及び電子電流がＰＮ接合の全面、換言すればライフタイム制御領域１１０の全面を横切って流れる。このため、電子及びホールの捕獲断面積が大きく、ライフタイム制御領域１１０内でのキャリア捕獲総量は比較的多くなる。このため、リカバリータイム（逆回復時間）を短くすることができる。   On the other hand, when the built-in diode is operated, that is, when a voltage for increasing the potential on the source electrode 111 side is applied between the source electrode 111 and the drain electrode 113, as shown in FIG. It flows across the entire surface of the junction, in other words, the entire surface of the lifetime control region 110. For this reason, the capture cross sections of electrons and holes are large, and the total amount of trapped carriers in the lifetime control region 110 is relatively large. For this reason, the recovery time (reverse recovery time) can be shortened.

この結果、ライフタイム制御領域１１０の軽イオン照射量、換言すれば結晶欠陥密度（再結合中心密度）の量をコントロールすることによって、所望のリカバリータイムが得られる。
つまり、軽イオンの照射量を増加してキャリアの再結合中心密度を増加すれば、ダイオードのリカバリータイムは相対的に短くすることができる。反対に、軽イオンの照射量を減少してキャリアの再結合中心密度を減少すれば、ダイオードのリカバリータイムは相対的に長くすることができる。上述のように、このようにダイオードのリカバリータイムをコントロールしても（リカバリータイムを相対的に短くしても）、トランジスタの順方向電圧は比較的低い値を維持する。 As a result, a desired recovery time can be obtained by controlling the light ion irradiation amount of the lifetime control region 110, in other words, the amount of crystal defect density (recombination center density).
That is, the recovery time of the diode can be relatively shortened by increasing the irradiation amount of light ions to increase the carrier recombination center density. On the contrary, the recovery time of the diode can be made relatively long by reducing the irradiation amount of light ions and reducing the recombination center density of carriers. As described above, even if the recovery time of the diode is controlled in this manner (even if the recovery time is relatively short), the forward voltage of the transistor maintains a relatively low value.

なお、半導体基板１００の一方の主面から見たときのトレンチの形状は、周知の種々の形状を遼宜選択できる。たとえば、格子形状、ストライプ形状、或いはアイランド形状にすることができる。
また、低い順方向電圧を良好に得るためには、ライフタイム制御領域１１０の下面を、トレンチ１０３、１０４の底面の延長線上に位置させるか、または、本実施形態のように、トレンチ１０３、１０４の底面の延長線と半導体基板の一方の主面との間に位置させるのが望ましい。 Note that various known shapes can be selected as the shape of the trench when viewed from one main surface of the semiconductor substrate 100. For example, a lattice shape, a stripe shape, or an island shape can be used.
In order to obtain a low forward voltage satisfactorily, the lower surface of the lifetime control region 110 is positioned on an extension line of the bottom surface of the trenches 103 and 104, or as in the present embodiment, the trenches 103 and 104 It is desirable to locate between the extension line of the bottom surface of the semiconductor substrate and one main surface of the semiconductor substrate.

しかしながら、要求される順方向電圧によっては、ライフタイム制御領域１１０の下面を、トレンチ１０３、１０４の底面の延長線上よりも半導体基板１００の他方の主面（下面）側に位置させることもできる。
しかし、この場合でも、本発明の効果が得られるように、トレンチ１０３、１０４の底面の延長線上よりも半導体基板１００の他方の主面（下面）側に形成されたライフタイム制御領域１１０の再結合中心の総量が、トレンチ１０３、１０４の底面の延長線上よりも半導体基板１００の一方の主面（上面）側に形成されたライフタイム制御領域の再結合中心の総量に比較して小さくなるように、望ましくは、トレンチ１０３、１０４の底面の延長線上よりも半導体基板１００の一方の主面（上面）側に形成されたライフタイム制御領域１１０の再結合中心の総量の１／３以下になるようにするのが良い。 However, depending on the required forward voltage, the lower surface of the lifetime control region 110 can be positioned on the other main surface (lower surface) side of the semiconductor substrate 100 with respect to the extended line of the bottom surface of the trenches 103 and 104.
However, even in this case, the lifetime control region 110 formed on the other main surface (lower surface) side of the semiconductor substrate 100 rather than on the extended line of the bottom surfaces of the trenches 103 and 104 can be regenerated so that the effect of the present invention can be obtained. The total amount of coupling centers is smaller than the total amount of recombination centers in the lifetime control region formed on one main surface (upper surface) side of the semiconductor substrate 100 than on the extension line of the bottom surfaces of the trenches 103 and 104. In addition, it is desirable that the total amount of recombination centers in the lifetime control region 110 formed on one main surface (upper surface) side of the semiconductor substrate 100 is less than 1/3 of the extension line of the bottom surface of the trenches 103 and 104. It is good to do so.

次に、本発明の他の実施形態に係る半導体装置の構成を図４に示す。本実施形態は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）に本発明を適用したものである。デバイスの構成としては、図１の半導体装置の構成上、異なるのは半導体基板２００の下面側に、図１における高濃度基板（ｎ＋型半導体基板）１０１の代わりに、第２導電型（ｐ＋型）の半導体領域２０１Ａと第１導電型（ｎ＋型）の半導体領域２０１Ｂを交互に形成して、第２導電型（ｐ＋型）の半導体領域２０１Ａの上側にＩＧＢＴが形成され、第１導電型（ｎ＋型）の半導体領域２０１Ｂの上側にダイオードが形成されるようにした点であり、他の構成は同様である。 Next, FIG. 4 shows a configuration of a semiconductor device according to another embodiment of the present invention. In the present embodiment, the present invention is applied to an IGBT (Insulated Gate Bipolar Transistor). The configuration of the device differs from the configuration of the semiconductor device of FIG. 1 in that the second conductivity type (p) is provided on the lower surface side of the semiconductor substrate 200 instead of the high concentration substrate (n + type semiconductor substrate) 101 in FIG. The + type semiconductor regions 201A and the first conductivity type (n + type) semiconductor regions 201B are alternately formed, and an IGBT is formed above the second conductivity type (p + type) semiconductor region 201A. A diode is formed above the one-conductivity type (n + -type) semiconductor region 201B, and the other configurations are the same.

図４において、本実施形態に係る半導体装置（ＩＧＢＴ）では、半導体基板２００の下面側に第２導電型（ｐ＋型）の半導体領域２０１Ａと第１導電型（ｎ＋型）の半導体領域２０１Ｂが交互に形成されており、これらの上面に低濃度エピタキシャル成長層（例えばｎ−型エピタキシャル成長層）２０２が形成されている。さらに、低濃度エピタキシャル成長層２０２内にエミッタ拡散領域（例えば、ｎ＋型拡散領域）２０８、及びチャネル拡散領域、すなわちベース領域（例えば、ｐ型拡散領域）２０７とが形成されている。 4, in the semiconductor device (IGBT) according to the present embodiment, the second conductivity type (p + type) semiconductor region 201A and the first conductivity type (n + type) semiconductor region 201B are provided on the lower surface side of the semiconductor substrate 200. Are alternately formed, and a low-concentration epitaxial growth layer (for example, an n − -type epitaxial growth layer) 202 is formed on the upper surface thereof. Further, an emitter diffusion region (for example, n + -type diffusion region) 208 and a channel diffusion region, that is, a base region (for example, p-type diffusion region) 207 are formed in the low concentration epitaxial growth layer 202.

半導体基板２００の一方の主面には、図５に示した従来の半導体装置と同様に、トレンチ２０３、２０４が設けられており、トレンチ２０３、２０４の側壁にはゲート絶縁膜として機能するシリコン酸化膜２０５が形成されている。
トレンチ２０３、２０４の内部には、例えば多結晶シリコン（ポリシリコン）からなる導体膜（ゲート電極）２０６が埋設されており、トレンチゲートが形成されている。 Similar to the conventional semiconductor device shown in FIG. 5, trenches 203 and 204 are provided on one main surface of the semiconductor substrate 200, and silicon oxide that functions as a gate insulating film is formed on the sidewalls of the trenches 203 and 204. A film 205 is formed.
Inside the trenches 203 and 204, a conductor film (gate electrode) 206 made of, for example, polycrystalline silicon (polysilicon) is embedded to form a trench gate.

この導体膜２０６は、図示のように、シリコン酸化膜２０５を介して、低濃度エピタキシャル成長層２０２の上側領域、チャネル拡散領域すなわちベース領域２０７、及びエミッタ拡散領域２０８の側面と接触している。
ライフタイム制御領域２１０は、この導体膜（ゲート電極）２０６と対向する低濃度エピタキシャル成長層２０２の上側領域に形成されており、隣り合うトレンチ２０３、２０４間を横切るように形成されている。
ここで、ライフタイム制御領域２１０とは、局所的に軽イオンを照射したり、局所的に電子線を照射したり、局所的に重金属（ライフタイムキラー）拡散をする等して、キャリアのライフタイムが他の領域におけるキャリアのライフタイムに比較して小さくされた領域をいう。本実施形態では、局所的に軽イオンを照射（導入）して、このライフタイム制御領域２１０を形成した。 As illustrated, the conductor film 206 is in contact with the upper region of the low-concentration epitaxial growth layer 202, the channel diffusion region, that is, the base region 207, and the side surfaces of the emitter diffusion region 208 through the silicon oxide film 205.
The lifetime control region 210 is formed in an upper region of the low-concentration epitaxial growth layer 202 facing the conductor film (gate electrode) 206, and is formed so as to cross between the adjacent trenches 203 and 204.
Here, the lifetime control region 210 refers to the life of the carrier by locally irradiating light ions, locally irradiating an electron beam, or locally diffusing heavy metal (lifetime killer). An area in which the time is made smaller than the carrier lifetime in other areas. In the present embodiment, the lifetime control region 210 is formed by locally irradiating (introducing) light ions.

また、本実施形態では、図１乃至図３に示した実施形態と同様に、ライフタイム制御領域２１０の上面は、べース領域２０７の下面よりも半導体基板２００の他方の主面側に位置し、ライフタイム制御領域２１０の上面とベース領域２０７の下面との間には、低濃度エピタキシャル成長層２０２の上側領域が薄く残存している。
また、ライフタイム制御領域２１０の下面は、トレンチ２０３、２０４の底面と半導体基板２００の一方の主面との間に位置し、ライフタイム制御領域２１０の下面とトレンチ２０３、２０４の底面の延長線との間には低濃度エピタキシャル成長層２０２の上側領域が薄く残存している。
本実施形態の場合も図１乃至図３に示した実施形態と同様の効果が得られる。 Further, in the present embodiment, as in the embodiment shown in FIGS. 1 to 3, the upper surface of the lifetime control region 210 is positioned on the other main surface side of the semiconductor substrate 200 with respect to the lower surface of the base region 207. However, the upper region of the low concentration epitaxial growth layer 202 remains thinly between the upper surface of the lifetime control region 210 and the lower surface of the base region 207.
The lower surface of the lifetime control region 210 is located between the bottom surfaces of the trenches 203 and 204 and one main surface of the semiconductor substrate 200, and is an extension line between the lower surface of the lifetime control region 210 and the bottom surfaces of the trenches 203 and 204. The upper region of the low-concentration epitaxial growth layer 202 remains thin.
In the case of this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 3 can be obtained.

本発明の実施形態に係る半導体装置の断面構造を示す図。1 is a diagram showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. 本発明の実施形態に係る半導体装置の素子動作時の状態を示す説明図。Explanatory drawing which shows the state at the time of element operation | movement of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置に内蔵するダイオードが動作した時の状態を示す説明図。Explanatory drawing which shows a state when the diode built in the semiconductor device which concerns on embodiment of this invention operate | moved. 本発明の他の実施形態に係る半導体装置の断面構造を示す図。The figure which shows the cross-section of the semiconductor device which concerns on other embodiment of this invention. 従来のトレンチゲート構造を有する半導体装置の断面構造を示す図。The figure which shows the cross-section of the semiconductor device which has the conventional trench gate structure. 図５に示した従来の半導体装置の等価回路を示す回路図。FIG. 6 is a circuit diagram showing an equivalent circuit of the conventional semiconductor device shown in FIG. 5.

符号の説明Explanation of symbols

１…半導体装置、１００…半導体基板、１０１…高濃度基板、１０２…低濃度エピタキシャル成長層、１０３、１０４…トレンチ、１０５…シリコン酸化膜、１０６…導体膜、１０７…ベース領域、１０８…ソース拡散領域、１１０…ライフタイム制御領域   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 100 ... Semiconductor substrate, 101 ... High concentration substrate, 102 ... Low concentration epitaxial growth layer, 103, 104 ... Trench, 105 ... Silicon oxide film, 106 ... Conductor film, 107 ... Base region, 108 ... Source diffusion region 110: Lifetime control area

Claims (8)

半導体基板上に形成されたトレンチの側壁にチャネルが形成される絶縁ゲート構造を有する半導体装置において、
隣り合うトレンチの側壁間にキャリアのライフタイムが他の領域におけるキャリアのライフタイムより比較して小さくしたライフタイム制御領域を形成したことを特徴とする半導体装置。 In a semiconductor device having an insulated gate structure in which a channel is formed on a sidewall of a trench formed on a semiconductor substrate,
A semiconductor device characterized in that a lifetime control region in which a carrier lifetime is made smaller than a carrier lifetime in another region is formed between sidewalls of adjacent trenches. 第１導電型の第１の半導体領域を備える半導体基板上に前記第１の半導体領域を介して互いに対向するように形成された第１及び第２のトレンチと、
前記第１及び第２のトレンチの側面に形成されたゲート絶縁膜と、
前記第１及び第２のトレンチの内部に形成されたゲート電極と、
前記第１のトレンチと第２のトレンチの間に形成され、且つ前記第１の半導体領域に接触するように形成された第２導電型の第２の半導体領域と、
前記第２の半導体領域に接触する、第１導電型の第３の半導体領域とを有し、
互いに対向する前記第１のトレンチと第２のトレンチとの間の、前記第１の半導体領域内にライフタイム制御領域が形成されていることを特徴とする半導体装置。 A first trench and a second trench formed on a semiconductor substrate having a first semiconductor region of a first conductivity type so as to face each other via the first semiconductor region;
A gate insulating film formed on side surfaces of the first and second trenches;
A gate electrode formed inside the first and second trenches;
A second semiconductor region of a second conductivity type formed between the first trench and the second trench and formed in contact with the first semiconductor region;
A third semiconductor region of a first conductivity type in contact with the second semiconductor region;
A semiconductor device, wherein a lifetime control region is formed in the first semiconductor region between the first trench and the second trench facing each other. 前記ライフタイム制御領域でのキャリアのライフタイムは、該ライフタイム制御領域以外の前記第1の半導体領域でのキャリアのライフタイム、及び前記第２の半導体領域でのキャリアのライフタイム、及び前記第３の半導体領域でのキャリアのライフタイムよりも小さいことを特徴とする請求項１または２のいずれかに記載の半導体装置。   The carrier lifetime in the lifetime control region is the carrier lifetime in the first semiconductor region other than the lifetime control region, the carrier lifetime in the second semiconductor region, and the first 3. The semiconductor device according to claim 1, wherein the semiconductor device has a lifetime smaller than a lifetime of carriers in the semiconductor region. 前記第１の半導体領域と前記第２の半導体領域とによってＰＮ接合ダイオードが形成されていることを特徴とする請求項２または３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 2, wherein a PN junction diode is formed by the first semiconductor region and the second semiconductor region. 5. 前記ライフタイム制御領域は、前記トレンチの底面よりも前記第３の半導体領域側に形成されていることを特徴とする請求項２、３または４のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 2, wherein the lifetime control region is formed closer to the third semiconductor region than a bottom surface of the trench. 前記ライフタイム制御領域は、軽イオンを注入して形成された領域であることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the lifetime control region is a region formed by implanting light ions. 前記ライフタイム制御領域は、電子線を照射して形成された領域であることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the lifetime control region is a region formed by irradiation with an electron beam. 前記ライフタイム制御領域は、重金属を拡散して形成された領域であることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。

6. The semiconductor device according to claim 1, wherein the lifetime control region is a region formed by diffusing heavy metal.

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