JP2006513041A - Coated magnetic particles and their applications - Google Patents

Coated magnetic particles and their applications Download PDF

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Publication number
JP2006513041A
JP2006513041A JP2005508466A JP2005508466A JP2006513041A JP 2006513041 A JP2006513041 A JP 2006513041A JP 2005508466 A JP2005508466 A JP 2005508466A JP 2005508466 A JP2005508466 A JP 2005508466A JP 2006513041 A JP2006513041 A JP 2006513041A
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Prior art keywords
particles
coating
depositing
magnetic
solder
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JP2005508466A
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Japanese (ja)
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グリーゴ，トーマス，ピー．
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サーフェクト テクノロジーズ インク．
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D15/00—Electrolytic or electrophoretic production of coatings containing embedded materials, e.g. particles, whiskers, wires
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    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
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Abstract

半田接合部、バンプ、バイア、ボンドリング、及びその他を含む構造を堆積させるためにコーティング及び／又は磁性粒子を使用する方法。粒子は、半田付け可能な材料によりコーティングしてよい。半田接合部については、リフロ後、半田材料は、マトリクス内に未融解粒子を備えてよく、これにより、接合部の強度を増加させ、接合部の配列のピッチを低減する。粒子及びコーティングは、より融点の高い合金を形成し、その後の複数のリフロステップを可能にしてよい。粒子及び／又はコーティングは、磁性を有してよい。外部磁場は、粒子積載量及び堆積位置を正確に制御するために、堆積中に加えてよい。これにより、不適合な電極電位を有する元素を、単一のステップで電着し得る。こうした磁場の使用により、構造の完全なシード金属化を必要とすることなく、バイア等、高アスペクト比の構造の充填が可能となる。更に、触媒材料によりコーティングされた磁性粒子で構成された触媒は、随意的に、中間層を含む。A method of using coatings and / or magnetic particles to deposit structures including solder joints, bumps, vias, bond rings, and others. The particles may be coated with a solderable material. For solder joints, after reflow, the solder material may comprise unmelted particles in the matrix, thereby increasing the strength of the joints and reducing the pitch of the array of joints. The particles and coating may form a higher melting alloy and allow multiple subsequent reflow steps. The particles and / or coating may be magnetic. An external magnetic field may be applied during deposition to accurately control particle loading and deposition position. Thereby, elements having incompatible electrode potentials can be electrodeposited in a single step. The use of such a magnetic field allows the filling of high aspect ratio structures such as vias without the need for complete seed metallization of the structure. Furthermore, the catalyst composed of magnetic particles coated with a catalyst material optionally includes an intermediate layer.

Description

＜関連出願の説明＞
本願は、２００２年１２月５日提出の米国仮特許出願第６０／４３１，３１５号「印刷可能半田ペースト用固体核半田粒子」と、２００３年２月１２日提出の米国仮特許出願第６０／４４７，１７５号「電気化学デバイス及びプロセス」と、２００３年１１月１２日提出の米国仮特許出願第６０／５１９，８１３号「粒子共電着」の出願の利益を主張する。本願は、２００１年５月３１日提出の米国特許出願第０９／８７２，２１４号「電気化学プロセス及び装置によるサブミクロン及びナノサイズ粒子のカプセル化」の一部継続出願である。列記した各出願の明細書は、出典を明示することによりその開示内容全体を本願明細書の一部とする。 <Description of related applications>
This application is based on US Provisional Patent Application No. 60 / 431,315 “Solid Core Solder Particles for Printable Solder Paste” filed on Dec. 5, 2002 and US Provisional Patent Application No. 60/431 filed on Feb. 12, 2003. No. 447,175 “Electrochemical Devices and Processes” and US Provisional Patent Application No. 60 / 519,813 “Particulate Electrodeposition” filed Nov. 12, 2003. This application is a continuation-in-part of US patent application Ser. No. 09 / 872,214, “Encapsulation of submicron and nano-sized particles by electrochemical processes and equipment,” filed May 31, 2001. The specification of each application listed is incorporated herein in its entirety by specifying the source.

本発明は、基板又は表面に粒子を堆積させる前に所望の材料によりコーティングした磁性又は非磁性粒子に関する。コーティングは、各粒子と密接に接触し、結果として、化学量的制御と酸化の最小化とを強化する。コーティングは、限定はされないが、半田材料又は触媒材料を含む、任意の望ましい材料にしてよい。核粒子及び／又はコーティングが磁性を有する場合、外部磁界は、堆積速度を増進するのに使用してよく、或いは、粒子を特定の位置へ方向付けるのに使用して、基板の不要な区域での堆積を最小化してよい。電着、スクリーン印刷、及びフォトステンシルバンピング等、多数のタイプの堆積プロセスを使用してよい。本発明は、更に、半導体のバイア又はバンプのような他の構造の特性を修正するための、非コーティング磁性又は非磁性粒子の使用に関する。   The present invention relates to magnetic or non-magnetic particles coated with a desired material prior to depositing the particles on a substrate or surface. The coating is in intimate contact with each particle, resulting in enhanced stoichiometric control and minimized oxidation. The coating may be any desired material, including but not limited to a solder material or a catalyst material. If the core particles and / or coating is magnetic, an external magnetic field may be used to increase the deposition rate, or it may be used to direct the particles to a specific location and in unwanted areas of the substrate. Deposition may be minimized. Many types of deposition processes may be used, such as electrodeposition, screen printing, and photo stencil bumping. The invention further relates to the use of non-coated magnetic or non-magnetic particles to modify the properties of other structures such as semiconductor vias or bumps.

以下の説明では、多数の刊行物を（複数の）著者及び刊行年別に参照しており、特定の刊行物は、最近の刊行日であるため、本発明に対する従来技術とはみなされないことに留意されたい。こうした刊行物の説明は、本明細書において、より完全な化学原理の背景として提示されるものであり、特許性の決定を目的として、こうした刊行物が従来技術であることを承認するものではない。   In the following description, a number of publications are referenced by author (s) and year of publication, and it is noted that a particular publication is not considered prior art to the present invention because it is the most recent publication date. I want to be. The descriptions of these publications are presented herein as a more complete background of chemical principles and are not an admission that such publications are prior art for purposes of determining patentability. .

ウェーハバンピング技術は、最近、ハイエンドコンピューティング及びネットワーキング市場において大きな注目を集めており、これは、こうした技術が高密度ＭＰＵ、ＡＳＩＣ、及びメモリデバイス構造での高い性能を可能にしてきたためである。フリップチップボールグリッドアレイ（ＦＣＢＧＡ）は、半田バンピング相互接続を使用すると同時に、エリアアレイ構成を可能にするパッケージタイプである。これは、従来のペリフェラルワイヤボンディング相互接続よりも遙かに優れた信号及び電力／接地の完全性を確保する。   Wafer bumping technology has recently received much attention in the high-end computing and networking market because such technology has enabled high performance in high density MPU, ASIC, and memory device structures. A flip chip ball grid array (FCBGA) is a package type that allows area array configurations while simultaneously using solder bumping interconnects. This ensures signal and power / ground integrity much better than conventional peripheral wire bonding interconnects.

携帯電話等の商品又は消費者製品について、パッケージサイズは、極めて重要となる。チップスケールパッケージ（ＣＳＰ）は、既に業界で広く認められている。しかしながら、真のチップサイズパッケージであるウェーハレベルＣＳＰ（ＷＬ−ＣＳＰ）等、更に小さなソリューションの探究は、依然として続いている。別の例として、フリップチップオンボード（ＦＣＯＢ）組立体用のバンプ付きダイも、製品の最終サイズを低減できる。   For products such as mobile phones or consumer products, the package size is extremely important. Chip scale packages (CSP) are already widely accepted in the industry. However, the search for smaller solutions, such as wafer level CSP (WL-CSP), which is a true chip size package, continues. As another example, bumped dies for flip chip on board (FCOB) assemblies can also reduce the final size of the product.

三つの主要なウェーハパンピングプロセスが存在し、これらは、蒸着、電気メッキ、及びスクリーン印刷である。蒸着法は、資本設備における大きな投資が必要であり、通常は、高い所有コストを伴う。電気メッキ法は、より微細なバンプピッチの傾向を促進することで知られているが、電気メッキ槽の制約のため、一部の半田材料は適していない。スクリーン印刷法は、通常、最も費用効率に優れているが、バンプピッチが２００ミクロン未満である時、深刻なバンプ高さの制限が存在する可能性がある。本発明に従って有用となる堆積プロセスには、更に、電着と、電気泳動と、フォトステンシルバンピングと、その他とが含まれる。   There are three main wafer pumping processes, these are vapor deposition, electroplating, and screen printing. Vapor deposition requires a large investment in capital equipment and is usually associated with high cost of ownership. The electroplating method is known to promote the tendency of finer bump pitches, but some solder materials are not suitable due to electroplating bath limitations. Screen printing methods are usually most cost effective, but severe bump height limitations may exist when the bump pitch is less than 200 microns. Deposition processes that are useful according to the present invention further include electrodeposition, electrophoresis, photostencil bumping, and others.

第四の、最近開発された先進的な印刷（フォトステンシルバンピング）バンプ法は、感光性レジスト膜を使用し、消費者向けから非常にハイエンドまで、あらゆる範囲の用途に対処できる。これは、部分的には、電気メッキ法に匹敵するバンプ高さと、標準的なスクリーン印刷に競合する原価構造との両方を可能にする先進的なスクリーン印刷バンピングプロセスの利点によるものである。この方法は、ウェーハ「シャトル」サービス、即ち、一ユーザ又は初期ツーリングコストを共有する多数のユーザ向けの、単一のウェーハ上での異なるデバイスの製造にとって理想的である。「シャトル」ウェーハは、個別のユーザ又は顧客への出荷前に単一化する必要があるため、単一チップ半田バンピングは、各デバイスに別々にバンプを与えるための効果的な方法となる。フォトステンシルバンピングは、１００マイクロメートルの低さのバンプピッチと、１００ミクロンの薄さのウェーハ上でのバンピングとを達成している。こうした進歩により、ＦＣＯＢは、システムの小型化にとって非常に重要なソリューションとなっている。必然的に、最適なソリューションでは、更に、バンピング、基板、パッケージング、組立、試験、及びボードレベルの組立の総費用を考慮する必要がある。フォトステンシルバンピングは、より均一な微細ピッチバンプのための現在の能力を拡張する。フォトステンシルバンピングを使用して製造されるバンプの高さは、電気メッキを使用することで可能となるものと同様であり、コストは代表的なスクリーン印刷法に競合する。例えば、フォトステンシルバンピングは、高さ１０５のバンプを２００ミクロンのピッチで製造可能であり、電気メッキは高さ１００ミクロンのバンプを製造し、スクリーン印刷は僅か７５ミクロンの高さのバンプを発生させる。この技術の重要な一態様は、パターン形成における傑出した特性と、アルカリ溶媒による剥離に依然として良好に反応する一方で、バンプ形成に必要な高温に耐えることができる事実とにより選択された、独自の感光性レジスト膜の使用である。更に、パターン形成における乾燥膜開口部の使用により、バンプの高さ均一性が大幅に改善される。   A fourth, recently developed advanced printing (photostencil bumping) bump method uses a photosensitive resist film and can handle a full range of applications from consumer to very high end. This is due, in part, to the advantages of an advanced screen printing bumping process that allows both bump height comparable to electroplating and cost structures that compete with standard screen printing. This method is ideal for wafer “shuttle” service, ie, the manufacture of different devices on a single wafer for one user or many users sharing initial tooling costs. Because “shuttle” wafers need to be singulated before shipment to individual users or customers, single chip solder bumping is an effective way to bump each device separately. Photostencil bumping achieves a bump pitch as low as 100 micrometers and bumping on a wafer as thin as 100 microns. These advances make FCOB an extremely important solution for system miniaturization. Inevitably, the optimal solution also needs to consider the total cost of bumping, board, packaging, assembly, testing, and board level assembly. Photo stencil bumping expands the current capability for more uniform fine pitch bumps. The height of the bumps produced using photo stencil bumping is similar to that made possible by using electroplating and the cost is competitive with typical screen printing methods. For example, photostencil bumping can produce bumps with a height of 105 at a pitch of 200 microns, electroplating produces bumps with a height of 100 microns, and screen printing produces bumps with a height of only 75 microns. . One important aspect of this technology is the unique properties selected for its outstanding properties in patterning and the fact that it can still withstand the high temperatures required for bump formation while still reacting well to alkaline solvent stripping. This is the use of a photosensitive resist film. Further, the use of the dry film opening in pattern formation greatly improves the bump height uniformity.

本発明は、上記の全てを含め、任意の堆積方法で使用してよい。   The present invention may be used with any deposition method, including all of the above.

半田バンピングにおける主要な材料、設計、及びプロセスの考慮事項は、次の通りである。   Key material, design, and process considerations in solder bumping are as follows:

１）バンプ材料は、理想的には、高温で共晶を形成し、無鉛となるべきである。   1) The bump material should ideally be eutectic at high temperatures and lead free.

２）バンプピッチは、基板の互換性を考慮して、可能な限り小さくするべきである（ビスマレイミドトリアジン［ＢＴ］、ビルドアップ、高熱膨張ガラスセラミック、その他）。   2) The bump pitch should be as small as possible in consideration of substrate compatibility (bismaleimide triazine [BT], build-up, high thermal expansion glass ceramic, etc.).

３）バンプ高さは、第一のレベルの信頼線を確保するのに十分となるべきである。   3) The bump height should be sufficient to ensure a first level confidence line.

４）バンプ構成は、エリアアレイ（ＭＰＵ／ＡＳＩＣ）又はペリフェラル（メモリ／アナログ）にしてよい。   4) The bump configuration may be an area array (MPU / ASIC) or a peripheral (memory / analog).

５）バンププロセスは、ウェーハレベル（蒸着、電気メッキ、及びスクリーン印刷）又は単一のダイ（ディンプルプレート）にしてよい。   5) The bump process may be at the wafer level (evaporation, electroplating, and screen printing) or a single die (dimple plate).

６）複数のリフロ処理ステップに対応するために、融点を調整することが望ましい。   6) It is desirable to adjust the melting point in order to cope with a plurality of reflow processing steps.

７）組立の前後に電気接触試験を行う必要がある。   7) It is necessary to conduct an electrical contact test before and after assembly.

８）バンプは、一部の用途で発生する可能性がある機械的衝撃、振動、クリープ、及び疲労に耐える十分な強度を有し、したがって、長期的な信頼性を確保するべきである。   8) The bump should have sufficient strength to withstand mechanical shock, vibration, creep and fatigue that may occur in some applications, and therefore should ensure long-term reliability.

９）材料には、リフロの前後で空隙が存在するべきではない。   9) There should be no voids in the material before and after reflow.

１０）コストは、最小化する必要がある。   10) Cost needs to be minimized.

欧州での電気電子機器廃棄物リサイクル指令（ＷＥＥＥ）及び特定有害物質使用制限指令（ＲＯＨＳ）の提案のため、無鉛バンピング材料の需要は増加している。更に、無鉛バンプは、システムオンチップ（ＳｏＣ）デバイスにおけるメモリマクロでのアルファ粒子効果を最小化する。銅配線上で無鉛バンプを使用して、単一のダイにおいて、１５３ミクロンのバンプピッチで１１，０００ほどのバンプを製造できる。   The demand for lead-free bumping materials is increasing due to proposals for the Electrical and Electronic Equipment Waste Recycling Directive (WEEE) and the Restriction of Use of Specific Hazardous Substances (ROHS) in Europe. In addition, lead free bumps minimize alpha particle effects in memory macros in system on chip (SoC) devices. Using lead-free bumps on copper wiring, as many as 11,000 bumps can be produced on a single die with a bump pitch of 153 microns.

上で説明した特徴を有する新しい半田材料の必要性が存在する。こうした特徴を改善する試みにおいて、既存の半田組成に元素粒子が追加されている（S. Jadhav et al., J. Electronic Materials 30 (9) 1197 (2002)、F. Guo et al., J. Electronic Materials 30 (9) 1073 (2001)、S. Hwang et al., J. Electronic Materials 31 (11) 1304 (2002)、S. Chol et al., J. Electronic Materials 28 (11) 1209 (1999)参照、全て出典を明示することによりその開示内容全体を本願明細書の一部とする）。非コーティング粒子は、マトリクス又はフィルタ材料と共に電着されてきた。しかしながら、こうしたアプローチは、多数の処理工程を必要とし、複雑性及びコストを増加させる。   There is a need for new solder materials having the features described above. In an attempt to improve these characteristics, elemental particles have been added to the existing solder composition (S. Jadhav et al., J. Electronic Materials 30 (9) 1197 (2002), F. Guo et al., J. Electronic Materials 30 (9) 1073 (2001), S. Hwang et al., J. Electronic Materials 31 (11) 1304 (2002), S. Chol et al., J. Electronic Materials 28 (11) 1209 (1999) The entire disclosure of which is hereby incorporated by reference, all clearly identifying the source). Uncoated particles have been electrodeposited with a matrix or filter material. However, such an approach requires a large number of processing steps, increasing complexity and cost.

加えて、半田ペーストは、元素粉末からブレンドされるが、短い保管寿命と、ペーストの層化（均一性、したがって信頼性を大幅に低下させる）と、一部の用途に適合しない有機結合剤の使用という不利点を有する。   In addition, the solder paste is blended from elemental powders, but with a short shelf life, paste layering (which significantly reduces uniformity and hence reliability), and organic binders that are not suitable for some applications. Has the disadvantage of use.

本発明は、更に、ブラインドバイアの充填を必要とする半導体製造手法に関し、柱形又は球形の終端デバイスの製造には、金属の加速堆積が必要となる。既存のプロセスは、電着、無電解メッキ、プラズマ蒸着を利用し、場合によっては、金属化スクリーン印刷インク及びペーストを利用する。   The present invention further relates to semiconductor fabrication techniques that require filling of blind vias, and the fabrication of columnar or spherical termination devices requires accelerated deposition of metal. Existing processes utilize electrodeposition, electroless plating, plasma deposition, and in some cases, metallized screen printing inks and pastes.

一般的な手法は、フォトレジスト又はフォトリソグラフィによって定められた特徴の電気メッキ充填である。基板の金属化によって電着が発生し、その後、従来の電着ステップに基づいて、電気化学堆積のプロセスにより、充填の堆積を制御するアンペア分の要件が満たされるまで、定められた特徴内に金属堆積物が蓄積される。こうしたタイプの手法の実時間のプロセスは、完全な密度の構造を犠牲にする特徴内の閉塞又はピンチを回避するために、二時間から１０又は１２時間程度までに変化する。   A common approach is electroplating of features defined by photoresist or photolithography. Electrodeposition occurs due to metallization of the substrate, and then within the defined characteristics until the amperage requirement to control the deposition of the fill is met by the process of electrochemical deposition based on conventional electrodeposition steps. Metal deposits accumulate. The real-time process of these types of approaches varies from two hours to as much as 10 or 12 hours to avoid blockages or pinches within features that sacrifice full density structure.

このプロセスに伴う時間は、化学的又は費用効率に優れた処理につながらない。結果的な特徴は、電着を実行するための電流バスフローを提供するために、非常に複雑なシード金属化を必要とする。このプロセスは、シード金属層の複雑なプラズマ蒸着を必要とする。このシード金属層は、バイア特徴のアスペクト比が１対１０を越える時、達成するのが非常に複雑になる。現行の実践では、更に複雑なクロススパッタリング方法を使用するが、得られる結果は、高品質で費用効率に優れたプロセスを保証するのに十分ではない。   The time associated with this process does not lead to a chemical or cost effective treatment. The resulting feature requires very complex seed metallization to provide current bus flow for performing electrodeposition. This process requires complex plasma deposition of the seed metal layer. This seed metal layer is very complicated to achieve when the aspect ratio of the via feature exceeds 1:10. Current practice uses more complex cross-sputtering methods, but the results obtained are not sufficient to ensure a high quality and cost effective process.

本発明は、更に、触媒作用のための磁性材料の使用に関する。膜電極組立体（ＭＥＡ）の製造には、活性の高い触媒層を提供するＰＥＭ及び触媒の適切な相互浸透のための可溶性ナフィオンと、熱と、圧力との正しい組み合わせを達成するために、専有である場合の多い大量の技術が関与し、その多くは試行錯誤によって開発されてきた。通常は、懸濁貴金属の黒色インク又は炭素支持貴金属のインクを、炭素フェルト電極にブラシで塗るか、或いは、テフロン（登録商標）面での触媒インクの蒸着によって触媒デカールの形にして、その後、ＰＥＭ層への圧力転写を行う。   The invention further relates to the use of magnetic materials for catalysis. The manufacture of membrane electrode assemblies (MEAs) is dedicated to achieving the correct combination of heat and pressure with soluble Nafion for proper interpenetration of PEM and catalyst to provide a highly active catalyst layer. Many technologies are often involved, many of which have been developed by trial and error. Typically, a suspended precious metal black ink or carbon-supported precious metal ink is brushed onto a carbon felt electrode or formed into a catalyst decal by deposition of the catalyst ink on a Teflon surface, then Pressure transfer to the PEM layer is performed.

触媒作用を強化するための磁性材料の使用は公知である。Ｌｅｄｄｙらが行った電極製造のアプローチは、炭素に支持されポリマに覆われた磁性粒子を、可用性ナフィオンと共に混合してインクを形成することに依存しており、結果として、磁性粒子の多量の塊状化と、分離した電気触媒材料面（Ｐｔ等）との接触の減少が生じた。この方法では、磁性面と触媒面との間の距離の広範な分布を含む触媒層が生成されるが、試験結果は、非常に魅力的であり、対照と比較して出力レベルの三倍の改善を実証している。こうした結果の定量的分析は、磁気的に修飾された触媒層の微細構造に関する十分な知識の欠如により、複雑なものとなるが、ＣＯが存在する時、触媒の約２５％のみが活性化されると推定される。   The use of magnetic materials to enhance catalysis is known. The electrode manufacturing approach taken by Leddy et al. Relies on mixing carbon-supported, polymer-covered magnetic particles with availability Nafion to form an ink, resulting in a large volume of magnetic particles. And reduced contact with the separated electrocatalyst material surface (Pt, etc.). This method produces a catalyst layer with a wide distribution of distances between the magnetic and catalyst surfaces, but the test results are very attractive and are three times the output level compared to the control. Proven improvement. The quantitative analysis of these results is complicated by the lack of sufficient knowledge about the microstructure of the magnetically modified catalyst layer, but only about 25% of the catalyst is activated when CO is present. It is estimated that.

磁性の高い粒子から触媒層を形成する試みでは平滑で物理的に安定した層が得られないことから、このアプローチは、比較的弱い磁性粒子の使用に限定されてきた。磁場の強い粒子は、ベッド層成形体を破砕及び変形させることで電極の完全性に影響を与える望ましくない力をもたらす。インクにおける磁性粒子の導入は、供給中、及び供給したインクの乾燥後、磁力が粒子を互いに引き寄せる間に、薄層を付与し安定させる方法等、新たな問題を持ち込む。例えば、Ｌｅｄｄｙらの米国特許第５，８１７，２２１号、第５，９２８，８０４号、第６，００１，２４８号、第６，３０３，２４２号、第６，３２２，６７６号、及び第６，４７９，１７６号を参照されたく、これらの明細書は出典を明示することによりその開示内容全体を本願明細書の一部とする。Ｌｅｄｄｙらの方法は、最終生産物の不均一性と複雑な製造プロセスとを発生させる各成分の分離を含め、その他の不利点を有する。   This approach has been limited to the use of relatively weak magnetic particles because attempts to form a catalyst layer from highly magnetic particles do not yield a smooth and physically stable layer. Particles with a strong magnetic field result in undesirable forces that affect electrode integrity by crushing and deforming the bed layer compact. The introduction of magnetic particles in the ink introduces new problems such as a method of applying and stabilizing a thin layer while supplying and drying the supplied ink while the magnetic force pulls the particles together. For example, Leddy et al., US Pat. Nos. 5,817,221, 5,928,804, 6,001,248, 6,303,242, 6,322,676, and 6, No. 479,176, which are hereby incorporated by reference in their entirety. The Leddy et al. Method has other disadvantages, including the separation of each component that generates end product heterogeneity and complex manufacturing processes.

本発明は、コーティング及び／又は磁性粒子を使用した構造を堆積させる方法と、結果として生じる構造との両方である。堆積方法は、一部として、電着、電気泳動、電気メッキ、蒸着、スクリーン印刷、及びフォトステンシルバンピングを含む。   The present invention is both a method of depositing structures using coatings and / or magnetic particles and the resulting structure. Deposition methods include, in part, electrodeposition, electrophoresis, electroplating, vapor deposition, screen printing, and photo stencil bumping.

本発明の主要な利点は、コーティングと粒子との密接な接触により、結果として生じる構造の化学量が他の方法を使用して堆積させた構造よりも均一になることである。   A major advantage of the present invention is that intimate contact between the coating and the particles results in a more uniform stoichiometry of the resulting structure than structures deposited using other methods.

本発明の主要な利点は、粒子及びコーティング材料を同時に堆積させることで、酸化物汚染が最小化されることである。   A major advantage of the present invention is that oxide contamination is minimized by simultaneously depositing particles and coating material.

本発明の主要な目的は、基板上にコーティング粒子を堆積させ、粒子をリフロさせて、半田接合部を形成する方法を提供することである。コーティングは、好ましくは、半田付け可能な材料である。結果として生じる半田は、固化マトリクス内に未融解粒子を備えてよい。こうした粒子の存在は、半田を強化し、圧縮及び剪断応力に対する耐性を高める。粒子は、更に、半田バンプ又は同様の構造の表面張力を変更し、達成可能なバンプピッチを低減し、高いバンプ密度を可能にする。粒子及びコーティングは、合金を形成するためのリフロ中に、部分的又は完全に反応してよい。合金は、好ましくは、コーティングより高い融点を有し、その後の複数のリフロステップを可能にする。   The main objective of the present invention is to provide a method of depositing coating particles on a substrate and reflowing the particles to form a solder joint. The coating is preferably a solderable material. The resulting solder may comprise unmelted particles within the solidification matrix. The presence of such particles strengthens the solder and increases resistance to compressive and shear stresses. The particles also alter the surface tension of solder bumps or similar structures, reducing the achievable bump pitch and allowing for high bump density. The particles and coating may react partially or completely during reflow to form the alloy. The alloy preferably has a higher melting point than the coating, allowing multiple subsequent reflow steps.

本発明の主要な目的は、磁性のある粒子、或いは磁性材料によりコーティングされた粒子を堆積させることである。粒子は、インク又はペースト中に懸濁させてよい。代替として、粒子は、電解液において共堆積させてよい。磁場は、粒子積載量を制御すると共に、粒子の堆積位置を正確に制御するために使用される。加えて、適合しない電極電位を有する材料を、一ステップで堆積させ得る。   The main object of the present invention is to deposit magnetic particles or particles coated with a magnetic material. The particles may be suspended in the ink or paste. Alternatively, the particles may be co-deposited in the electrolyte. The magnetic field is used to control the particle loading and accurately control the particle deposition position. In addition, materials with incompatible electrode potentials can be deposited in one step.

本発明の主な目的は、構造の完全なシード金属化の必要なく、バイアの充填等、高アスペクト比構造の堆積を可能にすることである。磁場は、以前に金属化された表面を越えて、伝導性粒子を方向付けるために利用してよく、これにより、電気接触を形成し、完了まで堆積を継続できる。   The main objective of the present invention is to allow the deposition of high aspect ratio structures, such as via filling, without the need for complete seed metallization of the structure. A magnetic field may be utilized to direct the conductive particles beyond the previously metallized surface, thereby making electrical contact and allowing the deposition to continue until completion.

本発明は、更に、触媒材料によりコーティングされた磁性粒子を備えた触媒に関する。磁場の存在は、触媒の性能を改善することが知られている。粒子上での制御されたコーティング形状は、表面の磁場が更に容易に制御されることを意味する。粒子は、随意的に、粒子と外部コーティングとの間に少なくとも一つの中間層を有し、中間層は、拡散障壁として機能し、磁性粒子が触媒を汚染するのを防止する
本発明のその他の目的、利点、新たな特徴、及び応用性の更なる範囲は、添付図面と併せて、以下の詳細な説明において一部が述べられており、以下を検討することで当業者には一部が明らかとなり、或いは、本発明の実践により学習され得よう。本発明の目的及び利点は、付記した特許請求の範囲において特に指摘した手段及び組み合わせを用いて、実現及び達成し得る。 The invention further relates to a catalyst comprising magnetic particles coated with a catalyst material. The presence of a magnetic field is known to improve the performance of the catalyst. A controlled coating shape on the particles means that the surface magnetic field is more easily controlled. The particles optionally have at least one intermediate layer between the particles and the outer coating, the intermediate layer acting as a diffusion barrier and preventing the magnetic particles from contaminating the catalyst. Additional scope of objects, advantages, new features, and applicability are set forth in part in the following detailed description, in conjunction with the accompanying drawings, and in part will be apparent to those skilled in the art upon consideration of the following. It will become apparent or may be learned by practice of the present invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

添付図面は、明細書に組み込まれ、その一部を形成するものであり、本発明のいくつかの実施形態を例示し、説明と共に、本発明の原理を明らかにする役割を果たす。図面は、本発明の好適な実施形態を例示する目的のものに過ぎず、本発明を限定するものと解釈されるべきではない。   The accompanying drawings, which are incorporated in and form a part of the specification, illustrate several embodiments of the invention and, together with the description, serve to clarify the principles of the invention. The drawings are only for purposes of illustrating the preferred embodiments of the invention and are not to be construed as limiting the invention.

本発明は、コーティング粒子を使用して製造された半田材料に関する。明細書及び請求項全体での使用において、「半田材料」とは、金属フィラ、粒子接合材料、構造接合材料、蝋付け材料、溶接材料、及びその他も意味する。   The present invention relates to a solder material manufactured using coating particles. As used throughout the specification and claims, “solder material” also means metal fillers, particle bonding materials, structural bonding materials, brazing materials, welding materials, and others.

コーティング粉末は、好ましくは、錫、錫／鉛、錫／銀、又は電子部品の接合に適したその他の組成といった、半田付け可能な金属又は合金によって、随意的に電気メッキによってコーティングされた、例えば、ニッケル又は銅の金属元素核を備える。核粉末は、数ミクロン、或いは更にサブミクロンを含む任意のサイズにしてよく、したがって、任意の製造プロセスに適合させることが可能である。核材料は、カプセル化堆積物の融点より高い融点を有するニッケル、銅、又はその他の伝導性粉末にしてよい。半田材料は、共晶を形成してよい。コーティングステップは、凝集なしで達成し得る。コーティング粉末は、必要に応じて、基板に電着させ得る。代替として、コーティング粉末は、従来のフォトステンシルを介してウェーハに印刷可能な、即ち、スクリーン印刷可能な、ペースト又はインクに混合し、例えば、フリップチップボンディング用の強化された球形バンプを作成するためにリフロさせてよい。   The coating powder is preferably coated with a solderable metal or alloy, such as tin, tin / lead, tin / silver, or other composition suitable for joining electronic components, optionally by electroplating, for example A nickel or copper metal element nucleus. The core powder may be any size, including a few microns, or even sub-microns, and thus can be adapted to any manufacturing process. The core material may be nickel, copper, or other conductive powder having a melting point higher than that of the encapsulated deposit. The solder material may form a eutectic. The coating step can be accomplished without agglomeration. The coating powder can be electrodeposited onto the substrate as required. Alternatively, the coating powder can be printed on the wafer via a conventional photo stencil, i.e. screen-printed, mixed with paste or ink, for example to create enhanced spherical bumps for flip chip bonding. You may reflow.

この実施形態において、リフロ中、半田材料は融解し、核粒子全体及び基板表面上を湿潤させて広がり、半田バンプを形成する。固化すると、半田コーティングは、個別の粒子を共に結合させ、基板に接合する。固化したバンプは、埋め込まれた未融解の元素核粒子を含む。図１は、二種類のＦＣＢＧＡパッケージ構成を表しており、図１Ａは、リフロ前のガラスセラミック基板用のバンプを表し、図１Ｂは、リフロ後の同じバンプを示す。図１Ｃは、リフロ前の積層基板上に堆積したバンプを表し、図１Ｄは、エッチング及びリフロ後のバンプを示している。図１Ｃ及び１Ｄは、未融解粒子を備える複合半田バンプを示している。   In this embodiment, during reflow, the solder material melts and wets and spreads over the entire core particle and substrate surface to form solder bumps. When solidified, the solder coating bonds the individual particles together and bonds them to the substrate. The solidified bumps contain embedded unmelted elemental core particles. FIG. 1 shows two FCBGA package configurations, FIG. 1A shows the bumps for the glass ceramic substrate before reflow, and FIG. 1B shows the same bumps after reflow. FIG. 1C shows bumps deposited on the laminated substrate before reflow, and FIG. 1D shows bumps after etching and reflow. 1C and 1D show a composite solder bump with unmelted particles.

結果的に生じる構造は、何らかの粒子を含有しない半田に比べ大幅に高い圧縮及び剪断強度を備えた複合又は凝集材料となる。機械的衝撃、振動、及びその他に対する耐性だけでなく、高温であっても、結果として生じるバンプが半田と基板との熱膨張係数の不一致による剪断応力に耐えられるほどに強いことから、この強化は、信頼性を高める。これにより、アンダフィルの必要性が排除され、コストと製造ステップとが節減される。   The resulting structure is a composite or agglomerated material with significantly higher compressive and shear strength than solder that does not contain any particles. This enhancement is not only resistant to mechanical shock, vibration, and others, but also because the resulting bumps are strong enough to withstand shear stresses due to mismatched thermal expansion coefficients between the solder and the board, even at high temperatures. , Increase reliability. This eliminates the need for underfill and saves costs and manufacturing steps.

この実施形態において、核材料は融解しないが、核粒子とコーティングとの間の反応は存在してもよい。リフロ中、核粒子とコーティングとの間の界面では、それぞれの原子の相互拡散により、固溶体又は金属間化合物が形成されてよい。この拡散は、半田が液体である時に発生する場合があり、結果として、界面の液体では組成上の変化が生じ、この場合、反応は、一時的液相接合として知られている。代替として、半田コーティングの融点未満の温度でリフロが実行される場合、反応は、固体状態拡散接合と呼ばれる。いずれの場合でも、結果として生じる界面化合物は、元の半田コーティングより高い融解温度を有し得るため、特に、全ての半田材料が核材料と反応した場合、材料は、元の半田材料の融点より高い温度での複数のリフロサイクルに耐えることが可能となる。この接合は、半田接合部の強度を劇的に増加させる役割を果たす。複数の元素粉末で構成された従来の半田ペーストは、反応物質の密接ではない接触による不均一性の問題を有する。したがって、こうしたペーストは、事前の不完全な成分の反応により二次的なリフロを受けるため、複数のリフロサイクルに耐えられない。多重リフロ能力は、システムと組み合わせる際にデバイスを更に半田付けし、マザーボードの基板又は電子基板に接合する必要があることから、電子デバイスのレベル１の半田付けにとって重要な態様となる。   In this embodiment, the core material does not melt, but there may be a reaction between the core particles and the coating. During reflow, solid solutions or intermetallic compounds may be formed at the interface between the core particles and the coating by interdiffusion of the respective atoms. This diffusion can occur when the solder is liquid, resulting in a compositional change in the interfacial liquid, in which case the reaction is known as temporary liquid phase bonding. Alternatively, if reflow is performed at a temperature below the melting point of the solder coating, the reaction is referred to as solid state diffusion bonding. In any case, the resulting interfacial compound can have a higher melting temperature than the original solder coating, so that the material is more than the melting point of the original solder material, especially when all the solder material has reacted with the core material. It can withstand multiple reflow cycles at high temperatures. This joint serves to dramatically increase the strength of the solder joint. Conventional solder pastes composed of a plurality of elemental powders have the problem of non-uniformity due to intimate contact of reactants. Therefore, these pastes cannot withstand a plurality of reflow cycles because they undergo secondary reflow due to the reaction of incomplete components in advance. The multiple reflow capability is an important aspect for level 1 soldering of electronic devices because the device needs to be further soldered and bonded to the motherboard or electronic board when combined with the system.

別の実施形態では、リフロ中に融解しない核粒子を使用するのではなく、融解する粉末材料を選択してよく、これにより、リフロ中、コーティングとの合金を形成する。合金は、共晶にしてよい。例えば、銀及び銅粒子が、錫によりコーティングされる。コーティング粒子は、基板に向けてスクリーニングされる。両方の元素金属の温度より高い温度でのリフロ中、共晶合金半田が形成される。こうした合金は公知だが、この方法の利点は、こうした材料を経済的に堆積できることである。多数の合金のためには、電解液の不適合性のため、合金の構成要素を形成する元素粉末のそれぞれを別個のステップで電着させる（即ち、イオン的に送給する）必要があることから、製造時間及びコストが増加する。加えて、各元素を堆積させるためにウェーハを多数のメッキセル間で移動させる必要があるため、既に堆積させた粉末の表面の酸化のリスクが大きくなる。何らかの酸化物の形成は、元素の反応を阻害する。別の方法には、後で反応させる元素多層の蒸着が伴うが、しかしながら、このプロセスは、非常に低速及び高価である。こうした方法は、不完全な反応と反応元素の密接ではない接触とによる最終生産物の不均一な化学量という欠点を有する。別の従来の方法では、事前に合金にした材料を堆積させており、こうした材料は非常に高いリフロ温度を必要とし、半田付け能力を大幅に低減し、高温に耐えられない他のデバイスコンポーネントに悪影響を与える可能性がある。全ての実施形態において、本発明のコーティング粉末は、単一のステップで電着させてよく、これにより、上記の問題を回避し、コスト及び製造時間を低減する。コーティング及び各粉末は常に密接に接触するため、湿潤が大幅に強化され、酸化は起こり得ない。   In another embodiment, rather than using core particles that do not melt during reflow, a powder material that melts may be selected, thereby forming an alloy with the coating during reflow. The alloy may be eutectic. For example, silver and copper particles are coated with tin. The coating particles are screened towards the substrate. During reflow at a temperature higher than the temperature of both elemental metals, eutectic alloy solder is formed. Although such alloys are known, the advantage of this method is that such materials can be deposited economically. For many alloys, due to electrolyte incompatibility, each of the elemental powders that form the alloy components must be electrodeposited (ie, ionically delivered) in a separate step. , Manufacturing time and cost increase. In addition, since it is necessary to move the wafer between a large number of plating cells in order to deposit each element, the risk of oxidation of the surface of the already deposited powder increases. Any oxide formation hinders the reaction of the elements. Another method involves the deposition of elemental multilayers that are subsequently reacted, however, this process is very slow and expensive. Such methods have the disadvantage of non-uniform stoichiometry of the final product due to incomplete reactions and intimate contact of the reactive elements. Another conventional method is to deposit pre-alloyed materials that require very high reflow temperatures, greatly reducing solderability and other device components that cannot withstand high temperatures. May have adverse effects. In all embodiments, the coating powder of the present invention may be electrodeposited in a single step, thereby avoiding the above problems and reducing cost and manufacturing time. Since the coating and each powder are always in intimate contact, wetting is greatly enhanced and no oxidation can occur.

本発明のコーティング粉末は、任意のタイプの相互接続で使用可能であり、例えば、フリップチップ半田バンプ、ワイヤボンド、又はステッチボンドといったレベル１又はチップレベル相互接続、或いは、表面実装又はスルーホール構成を含む従来のプリント回路基板の半田接合部であるレベル２相互接続で使用できる。   The coating powders of the present invention can be used in any type of interconnect, for example, level 1 or chip level interconnects such as flip chip solder bumps, wire bonds, or stitch bonds, or surface mount or through hole configurations. It can be used with level 2 interconnects, which are solder joints of conventional printed circuit boards.

コーティング及び各粉末の化学的及び物理的特性を一致させることで、必要に応じて、パッケージの冷却を強化する高い熱伝導率、及び電流容量又は高いインダクタンスのような改善された電気的特性等、最終的な材料でのその他の望ましい特性を達成できる。更に、粒子の追加により、融解した半田の表面張力が変化するため、高い粒子積載量（即ち、粒子濃度又は密度）において、低いバンプピッチ（即ち、増加したバンプ密度）を達成できる。リフロ中に球形を形成するのではなく、バンプは、球形のように横方向に同じ程度まで広がらない急峻な側面を備えた楕円形状を形成可能であり、これにより、バンプを互いに接近して配置できる。これは図２に例示されており、図２は、図１のリフロ半田バンプに対する粒子積載量の影響を概略的に表している。図２Ａは、図１Ｄと同一であり、粒子積載量を増加させると、バンプ形状は、球形から、狭小な側面を有するものへ変化する（図２Ｂ）。   Matching the chemical and physical properties of the coating and each powder, if necessary, high thermal conductivity to enhance the cooling of the package, and improved electrical properties such as current capacity or high inductance, etc. Other desirable properties in the final material can be achieved. Furthermore, the addition of particles changes the surface tension of the melted solder, so that a low bump pitch (ie, increased bump density) can be achieved at high particle loading (ie, particle concentration or density). Rather than forming a sphere during reflow, the bump can be shaped like an oval with a steep side that does not spread to the same extent in the lateral direction, so that the bumps are placed close together it can. This is illustrated in FIG. 2, which schematically represents the effect of particle loading on the reflow solder bumps of FIG. FIG. 2A is the same as FIG. 1D, and as the particle loading is increased, the bump shape changes from a spherical shape to one having a narrow side surface (FIG. 2B).

加えて、材料の最終的な化学組成は、例えば、純粋な錫等の半田材料のエレクトロマイグレーションのような特性の安定性を強化するために選択できる。これにより、特に、電子コンポーネント全体の障害を発生させることが分かっている固体状態の樹状突起の形成を防止することで、半田接合部の信頼性を増加させる。こうした特性は、半田バンプ、ボンドリング、及びバイアを一部として含む、本発明に従って形成された任意の構造に当てはまる。   In addition, the final chemical composition of the material can be selected to enhance the stability of properties such as electromigration of a solder material such as pure tin. This increases the reliability of the solder joint, particularly by preventing the formation of solid state dendrites known to cause failure of the entire electronic component. These characteristics apply to any structure formed in accordance with the present invention, including solder bumps, bond rings, and vias as part.

磁性を有する核粒子を選択することで、外部磁場を利用して、電着、フォトステンシルバンピング、及びスクリーン印刷の方法を使用することを一部として含め、半田の堆積を強化できる。こうした粒子、或いは粒子を含むペースト又はインクは、より精密に、所望の堆積位置へ正確に方向付けることができる。粒子積載量は、更に正確に制御できる。加えて、ニッケル等の元素又は合金で作成された磁性核粒子の独自の特性は、磁場の強化及びバンプ付きダイの電気試験を使用した新たな製造手法においても重要となる可能性がある。例えば、磁場は、半田材料の表面張力と、湿潤その他の特性とを変更し得る半田内の粉末の空間分布を制御するために、リフロ中に加えてよい。   By selecting magnetic core particles, solder deposition can be enhanced, including the use of external magnetic fields and electrodeposition, photostencil bumping, and screen printing methods. Such particles, or pastes or inks containing particles, can be more precisely directed to the desired deposition location. The particle loading can be controlled more accurately. In addition, the unique properties of magnetic core particles made of elements such as nickel or alloys can be important in new manufacturing techniques using magnetic field enhancement and electrical testing of bumped dies. For example, a magnetic field may be applied during reflow to control the spatial distribution of the powder in the solder that can alter the surface tension, wettability, and other properties of the solder material.

好ましくは磁性を有する粒子の共堆積は、バイア等のその他の微細加工構造の製造プロセス及び最終的な材料特性も改善できる。上記の利点の多くは、こうした他の構造に当てはまる。粒子は、磁性又は非磁性の非コーティング粒子又はコーティング粒子にしてよい。コーティング粒子は、磁気特性が望ましい場合、ニッケル等の磁性核を有してよい。代替として、磁性材料でコーティングされた非磁性核を備えてもよい。磁場を随意的に使用することで、より正確に粒子を所望の堆積位置へ方向付けることができる。更に、異種材料、例えば、大幅に異なる電極電位又は不適合な電解溶液を有するものを、一ステップで共堆積させてよく、時間及び製造コストが節減され、プロセスステップ間で発生する酸化物汚染の可能性が排除される。加えて、堆積材料の粒子積載量は、磁気の支援を用いて、より正確に制御し得る。最終的な材料は、堆積材料のマトリクスに埋め込まれた粒子で構成されてよい。粒子及び／又は粒子上のコーティングは、更なる処理ステップ中に、マトリクス材料と反応してよい。   Co-deposition of preferably magnetic particles can also improve the manufacturing process and final material properties of other microfabricated structures such as vias. Many of the above advantages apply to these other structures. The particles may be magnetic or non-magnetic uncoated particles or coated particles. The coating particles may have magnetic nuclei such as nickel if magnetic properties are desired. Alternatively, non-magnetic nuclei coated with a magnetic material may be provided. By optionally using a magnetic field, the particles can be directed more accurately to the desired deposition location. In addition, dissimilar materials, such as those with significantly different electrode potentials or incompatible electrolyte solutions, may be co-deposited in one step, saving time and manufacturing costs and possible oxide contamination that occurs between process steps. Sex is excluded. In addition, the particle loading of the deposited material can be more accurately controlled using magnetic assistance. The final material may consist of particles embedded in a matrix of deposited material. The particles and / or the coating on the particles may react with the matrix material during further processing steps.

好ましくは、充填物の電着中に、より正確に粒子を所望の位置へ方向付ける磁気の支援により、粒子を共堆積させることで、ＰＶＤ（プラズマ蒸着）によって実行される事前のシード層金属化中に形成するべき完全な膜に関する現在の要件を緩和できる。したがって、バイアの基部を金属のない状態にすることが可能であり、磁場によって引き込まれる粒子は、バイア内へと続くショルダ金属化部と接触して、電流バスをバイアの基部へ延長する。図３は、シリコン又はセラミック基板３００内のバイアの断面を示している。図３Ａは、完全であり、バイアの三次元形状全体の壁を覆うＰＶＤシード金属化部３１０を示している。図３Ｂは、不完全であり、バイアの基部に向かって次第に減少し、基部と、恐らくはバイアの長さの三分の一乃至三分の二とを、シード金属化部が存在しない状態にするＰＶＤ金属化部３２０を有する同じバイア形状を表している。   Pre-seed layer metallization, preferably performed by PVD (plasma deposition), by co-depositing the particles with the aid of magnetism, which more precisely directs the particles to the desired position during the electrodeposition of the filling The current requirements for the complete film to be formed in can be relaxed. It is therefore possible to leave the via base free of metal, and particles drawn by the magnetic field contact the shoulder metallization that continues into the via, extending the current bus to the via base. FIG. 3 shows a cross section of a via in a silicon or ceramic substrate 300. FIG. 3A shows a PVD seed metallization 310 that is complete and covers the walls of the entire three-dimensional shape of the via. FIG. 3B is imperfect and gradually decreases toward the base of the via, leaving the base and possibly one-third to two-thirds of the via length in the absence of seed metallization. The same via shape with PVD metallization 320 is represented.

充填物の電着中に、好ましくは磁気の支援により、伝導性で、好ましくは磁性を有する粒子３３０を後でバイア内へ共堆積させることで、粒子３３０は、非金属化バイアの基部へ電流の流れを延長し、電気的連続性をもたらし、一貫した信頼性及び再現性を有するバイアの電着充填物を提供することから、完全な金属化部は必要なくなる。   During electrodeposition of the filler, particles 330 are preferably co-deposited into the vias later, preferably with magnetic assistance, so that the particles 330 are energized to the base of the non-metallized vias. The complete metallization is not necessary because it provides a via electrodeposition fill that extends the flow of the metal, provides electrical continuity, and has consistent reliability and reproducibility.

粒子を電解質に導入し、好ましくは、磁気的にバイア内へ方向付けることで、バイアの充填速度は、広い範囲の粒子濃度に渡って直線的に加速可能であり、例えば、粒子サイズ及び積載の速度に応じて、６０％の固体濃度により、堆積速度を６０％増加し得る。電着のための粒子の通常の体積比は約１対３だが、その他の比も可能となる。図３Ｃに示したように、結果的な充填物３４０は、完全に緻密化した電着物マトリクス内で区切られた粒子３５０で構成される。こうした粒子を共堆積させることで、プロセスの堆積及び緻密化の両方を加速可能な、より有利な電流条件が形成される。   By introducing the particles into the electrolyte and preferably magnetically orienting them into the via, the via filling rate can be linearly accelerated over a wide range of particle concentrations, eg, particle size and loading Depending on the rate, a solids concentration of 60% can increase the deposition rate by 60%. The usual volume ratio of particles for electrodeposition is about 1: 3, but other ratios are possible. As shown in FIG. 3C, the resulting packing 340 is composed of particles 350 that are separated within a fully densified electrodeposit matrix. Co-depositing such particles creates more advantageous current conditions that can accelerate both process deposition and densification.

図３Ｄによれば、ウェーハ又は基板３６０は、その後、裏側３７０をプラズマエッチングして、基板材料を除去し、ウェーハ基板裏面において、バイア相互接続を介して形成されたバンプ３８０を露出してよい。エッチングの速度と、除去される基板の量とは、ウェーハ裏側の結果的なバンプのアスペクト比及び高さを含む形状を定義する。バイア充填プロセスにおける上記の改良に加え、粒子、好ましくはニッケル粒子の存在は、更に、バイアの熱伝導率の感知可能な改善を提供し、一貫した半田付け可能な表面を提供する。図３の図面は概略的であり、粒子及びバイアの特定の相対的サイズ、或いは特定の粒子濃度を表す意図はないことに留意されたい。   According to FIG. 3D, the wafer or substrate 360 may then plasma etch the back side 370 to remove the substrate material and expose the bumps 380 formed via via interconnects on the back side of the wafer substrate. The rate of etching and the amount of substrate removed defines the shape including the aspect ratio and height of the resulting bump on the backside of the wafer. In addition to the improvements described above in the via filling process, the presence of particles, preferably nickel particles, further provides a appreciable improvement in the thermal conductivity of the via and provides a consistent solderable surface. Note that the drawing of FIG. 3 is schematic and is not intended to represent a specific relative size of particles and vias or a specific particle concentration.

本発明に従って堆積させ得る別の構造は、通常、錫−金共晶半田で構成されるボンドリングである。好ましくは、１乃至２ミクロンのニッケル粒子を錫でコーティングし、金の電解質内で懸濁させ、単一のステップで金と一緒に共堆積させる。具体的なサイズの範囲を開示しているが、構造の特性を最適化するために、任意の粒子サイズを利用してよい。外部磁場の大きさ及び持続時間は、堆積させた構造における充填物の割合及び最終的な組成を部分的に決定する。その後の反応の後、錫−金組成が形成可能であり、好ましくは、８０：２０共晶組成となる。ニッケル粒子は、ボンドリングを機械的に補強する。代替として、同じく所望の共晶組成を製造する目的で、金の電解質中に懸濁させた純粋な錫粒子を、金と共に共堆積させてよい。後者の実施形態において、磁場は、共堆積を支援するために利用されない。   Another structure that can be deposited in accordance with the present invention is a bond ring typically comprised of a tin-gold eutectic solder. Preferably, 1-2 micron nickel particles are coated with tin, suspended in a gold electrolyte and co-deposited with gold in a single step. Although specific size ranges are disclosed, any particle size may be utilized to optimize structural properties. The magnitude and duration of the external magnetic field will in part determine the proportion of filler and the final composition in the deposited structure. After the subsequent reaction, a tin-gold composition can be formed, preferably an 80:20 eutectic composition. The nickel particles mechanically reinforce the bond ring. Alternatively, pure tin particles suspended in a gold electrolyte may be co-deposited with gold, also for the purpose of producing the desired eutectic composition. In the latter embodiment, the magnetic field is not utilized to support co-deposition.

触媒、電子的、又はその他の特性のために、コーティング又は非コーティングの様々な粒子材料を選択することで、本発明は、微細加工プロセス中に、基板に埋め込まれた受動コンポーネントデバイスを作成するために使用できる。こうしたデバイスには、一部として、レジスタ、キャパシタ、及びインダクタが含まれる。粒子、随意的なコーティング、及び電解質材料の選択は、例えば、電子部品、水素貯蔵フィールド、誘導又は磁気トランスデューサの特性を定義するのに有用となり得る。   By selecting various coated or uncoated particulate materials for catalytic, electronic, or other properties, the present invention creates passive component devices embedded in a substrate during a microfabrication process. Can be used for Such devices include, in part, resistors, capacitors, and inductors. The selection of particles, optional coatings, and electrolyte materials can be useful, for example, in defining the properties of electronic components, hydrogen storage fields, induction or magnetic transducers.

実施例−磁気核触媒粒子
コーティング磁気核粉末の使用の例は、一部として燃料電池を含む用途のための電気触媒材料の製造におけるものである。磁気核粉末の使用は、デバイスの製造可能性を改善するだけでなく、効率も強化する。本発明は、好ましくは金属であり、好ましくは白金である触媒材料により、好ましくはＮｉである磁性粒子をコーティングすることを含む。随意的に、ルテニウムのような他の元素を表面に追加し、粒子全体をカプセル化するか、或いは表面を部分的にコーティングして、触媒の機械的、電気化学的、電子的、及び／又は磁気的特性を調整してよい。部分的コーティングは、追加元素の分離した島を備えてよい。ルテニウムは、随意的に酸化させてよい。 Examples-Magnetic Nuclear Catalyst Particles An example of the use of coated magnetic nuclear powder is in the manufacture of electrocatalytic materials for applications that include fuel cells as part. The use of magnetic core powder not only improves device manufacturability, but also enhances efficiency. The present invention comprises coating magnetic particles, preferably Ni, with a catalyst material, preferably a metal, preferably platinum. Optionally, other elements such as ruthenium may be added to the surface to encapsulate the entire particle or partially coat the surface to provide mechanical, electrochemical, electronic, and / or catalytic activity. Magnetic properties may be adjusted. The partial coating may comprise isolated islands of additional elements. Ruthenium may optionally be oxidized.

触媒電極における磁性材料の使用は、改良された触媒特性を発生させる。核粒子の磁気モーメントは、デバイスの効率を改善し、汚染に対する触媒の耐性を高める。電気触媒を磁気粒子の表面に固定して、事実上、距離の分布ではなく、磁性材料から触媒表面までの単一の距離を提供することで、触媒表面における、或いは触媒表面を介した局所的磁場の推定に対する妥当な確実性が提供され、ＣＯ耐性に対する磁気の影響について、定量的な関係を確立できる。これは、既存の技術に対する別の利点となる。   The use of magnetic material in the catalytic electrode generates improved catalytic properties. The magnetic moment of the core particles improves the efficiency of the device and increases the resistance of the catalyst to contamination. By fixing the electrocatalyst to the surface of the magnetic particles, providing a single distance from the magnetic material to the catalyst surface, rather than a distribution of the distance in effect, it can be localized on or through the catalyst surface. Reasonable certainty for the estimation of the magnetic field is provided and a quantitative relationship can be established for the effect of magnetism on CO tolerance. This is another advantage over existing technology.

本発明の一実施形態は、強い自己誘引力を及ぼすＮｄ−Ｆｅ−Ｂ等の磁場の強い材料を利用した時でも、安定した均一な触媒積載量と、活性の高い電極を備えた膜電極組立体（ＭＥＡ）とを提供するために、信頼性の高い予測可能な形でイオノマ膜に投与又は圧入可能な磁性電極材料の製造である。本発明は、優れたＭＥＡ性能と、改質炭化水素からの水素中に存在するＣＯレベルに対する耐性とを提供し、更に、改良された耐摩耗性を提供する。随意的な保護界面層は、核粒子を触媒反応に関して不活性にすることが可能であり、磁場が最も強い各カプセル化磁気粒子に、好ましくはＰｔ及び／又はＰｔ／Ｒｕ触媒層の追加にとって理想的である堅牢な界面を直接提供する。非腐食金属接合層により完全にカプセル化した磁気粒子に貴金属層を予備形成することで、電気触媒は、ＭＥＡを形成する後続の処理ステップに関係なく、磁気材料の表面に可能な限り接近して配置される。保護Ｎｉ層又はＮｉ−Ｐｄ層によるカプセル化のケースでは、優れた耐食性が必要な場合、保護障壁金属も磁性を有し、磁気効果を強化するべきである。   One embodiment of the present invention is a membrane electrode assembly having a stable and uniform catalyst loading amount and a highly active electrode even when a material having a strong magnetic field such as Nd-Fe-B that exerts a strong self-attraction force is used. The production of a magnetic electrode material that can be administered or pressed into an ionomer membrane in a reliable and predictable way to provide a solid (MEA). The present invention provides excellent MEA performance and resistance to CO levels present in hydrogen from modified hydrocarbons, and further provides improved wear resistance. An optional protective interface layer can render the core particles inert with respect to the catalytic reaction and is ideal for each encapsulated magnetic particle with the strongest magnetic field, preferably for the addition of Pt and / or Pt / Ru catalyst layers. Provide a robust interface directly. By pre-forming the noble metal layer on magnetic particles fully encapsulated by the non-corrosive metal bonding layer, the electrocatalyst is as close as possible to the surface of the magnetic material, regardless of subsequent processing steps to form the MEA. Be placed. In the case of encapsulation with a protective Ni layer or Ni—Pd layer, if excellent corrosion resistance is required, the protective barrier metal should also be magnetic and enhance the magnetic effect.

本発明の好適な実施形態による、コーティング粒子の製造プロセスの例は、次の通りである。   An example of a process for producing coated particles according to a preferred embodiment of the present invention is as follows.

１．電気メッキ水溶液中で処理するのに適した、利用可能な金属及び金属酸化物粉末から、最適な粒子形状を使用する。基準には、磁気飽和、ダイポールの感受性に関する形状のアスペクト比、サイズ／分布、及び表面形態が含まれるべきである。   1. The optimum particle shape is used from available metal and metal oxide powders suitable for processing in an aqueous electroplating solution. Criteria should include magnetic saturation, shape aspect ratio with respect to dipole sensitivity, size / distribution, and surface morphology.

２．腐食環境に耐えられる適切な障壁コート金属を決定する。凝集のない完全な粒子のカプセル化を達成するのに必要な堆積物の重量増加を、酸性試験により検証する。   2. Determine the appropriate barrier coat metal that can withstand the corrosive environment. The sediment weight increase necessary to achieve complete particle encapsulation without agglomeration is verified by an acid test.

３．報告された、以前の触媒積載量に基づいて、白金の同等の比重量を計算する。３乃至１０重量パーセントの白金を提供するために、カプセル化磁性粒子上での非常に薄く均一な白金コーティングの電着のためのパラメータを決定する。   3. Calculate the equivalent specific weight of platinum based on the previous catalyst loading reported. In order to provide 3 to 10 weight percent platinum, parameters for electrodeposition of a very thin and uniform platinum coating on the encapsulated magnetic particles are determined.

４．高い度合いの核生成と、粒子表面上でのルテニウムの小さな島の形成とを発生させる条件下での、白金にコーティングされたカプセル化金属粒子上における部分的表面被覆となるルテニウムの随意的な堆積。   4). Optional deposition of ruthenium as a partial surface coating on encapsulated metal particles coated with platinum under conditions that generate a high degree of nucleation and the formation of small islands of ruthenium on the particle surface .

５．安定した均一な触媒層を、膜又はガス拡散電極に付与し、ナフィオン１１２を使用してＭＥＡを形成し、活性の高い電極層を実証する。   5). A stable and uniform catalyst layer is applied to the membrane or gas diffusion electrode and Nafion 112 is used to form the MEA to demonstrate a highly active electrode layer.

６．ナフィオンポリマと混合して、炭素フェルトに取り付けた、磁気的に支持される粒子の均一層の堆積。   6). Deposition of a homogeneous layer of magnetically supported particles mixed with Nafion polymer and attached to a carbon felt.

磁気粒子の化学的及び物理的安定性を確保するために、我々は、腐食しない保護障壁によってカプセル化された磁気ビーズを提供する回転式貫流電気メッキ装置を使用する電着に基づいた、不活性金属カプセル化手法を使用する。カプセル化プロセスは、数ミクロン乃至サブミクロンの範囲の直径である粒子にコーティングを電解付与するために特別に設計された、特許取得の回転式電気メッキ装置を使用する電着に基づくものである。こうしたプロセスの一例は、２００１年５月３１日提出の米国特許第０９／８７２，２１４号「電気化学的プロセス及び装置によるサブミクロン及びナノサイズ粒子のカプセル化」において開示されており、これは出典を明示することによりその開示内容全体を本願明細書の一部とする。このプロセスは、本発明の実施形態のいずれかによるコーティング粒子の製造に応用できる。非常に耐久性の高い白金又はパラジウム／ニッケル合金コーティングをニッケルアンダコートに付与及びアニールして、磁性材料がセルに浸出するのを防ぎ、白金又はルテニウム触媒元素を、磁場が最も高くなる可能性のある位置で表面に電着し得る。このアプローチは、ＰＥＭ燃料電池、ＰＥＭ電解装置、又は炭化水素改質装置におけるイオノマに基づくポリマとして不安定であることが知られているポリスチレンより堅牢で、化学的に不活性な層を提供し、ＭＥＡ内の磁性粒子の有益な効果に関与する重要な微細構造の開発を進展させる。この方法は、材料の一体化された合成物を提供し、電気触媒及び磁気材料を混合する技術による不確実性を軽減する。   In order to ensure the chemical and physical stability of magnetic particles, we are inert, based on electrodeposition using a rotary once-through electroplating device that provides magnetic beads encapsulated by a protective barrier that does not corrode Use metal encapsulation techniques. The encapsulation process is based on electrodeposition using a patented rotary electroplating apparatus specially designed for the electro-application of coatings to particles with diameters ranging from a few microns to sub-microns. An example of such a process is disclosed in US patent application Ser. No. 09 / 872,214 filed May 31, 2001, "Encapsulation of submicron and nano-sized particles by electrochemical processes and equipment" The entire disclosure of which is incorporated herein by reference. This process can be applied to the production of coated particles according to any of the embodiments of the present invention. A very durable platinum or palladium / nickel alloy coating is applied and annealed to the nickel undercoat to prevent the magnetic material from leaching into the cell and the platinum or ruthenium catalytic element can be the highest in the magnetic field. It can be electrodeposited on the surface at a certain position. This approach provides a more robust and chemically inert layer than polystyrene known to be unstable as an ionomer-based polymer in PEM fuel cells, PEM electrolyzers, or hydrocarbon reformers, Advances the development of important microstructures that contribute to the beneficial effects of magnetic particles in MEAs. This method provides an integrated composite of materials and reduces the uncertainty due to the technique of mixing electrocatalysts and magnetic materials.

粉末カプセル化プロセスに関する回転式貫流電着は、遠心力を利用して、電解陰極接点に対して、水溶液中のバルク材を密集させる。粒子材料は、上部開口部を介して積載され、メッキセルは、陰極接点に対して粉末を遠心力で投与する上で十分に高いｒｐｍで回転させる。電気メッキ溶液は、浸漬した陽極を介して回転セルの上部開口部において継続的に導入され、セルを通って流動し、ドーム形の上部陰極接点リングと、基部プレートとの間で層を成す焼結多孔性プラスチックリングを介して退出する。電気メッキは、周期的な停止及び／又は反対回転と、セルに対するＤＣ電源の連続的な切り替えとのサイクルにより実行され、均一な被覆と凝集（ブリッジング）の予防とのために粒子位置を循環させる。   Rotary through-flow electrodeposition for the powder encapsulation process utilizes centrifugal force to concentrate bulk material in aqueous solution against the electrolytic cathode contact. The particulate material is loaded through the top opening and the plating cell is rotated at a sufficiently high rpm to dispense the powder to the cathode contact with centrifugal force. The electroplating solution is continuously introduced in the upper opening of the rotating cell through the immersed anode, flows through the cell, and forms a layer between the dome-shaped upper cathode contact ring and the base plate. Exit through the perforated plastic ring. Electroplating is performed by cycling between periodic stops and / or counter-rotations and continuous switching of DC power to the cell and circulates through the particle locations for uniform coating and prevention of bridging. Let

装置を陰極モードではなく陽極において動作させるために、陽極と陰極とは随意的に切り替え可能である。ノズルと、陽極（陽極は異なる金属の堆積を提供するために容易に取り外し及び切り替え可能である）と、排出ポートとの連続的な位置決めは、化学物質を混合することなく、メッキ中の材料を複数のステップの化学プロセスに露出する方法を提供する。更に、メッキされたワークの継続的な浸漬は、従来のバレルメッキプロセスにおいてタンクからタンクへ移動する時に基板上で通常発生する酸化を防止する。継続的浸漬は、好ましくは、プロセスの全ステップを同じセルにおいて実行することで達成される。化学溶液は、各化学溶液の個別の循環のために、多孔性リングを介して、適切な返送排出部へ連続的に戻される。その後、高速回転中に濯ぎ水を導入することで、化学溶液は、異なる比重量により、最低限の希釈で交換される。その後、後続のステップが実行される。   In order to operate the device in the anode rather than in the cathode mode, the anode and cathode can be optionally switched. The continuous positioning of the nozzle, the anode (the anode can be easily removed and switched to provide a different metal deposit), and the discharge port allows the material being plated to be mixed without mixing chemicals. A method of exposing to a multi-step chemical process is provided. Furthermore, the continuous immersion of the plated workpiece prevents oxidation that normally occurs on the substrate when moving from tank to tank in a conventional barrel plating process. Continuous soaking is preferably accomplished by performing all steps of the process in the same cell. The chemical solution is continuously returned to the appropriate return discharge through the porous ring for individual circulation of each chemical solution. Subsequently, by introducing rinsing water during high speed rotation, the chemical solution is exchanged with minimal dilution due to different specific weights. Thereafter, subsequent steps are performed.

個別の粒子のニッケルメッキによる電解カプセル化の好適なセルプロセスフローは（一例として）次の通りである。   A suitable cell process flow for electrolytic encapsulation by nickel plating of individual particles is (as an example) as follows.

１．伝導性粉末の積載
２．濯ぎ
３．高温浸漬
４．開始／停止サイクルによるニッケル電気メッキ
５．濯ぎ
６．高温濯ぎ
７．真空乾燥
別の実施形態によれば、回転式貫流電着手法を使用して、酸化鉄（フェライト）粉末をカプセル化し、化学的に不活性の磁石核を形成し、その後、磁石核は、ニッケル障壁上に堆積させた白金層を備えた不活性永久磁石ビーズにする。この実施形態のプロセスステップは、次の通りである。 1. Loading of conductive powder 2. Rinse High temperature immersion 4. Nickel electroplating with start / stop cycle 5. Rinse 6. Hot rinsing Vacuum Drying According to another embodiment, a rotary once-through electrodeposition technique is used to encapsulate iron oxide (ferrite) powder to form chemically inert magnet nuclei, after which the magnet nuclei are nickel Inert permanent magnet beads with a platinum layer deposited on the barrier. The process steps of this embodiment are as follows.

直径３乃至５μｍの粒子サイズ範囲の金属合金粉末を使用し、０．２ａｍｐｓ／ｄｍ２未満のアンペア密度でスルファミン酸ニッケル溶液において電気メッキする
次に、更なる処理のために、この材料を濯いで、真空オーブンで乾燥させる。 Electroplating in a nickel sulfamate solution at an ampere density of less than 0.2 amps / dm 2 using a metal alloy powder with a particle size range of 3-5 μm in diameter. Next, the material is rinsed for further processing, Dry in a vacuum oven.

全体のアンペア時要件は、ニッケルを堆積させるために確立された物理定数を使用して、重量増加のパーセンテージによって制御され、０．９１３０８アンペア時により、二価のニッケル金属１グラムが堆積する。   The overall ampere hour requirement is controlled by the percentage of weight gain using the physical constant established to deposit nickel, with 0.91308 ampere hours depositing 1 gram of divalent nickel metal.

耐化学性及び不活性を保証する重量増加のパーセンテージを決定した後、約０．４ｍｇ／ｃｍ２未満の量での活性触媒の比重量を計算することで白金の重量増加を決定する。経験則として、比表面積は、粒子半径の１０倍の増加に対して、約三分の一だけ低下するため、直径１乃至５ミクロンの磁性支持部に対して２０ミクロン未満の触媒層の厚さを維持するには、幾分低いＰｔ及びＲｕ積載量が必要となり得る。   After determining the percentage of weight gain that ensures chemical resistance and inertness, the weight gain of platinum is determined by calculating the specific weight of the active catalyst in an amount less than about 0.4 mg / cm2. As a rule of thumb, the specific surface area decreases by about one third for a 10-fold increase in particle radius, so the thickness of the catalyst layer is less than 20 microns for a magnetic support of 1 to 5 microns in diameter. Somewhat lower Pt and Ru loading may be required to maintain

この付与当量は、白金金属を電着させるための物理定数によって制御され、０．５４９５７アンペア時により、四価の白金金属１グラムが堆積する。   This applied equivalent is controlled by a physical constant for electrodepositing platinum metal, and 1 gram of tetravalent platinum metal is deposited at 0.54957 amp hours.

結果的に生じる電気メッキ粒子は、完全で均一なＰｔ堆積を検証するために、走査型電子顕微鏡と、Ｐｔ表面被覆率を測定する電気メッキ白金堆積物のＥＰＭＡマッピングとを使用して検査される。Ｎｉカプセル化したフェライトに基づく磁性材料が必要なものより低い安定性を示す場合、異なる合金を障壁層として使用してよく、或いは、貴金属を高い積載量で付与してよく、或いは、Ｎｉ−Ｆｅ又はＡｌ−Ｎｉ−Ｃｏ等、代替の磁性材料を使用してよい。   The resulting electroplated particles are inspected using a scanning electron microscope and EPMA mapping of the electroplated platinum deposit to measure Pt surface coverage to verify complete and uniform Pt deposition. . If a Ni-encapsulated ferrite-based magnetic material exhibits lower stability than is necessary, a different alloy may be used as a barrier layer, or a precious metal may be applied at a higher loading, or Ni-Fe Alternatively, alternative magnetic materials such as Al—Ni—Co may be used.

コーティング粒子が設計仕様を満たすと判断した後、粒子は、アルニコ及びバリウムフェライト磁性材料を飽和可能な、中間エネルギ（４４０ジュール）低電圧コンデンサ放電式マグネタイザにより、粉末として永久磁石にすることができる。   After determining that the coated particles meet the design specifications, the particles can be made into permanent magnets as powders with an intermediate energy (440 joule) low voltage capacitor discharge magnetizer capable of saturating alnico and barium ferrite magnetic materials.

この実施形態にしたがって製造された通常直径３乃至５μｍのコーティング粒子は、図４において、概略的に断面が図示されている。粒子は、磁気を帯びており、陰極又は陽極で触媒電極として配置するために、インクに混合する準備ができている。粒子は、用途の要件に応じて、サブミクロンから百ミクロン超まで、任意の直径にしてよいことに留意されたい。   A coating particle with a typical diameter of 3-5 μm produced according to this embodiment is schematically shown in cross section in FIG. The particles are magnetic and are ready to be mixed with ink for placement as a catalytic electrode at the cathode or anode. Note that the particles may be any diameter, from sub-micron to over a hundred microns, depending on the requirements of the application.

粒子サイズの分布、形状、及び多孔性の度合いは、複合ＢＥＴによって判定してよく、エネルギ分散型Ｘ線分析と組み合わせた走査型電子顕微鏡（ＳＥＭ）を使用して、触媒堆積の深度と、付与した白金触媒層の純度とを確認してよい。   Particle size distribution, shape, and degree of porosity may be determined by composite BET, using a scanning electron microscope (SEM) in combination with energy dispersive X-ray analysis and depth of catalyst deposition. The purity of the platinum catalyst layer thus obtained may be confirmed.

コーティングの品質は、核から鉄が浸出するかを判定するために、硝酸等の酸の中に粒子を配置することで評価される。粒子が完全な状態を維持し、溶液の顕著な黄色化が観察されない場合、粒子は、１５％までの積載量で、ガラス状炭素電極上のナフィオン膜に組み込まれる。   The quality of the coating is assessed by placing the particles in an acid such as nitric acid to determine if iron leaches from the core. If the particles remain intact and no significant yellowing of the solution is observed, the particles are incorporated into the Nafion membrane on the glassy carbon electrode with a loading of up to 15%.

次に、触媒を電極に付与する必要がある。標準的なアプローチである電極に対する触媒層の直接付与は、大量生産プロセスの要求に適合することから、商業的な観点から魅力的となる。非接着ベラムに最初に投与したインク層のデカール転写のような、実験室において考案された方法は、現実の世界ではコストが高すぎる可能性がある。一方、多孔性ガス拡散電極への触媒溶液の直接的なブラシ塗布のような単純な付与方法は、定義が不明確であり、再現可能な形で実行して、最良の度合いの積載量、浸透、及び均一性を得るのが困難となる可能性がある。単純な直接的付与方法では、狭小なサイズ分布が関与する時、相対的粒子サイズの一致によって導かれる、細孔内への粒子の自発的な自己集合を発生させることが可能である。触媒層は、ＰＥＭ層と接触する触媒粒子の緻密層を形成するために、Ｌｅｄｄｙら、前掲の方法に従った形のように、本文献において説明された市販のソースから取得された膜又はカーボン紙電極上で、インクとして堆積させてよい。触媒層の厚さ及び均一性に関する厳しい許容誤差は、ナフィオンの濃度によって制御されるインク溶液の粘性を制御することで達成し得る。   Next, it is necessary to apply a catalyst to the electrode. Direct application of the catalyst layer to the electrode, which is a standard approach, is attractive from a commercial point of view because it meets the requirements of mass production processes. Methods devised in the laboratory, such as decal transfer of an ink layer first applied to a non-adhering vellum, can be too costly in the real world. On the other hand, simple application methods, such as direct brush application of catalyst solution to porous gas diffusion electrodes, are undefined and perform in a reproducible way to achieve the best loading and penetration And it may be difficult to obtain uniformity. In a simple direct application method, when a narrow size distribution is involved, it is possible to generate spontaneous self-assembly of particles into the pores, guided by relative particle size agreement. The catalyst layer is a membrane or carbon obtained from a commercial source described in this document, such as in a form according to Leddy et al., Supra, to form a dense layer of catalyst particles in contact with the PEM layer. It may be deposited as ink on a paper electrode. Tight tolerances on catalyst layer thickness and uniformity can be achieved by controlling the viscosity of the ink solution, which is controlled by the concentration of Nafion.

触媒層のスラリは、微細孔層が形成された電極上でテープキャスティングによってコーティングされた溶媒置換ナフィオン溶液において、陽極のためのカーボンブラックＶｕｌｃａｎ ＸＣ７２Ｒにより触媒コーティング磁性粒子を分散させることで準備してよい。粒子の分布は、キャスティング面の裏側の強い磁場によって保証される。   A catalyst layer slurry may be prepared by dispersing catalyst coated magnetic particles with carbon black Vulcan XC72R for the anode in a solvent-substituted Nafion solution coated by tape casting on an electrode with a microporous layer formed. . Particle distribution is ensured by a strong magnetic field behind the casting surface.

本発明の利点の一つは、ＭＥＡ上で粒子の単層を堆積させる際に磁場を使用する能力である。これにより、表面に位置しない白金が最小化又は排除され、したがって、フローストリームと直接的に接触しなくなり、デバイスのコストは大幅に低減される。加えて、磁場は、スクリーン印刷中に、触媒粒子の堆積を方向付け、フローストリームが従うパターンのみに限定するのに使用してよい。したがって、粒子は、使用されない場所には堆積せず、ここでもコストが劇的に低減される。本実施形態では、堆積方法は、好ましくはスクリーン印刷である。   One advantage of the present invention is the ability to use a magnetic field in depositing a monolayer of particles on the MEA. This minimizes or eliminates platinum that is not on the surface, and thus is not in direct contact with the flow stream, greatly reducing the cost of the device. In addition, the magnetic field may be used during screen printing to direct the deposition of catalyst particles and limit it to only the pattern that the flow stream follows. Thus, the particles do not accumulate where they are not used, and again the cost is dramatically reduced. In the present embodiment, the deposition method is preferably screen printing.

燃料電池に加えて、本発明は、充電式電池を含む電池、水素に基づくエネルギ発生装置、電子機器、及びＭＥＭＳに応用可能であり、充電サイクルの迅速化、長寿命、高出力、及び小型化を実現する。   In addition to fuel cells, the present invention is applicable to batteries, including rechargeable batteries, hydrogen-based energy generators, electronic devices, and MEMS, with faster charge cycles, longer life, higher output, and smaller size. To realize.

本発明の更なる実施形態は、多層又は階層組成を形成することであり、一つの層には、ターゲット材料を共堆積させ、その後、反応材料と共に第二の層を共堆積させることが可能であり、基板上に堆積した固体電池フィールドを形成する能力を提供する。階層化層を堆積させる能力を有することで、燃料電池膜を含む多くの電気化学デバイスは、組成の化学物質がこの分野の通常の電気化学セルの対極特性を示すように選択された層状の組成で製造できる。   A further embodiment of the present invention is to form a multilayer or hierarchical composition, where one layer can be co-deposited with a target material and then a second layer can be co-deposited with the reactive material. Yes, providing the ability to form a solid state battery field deposited on a substrate. By having the ability to deposit layered layers, many electrochemical devices, including fuel cell membranes, have a layered composition selected so that the chemicals in the composition exhibit the counter electrode characteristics of conventional electrochemical cells in the field. Can be manufactured.

以上、本発明について好適な実施形態を特に参照して詳細に説明してきたが、その他の実施形態も同じ結果を達成し得る。本発明の変更及び変形は当業者には自明であり、本発明はこうした全ての変形例及び均等物を包含するものである。上で引用した全ての特許及び刊行物の開示内容全体は、出典を明示することにより本願明細書の一部とする。   While the invention has been described in detail with particular reference to preferred embodiments, other embodiments can achieve the same results. Modifications and variations of the present invention will be apparent to those skilled in the art, and the present invention includes all such variations and equivalents. The entire disclosure of all patents and publications cited above are hereby incorporated by reference.

図１Ａ〜図１Ｄは、リフロ前後のＦＣＢＧＡパッケージ構成を示す図1A to 1D are diagrams showing FCBGA package configurations before and after reflow. 図２Ａ〜図２Ｂは、バンプ形状に対する粒子積載量の影響を示す図2A to 2B are diagrams showing the influence of the particle loading amount on the bump shape. 図３Ａは、バイアのＰＶＤシード金属化部を示す図、図３Ｂ〜３Ｄは、本発明に従って製造されたバイアの部分的ＰＶＤシード金属化部と、その後の充填及びエッチングとを示す図3A shows a PVD seed metallization of a via, and FIGS. 3B-3D show a partial PVD seed metallization of a via made in accordance with the present invention followed by filling and etching. 内部保護層を備えたコーティング触媒粉末の概略断面図Schematic cross section of coating catalyst powder with internal protective layer

Claims (37)

半田接合部を形成する方法であって、
少なくとも一つのコーティングを表面に備えた粒子を堆積させるステップと、
前記コーティングを少なくとも部分的に融解させるために前記粒子をリフロするステップと、を備え、これにより、実質的に連続した固化半田材料を形成する方法。 A method of forming a solder joint,
Depositing particles with at least one coating on the surface;
Reflowing the particles to at least partially melt the coating, thereby forming a substantially continuous solidified solder material. 前記堆積させるステップは、電着、電気泳動、電気メッキ、蒸着、スクリーン印刷、及びフォトステンシルバンピングで構成されたグループから選択されたプロセスによって堆積させるステップを備える、請求項１記載の方法。   The method of claim 1, wherein the depositing comprises depositing by a process selected from the group consisting of electrodeposition, electrophoresis, electroplating, evaporation, screen printing, and photostencil bumping. 前記堆積させるステップは、前記粒子をペースト又はインクに混合するステップを備える、請求項１記載の方法。   The method of claim 1, wherein the depositing comprises mixing the particles with a paste or ink. 前記堆積させるステップは、不適合な電極電位を備えた少なくとも二つの材料を一つの堆積ステップで電着させるステップを備える、請求項１記載の方法。   The method of claim 1, wherein the depositing comprises electrodepositing at least two materials with incompatible electrode potentials in one deposition step. 前記半田材料は、固化マトリクス内の未融解粒子を備える、請求項１記載の方法。   The method of claim 1, wherein the solder material comprises unmelted particles in a solidified matrix. 前記未融解粒子は、前記半田材料の少なくとも一つの強度を増加させる、請求項５記載の方法。   The method of claim 5, wherein the unmelted particles increase at least one strength of the solder material. 前記強度は、剪断強度及び圧縮強度で構成されたグループから選択される、請求項６記載の方法。   The method of claim 6, wherein the strength is selected from the group consisting of shear strength and compressive strength. 前記半田材料は、前記未融解粒子によって強化される、請求項６記載の方法。   The method of claim 6, wherein the solder material is strengthened by the unmelted particles. 前記リフロするステップは、合金を形成するステップを備える、請求項１記載の方法。   The method of claim 1, wherein the reflowing step comprises forming an alloy. 前記リフロするステップは、前記粒子の前記コーティングの実質的に全てを含む合金を形成するステップを備える、請求項９記載の方法。   The method of claim 9, wherein the reflowing step comprises forming an alloy that includes substantially all of the coating of the particles. 前記合金は、前記コーティングより実質的に高い融解温度を有する、請求項１０記載の方法。   The method of claim 10, wherein the alloy has a substantially higher melting temperature than the coating. 前記半田材料は、実質的に均一な化学量の分布を含む、請求項９記載の方法。   The method of claim 9, wherein the solder material comprises a substantially uniform distribution of stoichiometry. 前記半田材料は、組成において実質的に均一である、請求項１２記載の方法。   The method of claim 12, wherein the solder material is substantially uniform in composition. 前記堆積させるステップは、前記粒子の濃度を制御するステップを備え、これにより、基板表面に平行な方向での前記半田接合部のサイズを低減する、請求項１記載の方法。   The method of claim 1, wherein the depositing comprises controlling the concentration of the particles, thereby reducing the size of the solder joint in a direction parallel to the substrate surface. 更に、前記基板上の半田接合部のピッチを減少させるステップを備える、請求項１４記載の方法。   The method of claim 14, further comprising reducing a pitch of solder joints on the substrate. 前記粒子は、磁性を有する、請求項１記載の方法。   The method of claim 1, wherein the particles are magnetic. 前記堆積させるステップは、少なくとも一つの外部磁場により、粒子積載量を制御するステップを備える、請求項１６記載の方法。   The method of claim 16, wherein the depositing comprises controlling particle loading by at least one external magnetic field. 前記堆積させるステップは、少なくとも一つの外部磁場により、堆積位置を制御するステップを備える、請求項１６記載の方法。   The method of claim 16, wherein the depositing comprises controlling the deposition position with at least one external magnetic field. 前記リフロするステップは、少なくとも一つの外部磁場により、前記半田接合部内の粒子の分布を制御するステップを備える、請求項１６記載の方法。   The method of claim 16, wherein the reflowing step comprises controlling the distribution of particles in the solder joint with at least one external magnetic field. 基板上に堆積させる前にコーティングされた粒子を備える半田材料。   A solder material comprising particles coated before being deposited on a substrate. 粒子を共堆積させる方法であって、
懸濁液中で前記粒子を懸濁させるステップと、
前記流体に少なくとも一つの磁場を付加するステップと、
前記懸濁液の少なくとも一つの構成要素と共に前記粒子を共堆積させるステップと、
所望の構造を形成するステップと、を備える方法。 A method for co-depositing particles comprising:
Suspending the particles in suspension;
Applying at least one magnetic field to the fluid;
Co-depositing the particles with at least one component of the suspension;
Forming a desired structure. 前記付加するステップは、前記粒子の少なくとも一つの堆積位置を制御するステップを備える、請求項２１記載の方法。   The method of claim 21, wherein the adding comprises controlling at least one deposition location of the particles. 前記付加するステップは、粒子積載量を制御するステップを備える、請求項２１記載の方法。   The method of claim 21, wherein the adding step comprises controlling a particle load. 前記粒子は、磁性を有する、請求項２１記載の方法。   The method of claim 21, wherein the particles are magnetic. 前記粒子は、少なくとも一つのコーティングにより覆われている、請求項２２記載の方法。   24. The method of claim 22, wherein the particles are covered with at least one coating. 前記コーティングは、磁性を有する、請求項２５記載の方法。   26. The method of claim 25, wherein the coating is magnetic. 前記懸濁させるステップは、前記粒子を電解液中で懸濁させるステップを備える、請求項２１記載の方法。   The method of claim 21, wherein the suspending comprises suspending the particles in an electrolyte. 前記共堆積させるステップは、不適合な電極電位を備えた少なくとも二つの材料を一つの堆積ステップで共堆積させるステップを備える、請求項２７記載の方法。   28. The method of claim 27, wherein the co-depositing step comprises co-depositing at least two materials with incompatible electrode potentials in one deposition step. 前記懸濁させるステップは、前記粒子をインク又はペースト内に懸濁させるステップを備える、請求項２１記載の方法。   The method of claim 21, wherein the suspending comprises suspending the particles in an ink or paste. 前記形成するステップは、バイアを充填するステップを備える、請求項２２記載の方法。   23. The method of claim 22, wherein the forming step comprises filling a via. 前記形成するステップは、粒子の積載量を制御することで充填速度を加速するステップを備える、請求項３０記載の方法。   32. The method of claim 30, wherein the forming comprises accelerating a filling rate by controlling a particle load. 前記形成するステップは、更に、少なくとも一つの外部磁場により、粒子位置を制御するステップを備え、これにより、事前シード金属化部が前記バイア表面全体には存在しない状態で、前記バイア内での充填電着を可能にする、請求項３０記載の方法。   The forming step further comprises the step of controlling the particle position by means of at least one external magnetic field, whereby filling in the via with no pre-seed metallization present on the entire via surface. 31. A method according to claim 30, which enables electrodeposition. バイアを作成する方法であって、
前記バイアの表面の一部のみにシード金属化部を提供するステップと、
伝導性粒子を備える材料により前記バイアを充填するステップと、を備える方法。 A method of creating a via,
Providing a seed metallization on only a portion of the surface of the via;
Filling the via with a material comprising conductive particles. バイアの表面を部分的にのみコーティングするシード金属化層を備える前記バイア。   Said via comprising a seed metallization layer which only partially coats the surface of the via. 少なくとも一つの触媒材料によりコーティングされた磁気粒子を備える触媒。   A catalyst comprising magnetic particles coated with at least one catalyst material. 請求項３５の前記触媒を使用して堆積させた少なくとも一つの表面層を備える電極。   36. An electrode comprising at least one surface layer deposited using the catalyst of claim 35. 更に、前記粒子の第一のコーティングを備え、当該第一のコーティングは、前記粒子を含む元素の前記触媒材料への拡散を防止するために安定した障壁を備える、請求項３５記載の触媒。

36. The catalyst of claim 35, further comprising a first coating of the particles, the first coating comprising a stable barrier to prevent diffusion of elements comprising the particles into the catalyst material.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016015312A (en) * 2014-06-11 2016-01-28 積水化学工業株式会社 Conductive particle, method of producing conductive particle, conductive material and connection structure
KR20210086519A (en) * 2019-12-31 2021-07-08 덕산하이메탈(주) Solder ball and the manufacturing method thereof

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060011487A1 (en) * 2001-05-31 2006-01-19 Surfect Technologies, Inc. Submicron and nano size particle encapsulation by electrochemical process and apparatus
TW200533791A (en) * 2004-02-04 2005-10-16 Surfect Technologies Inc Plating apparatus and method
US20100291415A1 (en) * 2004-07-15 2010-11-18 Johna Leddy Methods for increasing carbon monoxide tolerance in fuel cells
US7524351B2 (en) * 2004-09-30 2009-04-28 Intel Corporation Nano-sized metals and alloys, and methods of assembling packages containing same
JP4564343B2 (en) * 2004-11-24 2010-10-20 大日本印刷株式会社 Manufacturing method of through hole substrate filled with conductive material
US20070007983A1 (en) * 2005-01-06 2007-01-11 Salmon Peter C Semiconductor wafer tester
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
US20070023923A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Flip chip interface including a mixed array of heat bumps and signal bumps
US7704919B2 (en) * 2005-08-01 2010-04-27 Brookhaven Science Associates, Llc Electrocatalysts having gold monolayers on platinum nanoparticle cores, and uses thereof
US7586747B2 (en) 2005-08-01 2009-09-08 Salmon Technologies, Llc. Scalable subsystem architecture having integrated cooling channels
US20070023889A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Copper substrate with feedthroughs and interconnection circuits
DE102005042109A1 (en) * 2005-09-05 2007-03-08 Siemens Ag Method for producing a metal powder and an electrically insulating plastic composite material, plastic composite material and electronic component
JP5119738B2 (en) * 2007-05-18 2013-01-16 トヨタ自動車株式会社 Electrode catalyst for alkaline fuel cell, alkaline fuel cell, and method for forming electrode catalyst for alkaline fuel cell
US8009442B2 (en) * 2007-12-28 2011-08-30 Intel Corporation Directing the flow of underfill materials using magnetic particles
EP2103719A1 (en) * 2008-03-18 2009-09-23 Technical University of Denmark A method for producing a multilayer structure
JP5430093B2 (en) * 2008-07-24 2014-02-26 デクセリアルズ株式会社 Conductive particles, anisotropic conductive film, joined body, and connection method
US20100031501A1 (en) * 2008-08-08 2010-02-11 Napra Co., Ltd. Method for filling through hole or non-through hole formed on board with filler
ITMI20081734A1 (en) * 2008-09-30 2010-04-01 Consiglio Nazionale Ricerche SPACIOUSLY CONTROLLED INCORPORATION OF A PARTICLE MICROMETRIC OR NANOMETRIC SCALE IN A CONDUCTIVE SURFACE LAYER OF A SUPPORT.
US20100096754A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor module, and method for fabricating the semiconductor package
TWI357830B (en) * 2009-05-08 2012-02-11 Ind Tech Res Inst Magnetic catalyst and method for manufacturing the
WO2011106421A2 (en) * 2010-02-24 2011-09-01 Ramirez Ainissa G Low melting temperature alloys with magnetic dispersions
US8348139B2 (en) * 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
US9620469B2 (en) 2013-11-18 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming post-passivation interconnect structure
EP2643851A1 (en) * 2010-11-22 2013-10-02 Fischer, Andreas A method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device
US8641845B2 (en) 2011-01-13 2014-02-04 Siemens Energy, Inc. Method of determining bond coverage in a joint
WO2012118476A1 (en) * 2011-02-28 2012-09-07 Hewlett-Packard Development Company L.P. Coating particles
GB2509888B (en) * 2012-09-17 2016-05-11 Nano Resources Ltd Magnetic structures
KR101284363B1 (en) * 2013-01-03 2013-07-08 덕산하이메탈(주) Metal core solder ball and heat dissipation structure of semiconductor device using the same
GB2510228B (en) 2013-11-19 2015-12-02 Peacekeeper International Ltd Electromagnetic data storage devices
CN104465583A (en) * 2014-12-09 2015-03-25 三星半导体(中国)研究开发有限公司 Ball grid array packaging piece and method for installing ball grid array packaging piece on substrate
US9721855B2 (en) 2014-12-12 2017-08-01 International Business Machines Corporation Alignment of three dimensional integrated circuit components
GB201600214D0 (en) * 2016-01-06 2016-02-17 Univ Coventry Material deposition in a magnetic field
CN106052197B (en) * 2016-05-30 2019-04-02 常州市常蒸热交换器科技有限公司 Plate evaporator and preparation method thereof
US10861629B1 (en) 2017-03-03 2020-12-08 Apple Inc. Solid state deposition of magnetizable materials
US10553555B2 (en) 2017-08-25 2020-02-04 International Business Machines Corporation Non-porous copper to copper interconnect
WO2021106721A1 (en) * 2019-11-26 2021-06-03 千住金属工業株式会社 Preform solder and bonding method using same
CN113394017B (en) * 2021-06-10 2023-11-03 北京工业大学 Method for diffusion sintering of neodymium iron boron through electroplating and electrophoresis collaborative deposition
KR20220168289A (en) * 2021-06-16 2022-12-23 삼성전기주식회사 Printed circuit board

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2866831A (en) * 1953-11-16 1958-12-30 Imperiral Chemical Ind Ltd Catalytic process for producing 1-methylcyclohexene
US2909641A (en) * 1958-05-02 1959-10-20 Republic Aviat Corp Tool for electro-shaping
US3421997A (en) * 1958-11-10 1969-01-14 Anocut Eng Co Electrode for electrolytic shaping
US3359195A (en) * 1963-10-29 1967-12-19 Hojyo Kazuya Automatic chromium plating apparatus
US3425926A (en) * 1965-07-27 1969-02-04 Kazuya Hojyo Apparatus for automatically electroplating various articles with chromium
JPS4965742A (en) * 1972-10-26 1974-06-26
US4120758A (en) * 1975-09-09 1978-10-17 Rippere Ralph E Production of powder metallurgy alloys
US4088545A (en) * 1977-01-31 1978-05-09 Supnet Fred L Method of fabricating mask-over-copper printed circuit boards
DE2802689A1 (en) * 1977-12-21 1979-06-28 Bbc Brown Boveri & Cie METHOD FOR CARRYING OUT AN ELECTROLYSIS PROCESS
US4302822A (en) * 1978-05-12 1981-11-24 Nippon Electric Co., Ltd. Thin-film magnetic bubble domain detection device and process for manufacturing the same
US4279707A (en) * 1978-12-18 1981-07-21 International Business Machines Corporation Electroplating of nickel-iron alloys for uniformity of nickel/iron ratio using a low density plating current
FR2446669A1 (en) * 1979-01-17 1980-08-14 Bienvenu Gerard METHOD AND DEVICE FOR IMPLEMENTING TRANSFERS OF MATERIAL OF PHYSICAL AND / OR CHEMICAL REACTIONS OR OF THERMAL TRANSFERS IN A FLUID MEDIUM
US4240881A (en) * 1979-02-02 1980-12-23 Republic Steel Corporation Electroplating current control
US4278245A (en) * 1979-11-23 1981-07-14 General Electric Company Apparatus for clamping a plurality of elements
US4377619A (en) * 1981-05-08 1983-03-22 Bell Telephone Laboratories, Incorporated Prevention of surface mass migration by means of a polymeric surface coating
US4441118A (en) * 1983-01-13 1984-04-03 Olin Corporation Composite copper nickel alloys with improved solderability shelf life
US4465264A (en) * 1983-05-27 1984-08-14 Olin Corporation Apparatus for producing acicular iron or iron alloy particles
US4701248A (en) * 1985-07-09 1987-10-20 Siemens Aktiengesellschaft Apparatus for electrolytic surface treatment of bulk goods
US4696729A (en) * 1986-02-28 1987-09-29 International Business Machines Electroplating cell
US4666568A (en) * 1986-10-10 1987-05-19 State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Portland State University Electrolytic codeposition of metals and nonmetallic particles
US5000827A (en) * 1990-01-02 1991-03-19 Motorola, Inc. Method and apparatus for adjusting plating solution flow characteristics at substrate cathode periphery to minimize edge effect
DE4227848B4 (en) * 1991-11-28 2009-05-07 Robert Bosch Gmbh Component carrier and method for holding a formed of a ferromagnetic material component
JPH0625899A (en) * 1992-07-10 1994-02-01 Nec Corp Electroplating device
US5277785A (en) * 1992-07-16 1994-01-11 Anglen Erik S Van Method and apparatus for depositing hard chrome coatings by brush plating
US5312532A (en) * 1993-01-15 1994-05-17 International Business Machines Corporation Multi-compartment eletroplating system
DE69431815D1 (en) * 1993-05-31 2003-01-09 Tdk Corp Magnetic recording / playback method
US5421987A (en) * 1993-08-30 1995-06-06 Tzanavaras; George Precision high rate electroplating cell and method
JP3126867B2 (en) * 1993-08-31 2001-01-22 上村工業株式会社 Plating apparatus and plating method for small items
US5565079A (en) * 1993-08-31 1996-10-15 Griego; Thomas P. Fine particle microencapsulation and electroforming
US6322676B1 (en) * 1998-03-25 2001-11-27 University Of Iowa Research Foundation Magnetic composites exhibiting distinct flux properties due to gradient interfaces
US5514258A (en) * 1994-08-18 1996-05-07 Brinket; Oscar J. Substrate plating device having laminar flow
US6001248A (en) * 1994-08-25 1999-12-14 The University Of Iowa Research Foundation Gradient interface magnetic composites and systems therefor
US5817221A (en) * 1994-08-25 1998-10-06 University Of Iowa Research Foundation Composites formed using magnetizable material, a catalyst and an electron conductor
US5879520A (en) * 1994-08-26 1999-03-09 Griego; Thomas P. Rotary electrodeposition apparatus
GB9425030D0 (en) * 1994-12-09 1995-02-08 Alpha Metals Ltd Silver plating
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US6030851A (en) * 1995-06-07 2000-02-29 Grandmont; Paul E. Method for overpressure protected pressure sensor
US5573859A (en) * 1995-09-05 1996-11-12 Motorola, Inc. Auto-regulating solder composition
US5764567A (en) * 1996-11-27 1998-06-09 International Business Machines Corporation Magnetic tunnel junction device with nonferromagnetic interface layer for improved magnetic field response
US5853995A (en) * 1997-01-07 1998-12-29 Research Development Foundation Large scale genotyping of diseases and a diagnostic test for spinocerebellar ataxia type 6
US6286206B1 (en) * 1997-02-25 2001-09-11 Chou H. Li Heat-resistant electronic systems and circuit boards
JP3352352B2 (en) * 1997-03-31 2002-12-03 新光電気工業株式会社 Plating apparatus, plating method and bump forming method
US6200453B1 (en) * 1997-10-20 2001-03-13 Rajev R. Agarrwal Monolith electroplating process
EP1055020A2 (en) * 1998-02-12 2000-11-29 ACM Research, Inc. Plating apparatus and method
US6565729B2 (en) * 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
WO1999054527A2 (en) * 1998-04-21 1999-10-28 Applied Materials, Inc. Electro-chemical deposition system and method of electroplating on substrates
US6497801B1 (en) * 1998-07-10 2002-12-24 Semitool Inc Electroplating apparatus with segmented anode array
KR100683268B1 (en) * 1998-09-08 2007-02-15 가부시키가이샤 에바라 세이사꾸쇼 Substrate plating device
KR100694563B1 (en) * 1998-10-05 2007-03-13 가부시키가이샤 에바라 세이사꾸쇼 Substrate plating device
US6773571B1 (en) * 2001-06-28 2004-08-10 Novellus Systems, Inc. Method and apparatus for uniform electroplating of thin metal seeded wafers using multiple segmented virtual anode sources
US6402923B1 (en) * 2000-03-27 2002-06-11 Novellus Systems Inc Method and apparatus for uniform electroplating of integrated circuits using a variable field shaping element
JP3049315B1 (en) * 1999-02-19 2000-06-05 名古屋大学長 Method for controlling crystal orientation of electrodeposited or electroless deposited film by magnetic field
US6193860B1 (en) * 1999-04-23 2001-02-27 Vlsi Technolgy, Inc. Method and apparatus for improved copper plating uniformity on a semiconductor wafer using optimized electrical currents
US6153320A (en) * 1999-05-05 2000-11-28 International Business Machines Corporation Magnetic devices with laminated ferromagnetic structures formed with improved antiferromagnetically coupling films
US6197182B1 (en) * 1999-07-07 2001-03-06 Technic Inc. Apparatus and method for plating wafers, substrates and other articles
FR2796656B1 (en) * 1999-07-22 2001-08-17 Pechiney Aluminium CONTINUOUS NICKELING PROCESS OF AN ALUMINUM CONDUCTOR AND CORRESPONDING DEVICE
US6251250B1 (en) * 1999-09-03 2001-06-26 Arthur Keigler Method of and apparatus for controlling fluid flow and electric fields involved in the electroplating of substantially flat workpieces and the like and more generally controlling fluid flow in the processing of other work piece surfaces as well
KR100352976B1 (en) * 1999-12-24 2002-09-18 한국기계연구원 Electrical Plating Process and Device for Ni Plate Layer Having Biaxial Texture
US6793794B2 (en) * 2000-05-05 2004-09-21 Ebara Corporation Substrate plating apparatus and method
JP3284496B2 (en) * 2000-08-09 2002-05-20 株式会社荏原製作所 Plating apparatus and plating solution removal method
US6610189B2 (en) * 2001-01-03 2003-08-26 Applied Materials, Inc. Method and associated apparatus to mechanically enhance the deposition of a metal film within a feature
US6942765B2 (en) * 2001-05-31 2005-09-13 Surfect Technologies, Inc. Submicron and nano size particle encapsulation by electrochemical process and apparatus
US20060011487A1 (en) * 2001-05-31 2006-01-19 Surfect Technologies, Inc. Submicron and nano size particle encapsulation by electrochemical process and apparatus
WO2003018875A1 (en) * 2001-08-27 2003-03-06 Surfect Techologies, Inc. Electrodeposition apparatus and method using magnetic assistance and rotary cathode for ferrous and magnetic particles
US6680128B2 (en) * 2001-09-27 2004-01-20 Agilent Technologies, Inc. Method of making lead-free solder and solder paste with improved wetting and shelf life
US6630360B2 (en) * 2002-01-10 2003-10-07 Advanced Micro Devices, Inc. Advanced process control (APC) of copper thickness for chemical mechanical planarization (CMP) optimization
US6913651B2 (en) * 2002-03-22 2005-07-05 Blue29, Llc Apparatus and method for electroless deposition of materials on semiconductor substrates
US20030196901A1 (en) * 2002-04-23 2003-10-23 Applied Materials, Inc. Method for plating metal onto wafers
JP3854902B2 (en) * 2002-07-03 2006-12-06 キヤノン株式会社 Plating apparatus and plating method
KR20100052577A (en) * 2002-07-18 2010-05-19 가부시키가이샤 에바라 세이사꾸쇼 Plating apparatus
US7223323B2 (en) * 2002-07-24 2007-05-29 Applied Materials, Inc. Multi-chemistry plating system
JP4058307B2 (en) * 2002-08-29 2008-03-05 大日本スクリーン製造株式会社 Plating equipment
US7287412B2 (en) * 2003-06-03 2007-10-30 Nano-Proprietary, Inc. Method and apparatus for sensing hydrogen gas
JP2004149872A (en) * 2002-10-31 2004-05-27 Renesas Technology Corp Plating apparatus and plating method
JP4330380B2 (en) * 2003-05-29 2009-09-16 株式会社荏原製作所 Plating apparatus and plating method
US20040124090A1 (en) * 2002-12-30 2004-07-01 Chen-Chung Du Wafer electroplating apparatus and method
JP4303484B2 (en) * 2003-01-21 2009-07-29 大日本スクリーン製造株式会社 Plating equipment
US20060049038A1 (en) * 2003-02-12 2006-03-09 Surfect Technologies, Inc. Dynamic profile anode
WO2004072331A2 (en) * 2003-02-12 2004-08-26 Surfect Technologies, Inc. Apparatus and method for highly controlled electrodeposition
TW200533791A (en) * 2004-02-04 2005-10-16 Surfect Technologies Inc Plating apparatus and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016015312A (en) * 2014-06-11 2016-01-28 積水化学工業株式会社 Conductive particle, method of producing conductive particle, conductive material and connection structure
KR20210086519A (en) * 2019-12-31 2021-07-08 덕산하이메탈(주) Solder ball and the manufacturing method thereof
KR102489331B1 (en) * 2019-12-31 2023-01-17 덕산하이메탈(주) Solder ball and the manufacturing method thereof

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