JP2006324346A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006324346A
JP2006324346A JP2005144410A JP2005144410A JP2006324346A JP 2006324346 A JP2006324346 A JP 2006324346A JP 2005144410 A JP2005144410 A JP 2005144410A JP 2005144410 A JP2005144410 A JP 2005144410A JP 2006324346 A JP2006324346 A JP 2006324346A
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layer
oxide film
conductivity type
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Akira Ohira
明 大平
Masayuki Inoue
真幸 井上
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To form an electric field alleviating layer without adding a manufacturing process, while raising breakdown voltage of a LOCOS offset drain-type MOS transistor by alleviating an electric field of the LOCOS oxide film end. <P>SOLUTION: A high concentration drain layer 109A of the LOCOS offset drain-type high breakdown voltage MOS transistor is formed with a fixed distance from the end of a LOCOS oxide film 105 in a p-type electric field alleviating layer 104, and a concentration gradient of the end of the LOCOS oxide film 105 is made gradual so as to raise breakdown voltage by preventing electric field concentration. On the other hand, an electric field alleviating layer can be formed by using a body layer of an LDMOS transistor, without adding a manufacturing process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、特にＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタのドレインの構造およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a drain structure of a LOCOS offset drain type high voltage MOS transistor and a manufacturing method thereof.

モーター駆動制御ＩＣなどにおける、ＭＯＳ型電界効果トランジスタ（ＭＯＳＦＥＴ）では、例えば数十Ｖ以上の高電圧をドレイン領域に印加して使用する場合がある。しかし、トランジスタがＯＦＦの状態で高電圧を印加すると、ゲート電極端部に電界集中が発生して、ゲート絶縁膜が破壊される場合がある。従って、このように使用されるトランジスタには、高いドレイン耐圧が要求されている。   In a MOS field effect transistor (MOSFET) in a motor drive control IC or the like, a high voltage of, for example, several tens of volts or more may be applied to the drain region. However, when a high voltage is applied with the transistor turned off, electric field concentration may occur at the end portion of the gate electrode, and the gate insulating film may be destroyed. Therefore, the transistor used in this way is required to have a high drain breakdown voltage.

そこで、ドレイン領域とゲート電極の端部との間にＬＯＣＯＳ法により厚い酸化膜を形成して、ドレイン領域からゲート端部をオフセットさせた、いわゆるＬＯＣＯＳオフセットドレイン型の高耐圧ＭＯＳトランジスタが提案されている（例えば、特許文献１参照）。また、ドレイン領域における電界集中の緩和を図る、高耐圧ＭＯＳトランジスタが提案されている（例えば、特許文献２参照）。   Therefore, a so-called LOCOS offset drain type high voltage MOS transistor is proposed in which a thick oxide film is formed between the drain region and the end of the gate electrode by the LOCOS method, and the gate end is offset from the drain region. (For example, refer to Patent Document 1). In addition, a high-breakdown-voltage MOS transistor that reduces electric field concentration in the drain region has been proposed (see, for example, Patent Document 2).

図４は特許文献２に記述されている、先行技術による半導体装置の断面図を示す。以下、従来の高耐圧ＭＯＳトランジスタについて図面を参照しながら説明する。   FIG. 4 is a sectional view of a semiconductor device according to the prior art described in Patent Document 2. A conventional high voltage MOS transistor will be described below with reference to the drawings.

この半導体装置は、まずＰ＋型高濃度ドレイン層３０９Ａとポリシリコンからなるゲート電極３０８の端部との間にＬＯＣＯＳ酸化膜３０５を形成し、ドレイン領域であるＰ＋型高濃度ドレイン層３０９Ａからゲート電極３０８の端部をオフセットさせ、これによりゲート電極３０８の端部での電界集中を防止している。ＬＯＣＯＳ酸化膜３０５の下には、ドレイン領域と同一の導電型からなるＰ−型オフセット層３０６を形成している。Ｐ−型オフセット層３０６の不純物濃度はＰ＋型高濃度ドレイン層３０９Ａよりも薄い。そして、耐圧向上のためにＰ＋型高濃度ドレイン層３０９Ａの側面と底面とを覆うように、Ｐ−型オフセット層３０６の不純物濃度より濃く、Ｐ＋型高濃度ドレイン層３０９Ａの不純物濃度より薄い同一の導電型からなる、Ｐ型電界緩和層３０４をドレイン領域として形成し、Ｐ＋型高濃度ドレイン層３０９ＡからＰ−型オフセット層３０６にかけての濃度勾配を緩やかにして電界集中を緩和し、耐圧を向上させている。図４において、符号３０１はＰ型シリコン基板を示し、符号３０２はＮ＋型埋め込み層を示し、符号３０３はＮ−型エピタキシャル層を示す。また、符号３０７はゲート酸化膜を示し、符号３０９ＢはＰ＋型高濃度ソース層を示す。 The semiconductor device is first formed a LOCOS oxide film 305 between the end portion of the gate electrode 308 made of P + -type high concentration drain layer 309A and polysilicon, a P + -type high concentration drain layer 309A is the drain region The end portion of the gate electrode 308 is offset, thereby preventing electric field concentration at the end portion of the gate electrode 308. Under the LOCOS oxide film 305, a P − type offset layer 306 having the same conductivity type as that of the drain region is formed. The impurity concentration of the P − type offset layer 306 is thinner than that of the P + type high concentration drain layer 309A. Then, so as to cover the side surfaces and the bottom surface of the P + -type high concentration drain layer 309A for improvement in withstand voltage, P - darker than the impurity concentration of the type offset layer 306, thinner than the impurity concentration of the P + -type high concentration drain layer 309A A P-type field relaxation layer 304 having the same conductivity type is formed as a drain region, and a concentration gradient from the P + -type high-concentration drain layer 309A to the P − -type offset layer 306 is relaxed to alleviate the electric field concentration. Has improved. In FIG. 4, reference numeral 301 denotes a P-type silicon substrate, reference numeral 302 denotes an N + type buried layer, and reference numeral 303 denotes an N − type epitaxial layer. Reference numeral 307 denotes a gate oxide film, and reference numeral 309B denotes a P + type high concentration source layer.

図５Ａ〜図５Ｄは、先行技術によるＰ型チャネルＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタの代表的な製造方法を示す工程断面図である。   5A to 5D are process cross-sectional views showing a typical method for manufacturing a P-type channel LOCOS offset drain type high voltage MOS transistor according to the prior art.

まず図５Ａに示すように、Ｐ型シリコン基板３０１上にＮ＋型埋め込み層３０２とＮ−型エピタキシャル層３０３とを順次形成する。このとき、Ｎ＋型埋め込み層３０２はＮ−型エピタキシャル層３０３よりも不純物濃度を濃く形成する。そして、Ｎ−型エピタキシャル層３０２の表面に、フォトレジスト３２０を塗布・現像し、これをマスクとしてＰ型電界緩和領域３０４を形成する。 First, as shown in FIG. 5A, an N + type buried layer 302 and an N − type epitaxial layer 303 are sequentially formed on a P type silicon substrate 301. At this time, the N + type buried layer 302 is formed with a higher impurity concentration than the N − type epitaxial layer 303. Then, a photoresist 320 is applied and developed on the surface of the N − type epitaxial layer 302, and a P type electric field relaxation region 304 is formed using this as a mask.

つぎに、図５Ｂに示すように、フォトレジスト３２０を除去した後、酸化膜３３０を形成し、その上部に窒化膜３３１を形成する。そして、活性領域となる部分に酸化膜３３０と窒化膜３３１とをパターニングする。そして、フォトレジスト３２１を塗布・現像し、これをマスクとしてＬＯＣＯＳオフセット領域となるＮ−型エピタキシャル層３０３の表面にＰ型不純物のボロンを注入し、それによって拡散層３０６Ａを形成する。 Next, as shown in FIG. 5B, after removing the photoresist 320, an oxide film 330 is formed, and a nitride film 331 is formed thereon. Then, the oxide film 330 and the nitride film 331 are patterned in a portion that becomes an active region. Then, photoresist 321 is applied and developed, and using this as a mask, P-type impurity boron is implanted into the surface of the N − -type epitaxial layer 303 to be a LOCOS offset region, thereby forming a diffusion layer 306A.

つぎに、図５Ｃに示すように、図５Ｂに示したフォトレジスト３２１を除去した後、窒化膜３３１をマスクとしてＬＯＣＯＳ酸化膜３０５を形成する。ＬＯＣＯＳ酸化膜３０５の下部のシリコンのうちボロンを注入した拡散層３０６ＡはＰ−型オフセット層３０６となる。Ｐ−型オフセット層３０６の不純物濃度はＰ型電界緩和層３０４より薄い濃度で形成される。つぎに、トランジスタのゲート部となるところにゲート酸化膜３０７を形成する。その上部に、ドレイン側のＬＯＣＯＳ酸化膜３０５に跨ってポリシリコンからなるゲート電極３０８を形成する。 Next, as shown in FIG. 5C, after removing the photoresist 321 shown in FIG. 5B, a LOCOS oxide film 305 is formed using the nitride film 331 as a mask. Of the silicon below the LOCOS oxide film 305, the diffusion layer 306 A into which boron has been implanted becomes a P − type offset layer 306. The impurity concentration of the P − type offset layer 306 is lower than that of the P type electric field relaxation layer 304. Next, a gate oxide film 307 is formed where the gate portion of the transistor is to be formed. On top of this, a gate electrode 308 made of polysilicon is formed across the LOCOS oxide film 305 on the drain side.

つぎに、図５Ｄに示すように、フォトレジスト３２２を塗布・現像し、これをマスクとしてＰ型不純物のボロンを高濃度にイオン注入し、それによってＰ＋型高濃度ドレイン層３０９ＡおよびＰ＋型高濃度ソース層３０９Ｂを形成する。このとき、ドレイン領域のＰ＋型高濃度ドレイン層３０９ＡはＬＯＣＯＳ酸化膜３０５をマスクとしたセルフアラインで注入される。Ｐ＋型高濃度ドレイン層３０９Ａの不純物濃度は、Ｐ型電界緩和層３０４よりも濃い濃度で形成される。 Next, as shown in FIG. 5D, a photoresist 322 is applied and developed, and using this as a mask, P-type impurity boron is ion-implanted at a high concentration, whereby the P + -type high-concentration drain layer 309A and the P + -type are implanted. A high concentration source layer 309B is formed. At this time, the P + -type high-concentration drain layer 309A in the drain region is implanted by self-alignment using the LOCOS oxide film 305 as a mask. The impurity concentration of the P + -type high-concentration drain layer 309A is higher than that of the P-type electric field relaxation layer 304.

つぎに、図には示さないが、層間絶縁膜としてＰＳＧ膜を形成し、Ｐ＋型高濃度ドレイン層３０９ＡおよびＰ＋型高濃度ソース層３０９Ｂおよびゲート電極３０８に接続孔（コンタクト）を設け、アルミ配線とパッシベーション膜とを形成することにより半導体装置が完成する。 Next, although not shown in the drawing, a PSG film is formed as an interlayer insulating film, and connection holes (contacts) are provided in the P + type high concentration drain layer 309A, the P + type high concentration source layer 309B, and the gate electrode 308, The semiconductor device is completed by forming the aluminum wiring and the passivation film.

以上のように、専用のＰ型電界緩和層３０４を導入することにより、Ｐ型高耐圧ＭＯＳトランジスタの高耐圧化を図ることができる。
特開昭５７−２１０６７４号公報 特開平１１−００８３８８号公報 As described above, by introducing the dedicated P-type electric field relaxation layer 304, it is possible to increase the breakdown voltage of the P-type high breakdown voltage MOS transistor.
Japanese Patent Laid-Open No. 57-210684 Japanese Patent Laid-Open No. 11-008388

しかしながら、先行技術においては、以下の課題が存在する。先行技術によるＰ型チャネルのＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタでは、Ｐ＋型高濃度ドレイン層３０９ＡはＬＯＣＯＳ酸化膜３０５をマスクとしたセルフアラインで形成されるため、ＬＯＣＯＳ酸化膜３０５の端部のバーズビーク付近の濃度勾配が急峻になり、その部分で電界が集中しやすくなる。また、ＬＯＣＯＳ酸化膜３０５の端部のバーズビーク付近は微小な結晶欠陥の発生が起こる。そのため、この部分に電界が集中すると、耐圧の低下・信頼性劣化が起こる。 However, the following problems exist in the prior art. In the P-type channel LOCOS offset drain type high breakdown voltage MOS transistor according to the prior art, the P + type high concentration drain layer 309A is formed by self-alignment using the LOCOS oxide film 305 as a mask. The concentration gradient near the bird's beak becomes steep, and the electric field tends to concentrate at that portion. In addition, a minute crystal defect occurs near the bird's beak at the end of the LOCOS oxide film 305. Therefore, when the electric field is concentrated on this portion, the breakdown voltage is lowered and the reliability is deteriorated.

一方、Ｐ型電界緩和層３０４を有し、Ｐ＋型高濃度ドレイン層３０９ＡからＰ−型オフセット層３０６にかけての濃度勾配を緩やかすることで、電界集中を防ぎ耐圧を向上させている。しかし、Ｐ型電界緩和層３０４を形成するためには工程追加が必要であるため、製造コストが高くなる。 On the other hand, the P-type electric field relaxation layer 304 is provided, and the concentration gradient from the P + -type high-concentration drain layer 309A to the P − -type offset layer 306 is moderated to prevent electric field concentration and improve the breakdown voltage. However, since an additional process is required to form the P-type electric field relaxation layer 304, the manufacturing cost increases.

上記課題に鑑みて、本発明は、ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタにおけるＬＯＣＯＳ酸化膜の端部のバーズビーク付近の電界集中を緩和することを目的とする。   In view of the above problems, an object of the present invention is to alleviate electric field concentration near a bird's beak at the end of a LOCOS oxide film in a LOCOS offset drain type high voltage MOS transistor.

また、本発明は、製造工程を追加することなく、上記電界緩和層を形成することを目的とする。   Moreover, an object of this invention is to form the said electric field relaxation layer, without adding a manufacturing process.

上記課題を解決するために、第１の発明の半導体装置は、半導体基板上に形成された第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタを含む半導体装置であり、第２導電型の半導体層に形成された第１導電型の電界緩和層および高濃度ドレイン層から成るドレイン領域と、半導体層に形成された第１導電型の高濃度ソース層から成るソース領域と、ドレイン領域とソース領域の間で半導体層表面の活性領域に形成されたゲート酸化膜と、ドレイン領域とゲート酸化膜の間の半導体層表面に形成されたＬＯＣＯＳ酸化膜と、ゲート酸化膜上にＬＯＣＯＳ酸化膜に跨って形成されたゲート電極と、ＬＯＣＯＳ酸化膜下に形成された第１導電型のオフセット層とを備えている。   In order to solve the above problems, a semiconductor device according to a first invention is a semiconductor device including an offset drain type MOS transistor having a channel of a first conductivity type formed on a semiconductor substrate, and a semiconductor of a second conductivity type. A drain region composed of a first conductivity type electric field relaxation layer and a high concentration drain layer formed in the layer; a source region composed of a first conductivity type high concentration source layer formed in the semiconductor layer; and a drain region and a source region A gate oxide film formed in the active region on the surface of the semiconductor layer, a LOCOS oxide film formed on the semiconductor layer surface between the drain region and the gate oxide film, and straddling the LOCOS oxide film on the gate oxide film A gate electrode formed; and a first conductivity type offset layer formed under the LOCOS oxide film.

そして、電界緩和層はオフセット層に隣接して形成され、電界緩和層の不純物濃度はオフセット層より濃く、かつ高濃度ドレイン層より薄く、高濃度ドレイン層は電界緩和層内に形成され、かつＬＯＣＯＳ酸化膜端より離間して形成されている。   The electric field relaxation layer is formed adjacent to the offset layer, the impurity concentration of the electric field relaxation layer is higher than that of the offset layer and lower than that of the high concentration drain layer, the high concentration drain layer is formed in the electric field relaxation layer, and LOCOS It is formed away from the end of the oxide film.

この構成によれば、高濃度ドレイン層を電界緩和層内に形成し、かつＬＯＣＯＳ酸化膜端より離間して形成しているので、オフセット層上のＬＯＣＯＳ酸化膜端のバーズビーク付近における不純物の濃度勾配が緩やかになり、従来よりも耐圧を向上することができる。   According to this configuration, since the high-concentration drain layer is formed in the electric field relaxation layer and is separated from the end of the LOCOS oxide film, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film on the offset layer Can be reduced, and the breakdown voltage can be improved as compared with the conventional case.

上記の構成において、ＬＯＣＯＳ酸化膜の端部から高濃度ドレイン層までの距離は０．８μｍ以上であることが好ましい。   In the above configuration, the distance from the end of the LOCOS oxide film to the high concentration drain layer is preferably 0.8 μm or more.

第２の発明の半導体装置の製造方法は、第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタを半導体基板上に形成する半導体装置の製造方法であり、第２導電型の半導体層上に酸化膜を介して窒化膜を形成する工程と、半導体層上の活性領域に窒化膜をパターニングする工程と、窒化膜をマスクとして半導体層に第１導電型のオフセット層を形成する工程と、窒化膜をマスクとして半導体層表面にＬＯＣＯＳ酸化膜を形成する工程と、ＬＯＣＯＳ酸化膜の形成工程の後に窒化膜を除去する工程と、半導体層表面の活性領域にゲート酸化膜を形成する工程と、ゲート酸化膜上にＬＯＣＯＳ酸化膜に跨ってゲート電極を形成する工程と、オフセット層に隣接した半導体層のドレイン領域に第１導電型の電界緩和層を形成する工程と、電界緩和層内に第１導電型の高濃度ドレイン層を形成し、第１導電型の高濃度ドレイン層に対してゲート電極を挟んだ位置で半導体層に第１導電型の高濃度ソース層とを形成する工程とを含む。   A method for manufacturing a semiconductor device according to a second aspect of the invention is a method for manufacturing a semiconductor device in which an offset drain type MOS transistor having a first conductivity type channel is formed on a semiconductor substrate, and is oxidized on the second conductivity type semiconductor layer. Forming a nitride film through the film; patterning the nitride film in an active region on the semiconductor layer; forming a first conductivity type offset layer on the semiconductor layer using the nitride film as a mask; Forming a LOCOS oxide film on the surface of the semiconductor layer using the mask as a mask, removing the nitride film after the LOCOS oxide film forming process, forming a gate oxide film in the active region of the semiconductor layer surface, and gate oxidation Forming a gate electrode over the LOCOS oxide film, and forming a first conductivity type electric field relaxation layer in a drain region of the semiconductor layer adjacent to the offset layer; Then, a high-concentration drain layer of the first conductivity type is formed in the electric field relaxation layer, and the high-concentration of the first conductivity type is formed in the semiconductor layer at a position sandwiching the gate electrode with respect to the high-concentration drain layer of the first conductivity type. Forming a source layer.

そして、高濃度ドレイン層はＬＯＣＯＳ酸化膜の端部から離間して形成されている。   The high concentration drain layer is formed away from the end of the LOCOS oxide film.

この方法によれば、高濃度ドレイン層を電界緩和層内に形成し、かつＬＯＣＯＳ酸化膜端より離間して形成しているので、オフセット層上のＬＯＣＯＳ酸化膜端のバーズビーク付近における不純物の濃度勾配が緩やかになり、従来よりも耐圧を向上することができる。   According to this method, since the high-concentration drain layer is formed in the electric field relaxation layer and separated from the end of the LOCOS oxide film, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film on the offset layer Can be reduced, and the breakdown voltage can be improved as compared with the conventional case.

第３の発明の半導体装置の製造方法は、第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタと第２導電型のチャネルを有するラテラル型ＤＭＯＳトランジスタとを同一半導体基板上に形成する半導体装置の製造方法であり、第２導電型の半導体層内にＭＯＳトランジスタ領域とＤＭＯＳトランジスタ領域とを分離する素子分離層を形成する工程と、半導体層上に酸化膜を介して窒化膜を形成する工程と、半導体層上の活性領域に窒化膜をパターニングする工程と、窒化膜をマスクとしてＭＯＳトランジスタ領域の半導体層に第１導電型のオフセット層を形成する工程と、窒化膜をマスクとして半導体層表面にＬＯＣＯＳ酸化膜を形成する工程と、ＬＯＣＯＳ酸化膜の形成工程の後に窒化膜を除去する工程と、半導体層表面の活性領域にゲート酸化膜を形成する工程と、ゲート酸化膜上にＬＯＣＯＳ酸化膜に跨ってゲート電極を形成する工程と、ＭＯＳトランジスタ領域のオフセット層に隣接した半導体層のドレイン領域に第１導電型の電界緩和層を形成すると同時に、ＤＭＯＳトランジスタ領域のゲート電極に挟まれたソース領域に第１導電型のボディ層を形成する工程と、ＭＯＳトランジスタ領域において、電界緩和層内に第１導電型の高濃度ドレイン層を形成し、第１導電型の高濃度ドレイン層に対してゲート電極を挟んだ位置でゲート電極を挟んだ半導体層に第１導電型の高濃度ソース層とを形成する工程と、ＤＭＯＳトランジスタ領域において、ボディ層内に第２導電型の高濃度ソース層を形成し、第２導電型の高濃度ソース層に対してゲート電極を挟んだ位置で半導体層に第２導電型のドレイン層とを形成する工程とを含む。   According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method in which an offset drain MOS transistor having a first conductivity type channel and a lateral DMOS transistor having a second conductivity type channel are formed on the same semiconductor substrate. A method of forming an element isolation layer that separates a MOS transistor region and a DMOS transistor region in a second conductivity type semiconductor layer; and a step of forming a nitride film on the semiconductor layer via an oxide film; A step of patterning a nitride film in the active region on the semiconductor layer; a step of forming an offset layer of a first conductivity type in the semiconductor layer of the MOS transistor region using the nitride film as a mask; and a surface of the semiconductor layer using the nitride film as a mask A step of forming a LOCOS oxide film, a step of removing the nitride film after the step of forming the LOCOS oxide film, and a semiconductor layer surface Forming a gate oxide film in the active region, forming a gate electrode over the LOCOS oxide film on the gate oxide film, and forming a first conductive layer in the drain region of the semiconductor layer adjacent to the offset layer in the MOS transistor region. Forming a first electric field relaxation layer and simultaneously forming a first conductivity type body layer in the source region sandwiched between the gate electrodes of the DMOS transistor region; and in the MOS transistor region, the first conductivity type in the electric field relaxation layer. Forming a high-concentration drain layer and forming a first-conductivity-type high-concentration source layer on a semiconductor layer sandwiching the gate electrode at a position sandwiching the gate electrode with respect to the first-conductivity-type high-concentration drain layer In the DMOS transistor region, a second conductivity type high concentration source layer is formed in the body layer, and a gate electrode is formed with respect to the second conductivity type high concentration source layer. And forming a second conductivity type drain layer of the semiconductor layer at the position I.

そして、ＭＯＳトランジスタ領域における高濃度ドレイン層はＬＯＣＯＳ酸化膜の端部から離間して形成されている。   The high-concentration drain layer in the MOS transistor region is formed away from the end of the LOCOS oxide film.

この方法によれば、高濃度ドレイン層を電界緩和層内に形成し、かつＬＯＣＯＳ酸化膜端より離間して形成しているので、オフセット層上のＬＯＣＯＳ酸化膜端のバーズビーク付近における不純物の濃度勾配が緩やかになり、従来よりも耐圧を向上することができる。   According to this method, since the high-concentration drain layer is formed in the electric field relaxation layer and separated from the end of the LOCOS oxide film, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film on the offset layer Can be reduced, and the breakdown voltage can be improved as compared with the conventional case.

また、ラテラル型ＤＭＯＳトランジスタのボディ層と同じ工程でＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタの電界緩和層を形成するので、製造工程を追加することなく電界緩和層を形成できる。   In addition, since the electric field relaxation layer of the LOCOS offset drain type high voltage MOS transistor is formed in the same process as the body layer of the lateral type DMOS transistor, the electric field relaxation layer can be formed without adding a manufacturing process.

第１の発明の半導体装置および第１の発明の半導体装置の製造方法によると、オフセット層上のＬＯＣＯＳ酸化膜の端部のバーズビーク付近の濃度勾配が緩やかになり、従来よりも耐圧が向上したＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタを実現することができる。   According to the semiconductor device of the first invention and the method of manufacturing the semiconductor device of the first invention, the concentration gradient in the vicinity of the bird's beak at the end of the LOCOS oxide film on the offset layer becomes gradual, and the breakdown voltage is improved compared to the conventional LOCOS. An offset drain type high voltage MOS transistor can be realized.

また、第２の発明の半導体装置の製造方法によると、ＬＤＭＯＳトランジスタのボディ層と同じ工程でＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタの電界緩和層を形成するので、製造工程を追加することなく電界緩和層を形成し、製造コストを削減することができる。したがって、第１の製造方法と同じ効果に加え第２の製造方法による効果も得るため、耐圧の向上と製造コストの削減を同時に実現することができる。   According to the method for manufacturing a semiconductor device of the second invention, since the electric field relaxation layer of the LOCOS offset drain type high voltage MOS transistor is formed in the same process as the body layer of the LDMOS transistor, the electric field relaxation is performed without adding a manufacturing process. Layers can be formed and manufacturing costs can be reduced. Therefore, in addition to the same effect as the first manufacturing method, the effect of the second manufacturing method is also obtained, so that the breakdown voltage can be improved and the manufacturing cost can be reduced simultaneously.

（実施の形態１）
以下、本発明の実施の形態１に係る半導体装置およびその製造方法について図面を参照しながら説明する。図１は実施の形態１に係る半導体装置の断面図を示す。 (Embodiment 1)
Hereinafter, a semiconductor device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.

この半導体装置は、Ｐ型電界緩和層（ドレイン領域）１０４とポリシリコンからなるゲート電極１０８の端部との間にＬＯＣＯＳ酸化膜１０５を形成し、ドレイン領域からゲート電極１０８の端部をオフセットさせている。ＬＯＣＯＳ酸化膜１０５の下部に、Ｐ型電界緩和層１０４と同一の導電型からなるＰ−型オフセット層１０６が形成されている。高濃度ドレイン層１０９Ａ（ドレイン領域）は、ドレイン側ＬＯＣＯＳ酸化膜１０５の端部のバーズビークから、一定の距離をおいて形成されている。なお、図１において、符号１０１はＰ型シリコン基板を示し、符号１０２はＮ＋型埋め込み層を示し、符号１０３はＮ−型エピタキシャル層を示す。また、符号１０７はゲート酸化膜を示し、符号１０９ＢはＰ＋型高濃度ソース層（ソース領域）を示す。符号１１０はＮ−型エピタキシャル層１０３の電位をとるためのＮ＋コンタクト層を示す。 In this semiconductor device, a LOCOS oxide film 105 is formed between a P-type field relaxation layer (drain region) 104 and an end portion of a gate electrode 108 made of polysilicon, and the end portion of the gate electrode 108 is offset from the drain region. ing. A P − type offset layer 106 having the same conductivity type as that of the P type electric field relaxation layer 104 is formed below the LOCOS oxide film 105. The high concentration drain layer 109 </ b> A (drain region) is formed at a certain distance from the bird's beak at the end of the drain side LOCOS oxide film 105. In FIG. 1, reference numeral 101 denotes a P-type silicon substrate, reference numeral 102 denotes an N + type buried layer, and reference numeral 103 denotes an N − type epitaxial layer. Reference numeral 107 denotes a gate oxide film, and reference numeral 109B denotes a P + type high concentration source layer (source region). Reference numeral 110 denotes an N + contact layer for taking the potential of the N − type epitaxial layer 103.

図６にＬＯＣＯＳ酸化膜１０５の端部からＰ＋型高濃度ドレイン層１０９Ａまでの距離と耐圧との関係を示す。図６から、Ｐ＋型高濃度ドレイン層１０９ＡをＬＯＣＯＳ酸化膜１０５の端部から０．８μｍ以上の距離に離すことで、微小欠陥が存在しやすいＬＯＣＯＳ酸化膜１０５の端部の濃度勾配が緩やかになり、電界集中が緩和され、耐圧が向上することがわかる。 FIG. 6 shows the relationship between the distance from the end of the LOCOS oxide film 105 to the P + -type high-concentration drain layer 109A and the breakdown voltage. From FIG. 6, by separating the P + -type high-concentration drain layer 109A at a distance of 0.8 μm or more from the end portion of the LOCOS oxide film 105, the concentration gradient at the end portion of the LOCOS oxide film 105 in which micro defects are likely to exist is gentle. It can be seen that the electric field concentration is relaxed and the breakdown voltage is improved.

図２Ａ〜図２Ｄは、本発明の実施の形態１のＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタの製造方法を示す工程断面図を示す。   2A to 2D are process sectional views showing a method of manufacturing the LOCOS offset drain type high voltage MOS transistor according to the first embodiment of the present invention.

まず図２Ａに示すように、Ｐ型シリコン基板１０１中にＮ＋型埋め込み層１０２、Ｎ−型エピタキシャル層１０３を順次形成する。ここで、Ｎ＋型埋め込み層１０２の不純物濃度は１×1018/cm3から１×1020/cm3程度、Ｎ−型エピタキシャル層１０３の不純物濃度は１×1015/cm3〜5×1015/cm3程度とする。そして、Ｎ−型エピタキシャル層１０３上に酸化膜１３０を形成し、その上部に窒化膜１３１を形成する。そして、活性領域となる部分に酸化膜１３０と窒化膜１３１とをパターニングする。 First, as shown in FIG. 2A, an N + type buried layer 102 and an N − type epitaxial layer 103 are sequentially formed in a P type silicon substrate 101. Here, the impurity concentration of the N + -type buried layer 102 is about 1 × 10 18 / cm 3 to 1 × 10 20 / cm 3 , and the impurity concentration of the N − -type epitaxial layer 103 is 1 × 10 15 / cm 3 to 5 ×. 10 15 / cm 3 or so. Then, an oxide film 130 is formed on the N − type epitaxial layer 103, and a nitride film 131 is formed thereon. Then, the oxide film 130 and the nitride film 131 are patterned in a portion that becomes an active region.

つぎに、フォトレジスト１２０を塗布・現像し、これをマスクとしてＬＯＣＯＳオフセット領域となるところに、ボロンを注入してＰ−型オフセット層１０６を形成する。Ｐ−型オフセット層１０６の注入ドーズ量は7×1012/cm2〜1.5×1013/cm2程度とする。 Next, a photoresist 120 is applied and developed, and boron is implanted into the LOCOS offset region using this as a mask to form the P − type offset layer 106. The implantation dose of the P − type offset layer 106 is about 7 × 10 12 / cm 2 to 1.5 × 10 13 / cm 2 .

つぎに、図２Ｂに示すように、図２Ａのフォトレジスト１２０を除去した後、窒化膜１３１をマスクとしてＬＯＣＯＳ酸化膜１０５を成長させる。ＬＯＣＯＳ酸化膜１０５は、例えばパイロジェニック酸化で1000℃100分程度の熱処理を行うことによって形成される。このときのＬＯＣＯＳ酸化膜１０５の膜厚は400nm〜600nm程度である。そして、トランジスタのゲート部となるところにゲート酸化膜１０７を形成する。その上部に、ドレイン側のＬＯＣＯＳ酸化膜１０５に跨ってポリシリコンからなるゲート電極１０８を形成する。   Next, as shown in FIG. 2B, after removing the photoresist 120 of FIG. 2A, a LOCOS oxide film 105 is grown using the nitride film 131 as a mask. The LOCOS oxide film 105 is formed, for example, by performing a heat treatment at 1000 ° C. for about 100 minutes by pyrogenic oxidation. At this time, the thickness of the LOCOS oxide film 105 is about 400 nm to 600 nm. Then, a gate oxide film 107 is formed where the transistor becomes a gate portion. A gate electrode 108 made of polysilicon is formed over the LOCOS oxide film 105 on the drain side.

つぎに、図２Ｃに示すように、Ｎ−型エピタキシャル層１０３のドレイン領域にボロンを注入することによりＰ型電界緩和層１０４を形成する。Ｐ型電界緩和層１０４の注入ドーズ量は4×1013/cm2〜8×1013/cm2程度とする。 Next, as shown in FIG. 2C, a P-type electric field relaxation layer 104 is formed by implanting boron into the drain region of the N − -type epitaxial layer 103. The implantation dose of the P-type field relaxation layer 104 is about 4 × 10 13 / cm 2 to 8 × 10 13 / cm 2 .

つぎに、図２Ｄに示すように、Ｐ型電界緩和層１０４中にＰ＋型高濃度ドレイン層１０９Ａを、Ｐ−型オフセット層上のＬＯＣＯＳ酸化膜１０５の端部のバーズビークから一定の距離をおいたＰ型電界緩和層１０４中にフォトレジスト１２１でマスキングをし、ボロンを注入することにより形成する。また、ゲート電極１０８を挟んでドレイン領域と反対の領域に、ゲート電極１０８に対してセルフアラインでＰ＋型高濃度ソース層１０９Ｂをボロン注入により形成する。Ｐ＋型高濃度ドレイン層１０９ＡとＰ＋型高濃度ソース層１０９Ｂとは同一の拡散層とする。Ｐ＋型高濃度ドレイン層１０９ＡとＰ＋型高濃度ソース層１０９Ｂの注入ドーズ量は2E15/cm2〜6E15/cm2程度とする。 Next, as shown in FIG. 2D, the P + -type high-concentration drain layer 109A is placed in the P-type electric field relaxation layer 104 at a certain distance from the bird's beak at the end of the LOCOS oxide film 105 on the P − -type offset layer. The P-type field relaxation layer 104 is formed by masking with a photoresist 121 and implanting boron. Further, a P + -type high concentration source layer 109B is formed by boron implantation in a region opposite to the drain region across the gate electrode 108 in a self-aligned manner with respect to the gate electrode 108. The P + type high concentration drain layer 109A and the P + type high concentration source layer 109B are the same diffusion layer. The implantation dose of the P + type high concentration drain layer 109A and the P + type high concentration source layer 109B is about 2E15 / cm 2 to 6E15 / cm 2 .

つぎに、図には示さないが、層間絶縁膜としてＰＳＧ膜とを形成し、Ｐ＋型高濃度ドレイン層１０９ＡとＰ＋型高濃度ソース層１０９Ｂおよびゲート電極１０８に接続孔（コンタクト）を設けてアルミ配線とパッシベーション膜とを形成することにより半導体装置が完成する。なお、Ｐ型電界緩和層１０４を形成する順序は、ＬＯＣＯＳ酸化膜を形成する前であってもよい。 Next, although not shown in the drawing, a PSG film is formed as an interlayer insulating film, and connection holes (contacts) are provided in the P + type high concentration drain layer 109A, the P + type high concentration source layer 109B, and the gate electrode 108. Thus, the semiconductor device is completed by forming the aluminum wiring and the passivation film. Note that the order of forming the P-type field relaxation layer 104 may be before the formation of the LOCOS oxide film.

上記の製造方法によると、Ｐ−型オフセット層１０６上のＬＯＣＯＳ酸化膜１０５の端部のバーズビーク付近の濃度勾配が緩やかになり、従来よりも耐圧が向上したＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタを実現することができる。 According to the above manufacturing method, the concentration gradient in the vicinity of the bird's beak at the end of the LOCOS oxide film 105 on the P − type offset layer 106 becomes gradual, and a LOCOS offset drain type high breakdown voltage MOS transistor with improved breakdown voltage compared to the prior art is realized. can do.

（実施の形態２）
実施の形態１はＰ型電界緩和層１０４を形成するために専用工程が必要となり製造コストの上昇につながる。そこで、本発明の実施の形態２では工程数を増やすことなく、Ｐ型電界緩和層を形成し耐圧を向上させる方法を提示する。以下、本発明の実施の形態２に係る半導体装置の製造方法について、図面を参照しながら説明する。 (Embodiment 2)
In the first embodiment, a dedicated process is required to form the P-type electric field relaxation layer 104, leading to an increase in manufacturing cost. Therefore, Embodiment 2 of the present invention presents a method for improving the breakdown voltage by forming a P-type electric field relaxation layer without increasing the number of steps. Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.

図３Ａ〜図３Ｄは、同一Ｐ型シリコン基板上にＰ型チャネルを有するラテラル型ＤＭＯＳトランジスタ（以下、ＬＤＭＯＳトランジスタと言う）と、Ｎ型チャネルを有するＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタを形成する本発明の実施の形態２の半導体装置の工程断面図を示す。   3A to 3D show a book in which a lateral DMOS transistor having a P-type channel (hereinafter referred to as an LDMOS transistor) and a LOCOS offset drain type high-breakdown-voltage MOS transistor having an N-type channel are formed on the same P-type silicon substrate. FIG. 10 is a process sectional view of the semiconductor device according to the second embodiment of the present invention.

まず図３Ａに示すように、Ｐ型シリコン基板２０１中のＬＤＭＯＳトランジスタ領域２５０およびＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０のそれぞれにＮ＋型埋め込み層２０２を形成する。そして、ＬＤＭＯＳトランジスタ領域２５０とＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０とを分離するために、分離領域２７０にＰ＋型分離埋め込み層２１２を形成する。その後、Ｎ−型エピタキシャル層２０３をＰ型シリコン基板２０１上に形成する。このとき、Ｎ＋型埋め込み層２０２の不純物濃度は１×1018/cm3から１×1020/cm3程度、Ｐ＋型分離埋め込み層２１２の不純物濃度は１×1017/cm3から１×1019/cm3程度、Ｎ−型エピタキシャル層２０３の不純物濃度は１×1015/cm3〜5×1015/cm3程度とする。そして、Ｎ−型エピタキシャル層２０３内にＬＤＭＯＳトランジスタ領域２５０とＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０との上部分離層である、Ｐ型分離層２１１を形成する。 First, as shown in FIG. 3A, an N + type buried layer 202 is formed in each of the LDMOS transistor region 250 and the LOCOS offset drain type high voltage MOS transistor region 260 in the P type silicon substrate 201. Then, in order to separate the LDMOS transistor region 250 and the LOCOS offset drain type high voltage MOS transistor region 260, a P + type isolation buried layer 212 is formed in the isolation region 270. Thereafter, an N − type epitaxial layer 203 is formed on the P type silicon substrate 201. At this time, the impurity concentration of the N + -type buried layer 202 is about 1 × 10 18 / cm 3 to 1 × 10 20 / cm 3 , and the impurity concentration of the P + -type isolation buried layer 212 is 1 × 10 17 / cm 3 to 1 × 10 19 / cm 3 approximately, N - impurity concentration type epitaxial layer 203 is set to 1 × 10 15 / cm 3 ~5 × 10 15 / cm 3 order. Then, a P-type isolation layer 211 that is an upper isolation layer between the LDMOS transistor region 250 and the LOCOS offset drain type high voltage MOS transistor region 260 is formed in the N − type epitaxial layer 203.

つぎに、図３Ｂに示すように、Ｎ−型エピタキシャル層２０３上に酸化膜２３０を形成し、その上部に窒化膜２３１を形成する。そして、活性領域となる部分に酸化膜２３０と窒化膜２３１とをパターニングする。 Next, as shown in FIG. 3B, an oxide film 230 is formed on the N − type epitaxial layer 203, and a nitride film 231 is formed thereon. Then, the oxide film 230 and the nitride film 231 are patterned in a portion that becomes an active region.

つぎに、フォトレジスト２２０を塗布・現像し、これをマスクとしてＬＯＣＯＳオフセット領域となるところに、ボロンを注入してＰ−型オフセット層２０６を形成する。Ｐ−型オフセット層２０６の注入ドーズ量は7×1012/cm2〜1.5×1013/cm2程度とする。 Next, a photoresist 220 is applied and developed, and using this as a mask, boron is implanted into a LOCOS offset region to form a P − type offset layer 206. The implantation dose of the P − type offset layer 206 is about 7 × 10 12 / cm 2 to 1.5 × 10 13 / cm 2 .

つぎに、図３Ｃに示すように、フォトレジスト２２０を除去した後、窒化膜２３１をマスクとしてＬＯＣＯＳ酸化膜２０５を成長させる。ＬＯＣＯＳ酸化膜２０５は、例えばパイロジェニック酸化で1000℃100分程度の熱処理を行うことによって形成される。このときのＬＯＣＯＳ酸化膜２０５の膜厚は400nm〜600nm程度である。そして、ＬＤＭＯＳトランジスタ領域２５０のゲート部となるところにゲート酸化膜２０７Ｂを形成し、その上部にドレイン側のＬＯＣＯＳ酸化膜２０５に跨ってポリシシリコンからなるゲート電極２０８Ｂを形成する。また、ゲート酸化膜２０７Ｂおよびゲート電極２０８Ｂの形成と同一条件同一工程で、ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０のゲート部となるところにゲート酸化膜２０７Ａを形成し、その上部にドレイン側のＬＯＣＯＳ酸化膜２０５に跨ってポリシリコンからなるゲート電極２０８Ａを形成する。   Next, as shown in FIG. 3C, after the photoresist 220 is removed, a LOCOS oxide film 205 is grown using the nitride film 231 as a mask. The LOCOS oxide film 205 is formed, for example, by performing heat treatment at 1000 ° C. for about 100 minutes by pyrogenic oxidation. At this time, the thickness of the LOCOS oxide film 205 is about 400 nm to 600 nm. Then, a gate oxide film 207B is formed at the gate of the LDMOS transistor region 250, and a gate electrode 208B made of polysilicon is formed over the drain LOCOS oxide film 205 thereon. The gate oxide film 207A is formed at the gate portion of the LOCOS offset drain type high breakdown voltage MOS transistor region 260 in the same process and the same process as the formation of the gate oxide film 207B and the gate electrode 208B. A gate electrode 208 A made of polysilicon is formed across the LOCOS oxide film 205.

つぎに、ＬＤＭＯＳトランジスタ領域２５０のゲート電極２０８Ｂに対してセルフアラインで、ボロン注入によりＰ型のボディ層２０４Ｂを形成し、この工程と同時にボロン注入によりＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０のドレイン領域にＰ型電界緩和層２０４Ａを形成する。   Next, a P-type body layer 204B is formed by boron implantation in a self-aligned manner with respect to the gate electrode 208B of the LDMOS transistor region 250, and simultaneously with this step, the drain of the LOCOS offset drain type high breakdown voltage MOS transistor region 260 is formed by boron implantation. A P-type electric field relaxation layer 204A is formed in the region.

つぎに、図３Ｄに示すように、ＬＤＭＯＳトランジスタ領域２５０のソース領域２１０Ａおよびドレイン領域２１０Ｂを、Ｎ型不純物の注入により形成する。そして、ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域２６０のＰ型電界緩和層２０４Ａ中にＰ＋型高濃度ドレイン層２０９Ａを、オフセット層上のＬＯＣＯＳ酸化膜端のバーズビークから一定の距離を空けるようにフォトレジストでマスキングをし、ボロンを注入することにより形成する。また、ゲート電極を挟んでドレイン領域と反対の領域に、ゲート電極２０８Ａに対してセルフアラインでＰ＋型高濃度ソース層２０９Ｂをボロン注入により形成する。Ｐ＋型高濃度ドレイン層２０９ＡとＰ＋型高濃度ソース層２０９Ｂとは同一の注入条件で形成される。Ｐ＋型高濃度ドレイン層２０９ＡとＰ＋型高濃度ソース層２０９Ｂの注入ドーズ量は2E15/cm2〜6E15/cm2程度とする。 Next, as shown in FIG. 3D, the source region 210A and the drain region 210B of the LDMOS transistor region 250 are formed by implanting N-type impurities. Then, the P + -type high-concentration drain layer 209A in the P-type field relaxation layer 204A of the LOCOS offset drain type high-breakdown-voltage MOS transistor region 260 is exposed to a certain distance from the bird's beak at the end of the LOCOS oxide film on the offset layer. It is formed by masking with a resist and implanting boron. Further, a P + type high concentration source layer 209B is formed by boron implantation in a region opposite to the drain region across the gate electrode in a self-aligned manner with respect to the gate electrode 208A. The P + type high concentration drain layer 209A and the P + type high concentration source layer 209B are formed under the same implantation conditions. The implantation dose of the P + -type high concentration drain layer 209A and the P + -type high concentration source layer 209B is about 2E15 / cm 2 to 6E15 / cm 2 .

なお、図３Ｄにおいて、符号２１３はＰ型のボディ層２０４Ｂの電位をとるためのコンタクト層を示す。符号２１４はＮ−型エピタキシャル層２０３の電位をとるためのＮ＋コンタクト層を示す。 In FIG. 3D, reference numeral 213 denotes a contact layer for taking the potential of the P-type body layer 204B. Reference numeral 214 denotes an N + contact layer for taking the potential of the N − type epitaxial layer 203.

つぎに、図には示さないが、層間絶縁膜としてＰＳＧ膜を形成し、Ｐ＋型高濃度ドレイン層２０９ＡとＰ＋型高濃度ソース層２０９Ｂとおよびゲート電極２０８に接続孔（コンタクト）を設けてアルミ配線とパッシベーション膜とを形成することにより半導体装置が完成する。 Next, although not shown in the drawing, a PSG film is formed as an interlayer insulating film, and connection holes (contacts) are provided in the P + type high concentration drain layer 209A, the P + type high concentration source layer 209B, and the gate electrode 208. Thus, the semiconductor device is completed by forming the aluminum wiring and the passivation film.

上記の製造方法によると、実施の形態１と同じ効果に加え、ＬＤＭＯＳトランジスタのボディ層２０４Ｂと同じ工程でＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタのＰ型電界緩和層２０４Ａを形成するので、製造工程を追加することなくＰ型電界緩和層２０４Ｂを形成し、製造コストを削減することができる。   According to the above manufacturing method, in addition to the same effects as those of the first embodiment, the P-type field relaxation layer 204A of the LOCOS offset drain type high voltage MOS transistor is formed in the same process as the body layer 204B of the LDMOS transistor. The P-type electric field relaxation layer 204B can be formed without adding, and the manufacturing cost can be reduced.

以上説明したように、本発明はＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタおよびその製造方法などに有用である。   As described above, the present invention is useful for a LOCOS offset drain type high voltage MOS transistor and a method for manufacturing the same.

本発明の実施の形態１に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す第１の工程断面図である。FIG. 10 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す第２の工程断面図である。It is 2nd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す第３の工程断面図である。It is 3rd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す第４の工程断面図である。It is 4th process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置の製造方法を示す第１の工程断面図である。It is 1st process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体装置の製造方法を示す第２の工程断面図である。It is 2nd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体装置の製造方法を示す第３の工程断面図である。It is 3rd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体装置の製造方法を示す第４の工程断面図である。It is 4th process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 従来技術に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a prior art. 従来技術に係る半導体装置の製造方法を示す第１の工程断面図である。It is 1st process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art. 従来技術に係る半導体装置の製造方法を示す第２の工程断面図である。It is 2nd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art. 従来技術に係る半導体装置の製造方法を示す第３の工程断面図である。It is 3rd process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art. 従来技術に係る半導体装置の製造方法を示す第４の工程断面図である。It is 4th process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art. ＬＯＣＯＳ酸化膜端から高濃度ドレイン層までの距離と耐圧の関係を示すグラフである。It is a graph which shows the relationship between the distance from a LOCOS oxide film edge to a high concentration drain layer, and a proof pressure.

符号の説明Explanation of symbols

１０１ Ｐ型シリコン基板
１０２ Ｎ＋型埋め込み層
１０３ Ｎ−型エピタキシャル層
１０４ Ｐ型電界緩和層
１０５ ＬＯＣＯＳ酸化膜
１０６ Ｐ−型オフセット層
１０７ ゲート酸化膜
１０８ ゲート電極
１０９Ａ Ｐ＋型高濃度ドレイン層
１０９Ｂ Ｐ＋型高濃度ソース層
１２０〜１２１ フォトレジスト
１３０ 酸化膜
１３１ 窒化膜
２０１ Ｐ型シリコン基板
２０２ Ｎ＋型埋め込み層
２０３ Ｎ−型エピタキシャル層
２０４Ａ ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタのＰ型電界緩和層
２０４Ｂ ＬＤＭＯＳトランジスタのボディ層
２０５ ＬＯＣＯＳ酸化膜
２０６ Ｐ−型オフセット層
２０７ ゲート酸化膜
２０８ ゲート電極
２０９Ａ ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタのＰ＋型高濃度ドレイン層
２０９Ｂ ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタのＰ＋型高濃度ソース層
２１０Ａ ＬＤＭＯＳトランジスタのＮ＋型高濃度ドレイン層
２１０Ｂ ＬＤＭＯＳトランジスタのＮ＋型高濃度ソース層
２１１ Ｐ型分離層
２１２ Ｐ型分離埋め込み層
２２０ フォトレジストマスク
２３０ 酸化膜
２３１ 窒化膜
２５０ ＬＤＭＯＳトランジスタ領域
２６０ ＬＯＣＯＳオフセットドレイン型高耐圧ＭＯＳトランジスタ領域
２７０ 分離領域
３０１ Ｐ型シリコン基板
３０２ Ｎ＋型埋め込み層
３０３ Ｎ−型エピタキシャル層
３０４ Ｐ型電界緩和層
３０５ ＬＯＣＯＳ酸化膜
３０６ Ｐ−型オフセット層
３０６Ａ 拡散層
３０７ ゲート酸化膜
３０８ ゲート電極
３０９Ａ Ｐ＋型高濃度ドレイン層
３０９Ｂ Ｐ＋型高濃度ソース層
３２０、３２１、３２２ フォトレジスト
３３０ 酸化膜
３３１ 窒化膜
101 P type silicon substrate 102 N + type buried layer 103 N − type epitaxial layer 104 P type electric field relaxation layer 105 LOCOS oxide film 106 P − type offset layer 107 gate oxide film 108 gate electrode 109A P + type high concentration drain layer 109B P + Type high concentration source layer 120-121 photoresist 130 oxide film 131 nitride film 201 P type silicon substrate 202 N + type buried layer 203 N − type epitaxial layer 204A P type field relaxation layer 204B of LOCOS offset drain type high voltage MOS transistor 204B body layer 205 LOCOS oxide film 206 P of the LDMOS transistor - type offset layer 207 gate oxide film 208 gate electrode 209A LOCOS offset drain type high voltage MOS transistor P + -type highly-doped de In layer 209B LOCOS offset drain type high voltage MOS transistor of the P + type high concentration source layer 210A LDMOS transistor of the N + -type high concentration drain layer 210B LDMOS transistor N + -type highly-doped source layer 211 P-type isolation layer 212 P-type isolation Buried layer 220 Photoresist mask 230 Oxide film 231 Nitride film 250 LDMOS transistor region 260 LOCOS offset drain type high voltage MOS transistor region 270 Isolation region 301 P type silicon substrate 302 N + type buried layer 303 N − type epitaxial layer 304 P type electric field relieving layer 305 LOCOS oxide film 306 P - -type offset layer 306A diffusion layer 307 gate oxide film 308 gate electrode 309A P + -type high concentration drain layer 309B P + -type highly concentrated Source layer 320, 321, 322 photoresist 330 oxide film 331 the nitride film

Claims (4)

半導体基板上に形成された第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタを含む半導体装置であって、
第２導電型の半導体層に形成された第１導電型の電界緩和層および高濃度ドレイン層から成るドレイン領域と、
前記半導体層に形成された第１導電型の高濃度ソース層から成るソース領域と、
前記ドレイン領域と前記ソース領域の間で前記半導体層表面の活性領域に形成されたゲート酸化膜と、
前記ドレイン領域と前記ゲート酸化膜の間の前記半導体層表面に形成されたＬＯＣＯＳ酸化膜と、
前記ゲート酸化膜上に前記ＬＯＣＯＳ酸化膜に跨って形成されたゲート電極と、
前記ＬＯＣＯＳ酸化膜下に形成された第１導電型のオフセット層とを備え、
前記電界緩和層は前記オフセット層に隣接して形成され、前記電界緩和層の不純物濃度は前記オフセット層より濃く、かつ前記高濃度ドレイン層より薄く、
前記高濃度ドレイン層は前記電界緩和層内に形成され、かつ前記ＬＯＣＯＳ酸化膜端より離間して形成されている半導体装置。 A semiconductor device including an offset drain type MOS transistor having a first conductivity type channel formed on a semiconductor substrate,
A drain region comprising a first conductivity type electric field relaxation layer and a high concentration drain layer formed in a second conductivity type semiconductor layer;
A source region comprising a high-concentration source layer of a first conductivity type formed in the semiconductor layer;
A gate oxide film formed in an active region of the semiconductor layer surface between the drain region and the source region;
A LOCOS oxide film formed on the surface of the semiconductor layer between the drain region and the gate oxide film;
A gate electrode formed on the gate oxide film across the LOCOS oxide film;
An offset layer of a first conductivity type formed under the LOCOS oxide film,
The electric field relaxation layer is formed adjacent to the offset layer, and the impurity concentration of the electric field relaxation layer is deeper than the offset layer and thinner than the high concentration drain layer,
The semiconductor device, wherein the high concentration drain layer is formed in the electric field relaxation layer and is spaced apart from an end of the LOCOS oxide film. 前記ＬＯＣＯＳ酸化膜の端部から前記高濃度ドレイン層までの距離は０．８μｍ以上である請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a distance from an end portion of the LOCOS oxide film to the high-concentration drain layer is 0.8 μm or more. 第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタを半導体基板上に形成する半導体装置の製造方法であって、
第２導電型の半導体層上に酸化膜を介して窒化膜を形成する工程と、
前記半導体層上の活性領域に前記窒化膜をパターニングする工程と、
前記窒化膜をマスクとして前記半導体層に第１導電型のオフセット層を形成する工程と、
前記窒化膜をマスクとして前記半導体層表面にＬＯＣＯＳ酸化膜を形成する工程と、
前記ＬＯＣＯＳ酸化膜の形成工程の後に前記窒化膜を除去する工程と、
前記半導体層表面の活性領域にゲート酸化膜を形成する工程と、
前記ゲート酸化膜上に前記ＬＯＣＯＳ酸化膜に跨ってゲート電極を形成する工程と、
前記オフセット層に隣接した前記半導体層のドレイン領域に第１導電型の電界緩和層を形成する工程と、
前記電界緩和層内に第１導電型の高濃度ドレイン層を形成し、前記第１導電型の高濃度ドレイン層に対して前記ゲート電極を挟んだ位置で前記半導体層に第１導電型の高濃度ソース層とを形成する工程とを含み、
前記高濃度ドレイン層は前記ＬＯＣＯＳ酸化膜の端部から離間して形成されている半導体装置の製造方法。 A method of manufacturing a semiconductor device, wherein an offset drain type MOS transistor having a channel of a first conductivity type is formed on a semiconductor substrate,
Forming a nitride film on the second conductivity type semiconductor layer via an oxide film;
Patterning the nitride film in an active region on the semiconductor layer;
Forming a first conductivity type offset layer on the semiconductor layer using the nitride film as a mask;
Forming a LOCOS oxide film on the surface of the semiconductor layer using the nitride film as a mask;
Removing the nitride film after forming the LOCOS oxide film;
Forming a gate oxide film in an active region of the semiconductor layer surface;
Forming a gate electrode on the gate oxide film across the LOCOS oxide film;
Forming an electric field relaxation layer of a first conductivity type in a drain region of the semiconductor layer adjacent to the offset layer;
A first conductivity type high-concentration drain layer is formed in the electric field relaxation layer, and the first conductivity type high-concentration drain layer is formed on the semiconductor layer at a position sandwiching the gate electrode with respect to the first conductivity type high-concentration drain layer. Forming a concentration source layer,
The method of manufacturing a semiconductor device, wherein the high-concentration drain layer is formed apart from an end portion of the LOCOS oxide film. 第１導電型のチャネルを有するオフセットドレイン型ＭＯＳトランジスタと第２導電型のチャネルを有するラテラル型ＤＭＯＳトランジスタとを同一半導体基板上に形成する半導体装置の製造方法であって、
第２導電型の半導体層内にＭＯＳトランジスタ領域とＤＭＯＳトランジスタ領域とを分離する素子分離層を形成する工程と、
前記半導体層上に酸化膜を介して窒化膜を形成する工程と、
前記半導体層上の活性領域に前記窒化膜をパターニングする工程と、
前記窒化膜をマスクとして前記ＭＯＳトランジスタ領域の前記半導体層に第１導電型のオフセット層を形成する工程と、
前記窒化膜をマスクとして前記半導体層表面にＬＯＣＯＳ酸化膜を形成する工程と、
前記ＬＯＣＯＳ酸化膜の形成工程の後に前記窒化膜を除去する工程と、
前記半導体層表面の活性領域にゲート酸化膜を形成する工程と、
前記ゲート酸化膜上に前記ＬＯＣＯＳ酸化膜に跨ってゲート電極を形成する工程と、
前記ＭＯＳトランジスタ領域の前記オフセット層に隣接した前記半導体層のドレイン領域に第１導電型の電界緩和層を形成すると同時に、前記ＤＭＯＳトランジスタ領域の前記ゲート電極に挟まれたソース領域に第１導電型のボディ層を形成する工程と、
前記ＭＯＳトランジスタ領域において、前記電界緩和層内に第１導電型の高濃度ドレイン層を形成し、前記第１導電型の高濃度ドレイン層に対して前記ゲート電極を挟んだ位置で前記ゲート電極を挟んだ前記半導体層に第１導電型の高濃度ソース層とを形成する工程と、
前記ＤＭＯＳトランジスタ領域において、前記ボディ層内に第２導電型の高濃度ソース層を形成し、前記第２導電型の高濃度ソース層に対して前記ゲート電極を挟んだ位置で前記半導体層に第２導電型のドレイン層とを形成する工程とを含み、
前記ＭＯＳトランジスタ領域における前記高濃度ドレイン層は前記ＬＯＣＯＳ酸化膜の端部から離間して形成されている半導体装置の製造方法。 A method of manufacturing a semiconductor device, wherein an offset drain MOS transistor having a first conductivity type channel and a lateral DMOS transistor having a second conductivity type channel are formed on the same semiconductor substrate,
Forming an element isolation layer that separates the MOS transistor region and the DMOS transistor region in the semiconductor layer of the second conductivity type;
Forming a nitride film on the semiconductor layer via an oxide film;
Patterning the nitride film in an active region on the semiconductor layer;
Forming a first conductivity type offset layer on the semiconductor layer in the MOS transistor region using the nitride film as a mask;
Forming a LOCOS oxide film on the surface of the semiconductor layer using the nitride film as a mask;
Removing the nitride film after forming the LOCOS oxide film;
Forming a gate oxide film in an active region of the semiconductor layer surface;
Forming a gate electrode on the gate oxide film across the LOCOS oxide film;
A first conductivity type electric field relaxation layer is formed in the drain region of the semiconductor layer adjacent to the offset layer in the MOS transistor region, and at the same time, a first conductivity type is formed in the source region sandwiched between the gate electrodes in the DMOS transistor region. Forming a body layer of
In the MOS transistor region, a high-concentration drain layer of a first conductivity type is formed in the electric field relaxation layer, and the gate electrode is placed at a position sandwiching the gate electrode with respect to the high-concentration drain layer of the first conductivity type. Forming a first conductivity type high-concentration source layer in the sandwiched semiconductor layer;
In the DMOS transistor region, a second conductivity type high concentration source layer is formed in the body layer, and the semiconductor layer is formed at a position sandwiching the gate electrode with respect to the second conductivity type high concentration source layer. Forming a drain layer of two conductivity types,
The method for manufacturing a semiconductor device, wherein the high-concentration drain layer in the MOS transistor region is formed apart from an end portion of the LOCOS oxide film.
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