JP2006237653A - Adhesive for bonding semiconductor device, and method of bonding the semiconductor device - Google Patents

Adhesive for bonding semiconductor device, and method of bonding the semiconductor device Download PDF

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JP2006237653A
JP2006237653A JP2006161915A JP2006161915A JP2006237653A JP 2006237653 A JP2006237653 A JP 2006237653A JP 2006161915 A JP2006161915 A JP 2006161915A JP 2006161915 A JP2006161915 A JP 2006161915A JP 2006237653 A JP2006237653 A JP 2006237653A
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semiconductor device
adhesive
wiring pattern
semiconductor element
circuit board
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Hiroshi Ogasawara
宏 小笠原
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Kyocera Chemical Corp
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Kyocera Chemical Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor devices with a high reliablility for connectivity that prevents voids and connection errors and an adhesive to be used for the purpose in alloy formation and junction through thermal eutectic crystal of a metal projection on a semiconductor device electronic pad and a wiring pattern on a circuit board. <P>SOLUTION: This semiconductor device manufacturing method has an epoxy resin adhesive 6, containing fine fillers interposed between a semiconductor device 1 with a metal projection 3 on an electrode pad 2 and a circuit board 4 with a wiring pattern 5, corresponding to the electrode pad. After positioning the metal projection on the semiconductor device and the wiring pattern on the circuit board, this method electrically connects the metal project and circuit board through eutectic alloy formation, by subjecting to heating and pressurization 7 and hardens 6' the adhesive to fix the semiconductor device and circuit board. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子の電極パツドと配線基板とを簡便に接続する半導体装置の製造方法、およびそれに使用される接着剤に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which an electrode pad of a semiconductor element and a wiring board are simply connected, and an adhesive used therefor.

近年、半導体素子を多数個用いるデバイス、機器の開発が促進されてきている。例えば、メモリーカード、液晶やＥＬのディスプレイパネル等が有り、これらはいずれも多数個のＩＣ、ＬＳＩを一定の面積を有する基板に、高密度にしかも薄型に搭載しなければならない。ＩＣ、ＬＳＩの実装手段としては熱圧接接続によるフリップチップ方式が公知である（例えば、特許文献１参照。）。   In recent years, development of devices and equipment using a large number of semiconductor elements has been promoted. For example, there are a memory card, a liquid crystal display panel, an EL display panel, and the like, all of which have to mount a large number of ICs and LSIs on a substrate having a certain area in a high density and in a thin shape. As a means for mounting an IC or LSI, a flip chip method using a thermal pressure connection is known (for example, see Patent Document 1).

しかしながら、熱圧接接続法には以下のような問題がある。   However, the hot press connection method has the following problems.

前記熱圧接接続によるフリップチップ方式は、半導体素子の電極パッド上に金属突起を形成し、配線基板上の配線パターンと半導体素子の金属突起を位置合せをし加熱して、光もしくは熱により接着樹脂を硬化させて、圧接のみにより金属突起と配線パターンの電気的接続を得るものである。したがって、熱圧接接続によるフリップチップ方式は、電気的接続を圧接のみにより行うため電極突起と配線パターンが固定されておらず、外部からの熱や機械的歪により配線基板に膨張や反りが発生して、接続部や半導体素子自体の剥離が発生しやすかった。   In the flip-chip method using the thermal pressure connection, metal protrusions are formed on the electrode pads of the semiconductor element, the wiring pattern on the wiring substrate and the metal protrusions of the semiconductor element are aligned and heated, and the adhesive resin is applied by light or heat. Is cured to obtain an electrical connection between the metal protrusion and the wiring pattern only by pressure welding. Therefore, in the flip chip method using the thermal pressure connection, the electrode protrusion and the wiring pattern are not fixed because the electrical connection is performed only by pressure welding, and expansion and warpage occur in the wiring board due to external heat and mechanical distortion. As a result, the connection part and the semiconductor element itself were easily peeled off.

熱圧接接続より接続信頼性の高い方法として、電極パッド上の金属突起と配線パターンとを熱共晶による合金形成を行う方法がある（例えば、特許文献２参照。）。   As a method having higher connection reliability than the thermal pressure connection, there is a method of forming an alloy by thermal eutectic between the metal protrusions on the electrode pad and the wiring pattern (for example, see Patent Document 2).

しかしながら、この熱共晶による合金形成接続法では、２８０〜４１８℃の温度範囲で共晶合金が形成されて金属突起と配線パターンの電気的接続がなされるが、接着剤樹脂はその熱共晶温度領域である２８０〜４１８℃において硬化が速すぎることにより、接続不良やボイドが発生するという問題があった。
特開昭６０−２６２４３０号公報 特開２０００−１００８６２公報 However, in this alloy formation connection method by thermal eutectic, a eutectic alloy is formed in a temperature range of 280 to 418 ° C. to electrically connect the metal projections and the wiring pattern. In the temperature range of 280 to 418 ° C., curing is too fast, resulting in problems such as poor connection and voids.
JP 60-262430 A Japanese Patent Laid-Open No. 2000-10082

本発明の目的は、このような従来の問題点を鑑み、半導体素子の電極パッド上の金属突起と配線基板の配線パターンとの熱共晶による合金形成接続法において、接続信頼性が高く、ボイド発生不良や樹脂硬化による接続不良が発生しない接続方法を可能にする半導体装置の製造方法とそれに使用する接着剤を提供することにある。   In view of the above-described conventional problems, the object of the present invention is to provide a high connection reliability and a void in the alloy forming connection method by thermal eutectic between the metal protrusion on the electrode pad of the semiconductor element and the wiring pattern of the wiring substrate. An object of the present invention is to provide a method of manufacturing a semiconductor device that enables a connection method that does not cause generation failures or connection failures due to resin curing, and an adhesive used therefor.

本発明者は、半導体素子の電極パッド上の金属突起と配線基板の配線パターンとの熱共晶合金形成接続法において、接着剤に用いる樹脂組成物中に適量の微細フィラーを入れることによって上記問題を解決することを見いだした。また、さらに該樹脂組成物の硬化特性を最適化させることにより、ボイド発生不良などをなくすことができるということを見いだした。   The inventor of the present invention relates to the above-mentioned problem by placing an appropriate amount of fine filler in a resin composition used as an adhesive in a method for forming a eutectic alloy between a metal protrusion on an electrode pad of a semiconductor element and a wiring pattern of a wiring board. Found to solve. Furthermore, it has been found that void generation defects and the like can be eliminated by optimizing the curing characteristics of the resin composition.

即ち、本発明の半導体装置の製造方法は、
電極パッド上に金属突起を有する半導体素子と、電極パッドに相対する配線パターンを有する配線基板との間に、微細フィラーを含むエポキシ樹脂系の接着剤を介在させ、半導体素子上の金属突起と配線基板上の配線パターンを位置合せした後、加熱加圧し、金属突起と配線パターンを共晶合金形成により電気的接続を得るとともに、接着剤を光もしくは熱により硬化させて、半導体素子と配線基板とを固定することを特徴とし、また本発明の接着剤は上記半導体装置の製造方法に適合して使用されるエポキシ樹脂系の接着剤である。 That is, the method for manufacturing a semiconductor device of the present invention includes:
An epoxy resin adhesive containing a fine filler is interposed between a semiconductor element having a metal protrusion on the electrode pad and a wiring substrate having a wiring pattern opposite to the electrode pad, and the metal protrusion and wiring on the semiconductor element After aligning the wiring pattern on the substrate, heat and pressure are applied, and the metal protrusions and the wiring pattern are electrically connected by forming a eutectic alloy, and the adhesive is cured by light or heat, so that the semiconductor element and the wiring substrate The adhesive of the present invention is an epoxy resin adhesive that is used in conformity with the method for manufacturing a semiconductor device.

本発明は、半導体素子の金属突起と配線基板の配線パターンとの電気的接続は熱共晶合金接続、半導体素子と配線基板との固定が接着樹脂で行われる製造方法において、微細フィラー入り接着剤を用いることによって、接着樹脂中にボイドがなく、高い信頼性を有する電気的接続を得ることができる。   The present invention relates to an adhesive containing a fine filler in a manufacturing method in which electrical connection between a metal protrusion of a semiconductor element and a wiring pattern of a wiring board is a thermoeutectic alloy connection, and fixing between the semiconductor element and the wiring board is performed with an adhesive resin. By using, there is no void in the adhesive resin, and a highly reliable electrical connection can be obtained.

まず接着剤について具体的に説明すると、例えば、ビスフェノールＡ型エポキシ樹脂（油化シェル株式会社製；エピコート８１８）９０ｇ、ジシアンジアミド１ｇ、ニッケル粉（福田金属製；平均粒径０．４μｍ）０．５ｇをロール混合し、接着剤組成物を得た。さらに、相当量のイミダゾール（四国化成社製；２ＭＺ）を加えて、４１８℃での硬化時間が０．５秒、２秒、１０秒、２０秒となるように接着剤をそれぞれ作製した。硬化時間は、測定温度のホットプレート上に接着剤組成物を０．２５ｇのせ、テフロン（登録商標）製ミニスパチュラでかきまぜ、糸引きがなくなった時間を測定する。   First, the adhesive will be specifically described. For example, 90 g of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd .; Epicoat 818), 1 g of dicyandiamide, 0.5 g of nickel powder (manufactured by Fukuda Metal; average particle size 0.4 μm) Were mixed with a roll to obtain an adhesive composition. Furthermore, a considerable amount of imidazole (manufactured by Shikoku Kasei Co., Ltd .; 2MZ) was added to prepare adhesives such that the curing time at 418 ° C. was 0.5 seconds, 2 seconds, 10 seconds and 20 seconds. The curing time is measured by placing 0.25 g of the adhesive composition on a hot plate at a measurement temperature, stirring with a Teflon (registered trademark) mini spatula, and eliminating stringing.

接着剤に使用するエポキシ樹脂、硬化剤、硬化促進剤などの配合原料は、エポキシ樹脂接着剤一般に使用されるものが制限なく使用できる。   As the compounding raw materials such as an epoxy resin, a curing agent, and a curing accelerator used for the adhesive, those generally used for an epoxy resin adhesive can be used without limitation.

次に、電子部品の製造にかかる実施例を、図１と表１〜３を用いて説明する。図１において、１は半導体素子、４は配線基板である。半導体素子１の電極パッド２として、Ｃｒ−Ｃｕ、Ｔｉ−Ｐｄ等の多層金属膜を被着せしめ、該電極パッド２上に電解メッキ法により金属突起３を形成する。金属突起３は、Ａｕ、Ａｇ、Ｃｕ、半田等の材料で３〜３０μｍの厚さに構成される。   Next, the Example concerning manufacture of an electronic component is described using FIG. 1 and Tables 1-3. In FIG. 1, 1 is a semiconductor element, and 4 is a wiring board. A multilayer metal film such as Cr—Cu or Ti—Pd is deposited as the electrode pad 2 of the semiconductor element 1, and a metal protrusion 3 is formed on the electrode pad 2 by electrolytic plating. The metal protrusion 3 is made of a material such as Au, Ag, Cu, or solder and has a thickness of 3 to 30 μm.

一方、配線基板４は、ガラス板、セラミック板、樹脂板、金属酸化物を表面に被覆した金属板等で構成され、その表面において、少なくとも半導体素子１の金属突起３と対応した位置に配線パターン５を形成してある。配線パターン５は、Ｃｕ、Ａｌ、Ａｕ、ＩＴＯ等を母体にし、酸化しやすい材質例えば、Ｃｕであれば、Ａｕメッキ、Ｓｎメッキ、半田メッキ等の処理を施してある。   On the other hand, the wiring substrate 4 is composed of a glass plate, a ceramic plate, a resin plate, a metal plate coated with a metal oxide, or the like, and on the surface thereof, the wiring pattern is at least at a position corresponding to the metal protrusion 3 of the semiconductor element 1. 5 is formed. The wiring pattern 5 is made of Cu, Al, Au, ITO or the like as a base material and is easily oxidized. For example, if it is Cu, it is subjected to processing such as Au plating, Sn plating, and solder plating.

上記配線基板４面上か若しくは半導体素子１の金属突起３を形成した面上に、前記配合で作成した接着剤７を塗布載置する（図１）。このとき、接着剤の代わりに接着シートを用いてもよい。なお樹脂組成物は、熱硬化でなく、光硬化によるものでもよい。   On the surface of the wiring substrate 4 or the surface on which the metal protrusions 3 of the semiconductor element 1 are formed, the adhesive 7 created by the above composition is applied and placed (FIG. 1). At this time, an adhesive sheet may be used instead of the adhesive. In addition, the resin composition may be not photocured but photocured.

次に、半導体素子１上の金属突起３と配線基板４上の配線パターン５とを、図１のごとく位置合せし、両者を加圧７せしめ、熱共晶温度範囲で加熱する。この加圧７により、樹脂６は半導体素子１の金属突起３側の全面に押し拡げられ、かつ、前記金属突起３と配線パターン５とはその加熱により熱共晶合金を作り、電気的接続を得る。この工程で、押し拡げられた樹脂６は、熱共晶温度範囲の熱もしくは光が加えられて、硬化樹脂６′となり、硬化樹脂６′により半導体素子１と配線基板４とは金属突起３と配線パターン６との電気的導通を継続したまま固定されることになる。   Next, the metal protrusion 3 on the semiconductor element 1 and the wiring pattern 5 on the wiring substrate 4 are aligned as shown in FIG. 1, and both are pressed 7 and heated in the thermal eutectic temperature range. By this pressurization 7, the resin 6 is spread over the entire surface of the semiconductor element 1 on the side of the metal protrusion 3, and the metal protrusion 3 and the wiring pattern 5 form a heat eutectic alloy by heating to make an electrical connection. obtain. In this step, the expanded resin 6 is subjected to heat or light in the thermal eutectic temperature range to become a cured resin 6 ′, and the semiconductor element 1 and the wiring substrate 4 are separated from the metal protrusion 3 by the cured resin 6 ′. It is fixed while continuing electrical continuity with the wiring pattern 6.

即ち、半導体素子１の金属突起３と配線基板４上の配線パターン５との電気的接続は熱共晶合金で行われ、半導体素子１と配線基板４との固定は硬化した樹脂６′によってなされるものである。このとき、微細フィラーが樹脂６中に存在することにより、ボイドがなく信頼性の高い接続を得ることができる。更にニッケル粉を使用した場合には、ニッケル粉によって、硬化樹脂６′の電極パッド２へのアンカー効果が得られ、信頼性の高い半導体装置を得ることができるのである。なお、微細フィラーとしては、エポキシ樹脂組成物用一般のフィラーが使用でき、２種類以上の微細フィラーを配合することも差支えない。   That is, the electrical connection between the metal protrusion 3 of the semiconductor element 1 and the wiring pattern 5 on the wiring board 4 is made of a heat eutectic alloy, and the semiconductor element 1 and the wiring board 4 are fixed by a cured resin 6 '. Is. At this time, since the fine filler is present in the resin 6, a highly reliable connection without voids can be obtained. Further, when nickel powder is used, the anchor effect of the cured resin 6 'to the electrode pad 2 is obtained by the nickel powder, and a highly reliable semiconductor device can be obtained. In addition, as a fine filler, the general filler for epoxy resin compositions can be used, and it may also mix | blend 2 or more types of fine fillers.

シリカ粉の配合量は、０．１〜４０重量％が好ましい。０．１重量％未満ではボイド低減に十分な効果がなく、４０重量％を超えると電極突起と配線パターン間の接続が十分でなくなる。   As for the compounding quantity of silica powder, 0.1 to 40 weight% is preferable. If it is less than 0.1% by weight, there is no sufficient effect for reducing voids, and if it exceeds 40% by weight, the connection between the electrode protrusion and the wiring pattern becomes insufficient.

ニッケル粉の配合量は、０．１〜３０重量％が好ましい。０．１重量％未満ではボイド低減に十分な効果がなく、３０重量％を超えると隣接電極間の絶縁性が十分でなくなる。 The blending amount of nickel powder is preferably 0.1 to 30% by weight. If it is less than 0.1% by weight, there is no sufficient effect for reducing voids, and if it exceeds 30% by weight, the insulation between adjacent electrodes becomes insufficient.

本発明は、半導体素子１上の金属突起３と配線基板４の配線パターン５との熱共晶合金による接続において、半導体素子１と配線基板４の間に介在せしめる接着剤樹脂組成物に微細フィラーを添加した接着剤を使用することにより、高い接続信頼性を得ることができ、また、ボイドの発生を抑制できるものである。接続信頼性結果およびボイド評価結果を表１、表２に示す。   The present invention provides a fine filler to the adhesive resin composition interposed between the semiconductor element 1 and the wiring board 4 in the connection between the metal protrusion 3 on the semiconductor element 1 and the wiring pattern 5 of the wiring board 4 by a thermal eutectic alloy. By using the adhesive to which is added, high connection reliability can be obtained, and generation of voids can be suppressed. Tables 1 and 2 show connection reliability results and void evaluation results.

Figure 2006237653
○印…１００％接続、△印…８０％接続、×印…５０％以下接続。
Figure 2006237653
 ○: 100% connected, Δ: 80% connected, x: 50% or less connected.

Ａｕメバンブ付きＩＣチップをＳｎメッキ回路パターン上に上記温度にて接合した後、接合部分の導通確認を行った。 After bonding the IC chip with Au membamboo onto the Sn plating circuit pattern at the above temperature, the conduction of the bonded portion was confirmed.

Figure 2006237653
○印…ボイドなし、△印…小さなボイド発生、×印…大きなボイド発生。
Figure 2006237653
 ○: No void, △: Small void generated, x: Large void generated.

Ａｕメバンブ付きＩＣチップをＳｎメッキ回路パターン上に上記温度にて接合した後、ボイドの目視確認を行った。 After bonding the IC chip with Au membamboo onto the Sn plating circuit pattern at the above temperature, the voids were visually confirmed.

また、接着剤組成物の樹脂の硬化時間は、３００℃〜４１８℃における硬化時間が１〜１５秒であることが好ましい。共晶接続では、３００〜４１８℃の温度範囲が用いられている。各共晶接続温度において樹脂硬化時間が１秒未満と速い場合、半導体素子の電極と配線基板の配線パターンが触れる前に樹脂が硬化してしまうため接続不良となる。また、硬化時間が１５秒を超えて遅い場合、反応熱量が小さくなりすぎることとなり、樹脂が硬化しなくなり、半導体素子と配線基板の固定が不可能となる。この硬化時間範囲を反応熱量で示すと４０〜５００ｍＪ／ｍｇとなる。その結果を表３に示す。   Further, the curing time of the resin of the adhesive composition is preferably 1 to 15 seconds at 300 to 418 ° C. In the eutectic connection, a temperature range of 300 to 418 ° C. is used. When the resin curing time is as fast as less than 1 second at each eutectic connection temperature, the resin is cured before the electrodes of the semiconductor element and the wiring pattern of the wiring substrate are touched, resulting in poor connection. In addition, when the curing time is longer than 15 seconds, the amount of reaction heat becomes too small, the resin is not cured, and the semiconductor element and the wiring board cannot be fixed. When this curing time range is indicated by the amount of reaction heat, it is 40 to 500 mJ / mg. The results are shown in Table 3.

Figure 2006237653
○印…１００％接続、△印…８０％接続、×印…５０％以下接続。
Figure 2006237653
 ○: 100% connected, Δ: 80% connected, x: 50% or less connected.

Ａｕメバンブ付きＩＣチップをＳｎメッキ回路パターン上に上記温度にて接合した後に、熱共晶合金層の目視確認を行った。 After joining the IC chip with Au membambou on the Sn plating circuit pattern at the above temperature, the thermal eutectic alloy layer was visually confirmed.

本発明の実施例における接着剤を使用した半導体装置の断面図である。It is sectional drawing of the semiconductor device using the adhesive agent in the Example of this invention.

符号の説明Explanation of symbols

１ 半導体素子
２ 電極パッド
３ 金属突起
４ 配線基板
５ 配線パターン
６（６′） 接着剤（硬化接着剤）
７ 加圧 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode pad 3 Metal protrusion 4 Wiring board 5 Wiring pattern 6 (6 ') Adhesive (hardening adhesive)
7 Pressurization

Claims (3)

電極パッド上に金属突起を有する半導体素子と、電極パッドに相対する配線パターンを有する配線基板との間に、シリカ粉を含み４１８℃における硬化時間が１〜１０秒であるエポキシ樹脂系の接着剤を介在させ、半導体素子上の金属突起と配線基板上の配線パターンを位置合せした後、４００〜４１８℃で加熱加圧し、金属突起と配線パターンを共晶合金形成により電気的接続を得るとともに、接着剤を光もしくは熱により硬化させて、半導体素子と配線基板とを固定することを特徴とする半導体装置の製造方法。   An epoxy resin adhesive containing silica powder and having a curing time of 1 to 10 seconds at 418 ° C. between a semiconductor element having a metal protrusion on the electrode pad and a wiring substrate having a wiring pattern opposite to the electrode pad After interposing the metal protrusion on the semiconductor element and the wiring pattern on the wiring board, the metal protrusion and the wiring pattern are heated and pressed at 400 to 418 ° C. to obtain electrical connection by forming a eutectic alloy, A method of manufacturing a semiconductor device, comprising: curing an adhesive with light or heat to fix a semiconductor element and a wiring board. シリカ粉が、平均粒径０．１〜５．０μｍであって、接着剤中に０．１〜４０重量％含まれる請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the silica powder has an average particle diameter of 0.1 to 5.0 [mu] m and is contained in the adhesive in an amount of 0.1 to 40% by weight. 請求項１または２記載の半導体装置の製造方法に適合して使用されるエポキシ樹脂系接着剤。   An epoxy resin adhesive used in conformity with the method for manufacturing a semiconductor device according to claim 1.
JP2006161915A 2006-06-12 2006-06-12 Adhesive for bonding semiconductor device, and method of bonding the semiconductor device Pending JP2006237653A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008169241A (en) * 2007-01-09 2008-07-24 Kyocera Chemical Corp Thermocompression adhesive for connecting flip chip, and method for mounting by using the same
JP2010010669A (en) * 2008-05-28 2010-01-14 Hitachi Chem Co Ltd Method of manufacturing semiconductor device, adhesive for sealing semiconductor, and semiconductor device
US8319319B2 (en) 2007-11-12 2012-11-27 Samsung Sdi Co., Ltd. Semiconductor package and mounting method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008169241A (en) * 2007-01-09 2008-07-24 Kyocera Chemical Corp Thermocompression adhesive for connecting flip chip, and method for mounting by using the same
US8319319B2 (en) 2007-11-12 2012-11-27 Samsung Sdi Co., Ltd. Semiconductor package and mounting method thereof
JP2010010669A (en) * 2008-05-28 2010-01-14 Hitachi Chem Co Ltd Method of manufacturing semiconductor device, adhesive for sealing semiconductor, and semiconductor device

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