JP2006202830A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2006202830A JP2006202830A JP2005010284A JP2005010284A JP2006202830A JP 2006202830 A JP2006202830 A JP 2006202830A JP 2005010284 A JP2005010284 A JP 2005010284A JP 2005010284 A JP2005010284 A JP 2005010284A JP 2006202830 A JP2006202830 A JP 2006202830A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 230000010355 oscillation Effects 0.000 claims description 57
- 239000003990 capacitor Substances 0.000 claims description 39
- 230000003071 parasitic effect Effects 0.000 abstract description 33
- 238000002955 isolation Methods 0.000 description 18
- 239000010410 layer Substances 0.000 description 13
- 239000013078 crystal Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
- H01L27/0682—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors comprising combinations of capacitors and resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0307—Stabilisation of output, e.g. using crystal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/014—Modifications of generator to ensure starting of oscillations
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
【解決手段】
半導体基板表面の、素子の下方の領域に、基板と異なる導電型のウエルを形成し、ウエルと基板との間の接合を逆方向にバイアスする一定の電圧を、素子に印加される信号の周波数において、逆バイアスされたウエルと基板との間の接合の容量のインピーダンスに比較して高いインピーダンスを有する抵抗を介して、印加する。
【選択図】図2
Description
20,120 半導体装置
14,114 インバータ
16,116 水晶発振子
22,122 半導体基板
24,124 ウエル
26,126 分離絶縁膜
30,130 容量素子
38 層間絶縁膜
42,46,52,54 コンタクト
44,48,56 配線
50 抵抗素子
Claims (5)
- 第1導電型の半導体基板上に形成された回路を含む半導体装置であって、
前記半導体基板上に、該半導体基板とは絶縁されて形成された、前記回路を構成する素子と、
前記半導体基板の表面の、前記素子の下方の領域に形成された、前記第1導電型とは異なる第2導電型のウエルとを有し、
前記ウエルに、該ウエルと前記半導体基板との間の接合を逆方向にバイアスする一定の電圧を、前記回路の動作時に前記素子に印加される信号の周波数において、前記逆方向にバイアスされたウエルと半導体基板との間の容量のインピーダンスに比較して大きなインピーダンスを有する抵抗を介して、印加することを特徴とする半導体装置。 - 前記素子が容量素子であることを特徴とする請求項1記載の半導体装置。
- 前記回路が、前記周波数で発振する発振回路であることを特徴とする請求項1または2記載の半導体装置。
- 前記半導体基板の表面に、前記ウエルに加えて、前記回路を構成するトランジスタが形成された前記第2導電型の第2のウエルが形成されており、
前記ウエルは、前記第2のウエルに比較して高い抵抗率を有することを特徴とする請求項1ないし3のいずれかに記載の半導体装置。 - 前記抵抗が、前記周波数において、前記逆方向にバイアスされたウエルと半導体基板との間の容量のインピーダンスに比較して、3倍以上のインピーダンスを有することを特徴とする請求項1ないし4のいずれかに記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005010284A JP2006202830A (ja) | 2005-01-18 | 2005-01-18 | 半導体装置 |
US11/330,194 US7557428B2 (en) | 2005-01-18 | 2006-01-12 | Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time |
CNA2006100049738A CN1815738A (zh) | 2005-01-18 | 2006-01-18 | 具有减小的寄生电容和短启动时间的半导体集成电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005010284A JP2006202830A (ja) | 2005-01-18 | 2005-01-18 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006202830A true JP2006202830A (ja) | 2006-08-03 |
Family
ID=36683030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005010284A Pending JP2006202830A (ja) | 2005-01-18 | 2005-01-18 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7557428B2 (ja) |
JP (1) | JP2006202830A (ja) |
CN (1) | CN1815738A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008098301A (ja) * | 2006-10-10 | 2008-04-24 | Seiko Npc Corp | 発振回路 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7981759B2 (en) * | 2007-07-11 | 2011-07-19 | Paratek Microwave, Inc. | Local oxidation of silicon planarization for polysilicon layers under thin film structures |
US8129817B2 (en) * | 2008-12-31 | 2012-03-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reducing high-frequency signal loss in substrates |
CN101866919B (zh) * | 2009-04-15 | 2012-12-12 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
DE102010011757B4 (de) * | 2010-03-17 | 2017-08-17 | Texas Instruments Deutschland Gmbh | Elektronische Vorrichtung zum Zwischenspeichern von Signalen eines temperaturkompensierten Quarzoszillators |
US8716994B2 (en) | 2012-07-02 | 2014-05-06 | Sandisk Technologies Inc. | Analog circuit configured for fast, accurate startup |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08316415A (ja) * | 1995-05-24 | 1996-11-29 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JP2000150798A (ja) * | 1998-11-17 | 2000-05-30 | Matsushita Electronics Industry Corp | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57194562A (en) | 1981-05-27 | 1982-11-30 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JPS6184048A (ja) | 1984-10-02 | 1986-04-28 | Nec Corp | 集積回路装置 |
JPS6329962A (ja) | 1986-07-23 | 1988-02-08 | Sony Corp | 半導体装置 |
JP2798020B2 (ja) * | 1995-10-25 | 1998-09-17 | 日本電気株式会社 | 半導体集積回路 |
JPH10163429A (ja) * | 1996-11-29 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置 |
US6576977B1 (en) * | 2002-09-17 | 2003-06-10 | National Semiconductor Corporation | Low cost bias technique for dual plate integrated capacitors |
JP4514460B2 (ja) * | 2004-01-29 | 2010-07-28 | 富士通セミコンダクター株式会社 | 発振回路および半導体装置 |
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2005
- 2005-01-18 JP JP2005010284A patent/JP2006202830A/ja active Pending
-
2006
- 2006-01-12 US US11/330,194 patent/US7557428B2/en active Active
- 2006-01-18 CN CNA2006100049738A patent/CN1815738A/zh active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08316415A (ja) * | 1995-05-24 | 1996-11-29 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JP2000150798A (ja) * | 1998-11-17 | 2000-05-30 | Matsushita Electronics Industry Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008098301A (ja) * | 2006-10-10 | 2008-04-24 | Seiko Npc Corp | 発振回路 |
Also Published As
Publication number | Publication date |
---|---|
CN1815738A (zh) | 2006-08-09 |
US20060157822A1 (en) | 2006-07-20 |
US7557428B2 (en) | 2009-07-07 |
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