JP2006166509A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP2006166509A
JP2006166509A JP2004350636A JP2004350636A JP2006166509A JP 2006166509 A JP2006166509 A JP 2006166509A JP 2004350636 A JP2004350636 A JP 2004350636A JP 2004350636 A JP2004350636 A JP 2004350636A JP 2006166509 A JP2006166509 A JP 2006166509A
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semiconductor device
power semiconductor
circuit board
main circuit
power
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Yasushi Nakajima
泰 中島
Masanobu Obara
雅信 小原
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Power Conversion In General (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device with reduction in inductance, surge voltage, and size. <P>SOLUTION: The power semiconductor device includes a water-cooled block provided with a cooling face, a sealing resin disposed on the cooling face and containing a power semiconductor element, a power module provided with a main terminal for protruding from a first side face of the sealing resin and a control terminal for protruding from a second side face parallel to the first side face, a main circuit board connected to the main terminal, and a control board connected to the control terminal. A pair of the main circuit board and the control terminal are disposed through the power module. The main terminal comprises a first region parallel to the cooling face, and a second region bent from the first region at an angle θ in the same plane as the main circuit board. The main circuit board and the second region are fixed by a bolt and a nut for penetrating them. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はパワー半導体装置に関し、特に、水冷ブロック一体型のパワー半導体装置に関する。   The present invention relates to a power semiconductor device, and more particularly to a water-cooled block integrated power semiconductor device.

従来、複数のパワーモジュールを含むパワー半導体装置では、平坦な冷却板の上に複数のパワーモジュールを並置するとともに、各パワーモジュールに、制御基板、主回路基板を接続していた（例えば、特許文献１参照）。
特開２００４−１２８０９９号公報 Conventionally, in a power semiconductor device including a plurality of power modules, a plurality of power modules are juxtaposed on a flat cooling plate, and a control board and a main circuit board are connected to each power module (for example, Patent Documents). 1).
JP 2004-128099 A

しかしながら、例えば１０個のパワーモジュールを使用する場合のようにパワーモジュールが多くなると、パワーモジュールが配置される冷却板の面積が大きくなるとともに、制御基板、主回路基板も大きくなり、パワー半導体装置が大型化するという問題があった。   However, when the number of power modules increases, for example, when 10 power modules are used, the area of the cooling plate on which the power modules are arranged increases, and the control board and main circuit board also increase. There was a problem of increasing the size.

また、制御基板、主回路基板が大きくなることは、それぞれの基板に設けられた配線の引回し距離の増大につながり、特に、主回路基板に形成された閉回路では、配線の引回し距離が大きくなると閉回路のインダクタンスが大きくなり、パワー半導体装置のスイッチング時に大きなサージ電圧が発生し、パワー半導体装置のスイッチング損失が増えたり、耐電圧の高いパワーチップを用いる必要が生じるという問題もあった。   In addition, an increase in the size of the control board and the main circuit board leads to an increase in the routing distance of the wirings provided on the respective boards. In particular, in the closed circuit formed on the main circuit board, the wiring routing distance is increased. When it is increased, the inductance of the closed circuit is increased, and a large surge voltage is generated at the time of switching of the power semiconductor device, so that there is a problem that the switching loss of the power semiconductor device increases or a power chip having a high withstand voltage needs to be used.

特に、パワーモジュールの主端子と主回路基板とをボルトとナットで固定する場合、固定のための空間的なマージンが必要となり、主端子を長くする必要が生じ、インダクタンスが大きくなってサージ電圧が大きくなるという問題があった。   In particular, when the main terminal of the power module and the main circuit board are fixed with bolts and nuts, a space margin for fixing is required, the main terminal needs to be lengthened, the inductance increases, and the surge voltage is increased. There was a problem of getting bigger.

そこで、本発明は、パワーモジュールを含むパワー半導体装置において、サージ電圧が小さくかつ小型化が可能なパワー半導体装置の提供を目的とする。   Therefore, an object of the present invention is to provide a power semiconductor device including a power module, which can reduce the surge voltage and can be miniaturized.

本発明は、冷却面を備えた水冷ブロックと、冷却面上に配置され、パワー半導体素子を含む封止樹脂と、封止樹脂の第１側面から突出した主端子と、第１側面に対して略平行な第２側面から突出した制御端子とを備えたパワーモジュールと、パワーモジュールを挟んで配置された１対の主回路基板と制御端子であって、主端子に接続された主回路基板と制御端子に接続された制御基板とを含み、主端子が、冷却面に略平行な第１領域と、主回路基板と略同一平面となるように該第１領域から角度（曲げ角）θだけ屈曲した第２領域からなり、主回路基板と第２領域とが、これらを貫通するボルトとナットにより固定されたことを特徴とするパワー半導体装置である。   The present invention relates to a water cooling block having a cooling surface, a sealing resin disposed on the cooling surface and including a power semiconductor element, a main terminal protruding from the first side surface of the sealing resin, and a first side surface. A power module having a control terminal projecting from a substantially parallel second side surface, a pair of main circuit boards and a control terminal arranged across the power module, the main circuit board connected to the main terminal; And a control board connected to the control terminal, the main terminal being substantially parallel to the cooling surface, and an angle (bending angle) θ from the first area so as to be substantially flush with the main circuit board. A power semiconductor device comprising a bent second region, wherein the main circuit board and the second region are fixed by bolts and nuts penetrating them.

以上のように、本発明にかかるパワー半導体装置では、インダクタンスが小さくでき、サージ電圧が小さくかつ小型化が可能なパワー半導体装置を提供することができる。   As described above, the power semiconductor device according to the present invention can provide a power semiconductor device in which the inductance can be reduced, the surge voltage can be reduced, and the size can be reduced.

以下に、図面を参照しながら、本発明の好適な実施の形態について説明する。なお、以下の説明では、「上」、「下」、「左」、「右」およびこれらの用語を含む名称を適宜使用するが、これらの方向は図面を参照した発明の理解を容易にするために用いるものであり、実施形態を上下反転、あるいは任意の方向に回転した形態も、当然に本願発明の技術的範囲に含まれる。   Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, “top”, “bottom”, “left”, “right” and names including these terms are used as appropriate, but these directions facilitate understanding of the invention with reference to the drawings. Therefore, a mode in which the embodiment is inverted upside down or rotated in an arbitrary direction is naturally included in the technical scope of the present invention.

実施の形態１．
図１は、全体が１００で表される、本発明の実施の形態１にかかるパワー半導体装置の概略図である。
パワー半導体装置１００は、水冷ブロック１０を含む。水冷ブロック１０は、例えばＰＰＳ（Polyphenylene Sulfide）、エポキシ樹脂、Ａｌ２Ｏ３等のセラミックからなる。水冷ブロック１０の冷却面１２には冷媒の流路１１が設けられている。冷却面１２の上には、パワーモジュール２０が配置され、水冷ブロック１０とパワーモジュール２０とがサブモジュール４０を構成している。 Embodiment 1 FIG.
FIG. 1 is a schematic diagram of a power semiconductor device according to a first embodiment of the present invention, the whole being represented by 100.
The power semiconductor device 100 includes a water cooling block 10. The water cooling block 10 is made of, for example, PPS (Polyphenylene Sulfide), epoxy resin, ceramic such as Al 2 O 3 . A coolant flow path 11 is provided on the cooling surface 12 of the water cooling block 10. The power module 20 is disposed on the cooling surface 12, and the water cooling block 10 and the power module 20 constitute a sub module 40.

図２は、パワーモジュール２０の断面図である。パワーモジュール２０は、例えば銅からなる放熱板２１を含む。放熱板２１の上には、例えば半田２２によりパワー半導体素子２３が固定されている。パワー半導体素子２３は、例えば、ＩＧＢＴ、パワーＦＥＴ、ダイオード等からなる。更にパワーモジュール２０は、パワー半導体素子２３とアルミニウム等の金属ワイヤや金属リード２６で接続された主端子２４および制御端子２５を含む。主端子２４、制御端子２５は、例えば銅からなり、パワーモジュール２０の対向する側面にそれぞれ設けられている。パワー半導体素子２３等は、例えばエポキシ樹脂からなる封止樹脂２７により封止されている。   FIG. 2 is a cross-sectional view of the power module 20. The power module 20 includes a heat sink 21 made of, for example, copper. A power semiconductor element 23 is fixed on the heat radiating plate 21 by, for example, solder 22. The power semiconductor element 23 is made of, for example, an IGBT, a power FET, a diode, or the like. The power module 20 further includes a main terminal 24 and a control terminal 25 connected to the power semiconductor element 23 by a metal wire such as aluminum or a metal lead 26. The main terminal 24 and the control terminal 25 are made of, for example, copper, and are respectively provided on opposite side surfaces of the power module 20. The power semiconductor element 23 and the like are sealed with a sealing resin 27 made of, for example, an epoxy resin.

図３は、パワー半導体装置１００に用いられる他のパワーモジュール３０の断面図である。図３中、図２と同一符号は同一又は相当箇所を示す。パワーモジュール３０は、放熱板２１の裏面に、例えば厚み１００μｍの銅箔からなる保護膜２９で覆われた絶縁層２８が取り付けられている。   FIG. 3 is a cross-sectional view of another power module 30 used in the power semiconductor device 100. 3, the same reference numerals as those in FIG. 2 denote the same or corresponding parts. In the power module 30, an insulating layer 28 covered with a protective film 29 made of, for example, a copper foil having a thickness of 100 μm is attached to the back surface of the heat radiating plate 21.

また、図４は、パワー半導体装置１００に用いられる他の水冷ブロック１５の断面図である（パワーモジュール２０を含む）。水冷ブロック１５には、冷却液の入口１６、出口１７が設けられており、パワーモジュール２０の裏面と水冷ブロック１５とで形成されるダクト部１７に接続されている。入口１６からダクト部１７を通って出口１８に冷却液を流すことにより、パワーモジュール２０からの熱を奪い、ラジエータ等の熱交換器（図示せず）に輸送する。   FIG. 4 is a cross-sectional view of another water cooling block 15 used in the power semiconductor device 100 (including the power module 20). The water cooling block 15 is provided with an inlet 16 and an outlet 17 for cooling liquid, and is connected to a duct portion 17 formed by the back surface of the power module 20 and the water cooling block 15. By flowing the coolant from the inlet 16 through the duct portion 17 to the outlet 18, heat from the power module 20 is taken and transported to a heat exchanger (not shown) such as a radiator.

本実施の形態にかかるパワー半導体装置１００では、バスバー基板からなる主回路基板５０と、制御基板６０とが略平行に配置され、その間に複数のサブモジュール４０が階段状に配置されている。サブモジュール４０の水冷ブロック１０には、傾斜面１３が設けられ、傾斜面１３に沿って主端子２４が折り曲げられている。傾斜面１３には凹部１４が設けられ、ナット５２がはめ込まれている。主端子２４には孔部５３が設けられており、主回路基板５０と孔部５３とを貫通するボルト５１と、ナット５２により、主端子２４が主回路基板５０に固定される。なお、ボルト５１とナット５２は、水冷ブロック１０の流路１１と干渉しない位置に配置されている。   In the power semiconductor device 100 according to the present embodiment, a main circuit board 50 made of a bus bar board and a control board 60 are arranged substantially in parallel, and a plurality of submodules 40 are arranged in a stepped manner therebetween. The water cooling block 10 of the submodule 40 is provided with an inclined surface 13, and the main terminal 24 is bent along the inclined surface 13. The inclined surface 13 is provided with a recess 14 and a nut 52 is fitted therein. The main terminal 24 is provided with a hole 53, and the main terminal 24 is fixed to the main circuit board 50 by a bolt 51 and a nut 52 that pass through the main circuit board 50 and the hole 53. Note that the bolt 51 and the nut 52 are arranged at positions that do not interfere with the flow path 11 of the water cooling block 10.

一方、制御端子２５は、制御基板６０に略垂直となるように折り曲げられ、制御基板６０を貫通した状態で固定されている。   On the other hand, the control terminal 25 is bent so as to be substantially perpendicular to the control board 60 and is fixed in a state of penetrating the control board 60.

一般に、パワー半導体装置では大電流をスイッチング動作させるが、このとき電気回路のインダクタンスが大きいと、スイッチングした時のサージ電圧が大きくなってしまう。サージ電圧が大きくなると、かかるサージ電圧によるパワー半導体素子の破壊が問題となるため、パワー半導体素子の耐電圧レベルを大きくする必要が生じる。この結果、パワー半導体素子のガードリングの幅を大きくしたり、チップの厚みを大きくしたりする必要が生じ、パワー半導体素子が大きくなってしまう。   Generally, in a power semiconductor device, a large current is switched, but if the inductance of the electric circuit is large at this time, the surge voltage at the time of switching becomes large. When the surge voltage increases, the breakdown of the power semiconductor element due to the surge voltage becomes a problem, so that the withstand voltage level of the power semiconductor element needs to be increased. As a result, it is necessary to increase the width of the guard ring of the power semiconductor element or increase the thickness of the chip, and the power semiconductor element becomes large.

また、サージ電圧が大きくなると、スイッチング時のスイッチング損失が大きくなり、パワー半導体装置の発熱量が大きくなるという問題がある。このような問題点を解決するために、パワー半導体装置の有するインダクタンスは、小さいほうが好ましい。   Further, when the surge voltage increases, there is a problem that switching loss at the time of switching increases and the amount of heat generated by the power semiconductor device increases. In order to solve such a problem, the power semiconductor device preferably has a small inductance.

ここで、例えば、パワーモジュール２０の主端子２４（Ｐ端子およびＮ端子）から平滑コンデンサ（図示しない）までの距離が大きいとインダクタンスが大きくなる。主回路基板５０を構成するバスバーは、通常、平行平板と呼ばれる、絶縁層を挟んでＰの導波路とＮの導波路が対向配置された配線構造からなる。かかる配線構造では、配線の引き回し距離が大きくなってもインダクタンスはほとんど増大しない。   Here, for example, when the distance from the main terminal 24 (P terminal and N terminal) of the power module 20 to the smoothing capacitor (not shown) is large, the inductance increases. The bus bar constituting the main circuit board 50 is generally formed of a wiring structure called a parallel plate in which a P waveguide and an N waveguide are opposed to each other with an insulating layer interposed therebetween. In such a wiring structure, the inductance hardly increases even if the wiring routing distance increases.

このため、平滑コンデンサに接続された回路のインダクタンスを小さくするためには、主回路基板５０のバスバーに接続されるパワーモジュールの主端子２４を短くすることが有効である。具体的には、パワーモジュール２０の封止樹脂２７から外部に露出した主端子２４の根元部分を、バスバーに近づけることが望ましい。   For this reason, in order to reduce the inductance of the circuit connected to the smoothing capacitor, it is effective to shorten the main terminal 24 of the power module connected to the bus bar of the main circuit board 50. Specifically, it is desirable that the base portion of the main terminal 24 exposed to the outside from the sealing resin 27 of the power module 20 is brought close to the bus bar.

ここで、複数のサブモジュール４０を階段状にずらさずに、同一平面上に並べた場合、主端子２４を主回路基板５０に接続するには、主端子２４をサブモジュール４０の上面よりも高い位置まで延ばす必要があり、本実施の形態にかかるパワー半導体装置１００より主端子２４が長くなり、インダクタンスが増加する。   Here, when the plurality of submodules 40 are arranged on the same plane without being shifted stepwise, in order to connect the main terminal 24 to the main circuit board 50, the main terminal 24 is higher than the upper surface of the submodule 40. The main terminal 24 is longer than the power semiconductor device 100 according to the present embodiment, and the inductance increases.

また、複数のサブモジュール４０を階段状にずらさずに、縦に重ねた場合、ナット部分とサブモジュール４０との間に干渉を避けるために、主端子２４を長くするか、又は水冷ブロックとパワー半導体装置を主端子２４と反対側にずらす必要が生じ、その結果、インダクタンスが増加する。   Further, when the plurality of submodules 40 are vertically stacked without being shifted stepwise, in order to avoid interference between the nut portion and the submodule 40, the main terminal 24 is lengthened, or the water cooling block and the power It becomes necessary to shift the semiconductor device to the side opposite to the main terminal 24, and as a result, the inductance increases.

このように、本発明にかかるパワー半導体装置１００では、複数のサブモジュール４０を階段状に配置し、階段の傾斜方向と略平行に主端子を折り曲げるとともに、制御端子を階段の傾斜方向と垂直に曲げる構成とすることにより、インダクタンスが小さくかつ組み立てやすい、小型のパワー半導体装置が得られる。   Thus, in the power semiconductor device 100 according to the present invention, the plurality of submodules 40 are arranged in a staircase shape, the main terminal is bent substantially parallel to the inclination direction of the staircase, and the control terminal is perpendicular to the inclination direction of the staircase. By adopting the bending configuration, a small power semiconductor device with small inductance and easy assembly can be obtained.

また、サブモジュール４０を同一平面上に配置した場合よりも制御基板６０の面積も小さくできる。   Further, the area of the control board 60 can be made smaller than when the submodule 40 is arranged on the same plane.

図５は、主端子２４の曲げ角θが異なるサブモジュール４０の概略図である。図５中、図１、２と同一符号は同一又は相当箇所を示す。また、図６は、曲げ角θと、主端子２４のネジ孔からパワーチップ２３までの距離の関係である。   FIG. 5 is a schematic view of the submodule 40 in which the bending angle θ of the main terminal 24 is different. In FIG. 5, the same reference numerals as those in FIGS. FIG. 6 shows the relationship between the bending angle θ and the distance from the screw hole of the main terminal 24 to the power chip 23.

サブモジュール４０の主端子２４に主回路基板（図示せず）を、ボルト５１とナット５２で固定するためには、主端子２４を曲げて、主回路基板とサブモジュール４０とが接触しないようにする必要がある。また、パワー半導体装置のインダクタンスを小さくするためには、主回路基板と主端子２４との接続部、即ち主端子２４に設けられたネジ孔からパワー半導体装置２３までの距離を小さくする必要がある。   In order to fix a main circuit board (not shown) to the main terminal 24 of the submodule 40 with bolts 51 and nuts 52, the main terminal 24 is bent so that the main circuit board and the submodule 40 do not contact each other. There is a need to. Further, in order to reduce the inductance of the power semiconductor device, it is necessary to reduce the distance from the connecting portion between the main circuit board and the main terminal 24, that is, the screw hole provided in the main terminal 24 to the power semiconductor device 23. .

図５では、パワーモジュール２０の側面から突出した主端子２４を、封止樹脂２７の近傍で、曲げ角（主端子２４の突出方向に対する角度）θだけ下方に曲げている。主端子２４の曲げ位置は、ナット２４が取り付けられる領域を考慮して決定される。
曲げ角θが大きいほど、主回路基板が取り付け易くなる一方、ボルト５１やナット５２と、サブモジュール４０との間の距離が小さくなる。両者の間の距離は、所定の絶縁距離以上とすることが好ましい。 In FIG. 5, the main terminal 24 protruding from the side surface of the power module 20 is bent downward by a bending angle θ (an angle with respect to the protruding direction of the main terminal 24) in the vicinity of the sealing resin 27. The bending position of the main terminal 24 is determined in consideration of the region where the nut 24 is attached.
The larger the bending angle θ, the easier the main circuit board can be attached, while the distance between the bolt 51 and nut 52 and the submodule 40 becomes smaller. The distance between the two is preferably greater than or equal to a predetermined insulation distance.

図５（ａ）に示すように、曲げ角θが大きい場合（例えばθ＝８０）、ナット５２やボルト５１の先端部はパワーモジュール２０の下部に回り込む。この結果、ボルト５１の先端部と水冷ブロック１０との間の絶縁距離ａ’を確保するためには、水冷ブロック１０を右の方向に移動させる必要がある。この結果、水冷ブロック１０に設けられた流路も右に移動し、パワー半導体素子２３の位置も流路の移動に伴って右に移動する。この結果、主端子２４に設けられたネジ孔からパワー半導体装置２３までの距離が大きくなる（図６のＡ参照）。   As shown in FIG. 5A, when the bending angle θ is large (for example, θ = 80), the tips of the nut 52 and the bolt 51 go around the lower part of the power module 20. As a result, in order to secure the insulation distance a 'between the tip of the bolt 51 and the water cooling block 10, it is necessary to move the water cooling block 10 in the right direction. As a result, the flow path provided in the water cooling block 10 also moves to the right, and the position of the power semiconductor element 23 also moves to the right as the flow path moves. As a result, the distance from the screw hole provided in the main terminal 24 to the power semiconductor device 23 increases (see A in FIG. 6).

図５（ｂ）に示すように、曲げ角θが中程度の場合（例えばθ＝５０）、主回路基板も取り付け易くなるとともに、絶縁距離ｂ、ｂ’も確保できる。この結果、主端子２４に設けられたネジ孔からパワー半導体装置２３までの距離を小さくできる（図６のＢ参照）。   As shown in FIG. 5B, when the bending angle θ is medium (for example, θ = 50), the main circuit board can be easily attached and the insulation distances b and b ′ can be secured. As a result, the distance from the screw hole provided in the main terminal 24 to the power semiconductor device 23 can be reduced (see B in FIG. 6).

図５（ｃ）に示すように、曲げ角θが小さい場合（例えばθ＝１８）、絶縁距離は容易に確保できるが、主回路基板とパワーモジュール２０との接触を避けるために、主端子２４を一端上方に折り曲げた後に、曲げ角θを確保するために、再度折り曲げる必要がある。この結果、主端子２４に設けられたネジ孔からパワー半導体装置２３までの距離が大きくなる（図６のＣ参照）。   As shown in FIG. 5C, when the bending angle θ is small (for example, θ = 18), the insulation distance can be easily secured, but in order to avoid contact between the main circuit board and the power module 20, the main terminal 24 is used. In order to secure the bending angle θ, it is necessary to bend again after bending one end upward. As a result, the distance from the screw hole provided in the main terminal 24 to the power semiconductor device 23 increases (see C in FIG. 6).

以上に説明したように、曲げ角θ＝８０の場合（図６のＡ）に比較して、曲げ角θ＝５０とした場合（図６のＢ）、主端子２４に設けられたネジ孔からパワー半導体装置２３までの距離が、約２０％短縮することができる。この結果、かかる配線に発生するインダクタンスを低減することが可能となる。実際には、曲げ角θは、４０°から６０°の範囲で用いることで、インダクタンスを低減できる。   As described above, when the bending angle θ = 50 (B in FIG. 6) compared to the bending angle θ = 80 (A in FIG. 6), the screw hole provided in the main terminal 24 The distance to the power semiconductor device 23 can be reduced by about 20%. As a result, it is possible to reduce inductance generated in such wiring. Actually, the inductance can be reduced by using the bending angle θ in the range of 40 ° to 60 °.

なお、本実施の形態１では、複数のサブモジュール４０が、主回路基板５０と制御基板６０との間に階段状に配置された構造について説明したが、サブモジュール４０は１つであっても良い。   In the first embodiment, the structure in which the plurality of submodules 40 are arranged stepwise between the main circuit board 50 and the control board 60 has been described. However, even if there is only one submodule 40. good.

実施の形態２．
図７は、全体が２００で表される、本発明の実施の形態２にかかるパワー半導体装置の概略図である。図７中、図１と同一符号は、同一又は相当箇所を示す。 Embodiment 2. FIG.
FIG. 7 is a schematic diagram of a power semiconductor device according to the second embodiment of the present invention, the whole being represented by 200. In FIG. 7, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

パワー半導体装置２００では、サブモジュール４０が１つだけであり、パワーモジュール２０の側面に対して垂直に制御端子２５が形成され、かかる制御端子２５に略直交するように制御基板６０が設けられている。制御基板６０は、水冷ブロック４０の側面に固定されても良い。   In the power semiconductor device 200, there is only one submodule 40, a control terminal 25 is formed perpendicular to the side surface of the power module 20, and a control board 60 is provided so as to be substantially orthogonal to the control terminal 25. Yes. The control board 60 may be fixed to the side surface of the water cooling block 40.

実施の形態３．
図８は、全体が３００で表される、本発明の実施の形態３にかかるパワー半導体装置の概略図である。図８中、図１と同一符号は、同一又は相当箇所を示す。 Embodiment 3 FIG.
FIG. 8 is a schematic diagram of the power semiconductor device according to the third embodiment of the present invention, the whole being represented by 300. 8, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

パワー半導体装置３００では、水冷ジャケット１０にナット５２を収納しない構造となっている。他の構造は、図１に示したパワー半導体装置１００と同様である。   The power semiconductor device 300 has a structure in which the nut 52 is not housed in the water cooling jacket 10. The other structure is the same as that of the power semiconductor device 100 shown in FIG.

本発明の実施の形態１にかかるパワー半導体装置の概略図である。1 is a schematic diagram of a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかるパワーモジュールの断面図である。It is sectional drawing of the power module concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる他のパワーモジュールの別の断面図である。It is another sectional view of other power modules concerning Embodiment 1 of the present invention. 本発明の実施の形態１にかかるパワーモジュールと水冷ブロックの断面図である。It is sectional drawing of the power module and water cooling block concerning Embodiment 1 of this invention. パワー半導体装置の概略図である。It is a schematic diagram of a power semiconductor device. パワー半導体装置の主端子の曲げ角度と、主回路基板とパワーモジュールとの間の距離との関係である。It is the relationship between the bending angle of the main terminal of a power semiconductor device, and the distance between a main circuit board and a power module. 本発明の実施の形態２にかかるパワー半導体装置の概略図である。It is the schematic of the power semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかるパワー半導体装置の概略図である。It is the schematic of the power semiconductor device concerning Embodiment 3 of this invention.

符号の説明Explanation of symbols

１０ 水冷ブロック、１１ 流路、１２ 冷却面、１３ 傾斜面、１４ 凹部、２０ パワーモジュール、２４ 主端子、２５ 制御端子、４０ サブモジュール、５０ 主回路基板、５１ ボルト、５２ ナット、５３ 孔部、６０ 制御基板、１００ パワー半導体装置。

10 water cooling block, 11 flow path, 12 cooling surface, 13 inclined surface, 14 recess, 20 power module, 24 main terminal, 25 control terminal, 40 submodule, 50 main circuit board, 51 bolt, 52 nut, 53 hole, 60 control board, 100 power semiconductor device.

Claims (8)

冷却面を備えた水冷ブロックと、
該冷却面上に配置され、パワー半導体素子を含む封止樹脂と、該封止樹脂の第１側面から突出した主端子と、該第１側面に対して略平行な第２側面から突出した制御端子とを備えたパワーモジュールと、
該パワーモジュールを挟んで配置された１対の主回路基板と制御端子であって、該主端子に接続された主回路基板と該制御端子に接続された制御基板とを含み、
該主端子が、該冷却面に略平行な第１領域と、該主回路基板と略同一平面となるように該第１領域から角度θだけ屈曲した第２領域からなり、
該主回路基板と該第２領域とが、これらを貫通するボルトとナットにより固定されたことを特徴とするパワー半導体装置。 A water cooling block with a cooling surface;
A sealing resin disposed on the cooling surface and including a power semiconductor element, a main terminal protruding from the first side surface of the sealing resin, and a control protruding from a second side surface substantially parallel to the first side surface A power module with terminals,
A pair of main circuit boards and control terminals arranged across the power module, the main circuit board connected to the main terminals, and a control board connected to the control terminals,
The main terminal comprises a first region substantially parallel to the cooling surface and a second region bent by an angle θ from the first region so as to be substantially flush with the main circuit board;
The power semiconductor device, wherein the main circuit board and the second region are fixed by bolts and nuts penetrating them. 上記主回路基板と上記制御基板とが、略平行に配置されたことを特徴とする請求項１に記載のパワー半導体装置。   The power semiconductor device according to claim 1, wherein the main circuit board and the control board are arranged substantially in parallel. 上記主回路基板と上記制御基板との間に、上記水冷ブロックとこれに取り付けられた上記パワーモジュールとからなる、複数のサブモジュールが、階段状に積層されたことを特徴とする請求項２に記載のパワー半導体装置。   3. The sub-module comprising the water-cooled block and the power module attached thereto is stacked in a step shape between the main circuit board and the control board. The power semiconductor device described. 上記制御基板が、上記冷却面に対して略垂直に配置されたことを特徴とする請求項１に記載のパワー半導体装置。   The power semiconductor device according to claim 1, wherein the control board is disposed substantially perpendicular to the cooling surface. 上記制御基板が、上記水冷ブロックの側面に固定されたことを特徴とする請求項４に記載のパワー半導体装置。   The power semiconductor device according to claim 4, wherein the control board is fixed to a side surface of the water cooling block. 上記水冷ブロックが、上記主回路基板に沿った傾斜面を有し、該傾斜面に設けられた凹部に上記ナットが収納されたことを特徴とする請求項１〜５のいずれかに記載のパワー半導体装置。   The power according to any one of claims 1 to 5, wherein the water cooling block has an inclined surface along the main circuit board, and the nut is housed in a recess provided in the inclined surface. Semiconductor device. 上記角度θが、略４０°以上で、略６０°以下であることを特徴とする請求項１〜６のいずれかに記載のパワー半導体装置。   The power semiconductor device according to claim 1, wherein the angle θ is approximately 40 ° or more and approximately 60 ° or less. 上記角度θが、略５０°以下であることを特徴とする請求項１〜６のいずれかに記載のパワー半導体装置。

The power semiconductor device according to claim 1, wherein the angle θ is approximately 50 ° or less.

JP2004350636A 2004-12-03 2004-12-03 Power semiconductor device Pending JP2006166509A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016606A (en) * 2011-07-04 2013-01-24 Daikin Ind Ltd Cooling structure of power module
JP2017199785A (en) * 2016-04-27 2017-11-02 カルソニックカンセイ株式会社 Cooling device for semiconductor device
WO2019030968A1 (en) * 2017-08-09 2019-02-14 株式会社日立製作所 Power conversion device and cooling method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016606A (en) * 2011-07-04 2013-01-24 Daikin Ind Ltd Cooling structure of power module
JP2017199785A (en) * 2016-04-27 2017-11-02 カルソニックカンセイ株式会社 Cooling device for semiconductor device
WO2019030968A1 (en) * 2017-08-09 2019-02-14 株式会社日立製作所 Power conversion device and cooling method therefor
JPWO2019030968A1 (en) * 2017-08-09 2020-04-02 株式会社日立製作所 Power conversion device and cooling method thereof

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