JP2006128519A - Method of manufacturing multilayer substrate - Google Patents

Method of manufacturing multilayer substrate Download PDF

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JP2006128519A
JP2006128519A JP2004317227A JP2004317227A JP2006128519A JP 2006128519 A JP2006128519 A JP 2006128519A JP 2004317227 A JP2004317227 A JP 2004317227A JP 2004317227 A JP2004317227 A JP 2004317227A JP 2006128519 A JP2006128519 A JP 2006128519A
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substrate
layer
conductor
insulating layer
conductor pattern
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Hiroshige Okawa
博茂 大川
Kenichi Kawabata
賢一 川畑
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TDK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To accurately control the thickness and electrical characteristics of each layer of a substrate simultaneously when the number of manufacturing steps of the multilayer substrate is reduced. <P>SOLUTION: A method of manufacturing the multilayer substrate includes a step of forming a via hole 15 by preparing a plurality of substrates 11 integrally having a conductor layer 12 and an insulating layer 13 which contains a thermoplastic resin as a main body, and opening a hole for the via hole in each insulating layer of the substrate; a step of forming a conductor pattern 12a by etching the conductor layer of the substrate; a smoothing pressing step of pressing individually the substrate to embed the conductor pattern in the insulating layer; and a step of stacking and pressing the plurality of the substrates which are smoothed and pressed, and integrating them. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多層基板の製造方法に係り、特に基板各層の厚さおよび電気的特性をより正確に制御しつつ基板基材を一括プレスして多層基板を形成する技術に関する。   The present invention relates to a method for manufacturing a multilayer substrate, and more particularly to a technique for forming a multilayer substrate by collectively pressing a substrate substrate while controlling the thickness and electrical characteristics of each layer of the substrate more accurately.

携帯電話機やノートブックパソコンのような電子機器の小型・薄型化、多機能・高性能化の進展に伴い、これらに使用するプリント配線板を多層化し、基板内部にコンデンサやインダクタ、抵抗等の回路素子を内蔵させた各種の基板構造が提案されている。かかる多層基板は、例えばビルドアップ工法により製造することができ、該工法は、高密度配線および高集積化が可能とされる。   As electronic devices such as mobile phones and notebook computers become smaller, thinner, multifunctional, and more advanced, printed wiring boards used for these devices are multilayered, and capacitors, inductors, resistors, and other circuits are built into the board. Various substrate structures with built-in elements have been proposed. Such a multilayer substrate can be manufactured, for example, by a build-up method, and this method enables high-density wiring and high integration.

また、多層基板の製造技術を開示するものとして下記特許文献がある。   Further, there is the following patent document that discloses a technique for manufacturing a multilayer substrate.

特開平７−２４０５８２号公報JP-A-7-240582 特開２００２−３０５３７８号公報JP 2002-305378 A 特開平１１−２８９１６３号公報JP 11-289163 A 特開平５−１１０２６２号公報Japanese Patent Laid-Open No. 5-110262

ところで、ビルドアップ工法は、高密度配線および層間接続の信頼性を期待できるという利点を有する一方で、基板各層を逐一積層して基板を形成していくため、製造工程数が多くならざるを得ないという難点がある。特に、基板層数が増大するにつれこの問題は一層顕在化する。   By the way, while the build-up method has an advantage that high-density wiring and reliability of interlayer connection can be expected, the number of manufacturing processes is inevitably increased because each substrate layer is laminated one by one. There is no difficulty. In particular, this problem becomes more apparent as the number of substrate layers increases.

一方、かかる問題を解消するため、多層基板の各層を構成する基板基材を予め形成しておき、これらを重ね合わせて一括して積層プレスする工法が提案されている（例えば上記特許文献１）。   On the other hand, in order to solve such a problem, a method has been proposed in which a substrate base material that constitutes each layer of a multilayer substrate is formed in advance, and these are stacked and stacked and pressed together (for example, Patent Document 1). .

ところが、このような一括積層プレスによる工法では、ビルドアップ工法に較べ製造工程の簡略化は図れるものの、導体パターンの厚さ（凸凹）によってその上に積層される上層が影響を受けて凸凹となりやすく、特に基板内部に回路素子を内蔵させる場合に所望の特性が得られないという問題が生じることがある。   However, in such a method using a batch lamination press, the manufacturing process can be simplified as compared with the build-up method, but the upper layer laminated on it is easily affected by the thickness of the conductor pattern (irregularity) and becomes uneven. In particular, there may be a problem that desired characteristics cannot be obtained when a circuit element is built in the substrate.

すなわち、一括積層プレス工法では、一般に絶縁層の上に所定の導体パターンを形成したシート状の複数の基材を位置合わせして重ね、これらを加熱プレスにより一体化するが、このとき、導体の厚さによって積層体の断面は、導体が存在する部分が上方に突出する一方、導体がない部分は下方に凹み、基板各層が全体として波打ったような凸凹した状態になってしまうのである。   That is, in the collective laminating press method, in general, a plurality of sheet-like base materials on which a predetermined conductor pattern is formed are aligned and stacked on an insulating layer, and these are integrated by heating press. Depending on the thickness, the cross section of the laminated body protrudes upward where the conductor is present, while the portion where there is no conductor is recessed downward, and each layer of the substrate becomes uneven as a whole.

特に、積層数も少なく、導体層に較べ絶縁層の厚さが格段に大きい時には、導体厚の影響はさほど考慮する必要はなかったが、電子機器の多機能化に伴い基板積層数が増加する一方、機器薄型化の要請から基板各層の厚さは年々小さくなる傾向にあり、導体層の厚さを無視することが出来ない状況になりつつある（一例を挙げれば、導体厚が１８μｍ程度、絶縁層の厚さが４０μｍ程度となる場合がある）。   In particular, when the number of laminated layers is small and the thickness of the insulating layer is much larger than the conductor layer, the influence of the conductor thickness does not need to be considered so much. However, the number of laminated substrates increases as the functionality of electronic devices increases. On the other hand, the thickness of each layer of the substrate tends to decrease year by year due to the demand for thinner equipment, and the thickness of the conductor layer cannot be ignored (for example, the conductor thickness is about 18 μm, The thickness of the insulating layer may be about 40 μm).

他方、上記特許文献２では、スルーホールに充填されるペーストが基材シート面から上方に突出して上層に影響を及ぼすことを防ぐために、ビア形成後に基材シートを仮プレスして基材シートを平坦化している。しかしながら、この文献記載の工法では、導体パターンの形成を仮プレスの後に行っており、導体パターンの凹凸がその上に積層される上層に悪影響を及ぼすという上記問題を解決することは依然として出来ない。   On the other hand, in Patent Document 2, in order to prevent the paste filled in the through hole from protruding upward from the surface of the base sheet and affecting the upper layer, the base sheet is temporarily pressed after the via is formed. It is flattened. However, in the construction method described in this document, the conductor pattern is formed after the temporary press, and the above problem that the unevenness of the conductor pattern adversely affects the upper layer laminated thereon cannot be solved.

さらに、従来の一括積層プレス工法では、一般に各基材を接合するため接着剤を介在させ積層を行っている（上記特許文献１〜３参照）。このため、絶縁層を形成する樹脂と接着剤という少なくとも２種類の材料が絶縁層に含まれることとなり、絶縁層の特性を所望の値に管理することが難しいという問題もある。特に、コンデンサを基板内に内蔵させる場合には、絶縁層の厚さだけでなく、その材料の性質（電気的特性）を正確に制御することは非常に重要となる。   Furthermore, in the conventional collective laminating press method, lamination is generally performed with an adhesive interposed in order to join the base materials (see Patent Documents 1 to 3 above). For this reason, at least two kinds of materials, that is, a resin and an adhesive forming the insulating layer are included in the insulating layer, and there is a problem that it is difficult to manage the characteristics of the insulating layer to a desired value. In particular, when a capacitor is built in a substrate, it is very important to accurately control not only the thickness of the insulating layer but also the properties (electrical characteristics) of the material.

したがって本発明の目的は、多層基板の製造工程数を減少させると同時に、基板各層の厚さおよび電気的特性をより正確に制御することを可能とする点にある。   Accordingly, it is an object of the present invention to reduce the number of manufacturing steps of a multilayer substrate and at the same time to more accurately control the thickness and electrical characteristics of each layer of the substrate.

前記目的を達成して課題を解決するため、本発明に係る第一の多層基板の製造方法は、導体層と熱可塑性樹脂を主体とする材料からなる絶縁層とを一体に有する基板基材を複数用意し、該複数の基板基材のうちの１以上の基板基材の各絶縁層にビアホール用の穴を開け、該穴に導体を配することにより当該基板基材にビアホールを形成するビア形成工程と、前記複数の基板基材のうち１以上の基板基材の導体層をエッチングして導体パターンを形成する回路形成工程と、該導体パターンを形成した基板基材を個別にプレスして前記導体パターンを前記絶縁層に埋め込む平滑プレス工程と、該導体パターンを絶縁層に埋め込んだ基板基材を含む前記複数の基板基材を積み重ねてプレスすることにより一体化する積層プレス工程とを含む。   In order to achieve the above object and solve the problem, a first multilayer substrate manufacturing method according to the present invention includes a substrate base material integrally including a conductor layer and an insulating layer made of a material mainly composed of a thermoplastic resin. A via for forming a via hole in the substrate base by preparing a plurality of holes, forming a hole for a via hole in each insulating layer of one or more of the plurality of substrate bases, and arranging a conductor in the hole A step of forming, a circuit forming step of forming a conductor pattern by etching a conductor layer of one or more of the plurality of substrate substrates, and pressing the substrate substrate on which the conductor pattern is formed individually A smooth pressing step of embedding the conductor pattern in the insulating layer, and a lamination pressing step of integrating the plurality of substrate base materials including the substrate base material in which the conductive pattern is embedded in the insulating layer by stacking and pressing. .

本発明に係る多層基板の製造方法では、導体層と熱可塑性樹脂を主体とする材料からなる絶縁層とを一体に有する複数の基板基材を一括してプレスして積層するが、この積層プレス工程の前に、導体パターンを形成した各基板基材について個別にプレスを行い、導体パターンを絶縁層に埋め込む処理を行う。したがって、基板基材の表面が平らとなって導体パターンによる凸凹が除かれ、導体パターンの厚みに起因する基板各層の凹凸や変形が生じることを防ぐことが出来る。   In the method for manufacturing a multilayer substrate according to the present invention, a plurality of substrate base materials integrally having a conductor layer and an insulating layer made of a material mainly composed of a thermoplastic resin are collectively pressed and laminated. Prior to the process, each substrate base material on which the conductor pattern is formed is individually pressed to embed the conductor pattern in the insulating layer. Accordingly, the surface of the substrate substrate is flattened to remove the unevenness due to the conductor pattern, and it is possible to prevent the unevenness and deformation of each layer of the substrate due to the thickness of the conductor pattern.

したがって、層間寸法（絶縁層の厚さ寸法）を高精度に制御することが可能となり、基板内に回路素子を内蔵させた場合にも、その特性をより精度良くコントロールすることが出来る。また、接着層（接着剤）を使用せず、各層導体間に介在される絶縁材料を、基板基材の絶縁層を構成する材料のみとすることが出来るから、絶縁層の電気的特性を制御しやすく、例えば基板内蔵のコンデンサを形成する場合にも、その特性を所望の正確な値に設定することが容易となる。   Therefore, the interlayer dimension (thickness dimension of the insulating layer) can be controlled with high accuracy, and the characteristics can be controlled with higher accuracy even when the circuit element is built in the substrate. In addition, since the insulating material interposed between the conductors of each layer can be made only of the material constituting the insulating layer of the substrate base material without using an adhesive layer (adhesive), the electrical characteristics of the insulating layer are controlled. For example, when forming a capacitor with a built-in substrate, it becomes easy to set the characteristic to a desired accurate value.

さらに、一括積層を行うから、ビルドアップ工法のような順次積層方式に較べ基板の製造工程数を減らすことが出来るうえ、次のような利点をも有する。   Furthermore, since the batch lamination is performed, the number of manufacturing steps of the substrate can be reduced as compared with the sequential lamination method such as the build-up method, and the following advantages are also obtained.

すなわち、順次積層方式であると基板各層間でプレスを受ける回数が区々となり（最初に積層される層ほど受けるプレスの回数が多くなる）、あるいは層構成を変えると熱履歴が異なるものとなって（例えば、８層の基板と６層の基板とでは、熱履歴が１回分異なることとなる）、所望の正確な特性を有する基板（絶縁層）を実現し難い面がある。これに対し本発明の方法によれば、基板のすべての層について、あるいは層構成が異なっても、適用されるプレスの回数を一定回数（例えば平滑プレスと積層プレスの２回）とすることが出来るから、プレス処理に伴う絶縁層の特性変化を抑え、より精度良く所望の特性を有する基板を製造することが可能となる。   In other words, in the case of the sequential lamination method, the number of times of pressing between the respective layers of the substrate varies (the number of times of pressing is increased as the first layer is laminated), or the thermal history differs when the layer configuration is changed. (For example, an 8-layer substrate and a 6-layer substrate have different thermal histories for one time), and it is difficult to realize a substrate (insulating layer) having desired accurate characteristics. On the other hand, according to the method of the present invention, the number of presses to be applied can be set to a fixed number of times (for example, two times of a smoothing press and a lamination press) for all the layers of the substrate or even if the layer configuration is different. Therefore, it is possible to suppress a change in the characteristics of the insulating layer due to the press treatment and manufacture a substrate having desired characteristics with higher accuracy.

また、絶縁層を形成する樹脂として熱硬化性樹脂を使用した場合には、半硬化の状態で絶縁層がめっき液に侵食されやすく、さらに硬化阻害が生じる可能性がある。これに対し本発明では、絶縁層に熱硬化性樹脂を使用せず、熱可塑性樹脂を主体とする材料によって絶縁層を形成するから、このような問題が生じることがない。   In addition, when a thermosetting resin is used as the resin for forming the insulating layer, the insulating layer is easily eroded by the plating solution in a semi-cured state, and there is a possibility of further inhibiting the curing. On the other hand, in the present invention, the thermosetting resin is not used for the insulating layer, and the insulating layer is formed of a material mainly composed of a thermoplastic resin, so that such a problem does not occur.

上記平滑プレス工程における導体パターンの「埋め込み」は、導体パターンの表面と絶縁層の表面が面一となるように（当該基板基材の表面が完全に平滑となるように）埋め込むことが望ましいが、本発明にいう上記平滑プレスは、導体パターンが絶縁層の表面から多少突出した状態に埋め込むプレス処理を除外するものではない。このようなプレス処理であっても、完全に埋め込んだ場合と比較すれば得られる効果は少なくなるものの、積層時における基板上層への影響を軽減するという同様の効果が得られるからである。   The “embedding” of the conductor pattern in the smooth pressing step is preferably performed so that the surface of the conductor pattern and the surface of the insulating layer are flush with each other (so that the surface of the substrate substrate is completely smooth). The smooth press referred to in the present invention does not exclude press treatment in which the conductor pattern is embedded in a state slightly protruding from the surface of the insulating layer. Even if such a press treatment is performed, a similar effect of reducing the influence on the upper layer of the substrate at the time of stacking can be obtained, although the effect obtained when compared with the case of completely embedding is reduced.

絶縁層を構成する熱可塑性樹脂としては、耐熱性の観点から芳香族ポリエステル、ポリフェニレーンサルファイド、ポリエーテルケトン、ポリエーテルサルフォン、ポリアリレート、または、シンジオタスティックポリスチレンが良い。なかでも、芳香族ポリエステルでは、溶剤可溶型の芳香族液晶ポリエステルが好ましい。フィラーを多く含有させることが出来るので、フィラーによる物性の調整がより可能で、たとえば誘電体粉末を多く含有させることで誘電率を高くすることが可能であり、さらに、薄い基板をドクターブレード法等の方法で容易に作成することが出来る。   As the thermoplastic resin constituting the insulating layer, aromatic polyester, polyphenylene sulfide, polyether ketone, polyether sulfone, polyarylate, or syndiotactic polystyrene is preferable from the viewpoint of heat resistance. Among these, as the aromatic polyester, a solvent-soluble aromatic liquid crystal polyester is preferable. Since a large amount of filler can be contained, it is possible to adjust the physical properties by using the filler. For example, it is possible to increase the dielectric constant by adding a large amount of dielectric powder. It can be easily created by this method.

このような溶剤可溶型の芳香族液晶ポリエステルとしては、例えば、下記式（１ａ）または式（１ｂ）で表される化合物を３０質量％以上含む溶媒に溶解する芳香族液晶ポリエステル樹脂ポリマーがある。尚、下記の式中、Ａはハロゲン原子またはトリハロゲン化メチル基、Ｂは水素原子、ハロゲン原子またはトリハロゲン化メチル基、ｉは１〜５の整数、ｊは１〜４の整数を示す。   Examples of such solvent-soluble aromatic liquid crystal polyester include an aromatic liquid crystal polyester resin polymer that dissolves in a solvent containing 30% by mass or more of a compound represented by the following formula (1a) or (1b). . In the following formula, A represents a halogen atom or a trihalogenated methyl group, B represents a hydrogen atom, a halogen atom or a trihalogenated methyl group, i represents an integer of 1 to 5, and j represents an integer of 1 to 4.

Figure 2006128519
Figure 2006128519

この場合、芳香族液晶ポリエステルは、芳香族ヒドロキシカルボン酸を単量体単位として含むポリマーであることが好ましく、この単量体単位を形成する芳香族ヒドロキシカルボン酸としては２−ヒドロキシ−６−ナフトエ酸が好適である。   In this case, the aromatic liquid crystal polyester is preferably a polymer containing an aromatic hydroxycarboxylic acid as a monomer unit, and the aromatic hydroxycarboxylic acid forming the monomer unit is 2-hydroxy-6-naphthoene. Acid is preferred.

また、芳香族液晶ポリエステルが、芳香族ヒドロキシカルボン酸単量体単位３０〜８０ｍｏｌ％、芳香族ジオール単量体単位１０〜３５ｍｏｌ％、および芳香族ジカルボン酸単量体単位１０〜３５ｍｏｌ％から構成されるポリマーであるとさらに好ましい。芳香族ヒドロキシカルボン酸単量体単位が３０ｍｏｌ％未満であると、得られるポリマーが液晶性を発現しなくなり、耐熱性が低下してしまう場合がある。一方、８０ｍｏｌ％を超えると、芳香族液晶ポリエステルの溶融性や溶媒への溶解性が低下する傾向にある。   The aromatic liquid crystal polyester is composed of 30 to 80 mol% aromatic hydroxycarboxylic acid monomer units, 10 to 35 mol% aromatic diol monomer units, and 10 to 35 mol% aromatic dicarboxylic acid monomer units. More preferred is a polymer. If the aromatic hydroxycarboxylic acid monomer unit is less than 30 mol%, the resulting polymer may not exhibit liquid crystallinity and heat resistance may be reduced. On the other hand, when it exceeds 80 mol%, the meltability of the aromatic liquid crystal polyester and the solubility in a solvent tend to be lowered.

また、芳香族液晶ポリエステルが上述の各単量体単位から構成される場合、芳香族ジオール単量体単位を形成する芳香族ジオールとしては、４，４’−ジヒドロキシビフェニルが好ましく、芳香族ジカルボン酸単量体単位を形成する芳香族ジカルボン酸としては、テレフタル酸、イソフタル酸または２，６−ナフタレンジカルボン酸が好ましい。   When the aromatic liquid crystal polyester is composed of the above-mentioned monomer units, the aromatic diol forming the aromatic diol monomer unit is preferably 4,4′-dihydroxybiphenyl, and aromatic dicarboxylic acid As the aromatic dicarboxylic acid forming the monomer unit, terephthalic acid, isophthalic acid or 2,6-naphthalenedicarboxylic acid is preferable.

さらに、溶媒に溶解させた芳香族液晶ポリエステル中には誘電体セラミック粉末を混入することが可能であり、混入する誘電体セラミック粉末の種類および量を、必要とされる基板の特性に応じて適宜設定することにより、所望の電気的特性（例えば誘電率やＱ値）を有する多層基板を容易に製造することが出来る。尚、本発明の製造方法における基板基材の絶縁層は、樹脂と誘電体セラミック粉末とを含む複合材料により形成されたものに限られるものではなく、樹脂のみにより構成されたものであっても良い。   Furthermore, it is possible to mix the dielectric ceramic powder in the aromatic liquid crystal polyester dissolved in the solvent. The type and amount of the dielectric ceramic powder to be mixed are appropriately determined according to the characteristics of the required substrate. By setting, a multilayer substrate having desired electrical characteristics (for example, dielectric constant or Q value) can be easily manufactured. In addition, the insulating layer of the substrate substrate in the manufacturing method of the present invention is not limited to one formed of a composite material including a resin and a dielectric ceramic powder, and may be formed only of a resin. good.

上記誘電体セラミック粉末としては、例えばマグネシウム、ケイ素、チタン、亜鉛、カルシウム、ストロンチウム、ジルコニウム、バリウム、スズ、ネオジウム、サマリウム、ビスマス、鉛、ランタン、リチウム及びタンタルからなる群より選ばれる少なくとも一種類の金属を含む金属酸化物粉末を用いることが出来る。より具体的には、チタン−バリウム−ネオジウム系セラミックス、チタン−バリウム−スズ系セラミックス、鉛−カルシウム系セラミックス、二酸化チタン系セラミックス、チタン酸バリウム系セラミックス、チタン酸鉛系セラミックス、チタン酸ストロンチウム系セラミックス、チタン酸カルシウム系セラミックス、チタン酸ビスマス系セラミックス、チタン酸マグネシウム系セラミックス、ＣａＷＯ4系セラミックス、Ｂａ（Ｍｇ，Ｎｂ）Ｏ3系セラミックス、Ｂａ（Ｍｇ，Ｔａ）Ｏ3系セラミックス、Ｂａ（Ｃｏ，Ｍｇ，Ｎｂ）Ｏ3系セラミックス、Ｂａ（Ｃｏ，Ｍｇ，Ｔａ）Ｏ3系セラミックスなどが、高誘電率の粉末として好ましく用いられる。その他、各種電気的特性の向上や機械的・物理物性の改良、材料形態の必要性に応じ、各種の充填剤を混入することが可能である。具体的には酸化チタン等の誘電材料、フェライト、軟磁性金属等の磁性材料、シリカ、アルミナ、ジルコニア、チタン酸カリウムウイスカ、チタン酸バリウムウイスカ、酸化亜鉛ウイスカ、ガラス繊維、ガラスビーズ、カーボン繊維、酸化マグネシウム（タルク）等が挙げられる。 Examples of the dielectric ceramic powder include at least one selected from the group consisting of magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, barium, tin, neodymium, samarium, bismuth, lead, lanthanum, lithium and tantalum. A metal oxide powder containing a metal can be used. More specifically, titanium-barium-neodymium ceramics, titanium-barium-tin ceramics, lead-calcium ceramics, titanium dioxide ceramics, barium titanate ceramics, lead titanate ceramics, strontium titanate ceramics , Calcium titanate ceramics, bismuth titanate ceramics, magnesium titanate ceramics, CaWO 4 ceramics, Ba (Mg, Nb) O 3 ceramics, Ba (Mg, Ta) O 3 ceramics, Ba (Co, Mg, Nb) O 3 ceramics, Ba (Co, Mg, Ta) O 3 ceramics, etc. are preferably used as the high dielectric constant powder. In addition, various fillers can be mixed according to the improvement of various electrical characteristics, the improvement of mechanical / physical properties, and the necessity of the material form. Specifically, dielectric materials such as titanium oxide, magnetic materials such as ferrite and soft magnetic metals, silica, alumina, zirconia, potassium titanate whisker, barium titanate whisker, zinc oxide whisker, glass fiber, glass beads, carbon fiber, Examples thereof include magnesium oxide (talc).

本発明に係る第二の多層基板の製造方法は、上記積層プレス工程で、前記積み重ねた基板基材のうちの最上層の基板基材が、導体パターンを形成していない未パターニングの導体層を有するものであり、かつ前記積み重ねた基板基材のうちの最下層の基板基材の絶縁層の下面に導体箔を配して前記積層プレスを行い、該積層プレス工程の後に、前記最上層の基板基材の導体層と、前記最下層の基板基材の絶縁層の下面に配した導体箔とをエッチングして当該多層基板の表層の導体パターンを形成する表層回路形成工程をさらに含む。   In the second multilayer substrate manufacturing method according to the present invention, an unpatterned conductor layer in which the uppermost substrate base material among the stacked substrate base materials is not formed with a conductor pattern in the above-described laminated press step. A conductive foil is disposed on the lower surface of the insulating layer of the lowermost substrate base material among the stacked substrate base materials, and the lamination press is performed. The method further includes a surface layer circuit forming step of etching the conductor layer of the substrate base material and the conductor foil disposed on the lower surface of the insulating layer of the lowermost substrate base material to form a conductor pattern of the surface layer of the multilayer substrate.

また、本発明に係る第三の多層基板の製造方法は、上記第一の製造方法の積層プレス工程において、少なくとも最上層の基板基材を含む１以上の基板基材に対し、少なくとも最下層の基板基材を含む１以上の基板基材を表裏反転した状態で前記複数の基板基材を積み重ねてプレスすることにより一体化する。   In addition, the third multilayer substrate manufacturing method according to the present invention is characterized in that, in the laminating press step of the first manufacturing method, at least the lowermost substrate substrate including at least the uppermost substrate substrate is at least the lowermost layer substrate. The one or more substrate base materials including the substrate base material are integrated by stacking and pressing the plurality of substrate base materials in a state where the front and back surfaces are reversed.

この第三の方法では、積層プレス工程において最上層を含む１以上の基板基材に対し、少なくとも最下層の基板基材を含む１以上の基板基材を表裏反転した状態で積層を行い、一体化のためのプレスを行う。このような積層方法によれば、基板の内層のみならず、基板の表層（上下両面または表裏両面）についても積層プレス前に導体パターンの形成を行うことができ、積層工程の後にさらに基板表層のパターン形成を行う必要がなくなるから、この点で多層基板の製造工程をより簡便化することが可能となる。   In this third method, the one or more substrate base materials including the uppermost layer are stacked in a state where the one or more substrate base materials including at least the lowermost substrate base material are reversed. Press for conversion. According to such a laminating method, a conductor pattern can be formed before laminating press not only on the inner layer of the substrate but also on the surface layer (upper and lower surfaces or both surfaces) of the substrate. Since there is no need to perform pattern formation, the manufacturing process of the multilayer substrate can be further simplified in this respect.

さらに、上記本発明に係る多層基板の製造方法では、上記平滑プレス工程の後に、当該平滑プレスを行った基板基材の表面の金属表面を覆った樹脂を除去する樹脂除去処理工程をさらに含む場合がある。   Furthermore, in the method for manufacturing a multilayer substrate according to the present invention, after the smooth pressing step, the method further includes a resin removal processing step of removing the resin covering the metal surface of the substrate base material subjected to the smooth pressing. There is.

導体パターンを絶縁層に埋め込む平滑プレス工程を経た基板基材では、埋め込まれた導体パターンやビアホールの金属表面に絶縁層の樹脂が流れ、付着することがある。これに対し、上記樹脂除去処理を行うことにより、金属表面に付着した樹脂を除去し、層間接続の信頼性を高めることが出来る。樹脂除去処理としては、例えばウエットブラスト処理やプラズマ処理等を行う。   In a substrate base material that has undergone a smooth press process in which a conductor pattern is embedded in an insulating layer, the resin of the insulating layer may flow and adhere to the metal surface of the embedded conductor pattern or via hole. On the other hand, by performing the resin removal treatment, the resin adhering to the metal surface can be removed, and the reliability of interlayer connection can be improved. As the resin removal process, for example, a wet blast process or a plasma process is performed.

本発明によれば、一括積層で多層基板の製造工程を簡略化し、しかも同時に、導体パターンによる凸凹を無くして層間厚みおよび絶縁層の電気的特性をより正確に制御することが出来る。   According to the present invention, the manufacturing process of a multilayer substrate can be simplified by batch lamination, and at the same time, the unevenness due to the conductor pattern can be eliminated and the interlayer thickness and the electrical characteristics of the insulating layer can be controlled more accurately.

本発明の他の目的、特徴および利点は、以下の本発明の実施の形態の説明により明らかにする。   Other objects, features and advantages of the present invention will become apparent from the following description of embodiments of the present invention.

以下、添付図面の図１Ａから図２を参照しつつ本発明の実施形態を説明する。尚、各図中、同一の符号は、同一又は相当部分を示す。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1A to 2 of the accompanying drawings. In addition, in each figure, the same code | symbol shows the same or an equivalent part.

〔実施形態１〕
図１Ａ〜図１Ｆは、本発明の第一の実施形態に係る多層基板の製造方法を示す工程図である。同図に示すようにこの実施形態の製造方法では、まず、基板各層を形成する基板基材として、一面に銅箔層（導体層）１２を、他面に樹脂層（絶縁層）１３を備える樹脂付き銅箔（ＲＣＣ）１１を複数枚（この実施形態では、基板表層（上下面）を含めて１１層の多層基板を形成するため１０枚）用意し（図１Ａ（ａ））、各基材１１に位置合わせ用の基準穴（図示せず）をＮＣ（数値制御）加工機により開ける。 Embodiment 1
1A to 1F are process diagrams illustrating a method for manufacturing a multilayer substrate according to a first embodiment of the present invention. As shown in the figure, in the manufacturing method of this embodiment, first, a copper foil layer (conductor layer) 12 is provided on one surface and a resin layer (insulating layer) 13 is provided on the other surface as a substrate base material for forming each layer of the substrate. A plurality of copper foils (RCC) 11 with resin (in this embodiment, 10 sheets for forming an 11-layer multilayer substrate including the substrate surface layers (upper and lower surfaces)) are prepared (FIG. 1A (a)). A reference hole (not shown) for alignment is opened in the material 11 by an NC (numerical control) processing machine.

上記樹脂付き銅箔１１として本実施形態では、熱可塑性樹脂（例えば芳香族液晶ポリエステル）に誘電体セラミック粉末を混入した複合材料により樹脂層１３を形成したものを使用する。このような樹脂付き銅箔１１は、例えば、次の（１）から（３）の方法により形成することが出来る。（１）芳香族液晶ポリエステルを溶媒に溶解させるとともに、これに誘電体セラミック粉末を混入して複合材料ペーストを形成し、この複合材料ペーストを銅箔に塗布した後、溶媒を除去する。（２）前記複合材料ペーストをシート状に成形した複合材料シートに電解箔・圧延箔等の銅箔を被着させ、加熱等により当該複合材料シート中の芳香族液晶ポリエステルを溶融させて銅箔を接着する。（３）前記複合材料シート上に、めっき（無電解めっき、電解めっき又はこれらの組み合わせ）、スパッタ、蒸着等により直接銅箔を形成する。   In this embodiment, as the copper foil 11 with resin, a resin layer 13 formed of a composite material in which a dielectric ceramic powder is mixed into a thermoplastic resin (for example, aromatic liquid crystal polyester) is used. Such a resin-coated copper foil 11 can be formed, for example, by the following methods (1) to (3). (1) Aromatic liquid crystal polyester is dissolved in a solvent, and a dielectric ceramic powder is mixed therein to form a composite material paste. After applying this composite material paste to a copper foil, the solvent is removed. (2) Copper foil such as electrolytic foil and rolled foil is attached to a composite material sheet obtained by molding the composite material paste into a sheet shape, and the aromatic liquid crystal polyester in the composite material sheet is melted by heating or the like to obtain a copper foil. Glue. (3) A copper foil is directly formed on the composite material sheet by plating (electroless plating, electrolytic plating or a combination thereof), sputtering, vapor deposition, or the like.

尚、各基板基材１１の銅箔層（導体層）１２を形成する金属は、必ずしも銅に限られず、本発明では他の金属を使用しても良い。また、以下の説明では、多層基板の最上層に配される基材から最下層に配される基材までを順に第１基材、第２基材、…、第１０基材と称するが（図１Ｃ（ｒ）参照）、基材の積層数（基板の配線層の数）は、図示の例に特に限定されるものではない。   In addition, the metal which forms the copper foil layer (conductor layer) 12 of each board | substrate base material 11 is not necessarily restricted to copper, You may use another metal in this invention. In the following description, the base material disposed on the uppermost layer of the multilayer substrate to the base material disposed on the lowermost layer are sequentially referred to as a first base material, a second base material,. 1C (r)), the number of laminated base materials (number of wiring layers of the substrate) is not particularly limited to the example shown.

基準穴の加工後、レーザ光により各樹脂付き銅箔１１（第１基材１１ａから第１０基材１１ｊ）にビアホール用の穴１４を開け、穴底部の銅箔面に残留する樹脂スミアを界面活性剤による処理を施した後、超音波洗浄、ソフトエッチングを行い除去する（図１Ａ（ｂ））。その後、基材１１にドライフィルム２１をラミネートし（同図（ｃ））、露光および現像処理（同図（ｄ））を経て基材下面（樹脂層側）のドライフィルム２１を剥離する（同図（ｅ））。そして、ビアホール用の穴内に銅をめっき析出させることにより、ホール内が銅で充填されたフィルドビア１５を形成した後（同図（ｆ））、基材１１の表面のドライフィルム２１を除去する（同図（ｇ））。尚、上記フィルドビア１５の形成（図１Ａ（ｆ））にあたっては、ドライフィルム２１によって銅箔層１２の表面に形成されるめっきレジストに給電用の導体露出部を設け、この部分から給電し、電気めっきを行うことによりフィルドビア１５を形成する。   After processing the reference hole, via holes 14 are formed in the copper foils 11 with resin (from the first base material 11a to the tenth base material 11j) by laser light, and the resin smear remaining on the copper foil surface at the bottom of the hole is interfaced. After the treatment with the activator, it is removed by ultrasonic cleaning and soft etching (FIG. 1A (b)). Thereafter, a dry film 21 is laminated on the substrate 11 ((c) in the same figure), and the dry film 21 on the lower surface of the substrate (resin layer side) is peeled off after exposure and development processing ((d) in the same figure). (E). Then, copper is deposited in the hole for via hole to form the filled via 15 filled with copper in the hole ((f) in the figure), and then the dry film 21 on the surface of the substrate 11 is removed ( (G)). In forming the filled via 15 (FIG. 1A (f)), a conductor exposed portion for feeding is provided on the plating resist formed on the surface of the copper foil layer 12 by the dry film 21, and power is fed from this portion. Filled via 15 is formed by plating.

尚、上記ビアホールは、めっき金属で穴内が充填されたフィルドビアに限られるものではなく、穴内壁をめっき金属で覆っためっきスルーホール、あるいは導電ペーストを充填したビアホールとすることも可能である。尚、めっきスルーホールの場合には、スルーホール内壁面にめっき金属層を形成した後、スルーホール内に樹脂を充填する。さらに、上記ビアホールは、次のようにして形成することも出来る。すなわち、前記基材１１にドライフィルム２１をラミネート（図１Ａ（ｃ））する前に（同図（ｂ）のビアホール用の穴１４を開けた状態で）予め無電解めっきを行って導体層を形成し、その後、基材１１にドライフィルム２１をラミネートする。そして、スルーホール用の穴１４の形成部分以外の領域にレジストを配した後、電解めっきによりフィルドビア１５を形成し、前記レジストを剥離し、前記無電解めっきにより設けた導体層を例えばソフトエッチングにより除去する。このような工程によっても、上記ビアホール１５を形成することが出来る。   The via hole is not limited to a filled via filled with a plated metal, but may be a plated through hole whose inner wall is covered with a plated metal or a via hole filled with a conductive paste. In the case of a plated through hole, a plated metal layer is formed on the inner wall surface of the through hole, and then the resin is filled into the through hole. Further, the via hole can be formed as follows. That is, before laminating the dry film 21 on the substrate 11 (FIG. 1A (c)) (with the via hole 14 shown in FIG. 1 (b) opened), electroless plating is performed in advance to form a conductor layer. After that, the dry film 21 is laminated on the substrate 11. Then, after disposing a resist in a region other than the portion where the through hole 14 is formed, the filled via 15 is formed by electrolytic plating, the resist is peeled off, and the conductor layer provided by the electroless plating is formed by, for example, soft etching. Remove. The via hole 15 can also be formed by such a process.

ビアホール１５の形成後、各基材１１の両面に再びドライフィルム２２をラミネートし（図１Ａ（ｈ））、マスクパターンを通して露光焼付けを行い（図１Ｂ（ｉ））、現像して所定パターンのエッチングレジスト２２ａを形成する（同図（ｊ））。そして、露出している銅箔１２をエッチングで除去することにより導体パターン１２ａを形成した後（同図（ｋ））、レジスト２２ａ（ドライフィルム）を剥離する（同図（ｌ））。この工程で形成される導体パターン１２ａには、各種の基板内蔵素子（例えばコンデンサ、コイル、抵抗）を形成するためのパターンや基準電位電極、配線パターン等が含まれる。尚、多層基板の最上層を形成する樹脂付き銅箔（第１基材）１１ａについては、後に述べる積層工程の後に基板表層のパターン形成を行うため、上記ビアホール１５の形成だけを行い、この段階では導体パターンを形成しない。   After the via hole 15 is formed, the dry film 22 is laminated again on both surfaces of each substrate 11 (FIG. 1A (h)), exposure printing is performed through the mask pattern (FIG. 1B (i)), and development is performed to etch a predetermined pattern. A resist 22a is formed ((j) in the figure). Then, after the exposed copper foil 12 is removed by etching to form a conductor pattern 12a (FIG. (K)), the resist 22a (dry film) is peeled (FIG. (L)). The conductor pattern 12a formed in this step includes patterns for forming various types of substrate-embedded elements (for example, capacitors, coils, resistors), reference potential electrodes, wiring patterns, and the like. For the copper foil with resin (first base material) 11a forming the uppermost layer of the multilayer substrate, only the via hole 15 is formed in order to form a pattern on the substrate surface after the laminating process described later. Then, the conductor pattern is not formed.

導体パターン１２ａの形成後、多層基板の内部および下面に配されることとなる各基材（第２から第１０基材）１１ｂ〜１１ｊを加熱プレスすることにより導体パターン１２ａを樹脂層１３に埋め込む（同図（ｍ）／平滑プレス工程）。そして、基材両面にウエットブラストを施すことにより導体パターン１２ａおよびビアホール１５の表面に付着した樹脂を除去する。この樹脂除去処理を施すことにより、ビアホール１５側にとっては、後に述べる金属めっきをより確実に行うことが可能となり、また導体パターン１２ａ側にとっては、後に述べる一括積層時に層間接続をより確実に行うことができ、当該多層基板の層間接続の信頼性を高めることが可能となる。尚、かかる樹脂の除去処理は、プラズマ処理によって行うことも可能である。   After the formation of the conductor pattern 12a, each of the base materials (second to tenth base materials) 11b to 11j to be arranged on the inside and the lower surface of the multilayer substrate is heated and pressed to embed the conductor pattern 12a in the resin layer 13. ((M) in the figure / smooth press step). And the resin adhering to the surface of the conductor pattern 12a and the via hole 15 is removed by giving wet blast to both surfaces of a base material. By performing this resin removal treatment, the metal plating described later can be more reliably performed on the via hole 15 side, and the interlayer connection can be more reliably performed on the conductive pattern 12a side during the collective lamination described later. Thus, the reliability of interlayer connection of the multilayer substrate can be improved. The resin removal process can also be performed by a plasma process.

次に、基材両面にドライフィルム２３をラミネートし（同図（ｎ））、露光および現像工程（同図（ｏ））を経て基材下面（樹脂層側）のドライフィルム２３を剥離する（同図（ｐ））。そして、ビアホール１５の下面１５ａにＡｇ置換めっきを施した後（当該めっき層は図示せず）、基材上面（銅箔層側）のドライフィルム２３を剥離する（同図（ｑ））。尚、ビアホール下面１５ａに施す金属めっきは、Ａｇ置換めっき以外の、例えばＳｎ置換めっき等の金属めっきであっても良い。また、上記ドライフィルム２３のラミネートから剥離までの各工程（図１Ｂ（ｎ）〜（ｑ））は、導体パターン１２ａの表面にＡｇめっきが施されることを防ぐために行ったもので、省略することも可能である。   Next, the dry film 23 is laminated on both surfaces of the substrate ((n) in the figure), and the dry film 23 on the lower surface of the substrate (resin layer side) is peeled off through the exposure and development steps ((o) in the same figure) ( (P)). Then, after Ag substitution plating is performed on the lower surface 15a of the via hole 15 (the plating layer is not shown), the dry film 23 on the upper surface of the base material (copper foil layer side) is peeled off ((q) in the figure). The metal plating applied to the via hole lower surface 15a may be metal plating such as Sn substitution plating other than Ag substitution plating. Moreover, each process (FIG. 1B (n)-(q)) from the lamination of the said dry film 23 to peeling is performed in order to prevent that Ag plating is given to the surface of the conductor pattern 12a, and is abbreviate | omitted. It is also possible.

以上のようにして導体パターン１２ａを形成した９枚の基板基材（第２から第１０基材）１１ｂ〜１１ｊと、基板上面を形成する１枚の基板基材（第１基材）１１ａと、基板下面の導体パターンを形成するため第１０基材１１ｊの下面に配する銅箔１６とをスタックし、これらを加熱プレスして一体に積層する（図１Ｃ（ｒ）〜（ｓ））。積層後、多層基板の上下両面にドライフィルム２４をラミネートし、所定のマスクパターンを通して露光を行い（図１Ｄ（ｕ））、現像を行ってエッチングレジスト２４ａを作成する（同図（ｖ））。そして、エッチングにより基板表層（上下両面）の導体パターン１２ｂ，１６ａを形成し（図１Ｅ（ｗ））、ドライフィルム２４ａを除去する（同図（ｘ））。   Nine substrate substrates (second to tenth substrates) 11b to 11j on which the conductor pattern 12a is formed as described above, and one substrate substrate (first substrate) 11a that forms the upper surface of the substrate, Then, in order to form a conductor pattern on the lower surface of the substrate, the copper foil 16 disposed on the lower surface of the tenth base material 11j is stacked, and these are heated and pressed to be laminated together (FIGS. 1C (r) to (s)). After the lamination, dry films 24 are laminated on the upper and lower surfaces of the multilayer substrate, exposed through a predetermined mask pattern (FIG. 1D (u)), and developed to produce an etching resist 24a (FIG. (V)). Then, the conductive patterns 12b and 16a on the substrate surface (upper and lower surfaces) are formed by etching (FIG. 1E (w)), and the dry film 24a is removed (FIG. 1 (x)).

さらに、基板両面にソルダレジスト２５を塗布して上記基板表層に形成した導体パターン１２ｂ，１６ａにニッケルめっきおよび金めっきを施した後（図１Ｆ（ｙ））、ソルダレジスト２５を除去する（同図（ｚ））。   Further, after applying the solder resist 25 on both surfaces of the substrate and applying the nickel plating and the gold plating to the conductor patterns 12b and 16a formed on the substrate surface layer (FIG. 1F (y)), the solder resist 25 is removed (FIG. 1). (Z)).

〔実施形態２〕
図２は、本発明の第二の実施形態に係る多層基板の製造方法を示す工程図である。この実施形態の製造方法は、基板表層の導体パターンを一括積層プレスの後に行った前記第一の実施形態の方法と異なり、基板表層を含めたすべての配線層の導体パターンを積層工程の前に形成してしまい、それらを一括プレスして一体化するものである。 [Embodiment 2]
FIG. 2 is a process diagram showing a method for manufacturing a multilayer substrate according to the second embodiment of the present invention. The manufacturing method of this embodiment is different from the method of the first embodiment in which the conductor pattern of the substrate surface layer is performed after the collective laminating press, and the conductor patterns of all the wiring layers including the substrate surface layer are subjected to the laminating step. They are formed and integrated by pressing them together.

すなわち、本実施形態の方法では、まず、基板各層を形成する基板基材として、前記第一実施形態と同様に樹脂付き銅箔を用意する。一例として本実施形態では、前記第一の実施形態と同様に基板表層を含めて１１層の配線層を有する多層基板を形成するが、後に述べるように下層部の基材を上下反転させて積層プレスを行うことにより、基板下面の導体パターンは上記樹脂付き銅箔によって形成することが可能であるから、合計１０枚の樹脂付き銅箔を用意する。尚、本実施形態は、第一実施形態と異なり、後の積層工程で基板下面に銅箔を別途配する必要はない。   That is, in the method of this embodiment, first, a copper foil with resin is prepared as a substrate base material for forming each layer of the substrate, as in the first embodiment. As an example, in this embodiment, a multilayer substrate having 11 wiring layers including the substrate surface layer is formed in the same manner as in the first embodiment. However, as described later, the lower layer base material is turned upside down and stacked. Since the conductor pattern on the lower surface of the substrate can be formed by the above-mentioned copper foil with resin by performing pressing, a total of ten copper foils with resin are prepared. Note that, unlike the first embodiment, this embodiment does not require a separate copper foil on the lower surface of the substrate in the subsequent lamination process.

そしてこれらの樹脂付き銅箔（基材）に対し、前記第一実施形態と同様に、基準穴加工（図１Ａ（ａ））、ビアホール用の穴１４の穴開加工・デスミア（同図（ｂ））、ドライフィルム２１のラミネート（同図（ｃ））、露光・現像（同図（ｄ））、基材下面のドライフィルム２１の剥離（同図（ｅ））、フィルドビア１５の形成（同図（ｆ））、銅箔層側のドライフィルム２１の除去（同図（ｇ））、ドライフィルム２２のラミネート（同図（ｈ））、露光・現像・エッチングによる導体パターン１２ａの形成（図１Ｂ（ｉ）〜（ｋ））、ドライフィルムの剥離（同図（ｌ））、樹脂層１３への導体パターン１２ａの埋め込み（同図（ｍ））、ウエットブラストまたはプラズマ処理等のよる導体パターン１２ａ表面およびフィルドビア１５表面に付着した樹脂の除去、ドライフィルム２３のラミネート（同図（ｎ））、露光・現像（同図（ｏ））、ビアホール部へのＡｇ置換めっき（同図（ｐ））、並びに、基材上面のドライフィルムの剥離（同図（ｑ））の各工程を実施し、これにより所定の導体パターン１２ａを有しかつ該導体パターン１２ａが樹脂層１３に埋め込まれた基材１１（１１ａ〜１１ｊ）を準備する。   Then, for these copper foils with resin (base material), as in the first embodiment, reference hole processing (FIG. 1A (a)), drilling of holes 14 for via holes, desmear (FIG. (B) )), Dry film 21 laminating (FIG. (C)), exposure / development (FIG. (D)), peeling of dry film 21 on the lower surface of the substrate (FIG. (E)), formation of filled via 15 (same as above) (F), removal of the dry film 21 on the copper foil layer side (FIG. (G)), lamination of the dry film 22 (FIG. (H)), formation of the conductor pattern 12a by exposure, development and etching (FIG. 1B (i) to (k)), peeling of the dry film (FIG. 1L), embedding of the conductor pattern 12a in the resin layer 13 (FIG. 1M), conductor pattern by wet blasting or plasma treatment, etc. 12a surface and filled via 15 Removal of resin adhering to the surface, lamination of the dry film 23 (FIG. (N)), exposure / development (FIG. (O)), Ag substitution plating on the via hole (FIG. (P)), The substrate 11 (11a to 11a) having a predetermined conductor pattern 12a and having the conductor pattern 12a embedded in the resin layer 13 by performing each step of peeling the dry film on the upper surface of the material ((q) in the figure). 11j) is prepared.

そして、上記導体パターンを形成した１０枚の基板基材１１ａ〜１１ｊをスタックし、これらを加熱プレスして一体に積層する（図２（ａ）〜（ｂ））。ここで、本実施形態では、多層基板の上層部を形成する一群の基材１１ａ〜１１ｅに対し、多層基板の下層部を形成する一群の基材１１ｆ〜１１ｊが上下（表裏）反転された状態でスタックし積層プレスを行う。   Then, the 10 substrate base materials 11a to 11j on which the conductor pattern is formed are stacked, and these are heated and pressed to be laminated together (FIGS. 2A to 2B). Here, in the present embodiment, a group of base materials 11f to 11j that form a lower layer portion of the multilayer substrate are turned upside down (front and back) with respect to a group of base materials 11a to 11e that form the upper layer portion of the multilayer substrate. Stack with and perform lamination press.

具体的には、図２（ａ）に示すように、多層基板の最上層に配される基材１１ａから最下層に配される基材１１ｊまでを順に第１基材、第２基材、…、第１０基材としたときに、基板上層部を形成する第１基材１１ａから第５基材１１ｅまでの各基材は、銅箔層１２（導体パターン１２ａ）が上面側で樹脂層１３が下面側に位置するよう配置してあるのに対し、基板下層部を形成する第６基材１１ｆから第１０基材１１ｊまでの各基材は、銅箔層１２（導体パターン１２ａ）が下面側で樹脂層１３が上面側に位置するよう配置する。   Specifically, as shown in FIG. 2 (a), the first base material, the second base material, in order from the base material 11a disposed on the uppermost layer of the multilayer substrate to the base material 11j disposed on the lowermost layer, When the tenth base material is used, each base material from the first base material 11a to the fifth base material 11e that forms the upper layer portion of the substrate has a copper foil layer 12 (conductor pattern 12a) on the upper surface side and a resin layer 13 is arranged so as to be located on the lower surface side, whereas each of the base materials from the sixth base material 11f to the tenth base material 11j forming the substrate lower layer portion has the copper foil layer 12 (conductor pattern 12a). The resin layer 13 is disposed on the lower surface side so as to be positioned on the upper surface side.

尚、このように基板下層部を形成する基材１１ｆ〜１１ｊは、積層時に上下反転されるため、前記図１Ａ（ｂ）〜（ｍ）に係る各工程を経て形成されるビアホール１５並びに導体パターン１２ａを、当該基材を上下反転させることを考慮した配置としておく。また、反転させる基材の数（上部側の基材数および下部側の基材数）は、この例のほかにも、基板の層数や内層される素子や回路パターンの配置等に応じて様々に変更することがある。   In addition, since the base materials 11f to 11j forming the lower layer portion of the substrate are turned upside down at the time of lamination, the via hole 15 and the conductor pattern formed through the respective steps according to FIGS. 1A (b) to 1 (m). 12a is arranged in consideration of turning the substrate upside down. In addition to this example, the number of base materials to be reversed (the number of base materials on the upper side and the number of base materials on the lower side) depends on the number of layers of the substrate and the arrangement of elements and circuit patterns to be layered. There are various changes.

さらに、基材を反転させる境界部では、ビアホール同士を接続する必要が生じることがある（図示の例では、第５基材１１ｅと第６基材１１ｆの各ビアホール１５）。しかしながらこのような場合にも、ビアホール１５の径を多少大きく設定しておけば、積層時に基材同士が位置ずれを生じてもこれを吸収することができ、層間接続の信頼性を確保することが可能である。   Furthermore, it may be necessary to connect via holes at the boundary portion where the substrate is reversed (in the illustrated example, the via holes 15 of the fifth substrate 11e and the sixth substrate 11f). However, even in such a case, if the diameter of the via hole 15 is set to be slightly larger, it is possible to absorb the positional deviation between the substrates during lamination, and to ensure the reliability of interlayer connection. Is possible.

積層プレス後、導体パターンの表面に付着した樹脂をウエットブラストやプラズマ等の方法により除去し、表層の導体パターン１２ａにニッケルめっきおよび金めっきを施す。このようにして多層基板を形成することが出来る。   After the lamination press, the resin adhering to the surface of the conductor pattern is removed by a method such as wet blasting or plasma, and nickel plating and gold plating are applied to the surface conductor pattern 12a. In this way, a multilayer substrate can be formed.

以上、本発明の実施の形態について説明したが、本発明はこれらに限定されるものではなく、特許請求の範囲に記載の範囲内で種々の変更を行うことができることは当業者にとって明らかである。   Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it will be apparent to those skilled in the art that various modifications can be made within the scope of the claims. .

（ａ）から（ｈ）は、本発明の第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(A) to (h) are substrate cross-sectional views sequentially showing steps of a method for manufacturing a multilayer substrate according to the first embodiment of the present invention. （ｉ）から（ｑ）は、前記第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(I) to (q) are substrate cross-sectional views sequentially showing steps of the method for manufacturing a multilayer substrate according to the first embodiment. （ｒ）から（ｔ）は、前記第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(R) to (t) are substrate cross-sectional views sequentially showing steps of the method for manufacturing a multilayer substrate according to the first embodiment. （ｕ）から（ｖ）は、前記第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(U) to (v) are substrate cross-sectional views sequentially showing steps of the method for manufacturing a multilayer substrate according to the first embodiment. （ｗ）から（ｘ）は、前記第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(W) to (x) are substrate cross-sectional views sequentially showing steps of the method for manufacturing a multilayer substrate according to the first embodiment. （ｙ）から（ｚ）は、前記第一の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(Y) to (z) are substrate cross-sectional views sequentially showing steps of the method for manufacturing a multilayer substrate according to the first embodiment. （ａ）から（ｂ）は、本発明の第二の実施形態に係る多層基板の製造方法の工程を順に示す基板断面図である。(A) to (b) are substrate cross-sectional views sequentially showing steps of a method for manufacturing a multilayer substrate according to a second embodiment of the present invention.

符号の説明Explanation of symbols

１１，１１ａ〜１１ｊ 基板基材（樹脂付き銅箔）
１２ 銅箔層（導体層）
１２ａ，１２ｂ，１６ａ 導体パターン
１３ 樹脂層（絶縁層）
１４ ビアホール用穴
１５ フィルドビア
１６ 銅箔
２１，２２，２３，２４ ドライフィルム 11, 11a-11j Substrate base material (copper foil with resin)
12 Copper foil layer (conductor layer)
12a, 12b, 16a Conductor pattern 13 Resin layer (insulating layer)
14 hole for via hole 15 filled via 16 copper foil 21, 22, 23, 24 dry film

Claims (5)

導体層と熱可塑性樹脂を主体とする材料からなる絶縁層とを一体に有する基板基材を複数用意し、該複数の基板基材のうちの１以上の基板基材の各絶縁層にビアホール用の穴を開け、該穴に導体を配することにより当該基板基材にビアホールを形成するビア形成工程と、
前記複数の基板基材のうち１以上の基板基材の導体層をエッチングして導体パターンを形成する回路形成工程と、
該導体パターンを形成した基板基材を個別にプレスして前記導体パターンを前記絶縁層に埋め込む平滑プレス工程と、
該導体パターンを絶縁層に埋め込んだ基板基材を含む前記複数の基板基材を積み重ねてプレスすることにより一体化する積層プレス工程と、
を含むことを特徴とする多層基板の製造方法。 A plurality of substrate base materials integrally having a conductor layer and an insulating layer made of a material mainly composed of a thermoplastic resin are prepared, and a via hole is formed in each insulating layer of one or more of the plurality of substrate base materials. A via forming step of forming a via hole in the substrate base material by arranging a conductor in the hole,
A circuit forming step of forming a conductor pattern by etching a conductor layer of one or more substrate base materials among the plurality of substrate base materials;
A smooth press step of individually embedding the conductor pattern in the insulating layer by individually pressing the substrate substrate on which the conductor pattern is formed;
A laminating press step for integrating the plurality of substrate substrates including the substrate substrate having the conductor pattern embedded in an insulating layer by stacking and pressing;
A method for producing a multilayer substrate, comprising: 前記積層プレス工程では、前記積み重ねた基板基材のうちの最上層の基板基材は、導体パターンを形成していない未パターニングの導体層を有するものであり、かつ前記積み重ねた基板基材のうちの最下層の基板基材の絶縁層の下面に導体箔を配して前記積層プレスを行い、
該積層プレス工程の後に、前記最上層の基板基材の導体層と、前記最下層の基板基材の絶縁層の下面に配した導体箔とをエッチングして当該多層基板の表層の導体パターンを形成する表層回路形成工程をさらに含む
ことを特徴とする請求項１に記載の多層基板の製造方法。 In the lamination pressing step, the uppermost substrate base material among the stacked substrate substrates has an unpatterned conductor layer in which no conductor pattern is formed, and among the stacked substrate substrates, Conducting the laminating press by placing a conductor foil on the lower surface of the insulating layer of the substrate substrate of the lowermost layer,
After the lamination pressing step, the conductor layer of the uppermost substrate substrate and the conductor foil disposed on the lower surface of the insulating layer of the lowermost substrate substrate are etched to form a conductor pattern on the surface layer of the multilayer substrate. The method for producing a multilayer substrate according to claim 1, further comprising a step of forming a surface layer circuit. 前記積層プレス工程において、少なくとも最上層の基板基材を含む１以上の基板基材に対し、少なくとも最下層の基板基材を含む１以上の基板基材を表裏反転した状態で前記複数の基板基材を積み重ねてプレスすることにより一体化する
ことを特徴とする請求項１に記載の多層基板の製造方法。 In the laminating press step, the plurality of substrate bases in a state in which one or more substrate base materials including at least the lowermost substrate base material are reversed with respect to one or more substrate base materials including at least the uppermost substrate base material. The method for producing a multilayer substrate according to claim 1, wherein materials are integrated by stacking and pressing. 前記平滑プレス工程の後に、当該平滑プレスを行った基板基材の表面の金属表面を覆った樹脂を除去する樹脂除去処理工程
をさらに含むことを特徴とする請求項１から３のいずれか一項に記載の多層基板の製造方法。 The resin removal treatment process of removing the resin which covered the metal surface of the surface of the board | substrate base material which performed the said smooth press after the said smooth press process is characterized by the above-mentioned. The manufacturing method of the multilayer substrate as described in any one of. 前記絶縁層は、芳香族液晶ポリエステルと、該芳香族液晶ポリエステル中に混入させた誘電体セラミック粉末とを含む複合材料により形成されている
ことを特徴とする請求項１から４のいずれか一項に記載の多層基板の製造方法。 The insulating layer is formed of a composite material including an aromatic liquid crystal polyester and a dielectric ceramic powder mixed in the aromatic liquid crystal polyester. The manufacturing method of the multilayer substrate as described in any one of.
JP2004317227A 2004-10-29 2004-10-29 Method of manufacturing multilayer substrate Pending JP2006128519A (en)

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