JP2006041276A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006041276A JP2006041276A JP2004220664A JP2004220664A JP2006041276A JP 2006041276 A JP2006041276 A JP 2006041276A JP 2004220664 A JP2004220664 A JP 2004220664A JP 2004220664 A JP2004220664 A JP 2004220664A JP 2006041276 A JP2006041276 A JP 2006041276A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】半導体基板中に形成されたトレンチの内部にキャパシタ絶縁膜13を介して蓄積電極用の導電材を埋め込んだトレンチ型キャパシタを有し、導電材は、トレンチの下部に埋め込まれた第1の導電材14と、第1の導電材の上面の凹部に埋め込まれた第2の導電材17と、第1の導電材および第2の導電材の上部に接するよう埋め込まれた第3の導電材21とを具備する。
【選択図】 図8
Description
図8は、本発明の第1の実施形態に係るDRAMにおける基板プレート型のトレンチ型キャパシタを用いたDRAMセルの構造の一例を示す断面図である。
第1の実施形態では、基板プレート型のトレンチ型キャパシタを用いたDRAMセルの構造の一例示したが、転送ゲート用MOSFETをトレンチ側面の延長上方で垂直方向に形成した垂直トランジスタ型のDRAMセルの構造についても、第1の実施形態に準じて実現することが可能である。
図14は、本発明の第2の実施形態に係るDRAMにおける埋め込みプラグの一例として、絶縁層の上下配線間を接続するためのViaプラグの構造の一例を示す断面図である。このViaプラグは、半導体基板上の配線層上の絶縁層中に形成されたアスペクト比が高い微細なホールの内部に導電材を埋め込んだ場合を想定している。
第2の実施形態ではViaプラグの構造を実現した例を示したが、トレンチに接する基板側に拡散層を形成してキャパシタ電極の一方とし、トレンチの内部にキャパシタ絶縁膜を介して蓄積電極を埋め込む構造のトレンチ型キャパシタに対しても、第2の実施形態に準じて適用してもよい。
Claims (5)
- 半導体基板中に形成されたトレンチの内部にキャパシタ絶縁膜を介して蓄積電極用の導電材が埋め込まれたトレンチ型キャパシタを有し、前記導電材は、前記トレンチの下部に埋め込まれ、表面に凹部を有する第1の導電材と、前記第1の導電材の凹部に埋め込まれた第2の導電材と、前記第1の導電材および第2の導電材に接するよう前記第1および前記第2の導電材の上部に埋め込まれた第3の導電材とを具備することを特徴とする半導体装置。
- 半導体基板と、前記半導体基板の表層部に選択的に形成された第1導電型の半導体層と、前記半導体層上にゲート絶縁膜を介して形成された電荷転送ゲート用のMOSFETのゲート電極と、前記ゲート電極を挟んで前記半導体層の表層部に選択的に形成された第2導電型のソース・ドレイン領域と、前記ソース・ドレイン領域の一方に接続された蓄積電極を有する基板プレート型のトレンチ型キャパシタを有し、
前記トレンチ型キャパシタは、前記半導体基板中に達する深さまで形成されたトレンチの内面で前記第1導電型の半導体層より下方に形成されたキャパシタ絶縁膜と、前記トレンチの内面で前記キャパシタ絶縁膜の上方に形成されたカラー絶縁膜と、前記トレンチの内部に埋め込まれた蓄積電極用の導電材とを有し、前記導電材は、前記キャパシタ絶縁膜を介して前記トレンチの下部に埋め込まれ、上面に凹部を有する第1の導電材と、前記第1の導電材の凹部に埋め込まれた第2の導電材と、前記カラー絶縁膜を介して前記第1の導電材および第2の導電材の上部に接するよう埋め込まれた第3の導電材とを具備することを特徴とする半導体装置。 - 半導体基板上の絶縁層中に形成されたホールの内部に導電材を埋め込んでなる埋め込みプラグを有し、前記導電材は、前記ホールの内部に埋め込まれた第1の導電材と、前記第1の導電材中に発生した巣および前記第1の導電材の上面に発生した凹部のうち少なくとも凹部に埋め込まれた第2の導電材とを具備することを特徴とする半導体装置。
- 半導体基板中に形成されたトレンチの内部にキャパシタ絶縁膜を介して蓄積電極用の導電材が埋め込まれた構造を有するトレンチ型キャパシタ形成する際、導電材の埋め込みプロセスを複数回に分け、途中のプロセスで導電材中に発生している巣および導電材の上面に発生している凹部のうちの少なくとも凹部を埋め込むための専用の埋め込みプロセスを導入したことを特徴とする半導体装置の製造方法。
- 半導体基板上の絶縁層中にホールを形成する工程と、
前記ホールの内部に導電材を埋め込んだ後、前記導電材の上部を前記ホールの開口面より低い位置まで除去する工程と、
アモルファス・シリコンを低温で堆積した後、等方性エッチングによって前記アモルファス・シリコンのエッチバックを行うことにより、前記導電材の少なくとも上面の凹部を埋め込むことで上面をほぼ平坦化する工程と、
前記アモルファス・シリコンにより上面の凹部が埋め込まれた前記導電材上に配線層を形成する工程
とを具備することを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004220664A JP2006041276A (ja) | 2004-07-28 | 2004-07-28 | 半導体装置およびその製造方法 |
PCT/JP2005/014138 WO2006011632A2 (en) | 2004-07-28 | 2005-07-27 | Semiconductor device including a conductive layer buried in an opening and method of manufacturing the same |
US11/638,492 US7525142B2 (en) | 2004-07-28 | 2006-12-14 | Semiconductor device including a conductive layer buried in an opening and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004220664A JP2006041276A (ja) | 2004-07-28 | 2004-07-28 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2006041276A true JP2006041276A (ja) | 2006-02-09 |
Family
ID=35511307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004220664A Pending JP2006041276A (ja) | 2004-07-28 | 2004-07-28 | 半導体装置およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7525142B2 (ja) |
JP (1) | JP2006041276A (ja) |
WO (1) | WO2006011632A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9646879B2 (en) | 2013-12-27 | 2017-05-09 | Tokyo Electron Limited | Depression filling method and processing apparatus |
Families Citing this family (22)
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---|---|---|---|---|
US7294554B2 (en) * | 2006-02-10 | 2007-11-13 | International Business Machines Corporation | Method to eliminate arsenic contamination in trench capacitors |
US20110017581A1 (en) * | 2009-07-23 | 2011-01-27 | Keith Bryan Hardin | Z-Directed Switch Components for Printed Circuit Boards |
US8198548B2 (en) * | 2009-07-23 | 2012-06-12 | Lexmark International, Inc. | Z-directed capacitor components for printed circuit boards |
US8273996B2 (en) * | 2009-07-23 | 2012-09-25 | Lexmark International, Inc. | Z-directed connector components for printed circuit boards |
US8278568B2 (en) * | 2009-07-23 | 2012-10-02 | Lexmark International, Inc. | Z-directed variable value components for printed circuit boards |
US20110017502A1 (en) * | 2009-07-23 | 2011-01-27 | Keith Bryan Hardin | Z-Directed Components for Printed Circuit Boards |
US8735734B2 (en) * | 2009-07-23 | 2014-05-27 | Lexmark International, Inc. | Z-directed delay line components for printed circuit boards |
US8198547B2 (en) * | 2009-07-23 | 2012-06-12 | Lexmark International, Inc. | Z-directed pass-through components for printed circuit boards |
US8237061B2 (en) * | 2009-07-23 | 2012-08-07 | Lexmark International, Inc. | Z-directed filter components for printed circuit boards |
US20110017504A1 (en) * | 2009-07-23 | 2011-01-27 | Keith Bryan Hardin | Z-Directed Ferrite Bead Components for Printed Circuit Boards |
EP2666215A1 (en) * | 2011-01-21 | 2013-11-27 | Lexmark International, Inc. | Z-directed pass- through components for printed circuit boards |
US8790520B2 (en) | 2011-08-31 | 2014-07-29 | Lexmark International, Inc. | Die press process for manufacturing a Z-directed component for a printed circuit board |
US9009954B2 (en) | 2011-08-31 | 2015-04-21 | Lexmark International, Inc. | Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material |
US8752280B2 (en) | 2011-09-30 | 2014-06-17 | Lexmark International, Inc. | Extrusion process for manufacturing a Z-directed component for a printed circuit board |
US8658245B2 (en) | 2011-08-31 | 2014-02-25 | Lexmark International, Inc. | Spin coat process for manufacturing a Z-directed component for a printed circuit board |
US9078374B2 (en) | 2011-08-31 | 2015-07-07 | Lexmark International, Inc. | Screening process for manufacturing a Z-directed component for a printed circuit board |
US8943684B2 (en) * | 2011-08-31 | 2015-02-03 | Lexmark International, Inc. | Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board |
US9059030B2 (en) * | 2011-10-07 | 2015-06-16 | Micron Technology, Inc. | Memory cells having capacitor dielectric directly against a transistor source/drain region |
US8912452B2 (en) | 2012-03-29 | 2014-12-16 | Lexmark International, Inc. | Z-directed printed circuit board components having different dielectric regions |
US8822840B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for controlling transmission line impedance |
US8830692B2 (en) | 2012-03-29 | 2014-09-09 | Lexmark International, Inc. | Ball grid array systems for surface mounting an integrated circuit using a Z-directed printed circuit board component |
US8822838B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for reducing radiated emissions |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08172173A (ja) * | 1994-09-07 | 1996-07-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002289816A (ja) * | 2001-03-23 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US20040082137A1 (en) * | 2002-10-25 | 2004-04-29 | Nanya Technology Corporation | Process for filling polysilicon seam |
JP2004179451A (ja) * | 2002-11-28 | 2004-06-24 | Toshiba Corp | 半導体装置およびその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2819520B2 (ja) | 1991-05-07 | 1998-10-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Dramセル |
US6180480B1 (en) | 1998-09-28 | 2001-01-30 | International Business Machines Corporation | Germanium or silicon-germanium deep trench fill by melt-flow process |
DE10019090A1 (de) | 2000-04-12 | 2001-10-25 | Infineon Technologies Ag | Grabenkondensator sowie dazugehöriges Herstellungsverfahren |
US6638815B1 (en) | 2002-10-25 | 2003-10-28 | International Business Machines Corporation | Formation of self-aligned vertical connector |
US6960503B2 (en) * | 2003-11-16 | 2005-11-01 | Nanya Technology Corp. | Method for fabricating a trench capacitor |
-
2004
- 2004-07-28 JP JP2004220664A patent/JP2006041276A/ja active Pending
-
2005
- 2005-07-27 WO PCT/JP2005/014138 patent/WO2006011632A2/en active Application Filing
-
2006
- 2006-12-14 US US11/638,492 patent/US7525142B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08172173A (ja) * | 1994-09-07 | 1996-07-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002289816A (ja) * | 2001-03-23 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US20040082137A1 (en) * | 2002-10-25 | 2004-04-29 | Nanya Technology Corporation | Process for filling polysilicon seam |
JP2004179451A (ja) * | 2002-11-28 | 2004-06-24 | Toshiba Corp | 半導体装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9646879B2 (en) | 2013-12-27 | 2017-05-09 | Tokyo Electron Limited | Depression filling method and processing apparatus |
Also Published As
Publication number | Publication date |
---|---|
US7525142B2 (en) | 2009-04-28 |
WO2006011632A2 (en) | 2006-02-02 |
WO2006011632A3 (en) | 2006-07-13 |
US20070085125A1 (en) | 2007-04-19 |
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