JP2006013439A - Semiconductor element mounting structure - Google Patents

Semiconductor element mounting structure Download PDF

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JP2006013439A
JP2006013439A JP2005110188A JP2005110188A JP2006013439A JP 2006013439 A JP2006013439 A JP 2006013439A JP 2005110188 A JP2005110188 A JP 2005110188A JP 2005110188 A JP2005110188 A JP 2005110188A JP 2006013439 A JP2006013439 A JP 2006013439A
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semiconductor element
heat
mounting structure
element mounting
heat conduction
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Yutaka Kumano
豊 熊野
Tetsuyoshi Ogura
哲義 小掠
Toru Yamada
徹 山田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element mounting structure efficiently radiating heat generated from a plurality of semiconductor elements after mounting the plurality of semiconductor elements at high density. <P>SOLUTION: The semiconductor element mounting structure (1) includes: an electric insulating layer (11) containing a plurality of layers of electric insulating base materials (11a-11c); a first semiconductor element (12); a second semiconductor element (13); a heat-radiating part (14) provided on the main face (111) of the electric insulating layer (11); a first heat-conducting path (15) for connecting the heat-radiating part (14) and the first semiconductor element (12); and a second heat-conducting path (16) for connecting the heat-radiating part (14) and the second semiconductor element (13). The first semiconductor element (12) is arranged between at least a part of the heat-radiating part (14) and the second semiconductor element (13). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子が実装された多層配線基板、半導体パッケージ等の半導体素子実装構造体に関し、特に複数の半導体素子が実装された半導体素子実装構造体に関する。   The present invention relates to a semiconductor element mounting structure such as a multilayer wiring board or a semiconductor package on which a semiconductor element is mounted, and more particularly to a semiconductor element mounting structure on which a plurality of semiconductor elements are mounted.

携帯電話、ノートパソコン、デジタルカメラ等に代表されるモバイル電子機器は、その小型化、薄型化及び軽量化が急速に進んでいる。さらに高性能化や多機能化に対する要求も著しく、その要求に対応するため半導体素子及び回路部品の小型化や、これらの電子部品の高密度実装技術は飛躍的に進展している。また、近年の半導体素子分野では、微細加工技術の進展に伴い、半導体素子実装構造体の高集積化や大規模化が進んでいるため、半導体素子実装構造体の消費電力が大きくなり、半導体素子から発生する多量の熱に対する放熱処理が重要な課題となってきている。   Mobile electronic devices typified by mobile phones, notebook computers, digital cameras, and the like are rapidly becoming smaller, thinner and lighter. In addition, there are significant demands for higher performance and multi-functionality, and in order to meet such demands, miniaturization of semiconductor elements and circuit parts and high-density mounting technology for these electronic parts are making rapid progress. Further, in the recent semiconductor element field, with the progress of microfabrication technology, the integration density and the scale of the semiconductor element mounting structure have been increased, so that the power consumption of the semiconductor element mounting structure has increased. The heat dissipation treatment for the large amount of heat generated from the heat has become an important issue.

従来、半導体素子実装構造体の放熱手段としては、半導体素子実装構造体の表面に高熱伝導性金属で形成された放熱フィンを取り付けて、半導体素子から発生する熱を放熱する手段が知られている。   Conventionally, as a heat dissipation means for a semiconductor element mounting structure, a means for dissipating heat generated from a semiconductor element by attaching a heat dissipation fin formed of a highly thermally conductive metal to the surface of the semiconductor element mounting structure is known. .

図６に、上述した放熱手段を備えた従来の半導体素子実装構造体の模式断面図を示す。図６に示すように、半導体素子実装構造体１００は、基材１０１と、基材１０１の開口部１０１ａに配置された半導体素子１０２と、基材１０１の図中上面に熱伝導性接着剤１０３を介して設けられたアルミニウム等からなるヒートシンク１０４とを備えている。これにより、半導体素子１０２から発生する熱がヒートシンク１０４に伝導され、この熱がヒートシンク１０４に設けられた放熱フィンの表面１０４ａから空気中に放散される。また、半導体素子実装構造体１００では、半導体素子１０２の回路形成面１０２ａに設けられた電極（図示せず）が、金線１０５、内部配線１０６ａ及びビア導体１０７を介して外部配線１０６ｂに接続されている。更に、外部配線１０６ｂに接触するバンプ１０８が形成されている。   FIG. 6 is a schematic cross-sectional view of a conventional semiconductor element mounting structure provided with the above-described heat dissipation means. As shown in FIG. 6, the semiconductor element mounting structure 100 includes a base material 101, a semiconductor element 102 disposed in the opening 101 a of the base material 101, and a heat conductive adhesive 103 on the upper surface of the base material 101 in the drawing. And a heat sink 104 made of aluminum or the like provided through the. As a result, heat generated from the semiconductor element 102 is conducted to the heat sink 104, and this heat is dissipated into the air from the surface 104 a of the radiating fin provided on the heat sink 104. In the semiconductor element mounting structure 100, an electrode (not shown) provided on the circuit formation surface 102a of the semiconductor element 102 is connected to the external wiring 106b via the gold wire 105, the internal wiring 106a, and the via conductor 107. ing. Further, bumps 108 that come into contact with the external wiring 106b are formed.

しかし、このようなヒートシンクによる放熱手段を備えた半導体素子実装構造体は実装空間が大きくならざるを得ず、Multi Chip Package（ＭＣＰ）やSystem In Package（ＳＩＰ）等への適用が困難となってきている。このような課題を解決するために、ヒートシンクを用いることなく小型電子機器への搭載が可能な放熱構造を備えた半導体素子実装構造体が提案されている（例えば特許文献１〜３参照）。
特開平９−１５３６７９号公報 特開２００１−２４４６３８号公報 特開２０００−１２７６５号公報 However, a semiconductor device mounting structure having such a heat sink using a heat sink has to have a large mounting space, which makes it difficult to apply to Multi Chip Package (MCP) and System In Package (SIP). ing. In order to solve such a problem, a semiconductor element mounting structure having a heat dissipation structure that can be mounted on a small electronic device without using a heat sink has been proposed (see, for example, Patent Documents 1 to 3).
JP-A-9-153679 JP 2001-244638 A JP 2000-12765 A

しかしながら、上記特許文献１及び２に記載された半導体素子実装構造体は、単一の半導体素子をパッケージ、又は配線基板上に実装したものについての放熱構造であり、ＭＣＰや多層配線基板等の表面又は内部に高密度に実装された複数の半導体素子から発生する多量の熱を放熱させるには不充分であった。   However, the semiconductor element mounting structure described in Patent Documents 1 and 2 is a heat dissipation structure for a single semiconductor element mounted on a package or wiring board, and is a surface of an MCP, multilayer wiring board, or the like. Or it was insufficient to dissipate a large amount of heat generated from a plurality of semiconductor elements mounted in a high density inside.

また、上記特許文献３に記載された半導体素子実装構造体は、基板の表面に実装された半導体素子についての放熱構造であり、多層配線基板等に内蔵された半導体素子から発生する熱を放熱させるには不充分であった。   The semiconductor element mounting structure described in Patent Document 3 is a heat dissipation structure for a semiconductor element mounted on the surface of a substrate, and dissipates heat generated from the semiconductor element incorporated in the multilayer wiring board or the like. It was not enough.

本発明は上記課題を解決するものであり、複数の半導体素子を高密度に実装した上で、複数の半導体素子から発生する熱を効率良く放熱させることができる半導体素子実装構造体を提供する。   The present invention solves the above problems, and provides a semiconductor element mounting structure capable of efficiently dissipating heat generated from a plurality of semiconductor elements after mounting a plurality of semiconductor elements at high density.

本発明の半導体素子実装構造体は、複数層の電気絶縁基材を含む電気絶縁層と、第１半導体素子と、第２半導体素子とを含み、前記第１半導体素子は前記電気絶縁層内に配置され、前記第２半導体素子は前記電気絶縁層内又は前記電気絶縁層の主面に配置されている半導体素子実装構造体であって、
前記電気絶縁層の主面に設けられた放熱部と、
前記放熱部と前記第１半導体素子とを接続する第１導熱路と、
前記放熱部と前記第２半導体素子とを接続する第２導熱路とを含み、
前記第１半導体素子は、前記放熱部の少なくとも一部と前記第２半導体素子との間に配置されていることを特徴とする。 The semiconductor element mounting structure of the present invention includes an electrical insulation layer including a plurality of layers of electrical insulation substrates, a first semiconductor element, and a second semiconductor element, and the first semiconductor element is in the electrical insulation layer. The second semiconductor element is a semiconductor element mounting structure disposed in the electrical insulating layer or on the main surface of the electrical insulating layer,
A heat dissipating part provided on the main surface of the electrical insulating layer;
A first heat conduction path connecting the heat radiating portion and the first semiconductor element;
A second heat conduction path connecting the heat radiating portion and the second semiconductor element,
The first semiconductor element is disposed between at least a part of the heat radiating portion and the second semiconductor element.

本発明の半導体素子実装構造体によれば、複数の半導体素子を高密度に実装した上で、複数の半導体素子から発生する熱を効率良く放熱させることができる半導体素子実装構造体を提供することができる。   According to the semiconductor element mounting structure of the present invention, it is possible to provide a semiconductor element mounting structure capable of efficiently dissipating heat generated from a plurality of semiconductor elements after mounting a plurality of semiconductor elements at high density. Can do.

本発明の半導体素子実装構造体は、複数層の電気絶縁基材を含む電気絶縁層と、第１半導体素子と、第２半導体素子とを含み、第１半導体素子は電気絶縁層内に配置され、第２半導体素子は電気絶縁層内又は電気絶縁層の主面に配置されている。電気絶縁基材は特に限定されないが、例えば熱硬化性樹脂と無機質フィラーとの混合材料からなるもの等が使用できる。電気絶縁基材の層数についても特に限定されず、２層以上であればよい。また、電気絶縁基材の厚みは、例えば１０〜６００μｍの範囲である。また、第１及び第２半導体素子の実装は、公知の方法により行うことができ、例えばフリップチップ接合方式等により実装することができる（例えば、特開２００２−２６１４４９号公報等参照）。   The semiconductor element mounting structure of the present invention includes an electrical insulating layer including a plurality of layers of an electrical insulating base, a first semiconductor element, and a second semiconductor element, and the first semiconductor element is disposed in the electrical insulating layer. The second semiconductor element is disposed in the electrical insulating layer or on the main surface of the electrical insulating layer. The electrically insulating substrate is not particularly limited, and for example, a material made of a mixed material of a thermosetting resin and an inorganic filler can be used. The number of layers of the electrically insulating substrate is not particularly limited as long as it is two or more. Moreover, the thickness of an electrically insulating base material is the range of 10-600 micrometers, for example. The first and second semiconductor elements can be mounted by a known method, for example, by a flip chip bonding method (see, for example, JP-A-2002-261449).

そして、本発明の半導体素子実装構造体は、上記構成に加え、電気絶縁層の主面に設けられた放熱部と、放熱部と第１半導体素子とを接続する第１導熱路と、放熱部と第２半導体素子とを接続する第２導熱路とを含み、第１半導体素子が、放熱部の少なくとも一部と第２半導体素子との間に配置されている。これにより、第１及び第２半導体素子を高密度に実装することができる上、第１及び第２半導体素子のそれぞれに接続された第１及び第２導熱路を介して、第１及び第２半導体素子から発生する熱を放熱部から効率良く放熱させることができる。   In addition to the above configuration, the semiconductor element mounting structure according to the present invention includes a heat dissipating part provided on the main surface of the electrical insulating layer, a first heat conduction path connecting the heat dissipating part and the first semiconductor element, and a heat dissipating part. And a second heat conduction path connecting the second semiconductor element, and the first semiconductor element is disposed between at least a part of the heat radiating portion and the second semiconductor element. Thereby, the first and second semiconductor elements can be mounted with high density, and the first and second heat conducting paths connected to the first and second semiconductor elements, respectively, can be used. Heat generated from the semiconductor element can be efficiently radiated from the heat radiating portion.

放熱部としては、例えば、電気絶縁層の主面に熱プレス等により設けられた銅箔等の金属箔を、公知のフォトリソグラフィー法によりパターニングすることにより形成した導体パターンが使用できる。また、第１及び第２導熱路としては、例えば、電気絶縁基材の所望の位置にレーザー等により貫通孔を形成し、この貫通孔内に金属粉末及び樹脂（例えば、エポキシ樹脂等の熱硬化性樹脂）を含む熱伝導性ペーストを充填した後、熱プレス等により加熱、加圧処理して形成したサーマルビアを使用することができる。このようなサーマルビアは容易に形成することができるため、本発明に使用される第１及び第２導熱路として好ましい。なお、上記貫通孔の径は、例えば１００〜５００μｍ程度であればよい。また、熱伝導性ペーストの代わりに、例えば貫通孔内を金属めっき処理して第１及び第２導熱路を形成してもよい。更には、導体パターンとサーマルビアとを組み合わせたものを第１及び第２導熱路として使用することもできる。   As the heat radiating portion, for example, a conductor pattern formed by patterning a metal foil such as a copper foil provided on the main surface of the electrical insulating layer by hot pressing or the like by a known photolithography method can be used. In addition, as the first and second heat conduction paths, for example, a through hole is formed by a laser or the like at a desired position of the electrical insulating base material, and metal powder and resin (for example, epoxy resin or the like is thermally cured in the through hole. A thermal via formed by heating and pressurizing with a hot press or the like after filling with a heat conductive paste containing a conductive resin) can be used. Since such a thermal via can be easily formed, it is preferable as the first and second heat conduction paths used in the present invention. In addition, the diameter of the said through-hole should just be about 100-500 micrometers, for example. Further, instead of the heat conductive paste, for example, the first and second heat conduction paths may be formed by metal plating in the through holes. Further, a combination of a conductor pattern and a thermal via can be used as the first and second heat conduction paths.

また、第１及び第２半導体素子のそれぞれの単位体積あたりの発熱量（以下、「発熱密度」という）が異なる場合、本発明の半導体素子実装構造体は、第１半導体素子と第２半導体素子とを接続する架橋導熱路を更に含んでいてもよい。発熱密度の大きい半導体素子から発生する熱を、架橋導熱路を介して発熱密度の小さい半導体素子に分散させることができるため、第１及び第２半導体素子から発生する熱をより効率良く放熱させることができるからである。また、この構成では、発熱密度の相違する第１及び第２半導体素子が架橋導熱路により接続されているため、相互に熱移動が生じ、第１及び第２半導体素子の温度が平均化される。これにより、半導体素子実装構造体の内部の温度が均一となって、熱的歪みの発生を防止することができるため、半導体素子実装構造体内の電気接続の信頼性を向上できる。なお、架橋導熱路は、上述した第１及び第２導熱路の形成方法と同様の方法で形成できる。特に、上述したサーマルビアは容易に形成することができるため、本発明に使用される架橋導熱路として好ましい。   Further, when the first and second semiconductor elements have different heat generation amounts per unit volume (hereinafter referred to as “heat generation density”), the semiconductor element mounting structure of the present invention includes the first semiconductor element and the second semiconductor element. And a cross-linking heat conduction path connecting the two. Since heat generated from a semiconductor element having a large heat generation density can be dispersed to a semiconductor element having a low heat generation density via a bridge heat conduction path, heat generated from the first and second semiconductor elements can be radiated more efficiently. Because you can. Further, in this configuration, since the first and second semiconductor elements having different heat generation densities are connected by the bridging heat transfer path, heat transfer occurs, and the temperatures of the first and second semiconductor elements are averaged. . As a result, the temperature inside the semiconductor element mounting structure becomes uniform and the occurrence of thermal distortion can be prevented, so that the reliability of electrical connection in the semiconductor element mounting structure can be improved. In addition, a bridge | crosslinking heat conduction path can be formed by the method similar to the formation method of the 1st and 2nd heat conduction path mentioned above. In particular, the thermal via described above can be easily formed, and thus is preferable as a cross-linked heat conduction path used in the present invention.

また、本発明の半導体素子実装構造体において、第１及び第２半導体素子の少なくとも一方（以下、単に「半導体素子」ともいう）は、フリップチップ実装されていてもよい。半導体素子がフリップチップ実装されることにより、半導体素子実装構造体の小型化や薄型化が実現でき、モバイル電子機器の小型化や薄型化へのニーズに応えることができるからである。また、このとき、半導体素子と導熱路（第１又は第２導熱路）が、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されていてもよい。半導体素子から発生する熱をより効率良く放熱させることができるからである。さらには、集熱パッド及び集熱ランドのうち少なくとも一方の接続面が、凹凸形状に形成されていてもよい。接続面の面積を増大させることができるため、半導体素子から発生する熱をより効率良く放熱させることができるからである。なお、上記「接続面」とは、例えば半導体素子と導熱路との間に、集熱パッド、導熱用バンプ及び集熱ランドがこの順に形成されている場合、集熱パッド及び集熱ランドのいずれの場合も導熱用バンプに接触する面が上記「接続面」となる。また、接続面の面積をより増大させるには、上記「凹凸形状」における凸部の高さ（又は凹部の深さ）が、０．５〜１０μｍの範囲であることが好ましい。また、集熱パッド、導熱用バンプ及び集熱ランドとしては、それぞれ慣用のパッド、バンプ及びランドが使用できる。   In the semiconductor element mounting structure of the present invention, at least one of the first and second semiconductor elements (hereinafter also simply referred to as “semiconductor element”) may be flip-chip mounted. This is because flip-chip mounting of the semiconductor element can realize downsizing and thinning of the semiconductor element mounting structure, and can meet the needs for downsizing and thinning of the mobile electronic device. At this time, the semiconductor element and the heat conducting path (first or second heat conducting path) may be connected via at least one of the heat collecting pad, the heat conducting bump, and the heat collecting land. This is because the heat generated from the semiconductor element can be radiated more efficiently. Furthermore, at least one connection surface of the heat collection pad and the heat collection land may be formed in an uneven shape. This is because the area of the connection surface can be increased, so that the heat generated from the semiconductor element can be radiated more efficiently. The “connection surface” refers to any of the heat collection pad and the heat collection land when, for example, the heat collection pad, the heat conduction bump, and the heat collection land are formed in this order between the semiconductor element and the heat conduction path. Also in this case, the surface that contacts the heat-conducting bump is the “connection surface”. In order to further increase the area of the connection surface, it is preferable that the height of the convex portion (or the depth of the concave portion) in the “uneven shape” is in the range of 0.5 to 10 μm. Further, as the heat collecting pad, the heat conducting bump and the heat collecting land, conventional pads, bumps and lands can be used, respectively.

また、本発明の半導体素子実装構造体が架橋導熱路を更に含む場合は、第２半導体素子がフリップチップ実装され、かつ第２半導体素子と架橋導熱路が、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されていてもよい。第２半導体素子から発生する熱をより効率良く放熱させることができるからである。この場合も、集熱パッド及び集熱ランドの少なくとも一方の接続面が、凹凸形状に形成されていてもよい。接続面の面積を増大させることができるため、第２半導体素子から発生する熱をより効率良く放熱させることができるからである。なお、集熱パッド、導熱用バンプ及び集熱ランドには、上述と同様にそれぞれ慣用のパッド、バンプ及びランドが使用できる。   Further, when the semiconductor element mounting structure of the present invention further includes a bridge heat conduction path, the second semiconductor element is flip-chip mounted, and the second semiconductor element and the bridge heat conduction path are formed by the heat collection pad, the heat conduction bump, and the current collection path. It may be connected via at least one of the thermal lands. This is because the heat generated from the second semiconductor element can be radiated more efficiently. Also in this case, at least one connection surface of the heat collecting pad and the heat collecting land may be formed in an uneven shape. This is because the area of the connection surface can be increased, so that the heat generated from the second semiconductor element can be radiated more efficiently. Note that conventional pads, bumps, and lands can be used for the heat collection pads, the heat conduction bumps, and the heat collection lands in the same manner as described above.

また、本発明の半導体素子実装構造体は、第２半導体素子が、第１半導体素子よりも面積が大きく、かつ電気絶縁基材を介して第１半導体素子を覆うように配置されている半導体素子実装構造体であってもよい。面積がより大きい第２半導体素子と放熱部との間に、面積がより小さい第１半導体素子を収容できるため、半導体素子実装構造体の小型化が容易に実現できるからである。また、この構成によれば、第１及び第２導熱路を電気絶縁基材の厚み方向に貫通して形成することができるため、第１及び第２導熱路の長さをより短くできる。これにより、第１及び第２半導体素子から発生する熱を放熱部から更に効率良く放熱させることができる。この場合、第１半導体素子としては、例えば演算機能を有する半導体素子（例えば中央演算素子（ＣＰＵ））が使用でき、第２半導体素子としては、例えば記憶機能を有する半導体素子（例えばメモリ）が使用できる。演算機能を有する半導体素子の面積は、通常１．０ｃｍ2程度であり、記憶機能を有する半導体素子の面積は、通常３．０ｃｍ2程度であるため、上記構成の場合に用いる半導体素子として好適である。以下、本発明の実施形態について図面を参照して説明する。 In the semiconductor element mounting structure of the present invention, the second semiconductor element has a larger area than the first semiconductor element and is disposed so as to cover the first semiconductor element via the electrically insulating base material. It may be a mounting structure. This is because the first semiconductor element having a smaller area can be accommodated between the second semiconductor element having a larger area and the heat radiating portion, so that the semiconductor element mounting structure can be easily reduced in size. Moreover, according to this structure, since the 1st and 2nd heat conduction path can be penetrated and formed in the thickness direction of an electrically insulating base material, the length of a 1st and 2nd heat conduction path can be made shorter. Thereby, the heat generated from the first and second semiconductor elements can be radiated more efficiently from the heat radiating section. In this case, as the first semiconductor element, for example, a semiconductor element having an arithmetic function (for example, a central arithmetic element (CPU)) can be used, and for example, a semiconductor element having a memory function (for example, a memory) is used as the second semiconductor element. it can. Since the area of the semiconductor element having a calculation function is usually about 1.0 cm 2 and the area of the semiconductor element having a memory function is usually about 3.0 cm 2, it is suitable as a semiconductor element used in the above structure. is there. Embodiments of the present invention will be described below with reference to the drawings.

［第１実施形態］
まず、本発明の第１実施形態について適宜図面を参照して説明する。参照する図１は、本発明の第１実施形態に係る半導体素子実装構造体の模式断面図である。 [First Embodiment]
First, a first embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 1 to be referred to is a schematic cross-sectional view of the semiconductor element mounting structure according to the first embodiment of the present invention.

図１に示すように、第１実施形態に係る半導体素子実装構造体１は、電気絶縁基材１１ａ，１１ｂ，１１ｃを含む電気絶縁層１１と、電気絶縁基材１１ｂ内に配置された第１半導体素子１２と、電気絶縁基材１１ｃ内に配置された第２半導体素子１３と、電気絶縁層１１の電気絶縁基材１１ａ側の主面１１１に設けられた放熱部１４と、放熱部１４と第１半導体素子１２とを接続する第１導熱路１５と、放熱部１４と第２半導体素子１３とを接続する第２導熱路１６と、第１半導体素子１２と第２半導体素子１３とを接続する架橋導熱路１７とを含む。ここで、第１及び第２半導体素子１２，１３は、それぞれの発熱密度が異なる。また、第２導熱路１６は、電気絶縁基材１１ｃ内に配置された導体パターン１６ａと、電気絶縁基材１１ａ，１１ｂの厚み方向に形成されたサーマルビア１６ｂとから構成されている。また、第１導熱路１５は、電気絶縁基材１１ａの厚み方向に形成されたサーマルビアから構成され、架橋導熱路１７は、電気絶縁基材１１ｂの厚み方向に形成されたサーマルビアから構成されている。そして、第１半導体素子１２は、放熱部１４の一部と第２半導体素子１３との間に配置されている。これにより、第１及び第２半導体素子１２，１３を高密度に実装することができる上、第１及び第２半導体素子１２，１３のそれぞれに接続された第１及び第２導熱路１５，１６を介して、第１及び第２半導体素子１２，１３から発生する熱を放熱部１４から効率良く放熱させることができる。   As shown in FIG. 1, the semiconductor element mounting structure 1 according to the first embodiment includes an electrical insulation layer 11 including electrical insulation base materials 11a, 11b, and 11c, and a first disposed in the electrical insulation base material 11b. A semiconductor element 12, a second semiconductor element 13 disposed in the electrically insulating base material 11c, a heat radiating part 14 provided on the main surface 111 of the electric insulating layer 11 on the electric insulating base material 11a side, and a heat radiating part 14 The first heat conduction path 15 connecting the first semiconductor element 12, the second heat conduction path 16 connecting the heat radiating portion 14 and the second semiconductor element 13, and the first semiconductor element 12 and the second semiconductor element 13 are connected. And a cross-linking heat conduction path 17. Here, the first and second semiconductor elements 12 and 13 have different heat generation densities. The second heat conduction path 16 includes a conductor pattern 16a disposed in the electrical insulating base material 11c and thermal vias 16b formed in the thickness direction of the electrical insulating base materials 11a and 11b. The first heat conduction path 15 is composed of thermal vias formed in the thickness direction of the electrical insulating base material 11a, and the bridge heat conduction path 17 is composed of thermal vias formed in the thickness direction of the electrical insulation base material 11b. ing. The first semiconductor element 12 is disposed between a part of the heat radiation part 14 and the second semiconductor element 13. Accordingly, the first and second semiconductor elements 12 and 13 can be mounted with high density, and the first and second heat conduction paths 15 and 16 connected to the first and second semiconductor elements 12 and 13 respectively. Thus, heat generated from the first and second semiconductor elements 12 and 13 can be efficiently radiated from the heat radiating portion 14.

また、半導体素子実装構造体１は、架橋導熱路１７を含むため、第１半導体素子１２と第２半導体素子１３との温度差に起因する熱流束が架橋導熱路１７内に生じ、発熱密度のより大きい半導体素子から発熱密度のより小さい半導体素子へと熱が伝わる。これにより、第１及び第２半導体素子１２，１３から発生する熱をより効率良く放熱させることができる。この場合、発熱密度のより大きい半導体素子は、第１及び第２半導体素子１２，１３のいずれであってもよい。   Further, since the semiconductor element mounting structure 1 includes the bridge heat conduction path 17, a heat flux due to the temperature difference between the first semiconductor element 12 and the second semiconductor element 13 is generated in the bridge heat conduction path 17, and the heat generation density is reduced. Heat is transferred from a larger semiconductor element to a semiconductor element having a lower heat generation density. Thereby, the heat generated from the first and second semiconductor elements 12 and 13 can be radiated more efficiently. In this case, the semiconductor element having a higher heat generation density may be any of the first and second semiconductor elements 12 and 13.

以上、本発明の第１実施形態について説明したが、本発明は上記実施形態に限定されない。例えば、図１では、架橋導熱路１７を設けたが、本発明は架橋導熱路を設けなくてもよい。また、図１では、第１半導体素子１２と第２半導体素子１３との間に電気絶縁基材を１層のみ配置したが、２層以上の電気絶縁基材を配置してもよい。また、第２半導体素子１３を、電気絶縁層１１の電気絶縁基材１１ｃ側の主面１１２に実装してもよい。また、第１及び第２半導体素子１２，１３以外の半導体素子（図示せず）を更に実装してもよい。また、第１導熱路、第２導熱路、架橋導熱路及び放熱部の個数についても、図１に示す個数に限定されない。また、第１及び第２導熱路１５，１６が、それぞれ異なる断面積を有していてもよい。また、電気絶縁層１１の側面１１３に、第２放熱部（図示せず）を更に設けてもよい。また、図２に示すように、放熱部１４が、電気絶縁層１１の両側の主面１１１，１１２に設けられた半導体素子実装構造体１０としてもよい。図２に示す構成では、第２導熱路１６は、電気絶縁基材１１ｃの厚み方向に形成されたサーマルビアから構成されている。なお、図１及び図２においては、本発明を説明する上で必要となる部材のみを描画したが、通常、電気絶縁層１１には、電気信号を伝送するビア導体や電極端子等が設けられている。もちろん、第１導熱路１５や第２導熱路１６が、電気信号を伝送するビア導体としての役割を担っていてもよいし、放熱部１４が、電極端子としての役割を担っていてもよい。   The first embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment. For example, in FIG. 1, the bridging heat conduction path 17 is provided, but the present invention may not provide the bridging heat conduction path. In FIG. 1, only one layer of the electrically insulating base material is disposed between the first semiconductor element 12 and the second semiconductor element 13, but two or more layers of electrically insulating base material may be disposed. Further, the second semiconductor element 13 may be mounted on the main surface 112 of the electric insulating layer 11 on the electric insulating base material 11c side. Further, a semiconductor element (not shown) other than the first and second semiconductor elements 12 and 13 may be further mounted. Further, the numbers of the first heat transfer path, the second heat transfer path, the bridge heat transfer path, and the heat radiating portion are not limited to the numbers shown in FIG. Further, the first and second heat conducting paths 15 and 16 may have different cross-sectional areas. Further, a second heat radiating portion (not shown) may be further provided on the side surface 113 of the electrical insulating layer 11. In addition, as shown in FIG. 2, the heat dissipation portion 14 may be a semiconductor element mounting structure 10 provided on the main surfaces 111 and 112 on both sides of the electrical insulating layer 11. In the configuration shown in FIG. 2, the second heat conduction path 16 is composed of thermal vias formed in the thickness direction of the electrically insulating base material 11 c. In FIGS. 1 and 2, only members necessary for explaining the present invention are drawn, but the electrical insulating layer 11 is usually provided with via conductors and electrode terminals for transmitting electrical signals. ing. Of course, the 1st heat conduction path 15 and the 2nd heat conduction path 16 may play the role as a via conductor which transmits an electric signal, and the thermal radiation part 14 may play the role as an electrode terminal.

［第２実施形態］
次に、本発明の第２実施形態について適宜図面を参照して説明する。参照する図３は、本発明の第２実施形態に係る半導体素子実装構造体の模式断面図である。なお、図３において、上述した第１実施形態に係る半導体素子実装構造体１（図１参照）と同一構成のものには同一の符号を付し、その説明は省略する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 3 to be referred to is a schematic cross-sectional view of a semiconductor element mounting structure according to the second embodiment of the present invention. In FIG. 3, the same components as those of the semiconductor element mounting structure 1 (see FIG. 1) according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図３に示すように、第２実施形態に係る半導体素子実装構造体２は、４層の電気絶縁基材２１ａ〜２１ｄを含む電気絶縁層２１と、電気絶縁基材２１ｂ内に設けられた共通導熱路２２とを含み、第１及び第２導熱路１５，１６が、共通導熱路２２に接続されている。その他の構成は、上述した半導体素子実装構造体１（図１参照）と同様である。これにより、第１及び第２半導体素子１２，１３から発生する熱をより効率良く放熱させることができる。なお、共通導熱路２２の形成方法としては、放熱部１４の形成方法と同様の方法を用いることができる。また、共通導熱路２２が、グラウンド層や電源層としての役割を担っていてもよい。   As shown in FIG. 3, the semiconductor element mounting structure 2 according to the second embodiment includes an electric insulating layer 21 including four layers of electric insulating base materials 21a to 21d, and a common provided in the electric insulating base material 21b. The first and second heat transfer paths 15 and 16 are connected to the common heat transfer path 22. Other configurations are the same as those of the above-described semiconductor element mounting structure 1 (see FIG. 1). Thereby, the heat generated from the first and second semiconductor elements 12 and 13 can be radiated more efficiently. In addition, as a formation method of the common heat conduction path 22, the same method as the formation method of the thermal radiation part 14 can be used. Further, the common heat conduction path 22 may serve as a ground layer or a power supply layer.

以上、本発明の第２実施形態について説明したが、本発明は上記実施形態に限定されない。例えば、図３では、架橋導熱路１７を設けたが、本発明は架橋導熱路を設けなくてもよい。また、図３では、第１半導体素子１２と第２半導体素子１３との間に電気絶縁基材を１層のみ配置したが、２層以上の電気絶縁基材を配置してもよい。また、第２半導体素子１３を、電気絶縁層２１の電気絶縁基材２１ｄ側の主面２１２に実装してもよい。また、第１及び第２半導体素子１２，１３以外の半導体素子（図示せず）を更に実装してもよい。また、第１導熱路、第２導熱路、架橋導熱路及び放熱部の個数についても、図３に示す個数に限定されない。また、第１及び第２導熱路１５，１６が、それぞれ異なる断面積を有していてもよい。また、放熱部１４を電気絶縁層２１の両側の主面２１１，２１２に設けてもよい。また、電気絶縁層２１の側面２１３に、第２放熱部（図示せず）を更に設けてもよい。なお、図３においては、本発明を説明する上で必要となる部材のみを描画したが、通常、電気絶縁層２１には、電気信号を伝送するビア導体や電極端子等が設けられている。もちろん、第１導熱路１５や第２導熱路１６が、電気信号を伝送するビア導体としての役割を担っていてもよいし、放熱部１４が、電極端子としての役割を担っていてもよい。   The second embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment. For example, in FIG. 3, the bridge heat conduction path 17 is provided, but the present invention does not need to provide the bridge heat conduction path. In FIG. 3, only one layer of the electrically insulating base material is disposed between the first semiconductor element 12 and the second semiconductor element 13, but two or more layers of electrically insulating base material may be disposed. Further, the second semiconductor element 13 may be mounted on the main surface 212 of the electric insulating layer 21 on the electric insulating base material 21d side. Further, a semiconductor element (not shown) other than the first and second semiconductor elements 12 and 13 may be further mounted. Further, the numbers of the first heat transfer path, the second heat transfer path, the bridge heat transfer path, and the heat radiating portion are not limited to the numbers shown in FIG. Further, the first and second heat conducting paths 15 and 16 may have different cross-sectional areas. Further, the heat radiating portion 14 may be provided on the main surfaces 211 and 212 on both sides of the electrical insulating layer 21. Further, a second heat radiating portion (not shown) may be further provided on the side surface 213 of the electrical insulating layer 21. In FIG. 3, only members necessary for explaining the present invention are drawn. Usually, the electrical insulating layer 21 is provided with via conductors and electrode terminals for transmitting electrical signals. Of course, the 1st heat conduction path 15 and the 2nd heat conduction path 16 may play the role as a via conductor which transmits an electric signal, and the thermal radiation part 14 may play the role as an electrode terminal.

［第３実施形態］
次に、本発明の第３実施形態について適宜図面を参照して説明する。参照する図４は、本発明の第３実施形態に係る半導体素子実装構造体の模式断面図である。なお、図４において、上述した第１実施形態に係る半導体素子実装構造体１（図１参照）と同一構成のものには同一の符号を付し、その説明は省略する。 [Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 4 to be referred to is a schematic cross-sectional view of a semiconductor element mounting structure according to the third embodiment of the present invention. In FIG. 4, the same components as those of the semiconductor element mounting structure 1 (see FIG. 1) according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図４に示すように、第３実施形態に係る半導体素子実装構造体３は、第１及び第２半導体素子１２，１３がフリップチップ実装されている。また、第２導熱路１６は、電気絶縁基材１１ａ，１１ｂの厚み方向に形成されたサーマルビアから構成されている。また、第１半導体素子１２と第１導熱路１５の接続箇所には、第１半導体素子１２側から順に集熱パッド３１、導熱用バンプ３２及び集熱ランド３３が設けられている。同様に、第２半導体素子１３と第２導熱路１６の接続箇所、及び第２半導体素子１３と架橋導熱路１７の接続箇所には、それぞれ第２半導体素子１３側から順に集熱パッド３１、導熱用バンプ３２及び集熱ランド３３が設けられている。その他の構成は、上述した半導体素子実装構造体１（図１参照）と同様である。これにより、第１及び第２半導体素子１２，１３から、それぞれ第１及び第２導熱路１５，１６へ効率よく熱を伝導させることができるため、第１及び第２半導体素子１２，１３から発生する熱をより効率良く放熱させることができる。   As shown in FIG. 4, in the semiconductor element mounting structure 3 according to the third embodiment, the first and second semiconductor elements 12 and 13 are flip-chip mounted. Moreover, the 2nd heat conduction path 16 is comprised from the thermal via formed in the thickness direction of the electrically insulating base materials 11a and 11b. A heat collecting pad 31, a heat conducting bump 32, and a heat collecting land 33 are provided in order from the first semiconductor element 12 side at the connection portion between the first semiconductor element 12 and the first heat conducting path 15. Similarly, the heat collection pad 31 and the heat conduction line are connected to the connection portion between the second semiconductor element 13 and the second heat conduction path 16 and the connection portion between the second semiconductor element 13 and the bridge heat conduction path 17 in order from the second semiconductor element 13 side. Bumps 32 and heat collecting lands 33 are provided. Other configurations are the same as those of the above-described semiconductor element mounting structure 1 (see FIG. 1). Accordingly, heat can be efficiently conducted from the first and second semiconductor elements 12 and 13 to the first and second heat conduction paths 15 and 16, respectively. Therefore, the heat is generated from the first and second semiconductor elements 12 and 13. Heat can be dissipated more efficiently.

以上、本発明の第３実施形態について説明したが、本発明は上記実施形態に限定されない。例えば、図４では、架橋導熱路１７を設けたが、本発明は架橋導熱路を設けなくてもよい。また、第１半導体素子１２と第２半導体素子１３との間に配置される電気絶縁基材の層数についても、特に限定されない。また、第２半導体素子１３を、電気絶縁層１１の電気絶縁基材１１ｃ側の主面１１２に実装してもよい。また、第１及び第２半導体素子１２，１３以外の半導体素子（図示せず）を更に実装してもよい。また、第１導熱路、第２導熱路、架橋導熱路及び放熱部の個数についても、図４に示す個数に限定されない。また、第１及び第２導熱路１５，１６が、それぞれ異なる断面積を有していてもよい。また、放熱部１４を電気絶縁層１１の両側の主面１１１，１１２に設けてもよい。また、電気絶縁層１１の側面１１３に、第２放熱部（図示せず）を更に設けてもよい。なお、図４においては、本発明を説明する上で必要となる部材のみを描画したが、通常、電気絶縁層１１には、電気信号を伝送するビア導体や電極端子等が設けられている。もちろん、第１導熱路１５や第２導熱路１６が、電気信号を伝送するビア導体としての役割を担っていてもよいし、放熱部１４が、電極端子としての役割を担っていてもよい。   The third embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment. For example, in FIG. 4, the bridge heat conduction path 17 is provided, but the present invention does not need to provide the bridge heat conduction path. In addition, the number of layers of the electrically insulating substrate disposed between the first semiconductor element 12 and the second semiconductor element 13 is not particularly limited. Further, the second semiconductor element 13 may be mounted on the main surface 112 of the electric insulating layer 11 on the electric insulating base material 11c side. Further, a semiconductor element (not shown) other than the first and second semiconductor elements 12 and 13 may be further mounted. Further, the numbers of the first heat transfer path, the second heat transfer path, the bridge heat transfer path, and the heat radiating portion are not limited to the numbers shown in FIG. Further, the first and second heat conducting paths 15 and 16 may have different cross-sectional areas. Further, the heat radiating portion 14 may be provided on the main surfaces 111 and 112 on both sides of the electrical insulating layer 11. Further, a second heat radiating portion (not shown) may be further provided on the side surface 113 of the electrical insulating layer 11. In FIG. 4, only members necessary for explaining the present invention are drawn. Usually, the electrical insulating layer 11 is provided with via conductors and electrode terminals for transmitting electrical signals. Of course, the 1st heat conduction path 15 and the 2nd heat conduction path 16 may play the role as a via conductor which transmits an electric signal, and the thermal radiation part 14 may play the role as an electrode terminal.

［第４実施形態］
次に、本発明の第４実施形態について適宜図面を参照して説明する。参照する図５は、本発明の第４実施形態に係る半導体素子実装構造体の模式断面図である。なお、図５において、上述した第１実施形態に係る半導体素子実装構造体１（図１参照）と同一構成のものには同一の符号を付し、その説明は省略する。 [Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 5 to be referred to is a schematic cross-sectional view of a semiconductor element mounting structure according to the fourth embodiment of the present invention. In FIG. 5, the same components as those of the semiconductor element mounting structure 1 (see FIG. 1) according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図５に示すように、第４実施形態に係る半導体素子実装構造体４は、第２半導体素子４３が、電気絶縁基材１１ｂを介して第１半導体素子４２を覆うように配置されている。また、第２半導体素子４３は、第１半導体素子４２に比べ面積が大きく、発熱密度が小さい。例えば第１半導体素子４２としては、中央演算素子（ＣＰＵ）のような演算機能を有する半導体素子を使用することができ、第２半導体素子４３としては、メモリのような記憶機能を有する半導体素子を使用することができる。また、第２導熱路１６は、電気絶縁基材１１ａ，１１ｂの厚み方向に形成されたサーマルビアから構成されている。その他の構成は、上述した半導体素子実装構造体１（図１参照）と同様である。これにより、面積がより大きい第２半導体素子４３と放熱部１４との間に、面積がより小さい第１半導体素子４２を収容した上で、第１及び第２半導体素子４２，４３のそれぞれに接続された第１及び第２導熱路１５，１６を介して、第１及び第２半導体素子４２，４３から発生する熱を放熱部１４から効率良く放熱させることができる。よって、放熱性が高い上、小型化が容易に実現できる半導体素子実装構造体を提供することができる。   As shown in FIG. 5, in the semiconductor element mounting structure 4 according to the fourth embodiment, the second semiconductor element 43 is disposed so as to cover the first semiconductor element 42 via the electrical insulating base material 11 b. The second semiconductor element 43 has a larger area and a lower heat generation density than the first semiconductor element 42. For example, a semiconductor element having a calculation function such as a central processing element (CPU) can be used as the first semiconductor element 42, and a semiconductor element having a storage function such as a memory is used as the second semiconductor element 43. Can be used. Moreover, the 2nd heat conduction path 16 is comprised from the thermal via formed in the thickness direction of the electrically insulating base materials 11a and 11b. Other configurations are the same as those of the above-described semiconductor element mounting structure 1 (see FIG. 1). Accordingly, the first semiconductor element 42 having a smaller area is accommodated between the second semiconductor element 43 having a larger area and the heat radiating portion 14, and then connected to the first and second semiconductor elements 42 and 43, respectively. The heat generated from the first and second semiconductor elements 42 and 43 can be efficiently radiated from the heat radiating portion 14 through the first and second heat conduction paths 15 and 16. Therefore, it is possible to provide a semiconductor element mounting structure that has high heat dissipation and can be easily reduced in size.

以上、本発明の第４実施形態について説明したが、本発明は上記実施形態に限定されない。例えば、図５では、架橋導熱路１７を設けたが、本発明は架橋導熱路を設けなくてもよい。また、図５では、第１半導体素子４２と第２半導体素子４３との間に電気絶縁基材を１層のみ配置したが、２層以上の電気絶縁基材を配置してもよい。また、第２半導体素子４３を、電気絶縁層１１の電気絶縁基材１１ｃ側の主面１１２に実装してもよい。また、第１及び第２半導体素子４２，４３以外の半導体素子（図示せず）を更に実装してもよい。また、第１導熱路、第２導熱路、架橋導熱路及び放熱部の個数についても、図５に示す個数に限定されない。また、第１及び第２導熱路１５，１６が、それぞれ異なる断面積を有していてもよい。また、放熱部１４を電気絶縁層１１の両側の主面１１１，１１２に設けてもよい。また、電気絶縁層１１の側面１１３に、第２放熱部（図示せず）を更に設けてもよい。なお、図５においては、本発明を説明する上で必要となる部材のみを描画したが、通常、電気絶縁層１１には、電気信号を伝送するビア導体や電極端子等が設けられている。もちろん、第１導熱路１５や第２導熱路１６が、電気信号を伝送するビア導体としての役割を担っていてもよいし、放熱部１４が、電極端子としての役割を担っていてもよい。   Although the fourth embodiment of the present invention has been described above, the present invention is not limited to the above embodiment. For example, in FIG. 5, the bridging heat conduction path 17 is provided, but the present invention may not provide the bridging heat conduction path. In FIG. 5, only one layer of the electrically insulating base material is disposed between the first semiconductor element 42 and the second semiconductor element 43, but two or more layers of electrically insulating base material may be disposed. Further, the second semiconductor element 43 may be mounted on the main surface 112 of the electric insulating layer 11 on the electric insulating base material 11c side. Further, semiconductor elements (not shown) other than the first and second semiconductor elements 42 and 43 may be further mounted. Further, the numbers of the first heat transfer path, the second heat transfer path, the bridge heat transfer path, and the heat radiating portion are not limited to the numbers shown in FIG. Further, the first and second heat conducting paths 15 and 16 may have different cross-sectional areas. Further, the heat radiating portion 14 may be provided on the main surfaces 111 and 112 on both sides of the electrical insulating layer 11. Further, a second heat radiating portion (not shown) may be further provided on the side surface 113 of the electrical insulating layer 11. In FIG. 5, only members necessary for explaining the present invention are drawn, but the electrical insulating layer 11 is usually provided with via conductors and electrode terminals for transmitting electrical signals. Of course, the 1st heat conduction path 15 and the 2nd heat conduction path 16 may play the role as a via conductor which transmits an electric signal, and the thermal radiation part 14 may play the role as an electrode terminal.

上述したように、本発明における半導体素子実装構造体は、複数の半導体素子を高密度に実装した上で、複数の半導体素子から発生する熱を効率良く放熱させることができるため、ＭＣＰや多層配線基板等の半導体素子実装構造体の小型化を容易に達成することができる。よって、携帯電話等の小型化や薄型化が要求される電子機器に好適に使用できる。   As described above, the semiconductor element mounting structure according to the present invention can efficiently dissipate heat generated from a plurality of semiconductor elements after mounting a plurality of semiconductor elements at high density. Miniaturization of a semiconductor element mounting structure such as a substrate can be easily achieved. Therefore, it can be suitably used for an electronic device such as a mobile phone that requires a reduction in size and thickness.

本発明の第１実施形態に係る半導体素子実装構造体の模式断面図である。It is a schematic cross section of the semiconductor element mounting structure according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体素子実装構造体の変形例を示す模式断面図である。It is a schematic cross section which shows the modification of the semiconductor element mounting structure which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体素子実装構造体の模式断面図である。It is a schematic cross section of a semiconductor element mounting structure according to a second embodiment of the present invention. 本発明の第３実施形態に係る半導体素子実装構造体の模式断面図である。It is a schematic cross section of the semiconductor element mounting structure concerning a 3rd embodiment of the present invention. 本発明の第４実施形態に係る半導体素子実装構造体の模式断面図である。It is a schematic cross section of the semiconductor element mounting structure according to the fourth embodiment of the present invention. 従来の放熱手段を備えた半導体素子実装構造体の模式断面図である。It is a schematic cross section of the semiconductor element mounting structure provided with the conventional heat dissipation means.

符号の説明Explanation of symbols

１，２，３，４，１０ 半導体素子実装構造体
１１，２１ 電気絶縁層
１１ａ，１１ｂ，１１ｃ，２１ａ，２１ｂ，２１ｃ，２１ｄ 電気絶縁基材
１２，４２ 第１半導体素子
１３，４３ 第２半導体素子
１４ 放熱部
１５ 第１導熱路
１６ 第２導熱路
１６ａ 導体パターン
１６ｂ サーマルビア
１７ 架橋導熱路
２２ 共通導熱路
３１ 集熱パッド
３２ 導熱用バンプ
３３ 集熱ランド
１１１，１１２，２１１，２１２ 主面
１１３，２１３ 側面

1, 2, 3, 4, 10 Semiconductor device mounting structure 11, 21 Electrical insulation layer 11a, 11b, 11c, 21a, 21b, 21c, 21d Electrical insulation substrate 12, 42 First semiconductor device 13, 43 Second semiconductor Element 14 Heat radiation portion 15 First heat conduction path 16 Second heat conduction path 16a Conductor pattern 16b Thermal via 17 Bridged heat conduction path 22 Common heat conduction path 31 Heat collection pad 32 Heat conduction bump 33 Heat collection land 111, 112, 211, 212 Main surface 113 , 213 Side

Claims (11)

複数層の電気絶縁基材を含む電気絶縁層と、第１半導体素子と、第２半導体素子とを含み、前記第１半導体素子は前記電気絶縁層内に配置され、前記第２半導体素子は前記電気絶縁層内又は前記電気絶縁層の主面に配置されている半導体素子実装構造体であって、
前記電気絶縁層の主面に設けられた放熱部と、
前記放熱部と前記第１半導体素子とを接続する第１導熱路と、
前記放熱部と前記第２半導体素子とを接続する第２導熱路とを含み、
前記第１半導体素子は、前記放熱部の少なくとも一部と前記第２半導体素子との間に配置されていることを特徴とする半導体素子実装構造体。 An electrical insulating layer including a plurality of layers of an electrical insulating substrate, a first semiconductor element, and a second semiconductor element, wherein the first semiconductor element is disposed in the electrical insulating layer, and the second semiconductor element is A semiconductor element mounting structure disposed in an electrical insulating layer or on a main surface of the electrical insulating layer,
A heat dissipating part provided on the main surface of the electrical insulating layer;
A first heat conduction path connecting the heat radiating portion and the first semiconductor element;
A second heat conduction path connecting the heat radiating portion and the second semiconductor element,
The semiconductor element mounting structure, wherein the first semiconductor element is disposed between at least a part of the heat radiating portion and the second semiconductor element. 前記第１及び第２半導体素子は、それぞれの単位体積あたりの発熱量が異なり、
前記半導体素子実装構造体は、前記第１半導体素子と前記第２半導体素子とを接続する架橋導熱路を更に含む請求項１に記載の半導体素子実装構造体。 The first and second semiconductor elements have different calorific values per unit volume,
The semiconductor element mounting structure according to claim 1, wherein the semiconductor element mounting structure further includes a bridging heat conduction path that connects the first semiconductor element and the second semiconductor element. 前記第１及び第２半導体素子の少なくとも一方は、フリップチップ実装されている請求項１又は請求項２に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to claim 1, wherein at least one of the first and second semiconductor elements is flip-chip mounted. 前記第１半導体素子は、フリップチップ実装されており、
前記第１半導体素子と前記第１導熱路は、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されている請求項１に記載の半導体素子実装構造体。 The first semiconductor element is flip-chip mounted,
2. The semiconductor element mounting structure according to claim 1, wherein the first semiconductor element and the first heat conducting path are connected via at least one of a heat collecting pad, a heat conducting bump, and a heat collecting land. 前記第２半導体素子は、フリップチップ実装されており、
前記第２半導体素子と前記第２導熱路は、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されている請求項１に記載の半導体素子実装構造体。 The second semiconductor element is flip-chip mounted,
2. The semiconductor element mounting structure according to claim 1, wherein the second semiconductor element and the second heat conducting path are connected via at least one of a heat collecting pad, a heat conducting bump, and a heat collecting land. 前記第２半導体素子は、フリップチップ実装されており、
前記第２半導体素子と前記架橋導熱路は、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されている請求項２に記載の半導体素子実装構造体。 The second semiconductor element is flip-chip mounted,
3. The semiconductor element mounting structure according to claim 2, wherein the second semiconductor element and the bridging heat conduction path are connected via at least one of a heat collection pad, a heat conduction bump, and a heat collection land. 前記集熱パッド及び前記集熱ランドの少なくとも一方の接続面は、凹凸形状に形成されている請求項４〜６のいずれか１項に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to any one of claims 4 to 6, wherein at least one connection surface of the heat collecting pad and the heat collecting land is formed in an uneven shape. 前記第２半導体素子は、前記第１半導体素子よりも面積が大きく、かつ前記電気絶縁基材を介して前記第１半導体素子を覆うように配置されている請求項１に記載の半導体素子実装構造体。   2. The semiconductor element mounting structure according to claim 1, wherein the second semiconductor element has a larger area than the first semiconductor element and is disposed so as to cover the first semiconductor element via the electrically insulating base material. body. 前記第１半導体素子は、演算機能を有する半導体素子であり、
前記第２半導体素子は、記憶機能を有する半導体素子である請求項８に記載の半導体素子実装構造体。 The first semiconductor element is a semiconductor element having an arithmetic function,
The semiconductor element mounting structure according to claim 8, wherein the second semiconductor element is a semiconductor element having a memory function. 前記第１及び第２導熱路の少なくとも一方は、少なくとも一部が金属粉末と樹脂とを含む熱伝導性ペーストから形成されている請求項１に記載の半導体素子実装構造体。   2. The semiconductor element mounting structure according to claim 1, wherein at least one of the first and second heat conduction paths is formed of a heat conductive paste including at least a part of a metal powder and a resin. 前記架橋導熱路の少なくとも一部は、金属粉末と樹脂とを含む熱伝導性ペーストから形成されている請求項２に記載の半導体素子実装構造体。

The semiconductor element mounting structure according to claim 2, wherein at least a part of the cross-linked heat conduction path is formed from a heat conductive paste containing a metal powder and a resin.

JP2005110188A 2004-05-21 2005-04-06 Semiconductor element mounting structure Withdrawn JP2006013439A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180002611A (en) * 2015-03-26 2018-01-08 에프코스 아게 Carrier for semiconductor device with passive cooling function
CN111613586A (en) * 2019-02-26 2020-09-01 罗姆股份有限公司 Electronic device and method for manufacturing electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180002611A (en) * 2015-03-26 2018-01-08 에프코스 아게 Carrier for semiconductor device with passive cooling function
KR102350223B1 (en) 2015-03-26 2022-01-14 티디케이 일렉트로닉스 아게 Carrier for semiconductor devices with passive cooling function
CN111613586A (en) * 2019-02-26 2020-09-01 罗姆股份有限公司 Electronic device and method for manufacturing electronic device
CN111613586B (en) * 2019-02-26 2024-03-12 罗姆股份有限公司 Electronic device and method for manufacturing electronic device

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