JP2005535135A - Method for manufacturing an electrical substrate frame, method for manufacturing a surface mountable semiconductor device and substrate frame strip - Google Patents
Method for manufacturing an electrical substrate frame, method for manufacturing a surface mountable semiconductor device and substrate frame strip Download PDFInfo
- Publication number
- JP2005535135A JP2005535135A JP2004526605A JP2004526605A JP2005535135A JP 2005535135 A JP2005535135 A JP 2005535135A JP 2004526605 A JP2004526605 A JP 2004526605A JP 2004526605 A JP2004526605 A JP 2004526605A JP 2005535135 A JP2005535135 A JP 2005535135A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- connection
- chip
- window
- plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 100
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims description 89
- 239000004020 conductor Substances 0.000 claims abstract description 149
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 239000002131 composite material Substances 0.000 claims abstract description 6
- 229920003023 plastic Polymers 0.000 claims description 51
- 239000004033 plastic Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 44
- 239000011248 coating agent Substances 0.000 claims description 36
- 238000000576 coating method Methods 0.000 claims description 36
- 238000002347 injection Methods 0.000 claims description 34
- 239000007924 injection Substances 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 230000005855 radiation Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002985 plastic film Substances 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 6
- 239000000178 monomer Substances 0.000 claims description 4
- 230000007261 regionalization Effects 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 115
- 238000001746 injection moulding Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 235000019219 chocolate Nutrition 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- SYJRVVFAAIUVDH-UHFFFAOYSA-N ipa isopropanol Chemical compound CC(C)O.CC(C)O SYJRVVFAAIUVDH-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本発明は、殊に発光ダイオード素子用の電気的な基板フレーム(10)の製造のための方法であって、電気的な第1及び第2の少なくとも1つの接続導体(2,3)を備えるものに関する。該方法は次のような工程を有しており:
a)電気絶縁性の支持体層(101)及び導電性の接続導体層(102)から成る層複合体の成形、
b)支持体層(101)のパターン形成、これによって該支持体層に接続導体層(102)への少なくとも1つの接触窓(7)を成形し、
c)接続導体層(102)のパターン形成、これによって電気的な第1及び第2の接続導体(2,3)を成形し、該接続導体のうちの少なくとも1つは接触窓(7)を通して電気的に接続可能になっている。本発明はさらに、接続導体層及び接続支持体層を備えた基板フレームストリップに関し、基板フレームストリップに、複数の素子領域を含む1つの区画が形成されており、この場合に接続導体層は隣接のそれぞれ2つの素子領域間の切断線に沿って少なくとも部分的に除去されている。The invention is a method for the manufacture of an electrical substrate frame (10), in particular for light-emitting diode elements, comprising electrical first and second at least one connecting conductor (2, 3). About things. The method comprises the following steps:
a) Molding of a layer composite comprising an electrically insulating support layer (101) and a conductive connecting conductor layer (102),
b) patterning the support layer (101), thereby forming at least one contact window (7) to the connecting conductor layer (102) in the support layer;
c) patterning of the connection conductor layer (102), thereby shaping the electrical first and second connection conductors (2, 3), at least one of the connection conductors passing through the contact window (7) It can be connected electrically. The present invention further relates to a substrate frame strip provided with a connection conductor layer and a connection support layer, wherein the substrate frame strip is formed with one section including a plurality of element regions, in which case the connection conductor layer is adjacent to each other. Each is at least partially removed along the cutting line between the two device regions.
Description
本発明は、電気的な基板フレームの製造、殊に表面実装可能な半導体素子用の電気的な基板フレームの製造のための方法であって、1つの半導体チップ、該半導体チップの電気的な少なくとも2つの接点に導電的に接続された外部の電気的な少なくとも2つの接続部、及びチップ被覆体を備えるものに関する。本発明はさらに、表面実装可能な半導体素子の製造のための方法及び基板フレームストリップに関する。 The invention relates to a method for the manufacture of an electrical substrate frame, in particular for the manufacture of an electrical substrate frame for a surface-mountable semiconductor element, comprising one semiconductor chip, the electrical at least of the semiconductor chip. The present invention relates to an external electrical at least two connection parts electrically connected to two contact points and a chip covering body. The invention further relates to a method and a substrate frame strip for the manufacture of surface-mountable semiconductor elements.
使用領域の拡大及び製造コストの削減のために、半導体構成部分若しくは半導体素子をより小さい寸法で構成することが試みられている。例えば携帯電話機のキーのバックライトのために極めて小さいルミネセンスダイオードを必要としている。 In order to expand the area of use and reduce manufacturing costs, attempts have been made to configure semiconductor components or semiconductor elements with smaller dimensions. For example, a very small luminescence diode is required for the backlight of a cellular phone key.
これまでに、寸法0402(これは0.5mm×1.0mmに相当する)の設置面積及び400μm乃至600μmの構成高さのルミネセンスダイオード・ケーシングは使用されるようになっている。例として、構造形式QTLP690C-xのFAIRCHILD SEMICONDUCTOR(R)のデーターシートを参照できる。対応する構成コンセプトは米国特許4843280号明細書に記載してある。 To date, luminescent diode casings with a footprint of size 0402 (which corresponds to 0.5 mm × 1.0 mm) and a height of 400 μm to 600 μm have been used. As an example, reference can be made to the FAIRCHILD SEMICONDUCTOR (R) data sheet in the structure format QTLP690C-x. A corresponding construction concept is described in US Pat. No. 4,843,280.
構成高さの更なるダウンサイズを望まれているものの、従来のケーシング構成では極めて困難である。 Although further downsizing of the construction height is desired, it is extremely difficult with the conventional casing construction.
本発明の課題は、表面実装可能な半導体素子、殊に表面実装可能な極小ルミネセンスダイオード素子及び/又はフォトダイオード素子のための構成を提供して、構成寸法、特に構成高さのさらなる縮小を可能にすることである。 The object of the present invention is to provide a structure for a surface-mountable semiconductor element, in particular a surface-mountable minimal luminescence diode element and / or a photodiode element, to further reduce the dimensions, in particular the height of the structure. Is to make it possible.
前記課題が、請求項1に記載の特徴を有する方法によって解決される。表面実装可能な半導体素子の製造のための方法は、請求項18若しくは請求項20に記載してある。基板フレームの有利な構成は請求項36に記載してある。
The object is solved by a method having the features of
前記方法及び基板フレームの有利な実施態様を従属請求項に記載してある。 Advantageous embodiments of the method and the substrate frame are described in the dependent claims.
前記方法においてはまず、電気絶縁性の支持体層及び導電性の接続導体層を備えるラミネートを成形する。ラミネートは有利にはもっぱら前記両方の層からのみ成っている。両方の層は全くパターン形成されておらず、例えば接着剤層によって互いに結合されていてよい。続く工程で、ラミネートの各素子層において支持体層に接続導体層への少なくとも1つの接触窓を成形し、かつ接続導体層に電気的な第1及び第2の少なくとも1つの接続導体を成形し、該接続導体のうちの少なくとも1つは接触窓を通して電気的に接続されるようになっている。 In the method, first, a laminate including an electrically insulating support layer and a conductive connecting conductor layer is formed. The laminate advantageously consists exclusively of both layers. Both layers are not patterned at all and may be bonded together, for example by an adhesive layer. In the subsequent step, at least one contact window to the connection conductor layer is formed on the support layer in each element layer of the laminate, and at least one electrical first and second connection conductors are formed on the connection conductor layer. , At least one of the connecting conductors is electrically connected through the contact window.
前述の基板フレームは素子ケーシングの、発光ダイオードチップの高さに比べて極めて低い高さを有する発光ダイオード素子に有利に適している。該基板フレームは、発光ダイオードが支持体層の接触窓内で熱伝導性の結合材、例えば導体接着剤若しくははんだを用いて直接に接続路に組み付けられる場合に発光ダイオードからの極めて良好な熱排出を可能にするものである。 The aforementioned substrate frame is advantageously suitable for light emitting diode elements having a very low height in the element casing relative to the height of the light emitting diode chip. The substrate frame provides a very good heat dissipation from the light emitting diodes when the light emitting diodes are assembled directly into the connection path using a thermally conductive bonding material, such as a conductive adhesive or solder, within the contact window of the support layer. Is possible.
支持体層のパターン形成は有利には、接続導体層のパターン形成の前に行われる。このような順序は逆にされてもよい。 The patterning of the support layer is advantageously performed before the patterning of the connecting conductor layer. Such an order may be reversed.
支持体層は有利には、マスキング及びエッチング技術によってパターン形成可能なプラスチック層、特にプラスチック・シート、特に有利にはポリイミドシートである。接続導体層は同じく有利には、マスキング及びエッチング技術によってパターン形成可能な導電性のシート、特に有利には金属シートである。支持体層及び接続導体層の厚さは80μmよりも小さく、殊に30μmと60μmとの間である。このような寸法規定は以下に述べるすべての実施態様にとっても当てはまる。 The support layer is preferably a plastic layer that can be patterned by masking and etching techniques, in particular a plastic sheet, particularly preferably a polyimide sheet. The connecting conductor layer is also preferably a conductive sheet that can be patterned by masking and etching techniques, particularly preferably a metal sheet. The thickness of the support layer and the connecting conductor layer is less than 80 μm, in particular between 30 μm and 60 μm. Such sizing is also true for all embodiments described below.
特に有利には、支持体層に第1の接続路への第1の接触窓、例えばチップ組み込み窓、並びに第2の接続路への第2の接触窓、例えば導線接続窓を成形するようになっている。 It is particularly advantageous to mold the support layer with a first contact window to the first connection path, for example a chip integration window, and a second contact window to the second connection path, for example a conductor connection window. It has become.
方法の特に有利な実施態様では支持体層は少なくとも、パターン形成すべき領域で有利には溶解可能なプラスチック層から成っている。支持体層は接触窓の面を除いて、かつ必要に応じて後で除去すべき領域も除いて有利には硬化によって溶解不能にされている。このことは、支持体層がほかの領域で溶解剤に対して耐性にされていることを意味している。 In a particularly advantageous embodiment of the method, the support layer comprises at least a plastic layer that is preferably soluble in the area to be patterned. The support layer is preferably rendered insoluble by curing, except for the face of the contact window and, if necessary, the areas to be removed later. This means that the support layer is made resistant to the solubilizer in other areas.
プラスチック層のパターン形成のために、まずプラスチック層上にマスク層、殊にフォトレジスト層を施すようになっている。マスク層は、接触窓の領域及び後で除去すべき別の領域がマスク層によって遮蔽されるようにパターン形成され、若しくはパターン形成して被着される。続いてプラスチック層は接続導体層に残すべき領域を硬化され、次いで少なくとも接触窓の領域でフォトレジスト層及びその下にあるプラスチック層は接続導体層から除去される。硬化されていないプラスチック層は有利には溶融によって接続導体層から除去される。 For patterning the plastic layer, a mask layer, in particular a photoresist layer, is first applied on the plastic layer. The mask layer is patterned or patterned and deposited such that the area of the contact window and other areas to be removed later are shielded by the mask layer. Subsequently, the plastic layer is cured in the areas to be left in the connecting conductor layer, and then the photoresist layer and the underlying plastic layer are removed from the connecting conductor layer at least in the area of the contact window. The uncured plastic layer is advantageously removed from the connecting conductor layer by melting.
方法の別の有利な実施態様ではプラスチック層のパターン形成のために、まずプラスチック層の上にフォトマスクを配置し、該フォトマスクは接触窓の領域を遮蔽するようになっている。続いてプラスチック層は、接続導体層に残すべき遮蔽されていない領域を硬化される。このためにプラスチック層は有利にはUV・放射(UV・ビーム)によって硬化される。これにとって有利には、ポリイミド・モノマーを含む材料が適している。別の例として、熱放射によって硬化可能なプラスチック層を用いてよい。次いでフォトマスク層は外されて、プラスチック層は接触窓の領域で接続導体層から除去される。このことは有利には湿式の化学的な溶解によって行われる。別の例として、プラズマ焼失除去も可能である。 In another advantageous embodiment of the method, for patterning the plastic layer, a photomask is first placed on the plastic layer, the photomask being adapted to shield the area of the contact window. The plastic layer is then cured in the unshielded areas that should remain in the connecting conductor layer. For this purpose, the plastic layer is preferably cured by UV radiation (UV beam). For this, materials containing polyimide monomers are suitable. As another example, a plastic layer curable by thermal radiation may be used. The photomask layer is then removed and the plastic layer is removed from the connecting conductor layer in the area of the contact window. This is preferably done by wet chemical dissolution. As another example, plasma burnout removal is also possible.
接続導体層は同じく有利にはマスクを用いかつ湿式の化学的なエッチング法によってパターン形成される。例えば金属層のためのこの種のパターン形成法は基板技術において公知であり、本発明の方法にも有利に用いられる。 The connecting conductor layer is also advantageously patterned using a mask and by wet chemical etching. Such patterning methods, for example for metal layers, are known in the substrate art and are advantageously used in the method of the invention.
複数の素子区分若しくは構成エレメント区分を備えた基板フレームストリップの製造のための方法においては、有利には接続導体層としての金属シート及び支持体層としてのポリイミドシートから成る1つのラミネートストリップに、前述の方法によって、複数の接触窓及び該接触窓に対応して配置(対応配置)された電気的な接続路を成形するようになっている。接触窓は接続路まで達している。接触窓及び該接触窓に対応配置された接続路から成る各グループは、ラミネートストリップ上の並べて配置された複数の素子区分から成る1つの区画(フィールド[field])においてそれぞれ1つの素子区分内に配置されている。 In a method for the production of a substrate frame strip with a plurality of element sections or component element sections, it is advantageous to combine a metal sheet as a connecting conductor layer and a polyimide sheet as a support layer into one laminate strip. By this method, a plurality of contact windows and electrical connection paths arranged corresponding to the contact windows are formed. The contact window reaches the connection path. Each group of contact windows and connection paths arranged corresponding to the contact windows is within one element section in one field (field) consisting of a plurality of element sections arranged side by side on the laminate strip. Is arranged.
特に有利な実施態様では、接続導体層は隣接の各2つの素子領域間の切断線(分割線)に沿って部分的に除去される。このような手段は、切断線に沿って例えばのこぎり加工(ソーイング)若しくは打ち抜きによって行われるラミネートストリップの分割切断を容易にして有利である。 In a particularly advantageous embodiment, the connecting conductor layer is partly removed along a cutting line (partition line) between each two adjacent element regions. Such a means is advantageous for facilitating the divisional cutting of the laminate strip which is carried out along the cutting line, for example by sawing or stamping.
本発明に基づく方法は特に有利には、少なくとも1つの半導体チップ、半導体チップの電気的な各接点に接続された外部の電気的な少なくとも2つの接続導体並びに、半導体チップの被覆若しくは封止のためのプラスチックケーシングを備える表面実装可能な半導体素子の製造のために適している。 The method according to the invention is particularly advantageous for at least one semiconductor chip, at least two external electrical connection conductors connected to electrical contacts of the semiconductor chip, and for covering or sealing the semiconductor chip. Suitable for the production of surface-mountable semiconductor elements with a plastic casing.
この場合に第1の実施態様では、まず導電性の接続導体層に電気絶縁性の支持体層を施すようになっている。次いで支持体層に少なくとも1つのチップ窓及び少なくとも1つの導線接続窓をパターン形成し、かつ接続導体層に外部の電気的な少なくとも2つの接続導体をパターン形成するようになっている。チップ窓内には後から半導体チップを組み込み、半導体チップの電気的な少なくとも1つの接点は、ボンディングワイヤによって導線接続窓を介して1つの接続導体に電気的に接続される。続いて、パターン形成された接続導体層、パターン形成された支持体層、半導体チップ及びボンディングワイヤから成るユニット(結合体)は射出成形金型内に装着され、射出成形金型内で半導体チップはボンディングワイヤも含めて被覆材料で射出成形被覆され、次いで被覆材料は少なくとも部分的に硬化される。 In this case, in the first embodiment, an electrically insulating support layer is first applied to the conductive connecting conductor layer. The support layer is then patterned with at least one chip window and at least one conductor connection window, and the connection conductor layer is patterned with at least two external electrical connection conductors. A semiconductor chip is later incorporated into the chip window, and at least one electrical contact of the semiconductor chip is electrically connected to one connection conductor via a conductor connection window by a bonding wire. Subsequently, a unit (combined body) composed of a patterned connection conductor layer, a patterned support layer, a semiconductor chip and a bonding wire is mounted in an injection mold, and the semiconductor chip is placed in the injection mold. The coating material, including bonding wires, is injection molded with the coating material, and then the coating material is at least partially cured.
複数の半導体素子の同時的な製造のための方法では、接続導体層及び支持体層から成るラミネートストリップに、それぞれ複数の素子領域(素子区分)から成る区画を形成するようになっており、区画内において各素子領域はそれぞれ少なくとも1つのチップ窓、少なくとも1つの導線接続窓及び外部の電気的な少なくとも2つの接続導体を有している。半導体チップは各チップ窓内に組み込まれる。次いで、半導体チップの電気的な接点はそれぞれボンディングワイヤを用いて導線接続窓を通して外部の電気的な接続導体に接続される。区画は個別に順次に若しくはグループ毎に順次に1つの射出成形金型内に装着され、この場合に射出成形金型はそれぞれ1つの区画にとって、該区画のすべての素子領域に亘って広がっていてかつほぼもっぱら半導体チップの側で中空室を形成する唯一のキャビティーを有している。キャビティー内に被覆材料を射出し、被覆材料はそこで少なくとも部分的に硬化される。次いで区画は射出成形金型から取り出されて、被覆材料及び支持体層、並びに必要に応じて接続導体層の分割切断によって、互いに分離された半導体素子に個別化(分割)される。 In the method for the simultaneous production of a plurality of semiconductor elements, sections each composed of a plurality of element regions (element sections) are formed on a laminate strip composed of a connection conductor layer and a support layer. Each element region has at least one chip window, at least one conductor connection window and at least two external electrical connection conductors. The semiconductor chip is incorporated in each chip window. Next, the electrical contacts of the semiconductor chip are each connected to an external electrical connection conductor through a conductor connection window using bonding wires. The compartments are mounted individually or sequentially in groups in one injection mold, in which case the injection molds for each compartment extend over the entire element area of the compartment. And it has a single cavity that forms a hollow chamber almost exclusively on the side of the semiconductor chip. The coating material is injected into the cavity where it is at least partially cured. The compartments are then removed from the injection mold and individualized (divided) into separate semiconductor elements by splitting the coating material and the support layer and, if necessary, the connecting conductor layer.
第2の実施態様では、同じくまず導電性の接続導体層に電気絶縁性の支持体層を施すようになっている。次いで支持体層に少なくとも1つのチップ窓を成形しかつ接続導体層に外部の電気的な少なくとも2つの接続導体を成形し、接続導体はチップ窓と部分的にオーバーラップしている。このような構成は例えば、電気的な少なくとも2つの接続導体を同一の側に配置されてなる半導体チップに適している。このようなチップはチップ窓内で接点と一緒に接続導体上に組み付けられて電気的に接続される。このようにして、パターン形成された接続導体層、パターン形成された支持体層及び半導体チップから成るユニットは続いて射出成形金型内に装着され、射出成形金型内で半導体チップは被覆材料によって射出成形被覆され、該被覆材料は続いて少なくとも部分的に硬化される。 In the second embodiment, an electrically insulating support layer is first applied to the conductive connecting conductor layer. Then, at least one chip window is formed on the support layer and at least two external electrical connection conductors are formed on the connection conductor layer, the connection conductor partially overlapping the chip window. Such a configuration is suitable, for example, for a semiconductor chip in which at least two electrical connection conductors are arranged on the same side. Such a chip is assembled on the connection conductor together with the contacts in the chip window to be electrically connected. In this way, the unit comprising the patterned connection conductor layer, the patterned support layer and the semiconductor chip is subsequently mounted in an injection mold, in which the semiconductor chip is covered by the coating material. It is injection molded coated and the coating material is subsequently at least partially cured.
複数の半導体素子の同時的な製造のための方法においては、接続導体層及び支持体層から成るラミネートストリップに、それぞれ複数の素子領域から成る複数の区画を形成し、この場合に各区画において各素子領域は、それぞれ少なくとも1つのチップ窓及び外部の電気的な少なくとも2つの接続導体を有している。次いで前述の方法と同様に各チップ窓内にそれぞれ少なくとも1つの半導体チップを組み込む。区画の射出成形被覆及び個別化は、前述の方法と同じ形式で行われる。 In the method for simultaneous manufacture of a plurality of semiconductor elements, a plurality of sections each including a plurality of element regions are formed on a laminate strip composed of a connecting conductor layer and a support layer, and in this case, each section is divided into each section. Each element region has at least one chip window and at least two external electrical connection conductors. Next, at least one semiconductor chip is incorporated in each chip window in the same manner as described above. The injection molding coating and individualization of the compartments takes place in the same manner as described above.
本発明に基づく該方法は、基板フレーム上に発光ダイオードを組み付けてなる発光ダイオード素子の製造に特に適している。 The method according to the invention is particularly suitable for the production of light-emitting diode elements comprising a light-emitting diode assembled on a substrate frame.
接続導体層(有利にはパターン形成された金属シートから成る)及び支持体層(有利にはパターン形成されたプラスチックシートから成る)を備えていて区画(該区画内に複数の素子領域が設けられている)を成形されている基板フレームストリップにおいて、接続導体層は隣接のそれぞれ2つの素子領域間の切断線に沿って少なくとも部分的に除去されている。接続導体層の切断線に沿った除去は、区画の射出成形被覆の後の基板フレームの分割切断(個別化)を容易にする。 A connecting conductor layer (preferably consisting of a patterned metal sheet) and a support layer (preferably consisting of a patterned plastic sheet) are provided with a compartment (in which a plurality of device regions are provided). The connecting conductor layer is at least partially removed along the cutting line between each two adjacent element regions. The removal of the connecting conductor layer along the cutting line facilitates the split cutting (individualization) of the substrate frame after the injection molding coating of the compartments.
接触窓は、チップ組み付け及び導線敷設位置の調節の際の容易な監視を可能にする。チップ組み付け位置及び/又は導線敷設位置の不当に大きな誤差は迅速に識別可能であり、それというのは半導体チップ若しくは接続導線は組み付けの後に接触窓の縁部に載っている場合にはシートに付着しないからである。このことは構成寸法を小さくすればするほど重要であり、それというのは一面で素子の信頼性は、チップ封体の容積を小さくすればするほどチップ組み付けの調節誤差によって大きく損なわれ、かつ他面で調節誤差を直ちに識別できない場合の不良品量は素子の高いパッケージ密度ひいては基板フレーム帯材の単位長さ当たりに形成される素子の数量の大きいことに基づき極めて大きくなるからである。 The contact window allows for easy monitoring during chip assembly and conductor laying position adjustment. Unreasonably large errors in the chip assembly position and / or conductor laying position can be quickly identified because the semiconductor chip or connecting conductor adheres to the sheet if it is on the edge of the contact window after assembly. Because it does not. This is more important as the component size is smaller, because the reliability of the device is greatly impaired by the adjustment error of the chip assembly as the volume of the chip envelope is reduced. This is because the amount of defective products in the case where the adjustment error cannot be immediately identified on the surface becomes extremely large due to the high package density of the elements and the large number of elements formed per unit length of the substrate frame strip.
本発明の有利なさらなる構成は図示の実施例に関連して説明する。 Advantageous further configurations of the invention are described in connection with the illustrated embodiment.
図1は、本発明の方法に基づき成形された半導体素子の第1の実施例の概略断面図であり、
図2は、本発明の方法に基づき成形された半導体素子の第2の実施例の概略断面図であり、
図3a乃至図3fは、本発明に基づく方法の1つの実施例の工程経過を示す概略図であり、
図4a乃至図4eは、本発明に基づく方法の別の実施例の工程経過を示す概略図であり、
図5a及び図5bは、本発明に基づく基板フレームの概略的な下面図及び概略的な平面図であり、
図6a及び図6bは、射出成形被覆された半導体チップを備える基板フレームストリップの一部分の概略的な平面図及び概略的な下面図であり、
図7は、基板フレームストリップの装着されている射出成形金型の部分的な概略断面図であり、
図8は、射出成形被覆された半導体チップを備えた基板フレームストリップの部分的な概略断面図である。
FIG. 1 is a schematic cross-sectional view of a first embodiment of a semiconductor device formed according to the method of the present invention,
FIG. 2 is a schematic cross-sectional view of a second embodiment of a semiconductor device molded according to the method of the present invention,
Figures 3a to 3f are schematic diagrams showing the process steps of one embodiment of the method according to the invention,
Figures 4a to 4e are schematic diagrams showing the process sequence of another embodiment of the method according to the invention,
5a and 5b are a schematic bottom view and schematic plan view of a substrate frame according to the present invention,
6a and 6b are a schematic plan view and a schematic bottom view of a portion of a substrate frame strip comprising an injection molded coated semiconductor chip;
FIG. 7 is a partial schematic cross-sectional view of an injection mold on which a substrate frame strip is mounted,
FIG. 8 is a partial schematic cross-sectional view of a substrate frame strip with an injection molded coated semiconductor chip.
図示の実施例で同じ機能の構成部分(構成要素)には同じ符号を付けてある。 In the illustrated embodiment, components (components) having the same function are denoted by the same reference numerals.
図1若しくは図2に示す表面実装可能な半導体素子、例えば例として光を発する半導体素子のための基板フレーム10の製造方法は、通常は次のような工程を有しており、即ち
a)電気絶縁性の支持体層101及び導電性の接続導体層102(これに適した材料は、例えば銅及び銅合金)から成る層複合体の製造、支持体層は有利にはポリイミド若しくは、ポリイミド含有の材料から成るプラスチック・シートである(図3a及び図4a)、
b)マスク及びエッチングによる支持体層101のパターン形成、この場合、支持体層内に第1の接触窓7及び第2の接触窓8を形成して、該接触窓は後の第1の接続導体2及び第2の接続導体3に通じ(図3b〜図3d及び図4b〜図4c)、
c)マスク及びエッチングによる接続導体層102のパターン形成、この場合、第1の電気的な接続導体2及び第2の電気的な接続導体3を形成して、該接続導体は第1の接触窓7若しくは第2の接触窓8を介して電気的に接続可能であり(図3e〜図3f及び図4d〜図4e)
工程c)は変化例として工程b)の前に行われてよい。接続支持体層101の厚さは30μm乃至60μmであり、このことは接続導体層102の厚さにも当てはまる。
The manufacturing method of the
b) Patterning of the
c) Pattern formation of the
Step c) may be performed before step b) as a variant. The thickness of the
支持体層101はパターン形成の前には少なくともパターン形成すべき領域をまだ硬化されておらずに、適当な溶剤によって除去可能であり、接触窓7,8の面を除いてかつ必要に応じて後でさらに除去すべき残りの領域を除いて溶解の前に硬化される。支持体層の硬化されていない領域は後で除去される。
Prior to pattern formation, the
プラスチック層のパターン形成のために、まずプラスチック層上にフォトレジスト層103を形成し(図3b)、フォトレジスト層は公知の方法でパターン形成されて、接触窓7,8の領域70,80はフォトレジスト層103によって被覆されている(図3c)。プラスチック層は、被覆されていない領域を有利にはUV・放射105によって硬化される(図3c)。続いて領域70,80でフォトレジスト層103及び該層の下側にあるプラスチック層は接続導体層102から離される。このための適当な溶剤は、例えばIPA(Isopropanol イソプロパノール)やアセトンである。
In order to pattern the plastic layer, first, a
プラスチック層のパターン形成のために異なる例では、まずプラスチック層の上にフォトマスク104を配置して、フォトマスクは接触窓7,8の領域70,80を遮蔽している(図4b)。次いでプラスチック層は、接続導体層102上に残されるべき領域を有利にはUV・放射105によって硬化される(図4b)。続いてフォトマスク104は取り除かれて、接触窓7,8の領域70,80でプラスチック層は適当な溶剤106を用いて接続導体層102からエッチング除去される(図4c)。
In a different example for patterning the plastic layer, a
複数の素子領域を有する導体フレームストリップ200を製造する方法では、各素子領域に前述の方法によって少なくとも1つの接触窓7及び少なくとも2つの接続導体2,3を成形するようになっている。
In the method of manufacturing the
隣接する各2つの素子領域間の切断線110に沿って接続導体層は有利には、接続導体層の除去された切欠き111,112を有している(図5a及び図6b)。
The connection conductor layer advantageously has
図1に示すように少なくとも1つの発光ダイオードチップ1若しくはレーザーダイオードチップ、該半導体チップ1の少なくとも2つの接点4,5に接続された少なくとも2つの接続導体2,3並びに、接続支持体9及びチップ被覆体6から成るチップケーシング11を備えた発光性の表面実装可能な構成素子の製造のための1つの方法では、
a)接続導体層102上に支持体層101を形成し、次いで支持体層101内に少なくとも1つのチップ窓7及び少なくとも1つの導線窓8をパターン形成しかつ接続導体層102内に外部の電気的な接続導体2,3をパターン形成し;
b)半導体チップ1をチップ窓7内に組み込み;
c)半導体チップ1の少なくとも1つの電気的な接点5を、ボンディングワイヤ50によって導線窓8を介して接続導体3に電気的に接続し;
d)パターン形成された接続導体層102、パターン形成された支持体層101、半導体チップ1及びボンディングワイヤ50から成るユニットを射出成形金型内に装着し、
e)半導体チップ1をボンディングワイヤ50と一緒に被覆材料6によって射出成形被覆し、次いで被覆材料を少なくとも部分的に硬化する。
As shown in FIG. 1, at least one light-emitting
a) A
b) incorporating the
c) at least one
d) A unit comprising the patterned
e) The
この種の構成素子の大量生産のためには、接続導体層102及び支持体層101から成る積層ストリップ内に、それぞれ少なくとも1つのチップ窓7、少なくとも1つの導線接続窓8及び少なくとも2つの接続導体2,3から成る複数の素子領域202を備えた区画201が成形される(図6a及び図6b、参照)。半導体チップ1をチップ窓7内に組み込みかつ半導体チップ1と接続導体2,3とを電気的に接続した後に、各区画(フィールド)は射出成形金型500(図7)内に装着されるようになっており、射出成形金型は、各区画201にとって該各1つの区画201のすべての素子領域202に亘って広がっていてかつもっぱら半導体チップ1の側で空間を成すそれぞれ唯一のキャビティー501を有している。被覆材料60をキャビティー501内に射出しかつ少なくとも部分的に硬化させた後に、区画201は射出成形金型500から取り出されて、被覆材料60及び支持体層101の分割によって、互いに分離された半導体素子に個別化される。
For mass production of this type of component, at least one
少なくとも1つの発光ダイオードチップ1若しくはレーザーダイオードチップ1、該半導体チップ1の電気的な少なくとも2つの接点4,5に接続された少なくとも2つの接続導体2,3及び、接続支持体9及びチップ被覆体6から成るチップケーシング11を備えた図2に示す自発光式の表面実装可能な素子の製造のための方法は、前述の方法に対してもっぱら次のことによって異なっており、即ち、各素子領域は1つのチップ窓のみを有し、導線接続窓を有しておらず、チップ1は反転されてチップ窓7内で、光の放出されるエピタキシャル側を接続導体2,3に向けて該接続導体上に組み付けられる。電気的な両方の接点4,5はチップ1の同じ側に存在している。接点4は接続導体2に接触し、かつ接点5は接続導体3に接触している。
At least one light-emitting
支持体層は、前に述べてあるように有利にはUV・放射(UV・照射)によって硬化可能である。別の例として支持体層は熱放射によって硬化可能であってよい。支持体層は有利にはポリイミド・モノマーから成っている。 The support layer is preferably curable by UV-radiation (UV-irradiation), as mentioned previously. As another example, the support layer may be curable by thermal radiation. The support layer preferably consists of a polyimide monomer.
本発明に基づく方法は有利には、電磁的なビームを放出及び/又は受け取る1つ若しくは複数の半導体チップを含む構成素子の製造のために適している。該方法は特に、寸法0402(0.5mm×1.0mmに相当)若しくはそれより小さくかつ高さ400μm、特に350μm以下のケーシング形状を有するルミネセンスダイオード・素子の製造に適している。 The method according to the invention is advantageously suitable for the manufacture of components comprising one or more semiconductor chips that emit and / or receive electromagnetic beams. The method is particularly suitable for the manufacture of luminescent diodes / elements having a casing shape of dimension 0402 (corresponding to 0.5 mm × 1.0 mm) or smaller and a height of 400 μm, in particular 350 μm or less.
光電式の構成素子においては、チップ被覆体若しくはチップ封止体は、電磁ビームを透過させる材料から、発光の場合に特に透明若しくは半透明な材料から形成される。有利な被覆材料は透明なプラスチック材料である。このような材料は知られているので、詳細は省略する。 In the photoelectric component, the chip covering body or the chip sealing body is formed from a material that transmits an electromagnetic beam, and from a transparent or translucent material particularly in the case of light emission. An advantageous coating material is a transparent plastic material. Since such materials are known, details are omitted.
混合色の光を放出するルミネセンスダイオード素子の製造のためには、チップ被覆体は発光物質を混合されており、発光物質はルミネセンスダイオードチップから放出された電磁ビームの少なくとも一部分を吸収して、次いで異なる波長及び色の電磁ビームを放出する。 For the manufacture of luminescent diode elements that emit light of mixed colors, the chip covering is mixed with a luminescent material that absorbs at least a portion of the electromagnetic beam emitted from the luminescent diode chip. And then emitting electromagnetic beams of different wavelengths and colors.
キャビティー内への被覆材料の射出は有利には側面からスリットノズルを介して行われる。被覆材料を少なくとも部分的に硬化させた後に、区画は射出成形金型から取り出されて、素子領域間でチップ被覆材料及び基板フレームを分割することによって個別の半導体素子に個別化される。 Injection of the coating material into the cavity is preferably effected from the side via a slit nozzle. After at least partially curing the coating material, the compartment is removed from the injection mold and individualized into individual semiconductor devices by dividing the chip coating material and the substrate frame between the device regions.
チップ被覆は有利には半導体チップ上及び必要に応じて1つ若しくは複数のボンディング線上の中央領域で、中央領域の周囲の縁部区分よりも大きな厚さで形成されている。このために、キャビティー501は、平面で見て各半導体チップ1と合致する、即ち覆い重なる複数の凹設部502を有している。これによって、被覆材料の体積は被覆材料の厚さを、許される領域、即ち縁部区分で、半導体チップの領域及び必要に応じて半導体チップへの1つ若しくは複数のボンディング線50の領域、即ち中央領域よりも小さくすることに基づき、減少されている。その結果、製造過程中に基板フレーム用積層板とチップ被覆との異なる熱膨張に起因する素子・区画の反りは避けられる。
The chip covering is preferably formed in the central region on the semiconductor chip and optionally on one or more bonding lines, with a thickness greater than the edge section around the central region. For this purpose, the
有利には区画の各1つの半導体チップ上にそれぞれ個別の1つの凹設部502を設けてあり、これによって被覆材料は射出成形の後に、並べて配置された複数の***部51を有し、即ち板チョコレートに類似の構造パターンを有している(図8、参照)。
Advantageously, there is a
区画の個別化は有利には、被覆材料及び基板フレームを***部51間の溝52で分割切断することによって行われる。
The individualization of the compartments is advantageously performed by dividing and cutting the coating material and the substrate frame at the grooves 52 between the
有利には射出成形金型500内への区画の装着の前に、基板フレーム上への被覆材料の付着の改善に役立つ付着媒体を支持体層101に塗布するとよい。このために、有利には上塗り用PIワニスを用いるとよい。
Advantageously, prior to mounting the compartments in the
個別化の後の半導体素子の技術的に簡単な取り扱いを目的として、基板フレームは射出成形金型内への装着の前に裏面に補助シート400を積層されてよい。補助シートは一面では接続導体2,3を機械的な損傷(引っ掻き)に対して保護し、かつ他面では接続導体を被覆材料の不都合な付着に対して、即ち基板フレームストリップの裏面への射出漏れに対して保護している。
For the purpose of technically simple handling of the semiconductor elements after individualization, the substrate frame may be laminated with an
補助シートは有利には、被覆材料と類似の熱膨張係数若しくは大きな熱膨張係数を有していて、区画の射出成形被覆の後に行われる被覆材料の硬化及び/又は冷却に際して被覆材料の、基板フレームよりも大きい収縮に起因して生じる区画の反りに抗して作用するようになっている。 The auxiliary sheet preferably has a coefficient of thermal expansion similar to or greater than that of the coating material, and the substrate frame of the coating material upon curing and / or cooling of the coating material after the injection molding coating of the compartment It acts against the warping of the compartment caused by greater contraction.
原理的に同じ目的で、ラミネートストリップは区画の外側に、異なる熱膨張及び/又は材料収縮に起因して生じる応力を減少させるために孔、貫通開口及び/又はスリットを有していてよい。 For the same purpose in principle, the laminate strip may have holes, through-openings and / or slits on the outside of the compartment in order to reduce the stresses caused by different thermal expansion and / or material shrinkage.
別の手段として若しくは付加的な手段として、反らせ形の射出成形金型を用いることも可能であり、該射出成形金型内では区画は、後で熱膨張係数の大きな材料を装填される側から見て凸面状に湾曲されている。 As another means or as an additional means, it is also possible to use a warped injection mold, in which the compartment is from the side which is subsequently loaded with a material having a high coefficient of thermal expansion. It is curved in a convex shape as seen.
半導体素子の電気的及び/又は光学的なテストを可能にするために、区画は個別化の前に被覆側にシートを被着され、次いで必要に応じて補助シートは基板フレームの裏面側から剥がされる。半導体素子の光学的な測定を必要とする場合には、シートは有利には電磁線を透過させるものであり、測定はシートを通して行われる。 To allow electrical and / or optical testing of the semiconductor elements, the compartments are coated with a sheet on the coated side prior to individualization, and then the auxiliary sheet is peeled off from the back side of the substrate frame if necessary. It is. If optical measurement of the semiconductor element is required, the sheet is preferably transparent to electromagnetic radiation and the measurement is performed through the sheet.
前述のすべての方法において、区画の個別化(分割切断)は有利には、鋸切断、レーザー切断及び/又は水流ジェット切断によって行われる。 In all the above-mentioned methods, the individualization of the compartments (split cutting) is advantageously performed by saw cutting, laser cutting and / or water jet cutting.
本発明は図示の実施例に限定されるものではなく、本発明の前述の実施例並びに請求項に記載の各手段は、個別に用いて、若しくは適切に組み合わせて用いて実施され得るものである。 The present invention is not limited to the embodiments shown in the drawings, and each of the means described in the above embodiments and claims of the present invention can be implemented individually or in appropriate combination. .
2,3 接続導体、 4,5 接点、 6 チップ被覆体、 7,8 接触窓、 9 接続支持体、 10 基板フレーム、 51 ***部、 52 溝、 60 被覆体、 70,80 領域、 101 支持体層、 102 接続導体層、 103 フォトレジスト層、 104 フォトマスク、 110 切断線、 111,112 切欠き、 201 区画、 202 素子領域、 400 補助シート、 500 射出成形金型、 501 キャビティー 2, 3 connection conductors, 4, 5 contacts, 6 chip cover, 7, 8 contact window, 9 connection support, 10 substrate frame, 51 raised portion, 52 groove, 60 cover, 70, 80 region, 101 support Layer, 102 connecting conductor layer, 103 photoresist layer, 104 photomask, 110 cutting line, 111, 112 notch, 201 section, 202 element region, 400 auxiliary sheet, 500 injection mold, 501 cavity
Claims (41)
a)電気絶縁性の支持体層(101)及び導電性の接続導体層(102)から成る層複合体を成形する工程、
b)支持体層(101)をパターン形成して、該支持体層に接続導体層(102)への少なくとも1つの接触窓(7)を成形する工程、
c)接続導体層(102)をパターン形成して、電気的な第1の接続導体(2)及び電気的な第2の接続導体(3)を成形する工程を有し、該接続導体の少なくとも1つの接続導体は接触窓(7)を介して電気的に接続されるものであることを特徴とする、電気的な基板フレームの製造のための方法。 Method for the manufacture of an electrical substrate frame (10), in particular a method for the manufacture of an electrical substrate frame for a light-emitting diode element, wherein the electrical first and second at least one A connecting composite (2, 3) comprising the following steps: a) forming a layer composite comprising an electrically insulating support layer (101) and a conductive connecting conductor layer (102) Process,
b) patterning the support layer (101) and forming at least one contact window (7) to the connecting conductor layer (102) in the support layer;
c) patterning the connection conductor layer (102) to form an electrical first connection conductor (2) and an electrical second connection conductor (3), wherein at least one of the connection conductors A method for manufacturing an electrical substrate frame, characterized in that one connection conductor is electrically connected via a contact window (7).
a)まず導電性の接続導体層(102)に電気絶縁性の支持体層(101)を施し、次いで支持体層(101)に少なくとも1つのチップ窓(7)及び少なくとも1つの導線接続窓(8)をパターン形成し、かつ接続導体層(102)に外部の電気的な接続導体(2,3)をパターン形成し、
b)半導体チップ(1)をチップ窓(7)内に組み込み、
c)半導体チップ(1)の電気的な少なくとも1つの接点(5)を、ボンディングワイヤ(50)によって導線接続窓(8)を介して1つの接続導体(3)に電気的に接続し、
d)パターン形成された接続導体層(102)、パターン形成された支持体層(101)、半導体チップ(1)及びボンディングワイヤ(50)から成るユニットを射出成形金型内に装着し、
e)半導体チップ(1)をボンディングワイヤ(50)も含み被覆材料(6)で射出成形被覆して、次いで被覆材料を少なくとも部分的に硬化することを特徴とする、表面実装可能な半導体素子の製造のための方法。 A method for manufacturing a surface-mountable semiconductor device comprising at least one semiconductor chip (1) and an external electrical connection connected to at least two electrical contacts (4, 5) of the semiconductor chip (1) Comprising at least two connecting conductors (2, 3) and a chip casing (11) comprising a connection support (9) and a chip covering (6),
a) First, an electrically insulating support layer (101) is applied to the conductive connection conductor layer (102), and then the support layer (101) is provided with at least one chip window (7) and at least one conductor connection window ( 8) and pattern external electrical connection conductors (2, 3) on the connection conductor layer (102),
b) incorporating the semiconductor chip (1) into the chip window (7);
c) electrically connecting at least one electrical contact (5) of the semiconductor chip (1) to one connection conductor (3) via a wire connection window (8) by means of a bonding wire (50);
d) A unit comprising a patterned connection conductor layer (102), a patterned support layer (101), a semiconductor chip (1) and a bonding wire (50) is mounted in an injection mold,
e) a surface-mountable semiconductor element, characterized in that the semiconductor chip (1), including the bonding wires (50), is injection-molded with a coating material (6) and then the coating material is at least partially cured. Method for manufacturing.
a)まず導電性の接続導体層(102)に電気絶縁性の支持体層(101)を施し、次いで支持体層(101)に少なくとも1つのチップ窓(7)をパターン形成し、かつ接続導体層(102)に外部の電気的な接続導体(2,3)をパターン形成し、この場合に両方の接続導体(2,3)をチップ窓(7)と部分的にオーバーラップさせ、
b)半導体チップ(1)をチップ窓(7)内で接続導体(2,3)上に組み付けて、半導体チップ(1)の第1の接点(4)及び第2の接点(5)を電気的な接続導体のうちの第1の接続導体(2)若しくは第2の接続導体(3)に接触させかつ該接続導体と電気的に接続し、
c)パターン形成された接続導体層(102)、パターン形成された支持体層(101)及び半導体チップ(1)から成るユニットを射出成形金型(500)内に装着し、
d)半導体チップ(1)を被覆材料(6)で射出成形被覆して、次いで被覆材料を少なくとも部分的に硬化することを特徴とする、表面実装可能な半導体素子の製造のための方法。 A method for manufacturing a surface-mountable semiconductor element, comprising at least one semiconductor chip (1), an external electrical connection connected to at least two electrical contacts (4, 5) of the semiconductor chip (1) And at least two connecting conductors (2, 3) and a chip casing (11) comprising a connection support (9) and a chip covering (6),
a) First, an electrically insulating support layer (101) is applied to the conductive connection conductor layer (102), and then at least one chip window (7) is patterned on the support layer (101), and the connection conductor is formed. Pattern external electrical connection conductors (2, 3) in layer (102), in which case both connection conductors (2, 3) partially overlap the chip window (7);
b) The semiconductor chip (1) is assembled on the connection conductors (2, 3) in the chip window (7), and the first contact (4) and the second contact (5) of the semiconductor chip (1) are electrically connected. Contacting the first connection conductor (2) or the second connection conductor (3) of the electrical connection conductors and electrically connecting to the connection conductor;
c) A unit consisting of a patterned connection conductor layer (102), a patterned support layer (101) and a semiconductor chip (1) is mounted in an injection mold (500),
d) A method for the production of surface-mountable semiconductor elements, characterized in that the semiconductor chip (1) is injection-molded coated with a coating material (6) and then the coating material is at least partially cured.
工程a)で、接続導体層(102)及び支持体層(101)から成る複合体に、それぞれ少なくとも1つのチップ窓(7)、少なくとも1つの導線接続窓(8)及び外部の電気的な少なくとも2つの接続導体(2,3)の備えられた複数の素子領域(202)から成る1つの区画(201)を形成し、
工程b)及び工程c)で、複数の半導体チップ(1)をチップ窓(7)内に組み込み、かつ半導体チップ(1)の電気的な接点(5)をボンディングワイヤ(50)によって外部の電気的な接続導体(3)に接続し、
工程d)で、区画を1つの射出成形金型(500)内に装着し、射出成形金型内に、区画(201)全体にとって該区画(201)のすべての素子領域(202)に亘って広がっていてかつほぼもっぱら半導体チップ(1)の側で中空室を形成する唯一のキャビティー(501)を設けてあり、
工程e)で、被覆材料(60)をキャビティー(501)内に射出して、そこで少なくとも部分的に硬化させ、
続いて、区画(201)を射出成形金型(500)から取り出して、被覆材料(60)及び支持体層(101)の切断によって、互いに分離された半導体素子に個別化することを特徴とする、半導体素子の製造のための方法。 A method for simultaneously manufacturing a plurality of semiconductor devices according to the method of claim 19,
In step a), at least one chip window (7), at least one conductor connection window (8) and at least an external electrical connection are formed on the composite comprising the connection conductor layer (102) and the support layer (101), respectively. Forming a section (201) consisting of a plurality of element regions (202) provided with two connecting conductors (2, 3);
In step b) and step c), a plurality of semiconductor chips (1) are incorporated into the chip window (7), and the electrical contacts (5) of the semiconductor chip (1) are externally connected by bonding wires (50). Connected to a typical connecting conductor (3)
In step d), the compartment is mounted in one injection mold (500), and within the injection mold, the entire compartment (201) spans all element regions (202) of the compartment (201). A single cavity (501) is provided which is wide and forms a hollow chamber almost exclusively on the side of the semiconductor chip (1);
In step e), the coating material (60) is injected into the cavity (501) where it is at least partially cured;
Subsequently, the section (201) is taken out from the injection mold (500) and is separated into semiconductor elements separated from each other by cutting the coating material (60) and the support layer (101). A method for the manufacture of semiconductor devices.
工程a)で、接続導体層(102)及び支持体層(101)から成る複合体に、それぞれ少なくとも1つのチップ窓(7)及び外部の電気的な少なくとも2つの接続導体(2,3)の備えられた複数の素子領域(202)から成る1つの区画(201)を形成し、
工程b)で、複数の半導体チップ(1)をチップ窓(7)内に組み込み、かつ所属の接続導体(2,3)に接続し、
工程c)で、区画を1つの射出成形金型(500)内に装着し、射出成形金型内に、区画(201)全体にとって該区画(201)のすべての半導体チップ(1)に亘って広がっていてかつほぼもっぱら半導体チップ(1)の側で中空室を形成する唯一のキャビティー(501)を設けてあり、
工程d)で、被覆材料(60)をキャビティー(501)内に射出して、そこで少なくとも部分的に硬化させ、
続いて、区画(201)を射出成形金型(500)から取り出して、被覆材料(60)及び支持体層(101)の切断によって、互いに分離された半導体素子に個別化することを特徴とする、半導体素子の製造のための方法。 A method for simultaneously manufacturing a plurality of semiconductor devices based on the method of claim 20,
In step a), at least one chip window (7) and at least two external electrical connection conductors (2, 3) are applied to the composite comprising the connection conductor layer (102) and the support layer (101), respectively. Forming a section (201) comprising a plurality of element regions (202) provided;
In step b), a plurality of semiconductor chips (1) are assembled in the chip window (7) and connected to the associated connecting conductors (2, 3),
In step c), the compartment is mounted in one injection mold (500), and within the injection mold, the entire compartment (201) spans all the semiconductor chips (1) in the compartment (201). A single cavity (501) is provided which is wide and forms a hollow chamber almost exclusively on the side of the semiconductor chip (1);
In step d), the coating material (60) is injected into the cavity (501) where it is at least partially cured;
Subsequently, the section (201) is taken out from the injection mold (500) and is separated into semiconductor elements separated from each other by cutting the coating material (60) and the support layer (101). A method for the manufacture of semiconductor devices.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US40127302P | 2002-08-05 | 2002-08-05 | |
DE10306557A DE10306557A1 (en) | 2002-08-05 | 2003-02-17 | Method for producing an electrical lead frame, method for producing a surface-mountable semiconductor component and lead frame strips |
PCT/DE2003/002522 WO2004015769A1 (en) | 2002-08-05 | 2003-07-25 | Method for the production of an electrically-conducting frame, method for production of a surface mounting semiconductor component and conductor frame strips |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009238937A Division JP5436137B2 (en) | 2002-08-05 | 2009-10-16 | Light-emitting semiconductor device that can be surface-mounted |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005535135A true JP2005535135A (en) | 2005-11-17 |
JP4653484B2 JP4653484B2 (en) | 2011-03-16 |
Family
ID=31716618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004526605A Expired - Fee Related JP4653484B2 (en) | 2002-08-05 | 2003-07-25 | Method for manufacturing an electrical substrate frame, method for manufacturing a surface-mountable semiconductor device and method for manufacturing a semiconductor device |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1527479A1 (en) |
JP (1) | JP4653484B2 (en) |
CN (1) | CN100533723C (en) |
TW (1) | TWI221027B (en) |
WO (1) | WO2004015769A1 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010287893A (en) * | 2009-06-11 | 2010-12-24 | Lsi Corp | Electronic device package and method of manufacture |
JP2011003853A (en) * | 2009-06-22 | 2011-01-06 | Stanley Electric Co Ltd | Method for manufacturing light emitting apparatus, light emitting apparatus, and mounting base thereof |
JP2012039122A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2012039120A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2012039121A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2012507157A (en) * | 2008-10-28 | 2012-03-22 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Carrier for semiconductor component, semiconductor component and method for manufacturing carrier |
JP2014022705A (en) * | 2012-07-24 | 2014-02-03 | Citizen Holdings Co Ltd | Semiconductor light-emitting device and manufacturing method of the same |
JP2016029732A (en) * | 2015-10-09 | 2016-03-03 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin mold and manufacturing methods thereof |
US9490411B2 (en) * | 2008-09-03 | 2016-11-08 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
JP2017050570A (en) * | 2016-12-07 | 2017-03-09 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin molding, and manufacturing methods therefor |
JP2017201702A (en) * | 2017-06-21 | 2017-11-09 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin molding, and manufacturing methods therefor |
JP2018121084A (en) * | 2018-05-09 | 2018-08-02 | 日亜化学工業株式会社 | Light-emitting device and method for manufacturing light-emitting devices |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7402462B2 (en) * | 2005-07-12 | 2008-07-22 | Fairchild Semiconductor Corporation | Folded frame carrier for MOSFET BGA |
KR100632003B1 (en) * | 2005-08-08 | 2006-10-09 | 삼성전기주식회사 | Led package having recess in heat transfer part |
CN104576631B (en) * | 2014-12-05 | 2020-03-17 | 复旦大学 | Photoelectric detection integrated chip |
DE102017105235B4 (en) * | 2017-03-13 | 2022-06-02 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Device with reinforcing layer and method for manufacturing a device |
DE102017123175B4 (en) * | 2017-10-05 | 2024-02-22 | Infineon Technologies Ag | Semiconductor component and method for its production |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2178231A (en) * | 1985-07-22 | 1987-02-04 | Quick Turnaround Logic Limited | Tape automatic bonding or circuitry to an electrical component |
JPH08298345A (en) * | 1995-04-26 | 1996-11-12 | Shichizun Denshi:Kk | Chip type light emitting diode |
WO1999004367A1 (en) * | 1997-07-18 | 1999-01-28 | Dai Nippon Printing Co., Ltd. | Ic module, ic card, sealing resin for ic module, and method for manufacturing ic module |
JPH11126803A (en) * | 1997-10-24 | 1999-05-11 | Hitachi Cable Ltd | Manufacture of tab tape |
JP2001308385A (en) * | 2000-04-24 | 2001-11-02 | Nippon Sheet Glass Co Ltd | Self-scanning light-emitting device |
JP2001354938A (en) * | 2000-06-12 | 2001-12-25 | Toray Ind Inc | Adhesive composition for semiconductor device, and adhesive sheet prepared by using the composition, semiconductor-connecting substrate, and semiconductor device prepared by using the composition |
JP2002026192A (en) * | 2000-07-03 | 2002-01-25 | Dainippon Printing Co Ltd | Lead frame |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2663987B2 (en) * | 1989-08-28 | 1997-10-15 | 住友金属鉱山株式会社 | Method for manufacturing double-layer film carrier |
US5156716A (en) * | 1991-04-26 | 1992-10-20 | Olin Corporation | Process for the manufacture of a three layer tape for tape automated bonding |
JPH07506935A (en) * | 1992-11-17 | 1995-07-27 | 新光電気工業株式会社 | Lead frame and semiconductor device using it |
US5861235A (en) * | 1996-06-26 | 1999-01-19 | Dow Corning Asia, Ltd. | Ultraviolet-curable composition and method for patterning the cured product therefrom |
JP3901427B2 (en) * | 1999-05-27 | 2007-04-04 | 松下電器産業株式会社 | Electronic device, manufacturing method thereof, and manufacturing device thereof |
-
2003
- 2003-07-25 JP JP2004526605A patent/JP4653484B2/en not_active Expired - Fee Related
- 2003-07-25 WO PCT/DE2003/002522 patent/WO2004015769A1/en active Application Filing
- 2003-07-25 EP EP03783921A patent/EP1527479A1/en not_active Withdrawn
- 2003-07-25 CN CNB03818897XA patent/CN100533723C/en not_active Expired - Fee Related
- 2003-08-01 TW TW092121128A patent/TWI221027B/en not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2178231A (en) * | 1985-07-22 | 1987-02-04 | Quick Turnaround Logic Limited | Tape automatic bonding or circuitry to an electrical component |
JPH08298345A (en) * | 1995-04-26 | 1996-11-12 | Shichizun Denshi:Kk | Chip type light emitting diode |
WO1999004367A1 (en) * | 1997-07-18 | 1999-01-28 | Dai Nippon Printing Co., Ltd. | Ic module, ic card, sealing resin for ic module, and method for manufacturing ic module |
JPH11126803A (en) * | 1997-10-24 | 1999-05-11 | Hitachi Cable Ltd | Manufacture of tab tape |
JP2001308385A (en) * | 2000-04-24 | 2001-11-02 | Nippon Sheet Glass Co Ltd | Self-scanning light-emitting device |
JP2001354938A (en) * | 2000-06-12 | 2001-12-25 | Toray Ind Inc | Adhesive composition for semiconductor device, and adhesive sheet prepared by using the composition, semiconductor-connecting substrate, and semiconductor device prepared by using the composition |
JP2002026192A (en) * | 2000-07-03 | 2002-01-25 | Dainippon Printing Co Ltd | Lead frame |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11094854B2 (en) | 2008-09-03 | 2021-08-17 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10700241B2 (en) | 2008-09-03 | 2020-06-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10573789B2 (en) | 2008-09-03 | 2020-02-25 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10573788B2 (en) | 2008-09-03 | 2020-02-25 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US10115870B2 (en) | 2008-09-03 | 2018-10-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US9537071B2 (en) * | 2008-09-03 | 2017-01-03 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
US9490411B2 (en) * | 2008-09-03 | 2016-11-08 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
JP2012507157A (en) * | 2008-10-28 | 2012-03-22 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Carrier for semiconductor component, semiconductor component and method for manufacturing carrier |
US8629549B2 (en) | 2008-10-28 | 2014-01-14 | Osram Opto Semiconductors Gmbh | Carrier body for a semiconductor component, semiconductor component and method for producing a carrier body |
JP2010287893A (en) * | 2009-06-11 | 2010-12-24 | Lsi Corp | Electronic device package and method of manufacture |
JP2011003853A (en) * | 2009-06-22 | 2011-01-06 | Stanley Electric Co Ltd | Method for manufacturing light emitting apparatus, light emitting apparatus, and mounting base thereof |
US8703513B2 (en) | 2009-06-22 | 2014-04-22 | Stanley Electric Co., Ltd. | Method for manufacturing light emitting apparatus, light emitting apparatus, and mounting base thereof |
US9041013B2 (en) | 2010-08-09 | 2015-05-26 | LG Innotek., Ltd. | Light emitting device and lighing system having the same |
US8519426B2 (en) | 2010-08-09 | 2013-08-27 | Lg Innotek Co., Ltd. | Light emitting device and lighting system having the same |
US8519427B2 (en) | 2010-08-09 | 2013-08-27 | Lg Innotek Co., Ltd. | Light emitting device and lighting system |
US8399904B2 (en) | 2010-08-09 | 2013-03-19 | Lg Innotek Co., Ltd. | Light emitting device and lighting system having the same |
JP2012039121A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2012039120A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2012039122A (en) * | 2010-08-09 | 2012-02-23 | Lg Innotek Co Ltd | Light emitting element |
JP2014022705A (en) * | 2012-07-24 | 2014-02-03 | Citizen Holdings Co Ltd | Semiconductor light-emitting device and manufacturing method of the same |
JP2016029732A (en) * | 2015-10-09 | 2016-03-03 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin mold and manufacturing methods thereof |
JP2017050570A (en) * | 2016-12-07 | 2017-03-09 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin molding, and manufacturing methods therefor |
JP2017201702A (en) * | 2017-06-21 | 2017-11-09 | 日亜化学工業株式会社 | Light-emitting device, resin package, resin molding, and manufacturing methods therefor |
JP2018121084A (en) * | 2018-05-09 | 2018-08-02 | 日亜化学工業株式会社 | Light-emitting device and method for manufacturing light-emitting devices |
Also Published As
Publication number | Publication date |
---|---|
JP4653484B2 (en) | 2011-03-16 |
WO2004015769A1 (en) | 2004-02-19 |
TW200402862A (en) | 2004-02-16 |
CN100533723C (en) | 2009-08-26 |
TWI221027B (en) | 2004-09-11 |
CN1675766A (en) | 2005-09-28 |
EP1527479A1 (en) | 2005-05-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5436137B2 (en) | Light-emitting semiconductor device that can be surface-mounted | |
JP4653484B2 (en) | Method for manufacturing an electrical substrate frame, method for manufacturing a surface-mountable semiconductor device and method for manufacturing a semiconductor device | |
US4729061A (en) | Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom | |
US5088008A (en) | Circuit board for mounting electronic components | |
US7488622B2 (en) | Method for producing a surface-mountable semiconductor component | |
US6645783B1 (en) | Method of producing an optoelectronic component | |
US4640010A (en) | Method of making a package utilizing a self-aligning photoexposure process | |
US5814870A (en) | Semiconductor component | |
JP2007511914A (en) | Economy, miniaturized construction and connection technology for light emitting diodes and other photoelectric modules | |
KR102407430B1 (en) | Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component | |
KR20080039904A (en) | Method for the production of a semiconductor component comprising a planar contact, and semiconductor component | |
US10629781B2 (en) | Semiconductor element and method for production thereof | |
KR20120080608A (en) | Optoelectronic module | |
KR100834136B1 (en) | Optical device package and method for manufacturing thereof | |
JP2010171217A (en) | Light-emitting element package, light-emitting device, and display | |
JP2018508984A (en) | Method for manufacturing a plurality of optoelectronic semiconductor elements and optoelectronic semiconductor elements | |
KR101161408B1 (en) | Light emitting diode package and manufacturing method for the same | |
EP3848981A1 (en) | Led module, mold and method for manufacturing the same | |
KR100963201B1 (en) | Substrate embedded chip and method of manufactruing the same | |
JPH10208875A (en) | Organic el element and manufacture therefor | |
JP3995906B2 (en) | Light emitting diode and manufacturing method thereof | |
US10396260B2 (en) | Method of producing an optoelectronic component and optoelectronic component | |
KR100554635B1 (en) | SMD type LED chip with enhanced emitting efficiency and manufacturing method thereof | |
US20230213715A1 (en) | Technologies for Increased Volumetric and Functional Efficiencies of Optical Packages | |
JP2020009913A (en) | Mounting board and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060517 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090410 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090416 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20090703 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20090710 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091016 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100428 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100728 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100804 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100830 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100908 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100928 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20101005 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101028 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101119 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101217 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4653484 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131224 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |