JP2005525690A - Phase change memory with higher pore position - Google Patents

Phase change memory with higher pore position Download PDF

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JP2005525690A
JP2005525690A JP2003525922A JP2003525922A JP2005525690A JP 2005525690 A JP2005525690 A JP 2005525690A JP 2003525922 A JP2003525922 A JP 2003525922A JP 2003525922 A JP2003525922 A JP 2003525922A JP 2005525690 A JP2005525690 A JP 2005525690A
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ローリー，タイラー・エイ
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Abstract

ポアの位置を高くした相変化型メモリセル（１０）は、相変化型メモリコンポーネントの製造プロセスを半導体基板（１２）の他の部分と物理的に分離することにより相変化型メモリの製造を容易にする。本発明の実施の一態様として、半導体基板（１２）内にあるコンタクト（１６）は、絶縁体（２０）により充填されたカップ状導体（１８）と電気的に結合している。カップ状導体（１８）は高い位置に設けられたポアまで電流を導くが、絶縁体（２０）は熱的に電気的にポアを絶縁する役割を果たす。The phase change memory cell (10) with a higher pore position facilitates the manufacture of the phase change memory by physically separating the manufacturing process of the phase change memory component from the rest of the semiconductor substrate (12). To. As one embodiment of the present invention, the contact (16) in the semiconductor substrate (12) is electrically coupled to the cup-shaped conductor (18) filled with the insulator (20). The cup-shaped conductor (18) conducts current to a pore provided at a high position, while the insulator (20) plays a role of thermally and electrically insulating the pore.

Description

本発明は、一般的に、相変化材（phase-change materials）を使用するメモリに関する。   The present invention relates generally to memories that use phase-change materials.

相変化材は少なくとも２つの異なる状態を呈することがある。それらの状態はアモルファス（非結晶）状態と結晶状態と呼ばれることがある。これらの状態間の転移は温度変化に応じて選択的に引き起こされる場合がある。アモルファス状態は一般的に結晶状態よりも電気抵抗率が高いために、これらの状態は区別が可能である。アモルファス状態はより無秩序な原子構造を有し、結晶状態はより規則正しく配列した原子構造を有する。一般的に、どのような相変化材も利用することができる。場合によっては、薄膜カルコゲニド（chalcogenide）合金材料が特に適することがある。   The phase change material can exhibit at least two different states. These states are sometimes called an amorphous (non-crystalline) state and a crystalline state. The transition between these states may be selectively triggered in response to temperature changes. Since the amorphous state generally has a higher electrical resistivity than the crystalline state, these states can be distinguished. The amorphous state has a more disordered atomic structure, and the crystalline state has a more ordered atomic structure. In general, any phase change material can be utilized. In some cases, thin film chalcogenide alloy materials may be particularly suitable.

相変化は可逆的に引き起こされる場合がある。従って、メモリはアモルファス状態から結晶状態に変化し、またアモルファス状態に戻ることが可能であり、その逆の過程も起きる場合がある。要するに、各メモリセルは、高抵抗状態と低抵抗状態との間を可逆的に変化するプログラマブル抵抗器と考えることができる。   Phase changes may be caused reversibly. Accordingly, the memory can change from the amorphous state to the crystalline state and return to the amorphous state, and vice versa. In short, each memory cell can be thought of as a programmable resistor that reversibly changes between a high resistance state and a low resistance state.

状況によっては、メモリセルは多数の状態を有することがある。このとき、各状態は電気抵抗によって区別できるので、多数の電気抵抗によって決まる状態が実現可能であり、それにより複数ビットのデータを単一セルに記憶することが可能となる。   In some situations, a memory cell can have multiple states. At this time, since each state can be distinguished by electric resistance, a state determined by a large number of electric resistances can be realized, and thereby, a plurality of bits of data can be stored in a single cell.

様々な相変化合金が知られている。一般的に、カルコゲニド合金は、周期表ＶＩ族に属する１つ以上の元素を含みうる。特に適した一群の合金としてはＧｅＳｂＴｅ合金がある。   Various phase change alloys are known. In general, chalcogenide alloys can include one or more elements belonging to Group VI of the periodic table. A particularly suitable group of alloys is GeSbTe alloys.

相変化材は、誘電材料を貫通する通路（passage）またはポア（pore：微細孔）の内側に形成される場合がある。相変化材は、通路のどちらか一方の端部においてコンタクト（contact）に結合されることがある。状態の転移は電流を流して相変化材を加熱することにより引き起こされることがある。   The phase change material may be formed inside a passage or pore through the dielectric material. The phase change material may be coupled to a contact at either end of the passage. The state transition may be caused by heating the phase change material by passing an electric current.

アクセスデバイスが、半導体集積回路基板内にその上に積層する相変化材を活性化するために設けられることがある。他の相変化型メモリコンポーネントも半導体基板内に一体化されることがある。集積回路配置構造（integrated topography）上にパターン形成することにより下地の集積回路配置構造に悪影響が及ぼされる場合がある。このため、以前に製作された集積回路配置構造に一切妨害を与えることのない仕方により、集積回路の他の部分の上に相変化型メモリを形成することが望ましいであろう。   An access device may be provided to activate the phase change material that is stacked on the semiconductor integrated circuit substrate. Other phase change memory components may also be integrated into the semiconductor substrate. Forming a pattern on an integrated circuit arrangement structure (integrated topography) may adversely affect the underlying integrated circuit arrangement structure. For this reason, it would be desirable to form phase change memory on other portions of the integrated circuit in a manner that does not interfere with any previously fabricated integrated circuit arrangement.

相変化型メモリの別の問題として、各メモリセルからの熱損失が大きくなるほどデバイスをプログラミングするために印加されなければならない電流が大きくなるということがある。このため、加熱された相変化材からの熱損失量を減らすことが望ましいであろう。同様に、相変化材全体にわたって熱を均一に分布させることが望ましい。しかしながら、現在提案されている多くの技術によれば、デバイスの電気抵抗はプログラミング後に局所的に変動するという結果がもたらされることがある。またこのような電気抵抗の局所的変動の結果、相変化型プログラミング中に局所的な領域に応力が発生することもある。   Another problem with phase change memory is that the greater the heat loss from each memory cell, the greater the current that must be applied to program the device. For this reason, it would be desirable to reduce the amount of heat loss from the heated phase change material. Similarly, it is desirable to distribute heat uniformly throughout the phase change material. However, many currently proposed techniques can result in the electrical resistance of the device fluctuating locally after programming. Also, as a result of such local variations in electrical resistance, stress may occur in local regions during phase change programming.

セルサイズを可能な限り小さくして製造コストを減らすことが望ましいであろう。また、製造工程数を最大限減らして製造コストを減らすことも望ましい。   It would be desirable to reduce the manufacturing cost by making the cell size as small as possible. It is also desirable to reduce the manufacturing cost by reducing the number of manufacturing steps as much as possible.

以上のことから、相変化型メモリとその製造技術を改良することが必要とされている。   In view of the above, it is necessary to improve the phase change memory and its manufacturing technology.

図１に、本発明の実施の一態様として、高い位置に設けられたポア（elevated pore）を含みうる相変化型メモリ１０を示す。基板１２は、ベースコンタクト（base contact）１６を通る電流を制御するアクセストランジスタ（図示せず）を含む集積回路を含みうる。浅いトレンチ型絶縁構造１４は、基板１２内に形成された構造の他の部分からメモリセル１０を絶縁する。本発明の実施の一態様によれば、基板１２上にはライナー導体（liner conductor）１８が配設される。本発明の実施の一態様によれば、このライナー導体１８は、管状でカップ状の形をしており、充填用絶縁体２０で満たされる中空になった中央領域が設けられることがある。ライナー導体１８は、ベースコンタクト１６から、高い位置に設けられたポアに上向きに電流を流す。   FIG. 1 shows a phase-change memory 10 that can include an elevated pore provided at a high position as one embodiment of the present invention. The substrate 12 may include an integrated circuit that includes an access transistor (not shown) that controls the current through the base contact 16. The shallow trench isolation structure 14 insulates the memory cell 10 from other parts of the structure formed in the substrate 12. According to one embodiment of the present invention, a liner conductor 18 is disposed on the substrate 12. According to one embodiment of the present invention, the liner conductor 18 is tubular and cup-shaped, and may be provided with a hollow central region filled with the filling insulator 20. The liner conductor 18 causes a current to flow upward from the base contact 16 to a pore provided at a high position.

高い位置に設けられたポアは、同じく管状でカップ状の抵抗または下部電極２２を含みうる。下部電極２２内側内部には、対向する１対のスペーサ２４と相変化層２８とによって画定されるポアが存在する。本発明の実施の一態様において、相変化層２８が管状でカップ状であってもよく、上部電極３０が詰められていてもよい。本発明の実施の一態様として、上部電極３０と相変化材２８とがパターン形成されていてもよい。   The elevated pore may include a tubular or cup-shaped resistor or lower electrode 22. Inside the lower electrode 22, there are pores defined by a pair of opposed spacers 24 and a phase change layer 28. In one embodiment of the present invention, the phase change layer 28 may be tubular and cup-shaped, and the upper electrode 30 may be packed. As an embodiment of the present invention, the upper electrode 30 and the phase change material 28 may be patterned.

以下、図２（図２Ａ〜図２Ｉ）を参照して、図１に示された構造を形成するためのプロセスについて説明する。図２Ａにおいて、最初に、エッチストップ層（etch stop layer）２６と誘電層３２とを貫いてポア（微細孔）３４が形成される。エッチストップ層２６は、それを取り巻く様々な層と比較してよりエッチングされにくい性質を持つ素材でありうる。本発明の実施の一態様として、このエッチストップ層２６は、窒化珪素（silicon nitride）またはＳｉ3Ｎ4でありうる。 Hereinafter, a process for forming the structure shown in FIG. 1 will be described with reference to FIG. 2 (FIGS. 2A to 2I). In FIG. 2A, first, pores (fine holes) 34 are formed through the etch stop layer 26 and the dielectric layer 32. The etch stop layer 26 may be a material having a property that is more difficult to be etched than various layers surrounding the etch stop layer 26. As an embodiment of the present invention, the etch stop layer 26 may be silicon nitride or Si 3 N 4 .

次に図２Ｂに示されているように、本発明の実施の一態様として、ライナー導体１８がポア３４の内側に積層されていてもよい。ライナー導体１８は、チタン、窒化チタン、タングステン、またはこれらの材料の組み合わせであってもよい。ライナー導体１８は、円筒形ポア３４の内側を覆い、充填材２０が詰められていてもよい。有利には、ライナー導体１８は、ポア３４の側壁を不断に密着して覆う。充填材２０は、熱的に及び電気的に絶縁性を有する。本発明の実施の一態様においては、この充填材２０は二酸化珪素でありうる。   Next, as shown in FIG. 2B, as one embodiment of the present invention, the liner conductor 18 may be laminated inside the pore 34. The liner conductor 18 may be titanium, titanium nitride, tungsten, or a combination of these materials. The liner conductor 18 may cover the inside of the cylindrical pore 34 and may be filled with a filler 20. Advantageously, the liner conductor 18 covers the side walls of the pores 34 in intimate contact. The filler 20 is thermally and electrically insulative. In one embodiment of the present invention, the filler 20 can be silicon dioxide.

次に図２Ｃの段階において、図２Ｂに示された構造が平坦化処理されていてもよい。本発明の実施の一態様において、平坦面Ｓを作り出すためにＣＭＰ（Chemical Mechanical Planarization：化学機械平坦化）工程が利用されることがある。平坦化処理の停止点をうまくコントロールするためにエッチストップ層２６を使用してもよい。   Next, in the stage of FIG. 2C, the structure shown in FIG. 2B may be planarized. In one embodiment of the present invention, a CMP (Chemical Mechanical Planarization) process may be used to create the flat surface S. An etch stop layer 26 may be used to better control the stop point of the planarization process.

図２Ｄに示されているように、充填材２０はコントロールされた距離までエッチングされる。このようにして、開口部３６がコントロールされた深さまで形成される。本発明の実施の一態様において、充填材２０のエッチングとしてドライ絶縁体エッチング（dry insulator etch）を実施してもよい。その後、ライナー導体１８のエッチングを行ってもよい。実施の一態様として、このライナー導体１８が、最小限のオーバーエッチングにより等方性エッチングされていてもよい。実施の一態様として、ライナー導体１８は、充填材２０のエッチング後にウェットエッチング（wet etch）を使用してエッチングされることがある。   As shown in FIG. 2D, the filler 20 is etched to a controlled distance. In this way, the opening 36 is formed to a controlled depth. In one embodiment of the present invention, dry insulator etching may be performed as the etching of the filler 20. Thereafter, the liner conductor 18 may be etched. As an embodiment, the liner conductor 18 may be isotropically etched with minimal overetching. In one implementation, the liner conductor 18 may be etched using a wet etch after the filler 20 is etched.

次に、図２Ｅに示されるように、本発明の実施の一態様として、抵抗または下部電極２２が積層されていてもよい。エッチストップ層２６の上面にある開口部３６は、下部電極２２で覆われていてもよい。そして、この下部電極２２は絶縁体４０で覆われていてもよい。下部電極２２によってライナー導体１８との電気的接続が提供されるため、基板１２内にあるベースコンタクト１６までの電気的接続が提供される。   Next, as shown in FIG. 2E, as an embodiment of the present invention, a resistor or lower electrode 22 may be stacked. The opening 36 on the upper surface of the etch stop layer 26 may be covered with the lower electrode 22. The lower electrode 22 may be covered with an insulator 40. Since the lower electrode 22 provides electrical connection with the liner conductor 18, electrical connection to the base contact 16 in the substrate 12 is provided.

その後、図２Ｅに示された構造に対してＣＭＰ等の平坦化プロセスが実行されて、図２Ｆに示された平坦化された構造が作り出される。そして、ライナー導体１８に対して溝切エッチング（recess etch）が施されて、Ｅで示された陥凹領域（recessed region）が形成される。実施の一態様として、この溝切エッチングは、短いウェットエッチング（short wet etch）であってもよい。   Thereafter, a planarization process, such as CMP, is performed on the structure shown in FIG. 2E to create the planarized structure shown in FIG. 2F. The liner conductor 18 is then subjected to a recess etch to form a recessed region indicated by E. In one embodiment, the grooving etch may be a short wet etch.

この後、ドライまたはウェット絶縁体エッチング等のエッチングプロセスを使用して絶縁体４０を取り除くことができ、その結果、図２Ｇに示されるように、Ｆで示されたポアが作り出されて下部電極２２が露出する。その後、図２Ｈに示されるように、側壁スペーサ２４が形成されてもよい。例えば、絶縁材を積層し、積層した絶縁材を異方性エッチングすることにより、側壁スペーサ２４を従来通りに形成してもよい。実施の一態様において、この側壁スペーサ２４は、窒化珪素または二酸化珪素でありうる。   After this, the insulator 40 can be removed using an etching process such as dry or wet insulator etching, resulting in the creation of pores denoted F and the lower electrode 22 as shown in FIG. 2G. Is exposed. Thereafter, as shown in FIG. 2H, sidewall spacers 24 may be formed. For example, the sidewall spacers 24 may be formed as usual by laminating insulating materials and anisotropically etching the laminated insulating materials. In one embodiment, the sidewall spacer 24 can be silicon nitride or silicon dioxide.

次に、図２Ｉに示されるように、図２Ｈの構造は、相変化層２８と上部電極層３０とによって被覆されていてもよい。実施の一態様において、相変化層２８は、カップ状であり、その側面をスペーサ２４によって画定され、その底面を下部電極２２によって画定されるポア内を下向きに延びる。実施の一態様において、相変化材は、Ｇｅ2Ｓｂ2Ｔｅ5でありうる。 Next, as shown in FIG. 2I, the structure of FIG. 2H may be covered by the phase change layer 28 and the upper electrode layer 30. In one embodiment, the phase change layer 28 is cup-shaped and extends downwardly in a pore defined by spacers 24 on its sides and bottom surfaces defined by lower electrodes 22. In one embodiment, the phase change material can be Ge 2 Sb 2 Te 5 .

上部電極２８は、複数の層から成るサンドウィッチ構造の場合がある。実施の一態様として、このサンドウィッチ構造は、底の方から順に、チタンと、窒化チタンと、アルミニウムとを含む。   The upper electrode 28 may have a sandwich structure composed of a plurality of layers. As an embodiment of this embodiment, the sandwich structure includes titanium, titanium nitride, and aluminum in order from the bottom.

このようにして、基板１２内のベースコンタクト１６からライナー導体１８を通って下部電極２２に至り、そして相変化層２８に至る電気的接続が構築される。最後に、実施の態様によっては、相変化層２８と上部電極３０とは、パターン形成されて、図１に示された構造が実現されることがある。   In this way, an electrical connection is established from the base contact 16 in the substrate 12 through the liner conductor 18 to the lower electrode 22 and to the phase change layer 28. Finally, in some embodiments, phase change layer 28 and upper electrode 30 may be patterned to achieve the structure shown in FIG.

実施の態様によっては、基板１２よりも上にポアを持ち上げることによって相変化型メモリセルを標準的なＣＭＯＳ（complementary metal oxide semiconductor）工程に取り込むことが容易になる。特に、ポアを持ち上げることによって、基板１２内の集積回路配置構造にパターン形成することを避けることができる。その結果、フォトリソグラフィ工程を平坦化された表面上で行うことができる。   In some embodiments, the phase change memory cell can be easily incorporated into a standard complementary metal oxide semiconductor (CMOS) process by raising the pore above the substrate 12. In particular, it is possible to avoid patterning the integrated circuit arrangement in the substrate 12 by lifting the pores. As a result, a photolithography process can be performed on the planarized surface.

実施の態様によっては、熱効率の良いデバイス構造は、デバイスのプログラミングに必要な電力を減らすことによって改良されたデバイス性能を実現する。相変化層２８により代表されるプログラマブル媒体の容積は、その周囲をほぼ断熱する。   In some embodiments, the thermally efficient device structure achieves improved device performance by reducing the power required to program the device. The volume of the programmable medium represented by the phase change layer 28 substantially insulates its periphery.

下部電極２２は、より低い電流で相変化を引き起こすための熱を与える。下部電極２２は比較的に薄く作られていてもよく、そのようにすることにより実施の態様によっては電極２２を通じての熱損失が小さくなる。さらに実施の態様によっては、プログラミング中の熱分布はより均一になり、プログラミング後のデバイス電気抵抗の局所変動がより小さく抑えられる。またこの構造によれば、実施の態様によっては相変化を生じさせる際に局所領域における応力の発生がより抑えられるという結果ももたらされる。   The lower electrode 22 provides heat to cause a phase change at a lower current. The lower electrode 22 may be made relatively thin, thereby reducing heat loss through the electrode 22 in some embodiments. Further, in some embodiments, the heat distribution during programming is more uniform, and local variations in device electrical resistance after programming are reduced. In addition, according to this structure, the occurrence of stress in the local region can be further suppressed when the phase change is caused in some embodiments.

同様に、実施の態様によっては、セルサイズを小さくすることができ、それにより製造コストが減少する。また、本構造を形成するのにマスキング工程を２工程だけ追加することが必要とされるだけでよく、それによってもコストが減少し、工程サイクル時間が短縮される。   Similarly, in some embodiments, the cell size can be reduced, thereby reducing manufacturing costs. Also, only two masking steps need be added to form this structure, which also reduces cost and process cycle time.

本発明は、限定された数の実施態様についてのみ説明がなされたが、当業者であればそれらの実施態様の多数の変更及び変形を考えることができるであろう。本願の特許請求の範囲は、全てのそのような変更及び変形を本発明の技術的思想の範囲内に入るものとしてカバーすることを意図している。   Although the present invention has only been described with respect to a limited number of embodiments, those skilled in the art will be able to contemplate many variations and modifications of those embodiments. The claims of this application are intended to cover all such changes and modifications as fall within the scope of the inventive concept.

本発明の実施の一態様におけるデバイスの拡大断面図である。It is an expanded sectional view of the device in one mode of implementation of the present invention. 図２Ａ〜図２Ｉは、本発明の実施の一態様に基づく図１に示されたデバイスの製造工程を説明するための拡大断面図である。2A to 2I are enlarged cross-sectional views for explaining a manufacturing process of the device shown in FIG. 1 according to one embodiment of the present invention.

Claims (30)

半導体構造基板内にベースコンタクトを形成するステップと、
該半導体構造基板を層により被覆するステップと、
該層を貫通して前記ベースコンタクトに至る電気的接続を形成するステップと、
該層を覆うように、前記ベースコンタクトと電気的に結合する相変化層を形成するステップと
を含んでなる方法。 Forming a base contact in a semiconductor structure substrate;
Coating the semiconductor structure substrate with a layer;
Forming an electrical connection through the layer to the base contact;
Forming a phase change layer electrically coupled to the base contact so as to cover the layer. 前記半導体構造基板を層により被覆するステップが、該半導体構造基板を少なくとも１つの絶縁層で被覆することを含む請求項１に記載の方法。   The method of claim 1, wherein coating the semiconductor structure substrate with a layer comprises coating the semiconductor structure substrate with at least one insulating layer. 前記絶縁層を貫通する通路を形成することを含む請求項２に記載の方法。   The method of claim 2 including forming a passage through the insulating layer. 前記通路に沿って前記電気的接続を形成することを含む請求項３に記載の方法。   4. The method of claim 3, comprising forming the electrical connection along the passage. 前記電気的接続を形成するステップが、カップ状電気的接続部を形成することを含む請求項４に記載の方法。   5. The method of claim 4, wherein forming the electrical connection comprises forming a cup-like electrical connection. 前記カップ状電気的接続部を絶縁体で充填することを含む請求項５に記載の方法。   6. The method of claim 5, comprising filling the cup-like electrical connection with an insulator. 前記カップ状電気的接続部に結合する下部電極を形成することを含む請求項６に記載の方法。   7. The method of claim 6, comprising forming a bottom electrode that couples to the cup-like electrical connection. カップ状下部電極を形成することを含む請求項７に記載の方法。   8. The method of claim 7, comprising forming a cup-shaped lower electrode. 前記カップ状下部電極の内側に側壁スペーサを形成することを含む請求項８に記載の方法。   9. The method of claim 8, comprising forming a sidewall spacer inside the cup-shaped lower electrode. 前記相変化層を形成するステップが、前記絶縁層及び前記側壁スペーサの上に相変化層を積層し、該相変化層を前記下部電極と電気的に接触させることを含む請求項９に記載の方法。   The method of claim 9, wherein forming the phase change layer includes stacking a phase change layer on the insulating layer and the sidewall spacer, and electrically contacting the phase change layer with the lower electrode. Method. 半導体構造基板と、
該半導体構造基板上に形成されたベースコンタクトと、
該半導体構造基板を上から覆う絶縁層と、
該絶縁層を貫通して形成されており、電気的接続部を含む通路と、
該電気的接続部と電気的に結合した相変化層と
を含んでなるメモリ。 A semiconductor structure substrate;
A base contact formed on the semiconductor structure substrate;
An insulating layer covering the semiconductor structure substrate from above;
A passage formed through the insulating layer and including an electrical connection;
A memory comprising a phase change layer electrically coupled to the electrical connection. 前記電気的接続部がカップ状である請求項１１に記載のメモリ。   The memory according to claim 11, wherein the electrical connection portion has a cup shape. 下部電極を含む請求項１２に記載のメモリ。   The memory of claim 12, comprising a bottom electrode. 前記下部電極上に側壁スペーサを含む請求項１３に記載のメモリ。   The memory of claim 13, comprising a sidewall spacer on the lower electrode. 前記相変化層が、前記側壁スペーサを覆って前記下部電極と接触するように形成されている請求項１４に記載のメモリ。   The memory according to claim 14, wherein the phase change layer is formed so as to cover the sidewall spacer and to be in contact with the lower electrode. 前記カップ状電気的接続部の内側に絶縁材を含む請求項１５に記載のメモリ。   The memory according to claim 15, further comprising an insulating material inside the cup-shaped electrical connection portion. 前記下部電極がカップ状である請求項１６に記載のメモリ。   The memory according to claim 16, wherein the lower electrode has a cup shape. 前記下部電極が、前記絶縁層の上面より下に陥凹的に設けられている請求項１７に記載のメモリ。   The memory according to claim 17, wherein the lower electrode is provided in a recessed manner below an upper surface of the insulating layer. 前記相変化層を覆う上部電極を含む請求項１８に記載のメモリ。   The memory of claim 18, further comprising an upper electrode covering the phase change layer. 半導体構造基板と、
該半導体構造基板の上に間隔を置いて配置された相変化層と、
該相変化層を前記半導体構造基板に電気的に結合させる管状コネクタと
を含んでなるメモリ。 A semiconductor structure substrate;
A phase change layer disposed on the semiconductor structure substrate at an interval;
And a tubular connector for electrically coupling the phase change layer to the semiconductor structure substrate. 前記半導体構造基板を覆う絶縁層を含む請求項２０に記載のメモリ。   21. The memory according to claim 20, further comprising an insulating layer covering the semiconductor structure substrate. 前記絶縁層を貫通するように形成された通路を含む請求項２１に記載のメモリ。   The memory of claim 21, comprising a passage formed to penetrate the insulating layer. 前記通路が、前記管状コネクタで内側を覆われている請求項２２に記載のメモリ。   The memory of claim 22, wherein the passage is lined with the tubular connector. 前記相変化層と前記管状コネクタとに電気的に結合した下部電極を含む請求項２０に記載のメモリ。   21. The memory of claim 20, including a lower electrode electrically coupled to the phase change layer and the tubular connector. 前記下部電極が管状である請求項２４に記載のメモリ。   The memory of claim 24, wherein the lower electrode is tubular. 前記管状コネクタがカップ状である請求項２０に記載のメモリ。   The memory of claim 20, wherein the tubular connector is cup-shaped. 前記下部電極がカップ状である請求項２６に記載のメモリ。   27. The memory according to claim 26, wherein the lower electrode is cup-shaped. 前記下部電極を覆い、該下部電極と前記相変化層との間に側壁スペーサを含む請求項２７に記載のメモリ。   28. The memory according to claim 27, comprising a sidewall spacer covering the lower electrode and between the lower electrode and the phase change layer. 前記側壁スペーサが前記通路の内側に設けられており、該側壁スペーサが円筒状である請求項２８に記載のメモリ。   29. The memory according to claim 28, wherein the side wall spacer is provided inside the passage, and the side wall spacer is cylindrical. 前記相変化層を覆う上部電極を含む請求項２９に記載のメモリ。   30. The memory of claim 29, comprising an upper electrode covering the phase change layer.
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