JP2005333073A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005333073A
JP2005333073A JP2004152199A JP2004152199A JP2005333073A JP 2005333073 A JP2005333073 A JP 2005333073A JP 2004152199 A JP2004152199 A JP 2004152199A JP 2004152199 A JP2004152199 A JP 2004152199A JP 2005333073 A JP2005333073 A JP 2005333073A
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wire
semiconductor chip
semiconductor device
electrode
disposed
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Jun Ishikawa
純 石川
Toshiaki Nagase
俊昭 長瀬
Hiroyuki Onishi
宏幸 大西
Koichi Akagawa
宏一 赤川
Sumiko Iida
寿美子 飯田
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Toyota Industries Corp
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Toyota Industries Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device preventing the disconnection and short circuit of a wire. <P>SOLUTION: A semiconductor chip 3 is mounted on a substrate 1 through a radiating board 2, and an external electrode 4 is arranged on the substrate 1. An electrode pad that is formed on the surface of the semiconductor chip 3 is connected with the external electrode 4 through a wire 5. In a region between the electrode pad of the semiconductor chip 3 and the wire bonding part of the external electrode 4, a rubber-like insulating member 7 is projected and formed on the corner 6 of the radiating board 2 located at the lower part of the wire 5. Even if the wire 5 is moved owing to the oscillation or the like from the outside, the direct contact of the wire 5 with the corner 6 of the radiating board 2 is prevented by the contact of the wire 5 with the insulating member 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、半導体装置に係り、半導体モジュールとして用いられる半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device used as a semiconductor module.

半導体パワーモジュールにおいては、例えば、基板上に放熱板を介して半導体チップが搭載され、この半導体チップの表面に形成されている電極パッドと基板上に配設された外部電極とがワイヤボンディングにより接続される。あるいは、放熱基板上にケースが形成されると共にケース内の放熱基板上に半導体チップが搭載され、半導体チップの電極パッドとケースに一体に形成されたインサート電極とがワイヤボンディングにより接続される。   In a semiconductor power module, for example, a semiconductor chip is mounted on a substrate via a heat sink, and electrode pads formed on the surface of the semiconductor chip and external electrodes disposed on the substrate are connected by wire bonding. Is done. Alternatively, a case is formed on the heat dissipation substrate, a semiconductor chip is mounted on the heat dissipation substrate in the case, and an electrode pad of the semiconductor chip and an insert electrode formed integrally with the case are connected by wire bonding.

このような構造を有する半導体パワーモジュールでは、半導体チップの電極パッドと外部電極あるいはインサート電極との間に高低差が生じ、外部から振動等を受けたり、ワイヤボンディング設備の異常でワイヤのループ高さが低くなったりして、ワイヤの中間部が放熱板の角部あるいはインサート電極の縁部に接触し、短絡したり、ワイヤが摩擦により断線するおそれがある。   In the semiconductor power module having such a structure, there is a difference in height between the electrode pad of the semiconductor chip and the external electrode or the insert electrode, and the wire loop height is affected by external vibration or abnormal wire bonding equipment. , The intermediate portion of the wire may come into contact with the corner of the heat sink or the edge of the insert electrode, causing a short circuit, or the wire may be broken due to friction.

特許文献１には、半導体チップの周辺部に絶縁物を形成して半導体チップの電極パッドからリードへ引き出すワイヤが半導体チップの縁部に接触して短絡したり、隣接するワイヤが互いに短絡することを防止する半導体装置が開示されている。   In Patent Document 1, an insulator is formed in the periphery of a semiconductor chip, and a wire drawn from the electrode pad of the semiconductor chip to the lead contacts the edge of the semiconductor chip and is short-circuited, or adjacent wires are short-circuited to each other. A semiconductor device for preventing the above is disclosed.

特開平３−１９６５３５号公報Japanese Patent Laid-Open No. 3-196535

しかしながら、特許文献１の半導体装置は、ワイヤと半導体チップの縁部や隣接するワイヤとの接触を防止する目的で半導体チップの周辺部に絶縁物を形成するものであり、これでは上述したような半導体パワーモジュールにおけるワイヤと放熱板の角部あるいはインサート電極の縁部との接触を防止することは困難である。また、特許文献１の半導体装置は、半導体チップやリードを保持するために、半導体チップ、リードの基端部及びワイヤが樹脂パッケージ等で封止された状態で使用され、上述した半導体パワーモジュールのようにワイヤが振動等によって移動するものではない。
この発明はこのような問題点を解消するためになされたもので、ワイヤの断線及び短絡を防止することができる半導体装置を提供することを目的とする。 However, the semiconductor device of Patent Document 1 forms an insulator on the periphery of the semiconductor chip for the purpose of preventing contact between the wire and the edge of the semiconductor chip or the adjacent wire. It is difficult to prevent contact between the wire and the corner of the heat sink or the edge of the insert electrode in the semiconductor power module. In addition, the semiconductor device of Patent Document 1 is used in a state in which the semiconductor chip, the base end portion of the lead, and the wire are sealed with a resin package or the like in order to hold the semiconductor chip or the lead. Thus, the wire is not moved by vibration or the like.
The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of preventing disconnection and short circuit of wires.

この発明に係る半導体装置は、半導体チップの電極パッドと半導体チップの近傍に配置された外部電極とが互いに高低差を有すると共にこれら両者間がワイヤにより接続される半導体装置において、半導体チップの電極パッドと外部電極のワイヤボンディング部との間の領域で且つワイヤの下方に位置する中間部材の表面上にゴム状の絶縁部材が突出形成されたものである。
半導体チップの電極パッドと外部電極のワイヤボンディング部との間の領域で且つワイヤの下方に位置する中間部材の表面上にゴム状の絶縁部材が形成されているため、外部からの振動等によりワイヤが移動しても、ワイヤは絶縁部材に接触することによりワイヤと中間部材との直接の接触が防止され、これによりワイヤの断線及び短絡が防止される。 According to another aspect of the present invention, there is provided a semiconductor device in which an electrode pad of a semiconductor chip and an external electrode arranged in the vicinity of the semiconductor chip have a difference in height and are connected to each other by a wire. A rubber-like insulating member protrudes from the surface of the intermediate member located between the wire and the wire bonding portion of the external electrode and below the wire.
A rubber-like insulating member is formed on the surface of the intermediate member located between the electrode pad of the semiconductor chip and the wire bonding portion of the external electrode and below the wire. Even if the wire moves, the wire comes into contact with the insulating member to prevent direct contact between the wire and the intermediate member, thereby preventing the wire from being disconnected or short-circuited.

基板とこの基板上に配置される放熱板をさらに備え、半導体チップは放熱板上に配置されると共に外部電極は基板上に配置され、中間部材は放熱板の角部から形成することができる。またこの場合、絶縁部材は、放熱板の面取りされた角部に配置されることが好ましい。
また、放熱基板とこの放熱基板上に配置されるケースをさらに備え、半導体チップはケース内の放熱基板上に配置されると共に外部電極はケースに一体に形成されたインサート電極からなり、中間部材はインサート電極の縁部から形成することができる。
さらに、絶縁部材は、熱硬化型、常温硬化型または紫外線硬化型の樹脂から形成することができる。 The semiconductor device may further include a substrate and a heat sink disposed on the substrate, the semiconductor chip may be disposed on the heat sink and the external electrode may be disposed on the substrate, and the intermediate member may be formed from a corner of the heat sink. In this case, it is preferable that the insulating member is disposed at a chamfered corner of the heat sink.
In addition, a heat dissipating substrate and a case disposed on the heat dissipating substrate are further provided, the semiconductor chip is disposed on the heat dissipating substrate in the case and the external electrode is formed of an insert electrode formed integrally with the case, and the intermediate member is It can be formed from the edge of the insert electrode.
Furthermore, the insulating member can be formed from a thermosetting resin, a room temperature curable resin, or an ultraviolet curable resin.

この発明によれば、半導体チップの電極パッドと外部電極のワイヤボンディング部との間の領域で且つワイヤの下方に位置する中間部材の表面上にゴム状の絶縁部材が突出形成されているため、ワイヤは絶縁部材に接触することによりこのワイヤと中間部材との直接の接触が防止され、これによりワイヤの断線及び短絡が防止される。   According to the present invention, the rubber-like insulating member protrudes on the surface of the intermediate member located between the electrode pad of the semiconductor chip and the wire bonding portion of the external electrode and below the wire. When the wire comes into contact with the insulating member, direct contact between the wire and the intermediate member is prevented, thereby preventing disconnection and short circuit of the wire.

以下、この発明の実施の形態を添付図面に基づいて説明する。
実施の形態１．
図１に、この発明の実施の形態１に係る半導体装置の全体構成を示す。この半導体装置は、半導体パワーモジュールとして用いられるものである。基板１上に銅板等からなる放熱板２を介して半導体チップ３が搭載されている。また、基板１上には外部電極４が配設されており、半導体チップ３の表面に形成された電極パッド（図示せず）と外部電極４とがワイヤ５により接続されている。また、半導体チップ３の電極パッドと外部電極４のワイヤボンディング部との間の領域において、ワイヤ５の下方に位置する放熱板２の角部６上には、この角部６に沿って延出するゴム状の絶縁部材７が形成されている。
図２に示されるように、絶縁部材７は放熱板２の角部６表面から上方に向けて凸状に突出するように形成されており、この絶縁部材７は弾性及び絶縁性を有している。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 shows an overall configuration of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device is used as a semiconductor power module. A semiconductor chip 3 is mounted on the substrate 1 via a heat sink 2 made of a copper plate or the like. An external electrode 4 is disposed on the substrate 1, and an electrode pad (not shown) formed on the surface of the semiconductor chip 3 and the external electrode 4 are connected by a wire 5. In addition, in the region between the electrode pad of the semiconductor chip 3 and the wire bonding portion of the external electrode 4, it extends along the corner portion 6 on the corner portion 6 of the heat sink 2 located below the wire 5. A rubber-like insulating member 7 is formed.
As shown in FIG. 2, the insulating member 7 is formed so as to protrude upward from the surface of the corner portion 6 of the heat radiating plate 2, and this insulating member 7 has elasticity and insulating properties. Yes.

次に、この実施の形態１の半導体装置の作用を説明する。この半導体装置では、半導体チップ３の電極パッドが外部電極４よりも高い位置にあり、外部からの振動等によりワイヤ５が移動しても、ワイヤ５の下方に位置する放熱板２の角部６上にゴム状の絶縁部材７が突出形成されているため、ワイヤ５は絶縁部材７に接触することにより、このワイヤ５の放熱板２の角部６との直接の接触が防止される。ここで、絶縁部材７は弾性を有しているため、ワイヤ５が絶縁部材７と摩擦して擦り切れることもなく、これによりワイヤ５の断線を防止することができる。   Next, the operation of the semiconductor device of the first embodiment will be described. In this semiconductor device, even if the electrode pad of the semiconductor chip 3 is located higher than the external electrode 4 and the wire 5 moves due to external vibration or the like, the corner 6 of the heat sink 2 positioned below the wire 5. Since the rubber-like insulating member 7 is formed so as to protrude above, the wire 5 is prevented from coming into direct contact with the corner portion 6 of the heat sink 2 by contacting the insulating member 7. Here, since the insulating member 7 has elasticity, the wire 5 is not rubbed due to friction with the insulating member 7, thereby preventing the wire 5 from being disconnected.

また、このようにワイヤ５が絶縁部材７に接触してワイヤ５の放熱板２の角部６との接触が防止されるため、ワイヤ５と放熱板２との短絡を防止することができる。
また、ワイヤ５の放熱板２の角部６との接触を防止するために、ワイヤ５のループ高さを大きくとる必要がなく、これにより小型の半導体装置を実現することができる。 Further, since the wire 5 comes into contact with the insulating member 7 and contact with the corner portion 6 of the heat sink 2 of the wire 5 is prevented, a short circuit between the wire 5 and the heat sink 2 can be prevented.
Further, it is not necessary to increase the loop height of the wire 5 in order to prevent the wire 5 from contacting the corner portion 6 of the heat radiating plate 2, thereby realizing a small semiconductor device.

なお、上述の実施の形態１において、図２に示されるように、絶縁部材７を放熱板２の角部６の表面上に配置する代わりに、図３に示されるように、放熱板２の角部６の先端を絶縁部材７により覆うように配置することもでき、このようにしてもワイヤ５が絶縁部材７に接触してワイヤ５の短絡及び断線を防止することができ、実施の形態１と同様の効果が得られる。
また、図４に示されるように、放熱板４の角部６を面取りし、この面取りされた角部８上に絶縁部材７を配置することができ、このようにしても実施の形態１と同様の効果を得ることができる。また、このようにすれば、ワイヤ５が放熱板２の角部８に対してさらに接触しにくくなり、ワイヤ５の短絡及び断線をより確実に防止することができる。 In the first embodiment described above, instead of disposing the insulating member 7 on the surface of the corner portion 6 of the heat sink 2 as shown in FIG. 2, as shown in FIG. The tip of the corner 6 can also be disposed so as to be covered with the insulating member 7, and even in this way, the wire 5 can contact the insulating member 7 to prevent the wire 5 from being short-circuited and disconnected, and the embodiment is described. The same effect as 1 is obtained.
Further, as shown in FIG. 4, the corner 6 of the heat sink 4 can be chamfered, and the insulating member 7 can be disposed on the chamfered corner 8, and even in this way, Similar effects can be obtained. Moreover, if it does in this way, it will become difficult to contact the wire 5 with respect to the corner | angular part 8 of the heat sink 2, and the short circuit and disconnection of the wire 5 can be prevented more reliably.

実施の形態２．
次に図５を参照して、この発明の実施の形態２に係る半導体装置を説明する。この実施の形態２の半導体装置は、図１に示した実施の形態１の半導体装置において、半導体チップ３を放熱板２を介して基板１上に搭載する代わりに、優れた放熱性を有する放熱基板１１の上に半導体チップ３を搭載したものである。すなわち、放熱基板１１上の周縁部にケース１２が配設されると共に、ケース１２内の放熱基板１１上に半導体チップ３が配置されている。また、この半導体装置は、外部電極としてケース１２に一体に形成されたインサート電極１３を有しており、半導体チップ３表面の電極パッドとこのインサート電極１３とがワイヤ１４により互いに接続されている。 Embodiment 2. FIG.
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. The semiconductor device of the second embodiment is a heat dissipation having excellent heat dissipation instead of mounting the semiconductor chip 3 on the substrate 1 via the heat sink 2 in the semiconductor device of the first embodiment shown in FIG. A semiconductor chip 3 is mounted on a substrate 11. That is, the case 12 is disposed at the peripheral edge on the heat dissipation substrate 11, and the semiconductor chip 3 is disposed on the heat dissipation substrate 11 in the case 12. The semiconductor device also has an insert electrode 13 formed integrally with the case 12 as an external electrode, and the electrode pad on the surface of the semiconductor chip 3 and the insert electrode 13 are connected to each other by a wire 14.

また、インサート電極１３のワイヤボンディング部と半導体チップ３の電極パッドとの間の領域において、ワイヤ１４の下方に位置するインサート電極１３の縁部１５上には、図６に示されるように、この縁部１５に沿って延出すると共にインサート電極１３の縁部１５表面から凸状に突出するようにゴム状の絶縁部材１６が配置されている。   Further, in the region between the wire bonding portion of the insert electrode 13 and the electrode pad of the semiconductor chip 3, on the edge portion 15 of the insert electrode 13 positioned below the wire 14, as shown in FIG. A rubber-like insulating member 16 is disposed so as to extend along the edge 15 and protrude in a convex shape from the surface of the edge 15 of the insert electrode 13.

このように、インサート電極１３が半導体チップ３の電極パッドより高い位置にあっても、ワイヤ１４が絶縁部材１６に接触することにより、このワイヤ１４とインサート電極１３の縁部１５との直接の接触が防止されるため、実施の形態１と同様に、ワイヤ１４の短絡及び断線を防止することができる。   Thus, even when the insert electrode 13 is located higher than the electrode pad of the semiconductor chip 3, the wire 14 comes into contact with the insulating member 16, so that the wire 14 and the edge 15 of the insert electrode 13 are in direct contact with each other. Therefore, the short circuit and disconnection of the wire 14 can be prevented as in the first embodiment.

なお、上述の実施の形態１及び２における絶縁部材７及び１６は、熱硬化型の樹脂、常温硬化型の樹脂、或いは紫外線硬化型の樹脂から形成することができ、特に、放熱板２及びインサート電極１３に塗布して高く盛ることができるように、硬化前には所定の粘性を有するものが好ましい。例えば、シリコーン樹脂からなる接着剤やポッティング材を用いることができる。   The insulating members 7 and 16 in the first and second embodiments described above can be formed from a thermosetting resin, a room temperature curable resin, or an ultraviolet curable resin. What has a predetermined viscosity before hardening is preferable so that it can apply | coat to the electrode 13 and can be piled up highly. For example, an adhesive made of silicone resin or a potting material can be used.

この発明の実施の形態１に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention. 実施の形態１における放熱板の角部近傍の構造を示す拡大断面図である。3 is an enlarged cross-sectional view showing a structure in the vicinity of a corner portion of a heat radiating plate in Embodiment 1. FIG. 実施の形態１の変形例における放熱板の角部近傍の構造を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing a structure in the vicinity of a corner portion of a heat sink in a modification of the first embodiment. 実施の形態１の別の変形例における放熱板の角部近傍に構造を示す拡大断面図である。FIG. 10 is an enlarged cross-sectional view showing a structure in the vicinity of a corner portion of a heat sink in another modification of the first embodiment. この発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 実施の形態２におけるインサート電極の縁部近傍の構造を示す拡大斜視図である。6 is an enlarged perspective view showing a structure in the vicinity of an edge portion of an insert electrode in Embodiment 2. FIG.

符号の説明Explanation of symbols

１ 基板、２ 放熱板、３ 半導体チップ、４ 外部電極、５、１４ ワイヤ、６ 放熱板の角部、７，１６ 絶縁部材、８ 放熱板の面取りされた角部、１１ 放熱基板、１２ ケース、１３ インサート電極、１５ インサート電極の縁部。   DESCRIPTION OF SYMBOLS 1 Board | substrate, 2 Heat sink, 3 Semiconductor chip, 4 External electrode, 5, 14 wire, 6 Corner | angular part of a heat sink, 7,16 Insulation member, 8 Chamfered corner | angular part of a heat sink, 11 Heat sink, 12 Case, 13 Insert electrode, 15 Edge of insert electrode.

Claims (5)

半導体チップの電極パッドと半導体チップの近傍に配置された外部電極とが互いに高低差を有すると共にこれら両者間がワイヤにより接続される半導体装置において、
半導体チップの電極パッドと外部電極のワイヤボンディング部との間の領域で且つワイヤの下方に位置する中間部材の表面上にゴム状の絶縁部材が突出形成されていることを特徴とする半導体装置。 In a semiconductor device in which an electrode pad of a semiconductor chip and an external electrode arranged in the vicinity of the semiconductor chip have a height difference with each other and the two are connected by a wire,
A semiconductor device characterized in that a rubber-like insulating member protrudes on the surface of an intermediate member located between the electrode pad of the semiconductor chip and the wire bonding portion of the external electrode and below the wire. 基板とこの基板上に配置される放熱板をさらに備え、半導体チップは前記放熱板上に配置されると共に外部電極は前記基板上に配置され、前記中間部材は前記放熱板の角部からなることを特徴とする請求項１に記載の半導体装置。   A heat sink disposed on the substrate; a semiconductor chip disposed on the heat sink; an external electrode disposed on the substrate; and the intermediate member comprising a corner of the heat sink. The semiconductor device according to claim 1. 前記絶縁部材は、前記放熱板の面取りされた角部に配置されることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the insulating member is disposed at a chamfered corner of the heat radiating plate. 放熱基板とこの放熱基板上に配置されるケースをさらに備え、半導体チップは前記ケース内の前記放熱基板上に配置されると共に外部電極は前記ケースに一体に形成されたインサート電極からなり、前記中間部材は前記インサート電極の縁部からなることを特徴とする請求項１に記載の半導体装置。   A heat dissipating substrate and a case disposed on the heat dissipating substrate; the semiconductor chip is disposed on the heat dissipating substrate in the case; and the external electrode is an insert electrode formed integrally with the case, the intermediate electrode The semiconductor device according to claim 1, wherein the member includes an edge portion of the insert electrode. 前記絶縁部材は、熱硬化型、常温硬化型または紫外線硬化型の樹脂からなることを特徴とする請求項１〜４のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating member is made of a thermosetting resin, a room temperature curable resin, or an ultraviolet curable resin.
JP2004152199A 2004-05-21 2004-05-21 Semiconductor device Pending JP2005333073A (en)

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