JP2005317790A - Interposer - Google Patents

Interposer Download PDF

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JP2005317790A
JP2005317790A JP2004134371A JP2004134371A JP2005317790A JP 2005317790 A JP2005317790 A JP 2005317790A JP 2004134371 A JP2004134371 A JP 2004134371A JP 2004134371 A JP2004134371 A JP 2004134371A JP 2005317790 A JP2005317790 A JP 2005317790A
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conductor via
interposer
conductor
aspect ratio
vias
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JP4489491B2 (en
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Takashi Kariya
隆 苅谷
Toshiki Furuya
俊樹 古谷
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interposer whereby such electronic components as an IC chip are prevented from generating their cracks caused by their thermal expansions and heat contractions, and their power supplies can stably be fed to them. <P>SOLUTION: The interposer 60 has a base substrate 61 formed out of a ceramics, and has a plurality of conductor vias 62 so passed through both sides of the base substrate 61 as to connect electrically an IC chip 70 connected with one of both sides with a printed wiring board 10 connected with the other of both sides. An aspect ratio Rasp of each conductor via 62 is not smaller than 4, and its diameter exceeds 30 μm. Further, the aspect ratio Rasp of each outside conductor via 62a of the conductor vias 62 which is disposed in the peripheral edge of the base substrate 61 is not smaller than the aspect ratio Rasp of each inside conductor via 62b disposed in the central portion of the base substrate 61. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、インターポーザに関し、詳しくは、セラミックにより形成されたベース基板と、該ベース基板の表裏両面を貫通し該表裏両面の一方に接続される電子部品と該表裏両面の他方に接続されるプリント配線板とを電気的に接続する複数の導体ビアと、を備えたインターポーザに関する。   The present invention relates to an interposer, and more specifically, a base substrate formed of ceramic, an electronic component that passes through both front and back surfaces of the base substrate and is connected to one of the front and back surfaces, and a print that is connected to the other of the front and back surfaces. The present invention relates to an interposer including a plurality of conductor vias that electrically connect a wiring board.

近年の集積回路（ＩＣ）技術の進展により、ＩＣチップの入出力端子の数が増大している。それに対応するため、ＩＣチップをプリント配線板に搭載する方式としてフリップチップ方式が採用されることがある。このフリップチップ方式では、ＩＣチップの主平面に入出力端子を格子状又は千鳥状等の二次元に配置し、樹脂製のプリント配線板の表面にもこれと対応する位置にパッドを形成し、両者をはんだバンプで接合する。ところで、ＩＣチップは、樹脂製のプリント配線板と比較して熱膨張係数が著しく小さいため、ＩＣチップの搭載時や使用時の発熱により両者の熱膨張係数差から接合材であるはんだバンプに剪断応力が働くこととなる。このため、ＩＣチップの発熱に伴う温度変化が繰り返し生じた場合、はんだバンプが破壊されるおそれがあった。そこで、ＩＣチップとプリント配線板の間に、熱膨張係数がＩＣチップとプリント配線板の有する熱膨張係数の中間の値を持つインターポーザ（中継基板）を介在させることにより、剪断応力を緩和することが提案されている（特許文献１）。
特開平１０−１２９９０号公報（段落００３７） With the recent progress of integrated circuit (IC) technology, the number of input / output terminals of an IC chip is increasing. In order to cope with this, a flip chip method may be adopted as a method of mounting an IC chip on a printed wiring board. In this flip chip method, input / output terminals are arranged two-dimensionally such as a grid or staggered pattern on the main plane of the IC chip, and pads are formed on the surface of the resin printed wiring board at positions corresponding thereto, Both are joined with solder bumps. By the way, since the IC chip has a remarkably small thermal expansion coefficient compared to a printed wiring board made of resin, heat is generated when the IC chip is mounted or used, so that the solder bump as a bonding material is sheared from the difference between the two thermal expansion coefficients. Stress will work. For this reason, when the temperature change accompanying the heat generation of the IC chip repeatedly occurs, the solder bump may be destroyed. Therefore, it is proposed to reduce the shear stress by interposing an interposer (relay substrate) having a thermal expansion coefficient intermediate between the IC chip and the printed wiring board between the IC chip and the printed wiring board. (Patent Document 1).
JP 10-12990 A (paragraph 0037)

ところで、多層プリント配線板は、インターポーザに比べて熱膨張係数が大きいため、加熱・冷却が繰り返されると膨張・収縮を繰り返すことによりインターポーザに応力が加わることになる。この応力は、多層プリント配線板の周縁部ほど大きくなる。一方、この種のインターポーザは、セラミックにより形成されたベース基板と、該ベース基板の表裏両面を貫通する銅等からなる導体ビアとを備えたものが知られているが、導体ビアはベース基板に比べて熱膨張係数が大きいため、加熱・冷却が繰り返されると膨張・収縮を繰り返すことによりベース基板に応力が加わることになる。以上のことから、インターポーザのベース基板のうち周縁部に位置する導体ビアと多層プリント配線板との接合部分周辺には、加熱・冷却が繰り返されると多層プリント配線板に起因する応力と導体ビアに起因する応力が加わることになり、場合によってはクラックが発生して多層プリント配線板とＩＣチップとの電気抵抗が大きくなることがあった。   By the way, the multilayer printed wiring board has a larger coefficient of thermal expansion than that of the interposer. Therefore, when heating and cooling are repeated, stress is applied to the interposer by repeating expansion and contraction. This stress increases as the peripheral edge of the multilayer printed wiring board increases. On the other hand, this type of interposer is known to have a base substrate made of ceramic and conductor vias made of copper or the like penetrating both the front and back surfaces of the base substrate. Since the coefficient of thermal expansion is larger than that, when heating and cooling are repeated, stress is applied to the base substrate by repeating expansion and contraction. From the above, around the joint portion between the conductor via located at the periphery of the base substrate of the interposer and the multilayer printed wiring board, stress and conductor via caused by the multilayer printed wiring board are caused by repeated heating and cooling. The resulting stress is applied, and in some cases, cracks occur and the electrical resistance between the multilayer printed wiring board and the IC chip increases.

本発明は、このような課題を解決するためになされたものであり、熱膨張・熱収縮によるクラックの発生を防止すると共にＩＣチップ等の電子部品へ安定して電源を供給することができるインターポーザを提供することを目的とする。   The present invention has been made in order to solve such problems, and can prevent generation of cracks due to thermal expansion and contraction and can stably supply power to an electronic component such as an IC chip. The purpose is to provide.

本発明は、上述の目的を達成するために以下の手段を採った。   The present invention adopts the following means in order to achieve the above-mentioned object.

即ち、本発明は、セラミックにより形成されたベース基板と、前記ベース基板の表裏両面を貫通し該表裏両面の一方に接続される電子部品と該表裏両面の他方に接続されるプリント配線板とを電気的に接続する複数の導体ビアと、を備えたインターポーザであって、
前記導体ビアはアスペクト比Ｒａｓｐが４以上で直径が３０μｍを超え、しかも前記導体ビアのうち前記ベース基板の周縁部に配置された外側導体ビアのアスペクト比Ｒａｓｐは前記ベース基板の中央部に配置された内側導体ビアのアスペクト比Ｒａｓｐ以上のものである。 That is, the present invention includes a base substrate made of ceramic, an electronic component that penetrates both the front and back surfaces of the base substrate and is connected to one of the front and back surfaces, and a printed wiring board that is connected to the other of the front and back surfaces. An interposer comprising a plurality of electrically connected vias,
The conductor via has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and the aspect ratio Rasp of the outer conductor via disposed in the peripheral portion of the base substrate in the conductor via is disposed in the central portion of the base substrate. The inner conductor via has an aspect ratio Rasp or higher.

このインターポーザのベース基板のうち導体ビアの周りには、加熱・冷却が繰り返されるとプリント配線板に起因する応力（プリント配線板に引っ張られることにより発生する応力）と導体ビアに起因する応力が加わるが、各導体ビアのアスペクト比Ｒａｓｐが４以上のため、各導体ビアに起因する応力は比較的小さい。また、プリント配線板に起因する応力は中央部よりも周縁部が大きいが、外側導体ビアのアスペクト比Ｒａｓｐが内側導体ビアのアスペクト比Ｒａｓｐ以上のため、導体ビアに起因する応力は中央部よりも周縁部が小さい。また、各導体ビアは直径が３０μｍを超えているため、応力が加えられたとしても電気的接続を確保しやすい。したがって、このインターポーザによれば、プリント配線板と接続された状態で加熱・冷却が繰り返されたとしても、ベース基板の周縁部に熱膨張・熱収縮によるクラックが発生するおそれがなく、ＩＣチップ等の電子部品へ安定して電源を供給することができる。なお、本発明において導体ビアのアスペクト比Ｒａｓｐとは、導体ビアの高さ／導体ビアの径（径が一様でないときには最小径）をいう。   Of the base substrate of this interposer, the stress caused by the printed wiring board (stress generated by being pulled by the printed wiring board) and the stress caused by the conductive via are applied around the conductor via when heating and cooling are repeated. However, since the aspect ratio Rasp of each conductor via is 4 or more, the stress caused by each conductor via is relatively small. Further, the stress caused by the printed wiring board is larger in the peripheral portion than in the central portion, but since the aspect ratio Rasp of the outer conductor via is equal to or larger than the aspect ratio Rasp of the inner conductor via, the stress caused by the conductor via is larger than that in the central portion. The periphery is small. Moreover, since each conductor via has a diameter exceeding 30 μm, it is easy to ensure electrical connection even if stress is applied. Therefore, according to this interposer, even if heating / cooling is repeated while being connected to the printed wiring board, there is no possibility that cracks due to thermal expansion / contraction will occur in the peripheral portion of the base substrate, such as an IC chip. Power can be stably supplied to the electronic components. In the present invention, the aspect ratio Rasp of the conductor via means the height of the conductor via / the diameter of the conductor via (the minimum diameter when the diameter is not uniform).

本発明のインターポーザにおいて、導体ビアのうち外側導体ビアのアスペクト比Ｒａｓｐは内側導体ビアのアスペクト比Ｒａｓｐの１．２５倍以上２倍以下であることが好ましい。この範囲であれば、本発明の効果が顕著になる。   In the interposer of the present invention, it is preferable that the aspect ratio Rasp of the outer conductor via among the conductor vias is not less than 1.25 times and not more than twice the aspect ratio Rasp of the inner conductor via. If it is this range, the effect of this invention will become remarkable.

本発明のインターポーザにおいて、導体ビアのうち少なくとも外側導体ビアは、クビレを持つ形状に形成されていることが好ましい。こうすれば、略ストレート形状の導体ビアに比べて、加熱・冷却を繰り返したときの電気抵抗の変化率を一層抑えることができる。このようなクビレを持つ形状に形成された外側導体ビアは、最大径／最小径が２以上４以下であることが好ましい。   In the interposer of the present invention, it is preferable that at least the outer conductor via among the conductor vias is formed in a shape having a constriction. In this way, the rate of change in electrical resistance when heating / cooling is repeated can be further suppressed as compared with a substantially straight conductor via. The outer conductor via formed in such a shape having a crease preferably has a maximum diameter / minimum diameter of 2 or more and 4 or less.

本発明のインターポーザにおいて、導体ビアが最外周からＮ列目（Ｎは２以上の整数）まで多重に形成されているときには外側導体ビアは最外周からＮ×２／３列までの範囲内で定められていることが好ましい。この範囲内の導体ビアに加わる応力は他の導体ビアに加わる応力に比べて大きいため、本発明を適用する意義が大きい。例えば、Ｎが１５のときには外側導体ビアを最外周から１０列目までの範囲内で定めることになるため、最外周１列のみ、最外周〜２列目まで、……、最外周〜１０列目までといった定め方がある。   In the interposer of the present invention, when conductor vias are formed in multiple layers from the outermost periphery to the Nth row (N is an integer of 2 or more), the outer conductor vias are determined within the range from the outermost periphery to N × 2/3 rows. It is preferable that Since the stress applied to the conductor vias within this range is greater than the stress applied to the other conductor vias, it is significant to apply the present invention. For example, when N is 15, the outer conductor vias are determined within the range from the outermost periphery to the 10th column, so that only the outermost periphery 1 row, the outermost periphery to the 2nd row,. There is a way to define up to eyes.

本発明のインターポーザにおいて、前記外側導体ビアは、プリント配線板上にて略平坦形状に形成されたパッドと接続されるようにしてもよい。このパッドは略平坦に形成されているため、窪んだ形状に形成されている場合に比べてはんだなどの接合部材によってインターポーザと接合するときに接合部材の内部にボイド（空隙）が形成されたり角部が形成されたりすることがない。このように、外側導体ビアとエクスターナルパッドとの接合部分には応力の集中しやすいボイドや角部が存在しないため、この接合部分は容易に破壊されない。したがって、長期にわたって接合信頼性を維持することができる。   In the interposer of the present invention, the outer conductor via may be connected to a pad formed in a substantially flat shape on the printed wiring board. Since this pad is formed to be substantially flat, a void (void) is formed inside the bonding member when the bonding member such as solder is bonded to the interposer as compared to the case where the pad is formed in a recessed shape. No part is formed. Thus, since there are no voids or corners where stress tends to concentrate at the junction between the outer conductor via and the external pad, this junction is not easily destroyed. Therefore, the bonding reliability can be maintained over a long period.

本発明のインターポーザにおいて、ベース基板の厚さは、プリント配線板の厚さの少なくとも０．１倍であることの好ましい。こうすれば、セラミック製のベース基板が割れにくくなる。   In the interposer of the present invention, the thickness of the base substrate is preferably at least 0.1 times the thickness of the printed wiring board. In this way, the ceramic base substrate is difficult to break.

次に、本発明の実施の形態を図面に基づいて説明する。図１は、本発明の一実施形態である半導体搭載用基板８０の断面図である。なお、以下には「上」や「下」と表現することがあるが、これは相対的な位置関係を便宜的に表現したものに過ぎないので、例えば上下を入れ替えたり上下を左右に置き換えたりしてもよい。   Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor mounting substrate 80 according to an embodiment of the present invention. In the following, “upper” and “lower” may be expressed, but this is merely a representation of the relative positional relationship for convenience. May be.

本実施形態の半導体搭載用基板８０は、多層プリント配線板１０にインターポーザ６０を電気的に接続することにより作製されたものである。多層プリント配線板１０は、本実施形態では厚さが１．０２ｍｍであり、図１に示すように、上下両面に形成された配線パターン２２同士をスルーホール導体２４を介して電気的に接続するコア基板２０と、このコア基板２０の上下に形成されたビルドアップ層３０と、ビルドアップ層３０の最上面に形成されたパッド群４０（図２参照）と、を備えている。また、半導体搭載用基板８０のインターポーザ６０に電子部品であるＩＣチップ（熱膨張係数は約３．５ｐｐｍ／℃）が電気的に接続される。   The semiconductor mounting board 80 of this embodiment is manufactured by electrically connecting the interposer 60 to the multilayer printed wiring board 10. The multilayer printed wiring board 10 has a thickness of 1.02 mm in this embodiment, and electrically connects the wiring patterns 22 formed on the upper and lower surfaces through through-hole conductors 24 as shown in FIG. A core substrate 20, a buildup layer 30 formed above and below the core substrate 20, and a pad group 40 (see FIG. 2) formed on the uppermost surface of the buildup layer 30 are provided. Further, an IC chip (thermal expansion coefficient is about 3.5 ppm / ° C.) that is an electronic component is electrically connected to the interposer 60 of the semiconductor mounting substrate 80.

コア基板２０は、ＢＴ（ビスマレイミド−トリアジン）樹脂やガラスエポキシ樹脂等からなるコア基板本体２１の上下両面に銅からなる配線パターン２２，２２と、コア基板本体２１の上下を貫通するスルーホールの内周面に形成された銅からなるスルーホール導体２４とを有しており、両配線パターン２２，２２はスルーホール導体２４を介して電気的に接続されている。このコア基板２０は、本実施形態では厚さ８００μｍであり、熱膨張係数は約１２〜２０ｐｐｍ／℃である。   The core substrate 20 includes wiring patterns 22 and 22 made of copper on both upper and lower surfaces of a core substrate body 21 made of BT (bismaleimide-triazine) resin, glass epoxy resin, and the like, and through holes penetrating the upper and lower sides of the core substrate body 21. A through-hole conductor 24 made of copper is formed on the inner peripheral surface, and both wiring patterns 22 and 22 are electrically connected via the through-hole conductor 24. In this embodiment, the core substrate 20 has a thickness of 800 μm and a thermal expansion coefficient of about 12 to 20 ppm / ° C.

ビルドアップ層３０は、コア基板２０の上下両面に樹脂絶縁層３１，３４と導体層３２，３５とを交互に積層したものである。ここで、樹脂絶縁層３１，３４としては、変成エポキシ系樹脂シート、ポリフェニレンエーテル系樹脂シート、ポリイミド系樹脂シート、シアノエステル系樹脂シートなどが挙げられ、その厚みは概ね２０〜８０μｍが好適である。このビルドアップ層３０は、コア基板２０の配線パターン２２と第１の導体層３２とは第１のバイアホール３３を介して電気的に接続され、第１の導体層３２と第２の導体層３５とは第２のバイアホール３６を介して電気的に接続されている。このようなビルドアップ層３０は、周知のサブトラクティブ法やアディティブ法（セミアディティブ法やフルアディティブ法を含む）により形成される。   The buildup layer 30 is formed by alternately laminating resin insulating layers 31 and 34 and conductor layers 32 and 35 on the upper and lower surfaces of the core substrate 20. Here, examples of the resin insulating layers 31 and 34 include a modified epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide resin sheet, and a cyanoester resin sheet, and the thickness is preferably about 20 to 80 μm. . In the build-up layer 30, the wiring pattern 22 of the core substrate 20 and the first conductor layer 32 are electrically connected via the first via hole 33, and the first conductor layer 32 and the second conductor layer are connected. 35 is electrically connected via a second via hole 36. Such a build-up layer 30 is formed by a known subtractive method or additive method (including a semi-additive method or a full additive method).

パッド群４０は、ビルドアップ層３０をなす第２の樹脂絶縁層３４の上面に形成されたエクスターナルパッド４１とインターナルパッド４３とで構成される群である。このパッド群４０は、本実施形態では図２に示すように、縦３０個×横３０個のパッド４１，４３を格子状に配置したものであり、換言すれば最外周から１５列目まで多重に形成されている。各パッド４１，４３はインターポーザ６０の下面に形成されたランド６４に対応する位置に設けられている。また、図２に示すように、パッド群４０が形成された領域のうち、最外周から１０列目までを外側領域Ａｅｘｔ（図２にて網掛けで表示）、この外側領域Ａｅｘｔよりも中央寄りの領域を内側領域Ａｉｎｔという。そして、外側領域Ａｅｘｔに配置されたパッドをエクスターナルパッド４１、内側領域Ａｉｎｔに配置されたパッドをインターナルパッド４３という。なお、図２では最外周から１０列目までをエクスターナルパッド４１としたが、最外周のみをエクスターナルパッド４１としてもよいし、最外周からｎ列目（ｎは２〜９の整数）までをエクスターナルパッド４１としてもよい。また、図２ではパッド４１，４３を格子状に配置したが、配置の仕方はこれに限定されるものではなく、例えば千鳥状に配置してもよいし、一部が格子状で残りが千鳥状又はランダムに配置してもよいし、一部が千鳥状で残りが格子状又はランダムに配置してもよいし、一部がランダムで残りが格子状又は千鳥状に配置してもよいし、全体にランダムに配置してもよい。   The pad group 40 is a group composed of an external pad 41 and an internal pad 43 formed on the upper surface of the second resin insulating layer 34 forming the buildup layer 30. In the present embodiment, as shown in FIG. 2, the pad group 40 is composed of 30 vertical pads × 30 horizontal pads 41 and 43 arranged in a grid pattern. In other words, the pad group 40 is multiplexed from the outermost periphery to the 15th column. Is formed. The pads 41 and 43 are provided at positions corresponding to lands 64 formed on the lower surface of the interposer 60. Also, as shown in FIG. 2, the outer region Aext (shown by shading in FIG. 2) from the outermost periphery to the tenth column in the region where the pad group 40 is formed, is closer to the center than the outer region Aext. This area is called an inner area Aint. The pads arranged in the outer area Aext are called external pads 41, and the pads arranged in the inner area Aint are called internal pads 43. In FIG. 2, the external pad 41 extends from the outermost periphery to the 10th row, but only the outermost periphery may be used as the external pad 41, or the external pad extends from the outermost periphery to the nth row (n is an integer of 2 to 9). The pad 41 may be used. In FIG. 2, the pads 41 and 43 are arranged in a grid pattern. However, the arrangement is not limited to this. For example, the pads 41 and 43 may be arranged in a zigzag pattern. May be arranged in a zigzag pattern or randomly, or a part may be arranged in a zigzag pattern and the rest may be arranged in a grid pattern or randomly, or a part of them may be arranged randomly and the rest in a grid pattern or zigzag pattern. , May be randomly arranged throughout.

エクスターナルパッド４１は、インターポーザ６０を介してＩＣチップ７０に電気的に接合されるものである。このエクスターナルパッド４１は、ビルドアップ層３０の第２の導体層３５のうち外周方向に引き出された配線パターン３５ａの略平坦な配線部分に形成されている。また、エクスターナルパッド４１が形成された配線パターン３５ａは、このエクスターナルパッド４１よりも外側に形成されたバイアホール３６ａを介して下方の第１の導体層３２と電気的に接合されている。   The external pad 41 is electrically joined to the IC chip 70 via the interposer 60. The external pad 41 is formed on a substantially flat wiring portion of the wiring pattern 35 a drawn out in the outer peripheral direction in the second conductor layer 35 of the buildup layer 30. Further, the wiring pattern 35 a on which the external pad 41 is formed is electrically joined to the first conductor layer 32 below through a via hole 36 a formed outside the external pad 41.

インターナルパッド４３は、インターポーザ６０を介してＩＣチップ７０に電気的に接合されるものである。このインターナルパッド４３は、ビルドアップ層３０の第２の樹脂絶縁層３４の上面で外向きに引き出されることなくこの樹脂絶縁層３４を略直下に貫通して下方の第１の導体層３２と接合され、ここでは第２の樹脂絶縁層３４を貫通する第２のバイアホール３６ｂと第２の導体層３５のうちバイアホール３６ｂの開口周縁部分を含んで形成されている。なお、バイアホール３６ｂを導体で充填してフィルドビアとし、このフィルドビアの直上部分をインターナルパッド４３としてもよい。   The internal pad 43 is electrically joined to the IC chip 70 via the interposer 60. The internal pad 43 penetrates the resin insulating layer 34 substantially directly below without being drawn outwardly on the upper surface of the second resin insulating layer 34 of the buildup layer 30 and the first conductor layer 32 below. Here, the second via hole 36b penetrating the second resin insulating layer 34 and the opening peripheral portion of the via hole 36b in the second conductor layer 35 are formed. The via hole 36b may be filled with a conductor to form a filled via, and a portion directly above the filled via may be used as the internal pad 43.

インターポーザ６０は、ジルコニアセラミック（熱膨張係数が約７ｐｐｍ／℃）により形成された厚さ２００μｍのベース基板６１と、このベース基板６１の表裏両面を貫通する複数の導体ビア６２と、この導体ビア６２の上面側に形成されたランド６３と、導体ビア６２の下面側に形成されたランド６４とを備えている。このインターポーザ６０では、ランド６３はＩＣチップ７０の裏面に設けられた入出力端子とはんだバンプ７１を介して電気的に接合され、ランド６４は多層プリント配線板１０のパッド群４０をなすエクスターナルパッド４１やインターナルパッド４３とはんだバンプ５１，５３を介して電気的に接合される。なお、ランド６３，６４を形成せず、導体ビア６２とＩＣチップ７０とを直接ハンダで接合したり導体ビア６２と多層プリント配線板１０とを直接はんだで接合してもよい。導体ビア６２は、クビレを持つ形状、具体的には上部の直径や下部の直径に比べて中間部の直径が小さい形状に形成されている。導体ビア６２のうちインターポーザ６０の周縁部に配置されたものを外側導体ビア６２ａと称し、中央部に配置されたものを内側導体ビア６２ｂと称することとする。図１では、導体ビア６２を便宜上数本しか示していないが、実際には図３の導体ビア６２の配置図のように、最外周から１５列目まで多重に形成され、最外周から１０列目まで（つまり全１５列の２／３まで、図３にて網掛けで表示）を外側導体ビア６２ａとし、それ以外を内側導体ビア６２ｂとしている。ここでは、外側導体ビア６２ａ及び内側導体ビア６２ｂについて、アスペクト比Ｒａｓｐつまり最小径（中間部の直径）に対する高さの比はいずれも４以上であり、最小径はいずれも３０μｍを上回っている。また、外側導体ビア６２ａのアスペクト比Ｒａｓｐは内側導体ビア６２ｂのアスペクト比Ｒａｓｐ以上に設計され、具体的には、外側導体ビア６０ａのアスペクト比Ｒａｓｐは内側導体ビア６０ｂの１．２５倍以上２倍以下となるように設計されている。なお、図３では導体ビア６２を格子状に配置した例を示したが、図４に示すように千鳥状に配置してもよいし、外周から列が数えられるのであればランダムに配置してもよい。   The interposer 60 includes a base substrate 61 having a thickness of 200 μm formed of zirconia ceramic (thermal expansion coefficient is about 7 ppm / ° C.), a plurality of conductor vias 62 penetrating both front and back surfaces of the base substrate 61, and the conductor vias 62. The lands 63 are formed on the upper surface side, and the lands 64 are formed on the lower surface side of the conductor vias 62. In this interposer 60, the lands 63 are electrically joined to the input / output terminals provided on the back surface of the IC chip 70 via solder bumps 71, and the lands 64 are external pads 41 forming the pad group 40 of the multilayer printed wiring board 10. Further, they are electrically joined via the internal pads 43 and the solder bumps 51 and 53. The lands 63 and 64 may not be formed, and the conductor via 62 and the IC chip 70 may be directly joined by solder, or the conductor via 62 and the multilayer printed wiring board 10 may be joined directly by solder. The conductor via 62 is formed in a shape having a constriction, specifically, a shape in which the diameter of the intermediate part is smaller than the diameter of the upper part and the diameter of the lower part. Of the conductor vias 62, those disposed at the peripheral edge of the interposer 60 are referred to as outer conductor vias 62a, and those disposed at the center are referred to as inner conductor vias 62b. In FIG. 1, only a few conductor vias 62 are shown for the sake of convenience, but actually, as shown in the layout diagram of the conductor vias 62 in FIG. The outer conductor vias 62a are formed up to the eyes (that is, up to 2/3 of the total 15 rows, shown by shading in FIG. 3), and the other portions are used as the inner conductor vias 62b. Here, regarding the outer conductor via 62a and the inner conductor via 62b, the ratio of the height to the aspect ratio Rasp, that is, the minimum diameter (the diameter of the intermediate portion) is 4 or more, and the minimum diameter is more than 30 μm. In addition, the aspect ratio Rasp of the outer conductor via 62a is designed to be greater than or equal to the aspect ratio Rasp of the inner conductor via 62b. Designed to be: Although FIG. 3 shows an example in which the conductor vias 62 are arranged in a grid pattern, the conductor vias 62 may be arranged in a zigzag pattern as shown in FIG. 4, or may be randomly arranged if the rows can be counted from the outer periphery. Also good.

次に、多層プリント配線板１０の製造例について図５〜図７に基づいて説明する。ここでは、厚さ０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる絶縁性基板２０３の両面に銅箔２０５がラミネートされている銅張り積層板２０１を出発材料とし（図５（ａ）参照）、この銅張り積層板２０１にドリルでスルーホール２０７を形成し、無電解めっきのあと電解めっきを施すことにより銅張り積層板２０１の上下面及びスルーホール２０７の表面を被覆するめっき層２０９を形成した（図５（ｂ）参照）。次に、スルーホール充填用樹脂組成物２１０をスルーホール２０７内にスキージを用いて充填し、乾燥したあと導体表面が露出するまで研磨して平坦化し、その後加熱処理を行うことによりスルーホール充填用樹脂組成物２１０を硬化させた（図５（ｃ）参照）。次いで、この基板を無電解銅めっき水溶液中に浸漬して基板表面に無電解銅めっき膜２１１を形成した後、電解銅めっきを施して電解銅めっき膜２１３を形成した（図５（ｄ）参照）。次いで、この基板を通常の写真法でパターン状にエッチングすることにより、上下両面に配線パターン２２を形成し、コア基板２０とした（図５（ｅ）参照）。なお、絶縁性基板２０３がコア基板本体２１、スルーホール２０７内のめっき層２０９がスルーホール導体２４となる。   Next, a manufacturing example of the multilayer printed wiring board 10 will be described with reference to FIGS. Here, a starting material is a copper-clad laminate 201 in which copper foil 205 is laminated on both surfaces of an insulating substrate 203 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm (FIG. 5 ( a)), through-holes 207 are formed in the copper-clad laminate 201 by a drill, and electroless plating is performed followed by electrolytic plating to cover the upper and lower surfaces of the copper-clad laminate 201 and the surface of the through-holes 207 A layer 209 was formed (see FIG. 5B). Next, the through-hole filling resin composition 210 is filled into the through-hole 207 using a squeegee, dried and then polished and flattened until the conductor surface is exposed, and then subjected to heat treatment to fill the through-hole. The resin composition 210 was cured (see FIG. 5C). Next, the substrate was immersed in an electroless copper plating aqueous solution to form an electroless copper plating film 211 on the surface of the substrate, and then subjected to electrolytic copper plating to form an electrolytic copper plating film 213 (see FIG. 5D). ). Next, this substrate was etched into a pattern by a normal photographic method, whereby wiring patterns 22 were formed on both the upper and lower surfaces to form the core substrate 20 (see FIG. 5E). The insulating substrate 203 serves as the core substrate body 21, and the plating layer 209 in the through hole 207 serves as the through hole conductor 24.

続いて、コア基板２０の表裏両面に絶縁層用樹脂フィルム３０１を真空圧着ラミネート法で貼り付け、貫通孔が形成されたマスクを介してこの絶縁層用樹脂フィルム３０１にＣＯ2ガスレーザにてスルーホール３０３を形成したあと加熱処理を行い、絶縁層用樹脂フィルム３０１を完全に硬化させて第１の樹脂絶縁層３１とした（図６（ａ）参照）。次に、この作製途中の基板を無電解銅めっき水溶液中に浸漬し、第１の樹脂絶縁層３１の表面（スルーホール３０３の内壁面も含む）に無電解銅めっき膜３０５を形成し、その後市販の感光性ドライフィルムを貼りつけ、マスクを載置して露光・現像することによりめっきレジスト３０７を設けた（図６（ｂ）参照）。次いで、この基板に電解銅めっきを施すことによりめっきレジスト非形成部に電解銅めっき膜３０９を形成し、その後めっきレジスト３０７を剥離除去した後、無電解銅めっき膜３０５のうち表面に露出した部分を硫酸と過酸化水素水との混合液でエッチング除去し、独立した回路パターンである第１の導体層３２を形成した（図６（ｃ）参照）。なお、第１の導体層３２は、第１の樹脂絶縁層３１の表面に形成された無電解銅めっき膜３０５及び電解銅めっき膜３０９の積層体からなる。このとき、第１の導体層３２は、第１のバイアホール３３（スルーホール３０３内に形成された無電解銅めっき膜３０５及び電解銅めっき膜３０９の積層体）を介してコア基板２０の配線パターン２２と導通している。この作製途中の基板の表裏両面に先ほど使用した絶縁層用樹脂フィルム３０１と同様の絶縁層用樹脂フィルムを真空圧着ラミネート法で貼り付け、先ほどと同様の手順で、貼り付けた絶縁層用樹脂フィルムを第２の樹脂絶縁層３４に加工し更に第２の導体層３５や第２のバイアホール３６を形成し、ビルドアップ層３０を完成した（図６（ｄ）参照）。なお、図６（ｄ）及び後述する図７は基板断面の上半分のみを示す。 Subsequently, the insulating layer resin films 301 are attached to both the front and back surfaces of the core substrate 20 by a vacuum pressure laminating method, and the insulating layer resin film 301 is through-holed by a CO 2 gas laser through a mask in which through holes are formed. After forming 303, heat treatment was performed to completely cure the insulating layer resin film 301 to form the first resin insulating layer 31 (see FIG. 6A). Next, the substrate in the middle of the production is immersed in an electroless copper plating aqueous solution, and an electroless copper plating film 305 is formed on the surface of the first resin insulating layer 31 (including the inner wall surface of the through hole 303). A commercially available photosensitive dry film was attached, a mask was placed, and exposure / development was performed to provide a plating resist 307 (see FIG. 6B). Next, electrolytic copper plating is applied to the substrate to form an electrolytic copper plating film 309 in the plating resist non-forming portion, and then the plating resist 307 is peeled and removed, and then the portion of the electroless copper plating film 305 exposed on the surface Was removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution to form a first conductor layer 32 having an independent circuit pattern (see FIG. 6C). The first conductor layer 32 is composed of a laminate of an electroless copper plating film 305 and an electrolytic copper plating film 309 formed on the surface of the first resin insulation layer 31. At this time, the first conductor layer 32 is connected to the core substrate 20 via the first via hole 33 (a laminate of the electroless copper plating film 305 and the electrolytic copper plating film 309 formed in the through hole 303). The pattern 22 is electrically connected. The insulating layer resin film similar to the insulating layer resin film 301 used earlier is pasted on both the front and back surfaces of the substrate in the middle of the production by the vacuum pressure laminating method, and the insulating layer resin film pasted in the same procedure as before. Was processed into the second resin insulation layer 34, and the second conductor layer 35 and the second via hole 36 were formed to complete the build-up layer 30 (see FIG. 6D). Note that FIG. 6D and FIG. 7 described later show only the upper half of the substrate cross section.

ビルドアップ層３０を形成した基板の両面に、ソルダーレジスト組成物を塗布し乾燥したあと露光・現像することにより、円パターン（マスクパターン）が形成されたソルダーレジスト層４５を形成した（図７（ａ）参照）。このとき、第２の導体層３５のうち最外周に形成された配線パターン３５ａの略平坦な配線部分を開口してエクスターナルパッド４１とすると共に、第２の導体層３５のうち最外周以外のパターンのバイアホール３６及びその周縁部分を開口してインターナルパッド４３とした。次に、パッド４１，４３にニッケルめっき層を形成し更にその上に無電解金めっき層を形成した後、パッド４１，４３上にはんだペーストを印刷してリフローすることによりはんだバンプ５１，５３を形成し、多層プリント配線板１０を完成させた（図７（ｂ）参照）。そして、この多層プリント配線板１０にインターポーザ６０を介して、ＩＣチップ７０を実装した。なお、ＩＣチップ７０とインターポーザ６０との間及びインターポーザ６０と多層プリント配線板１０との間にはアンダーフィルを充填してもよい。   A solder resist layer 45 having a circular pattern (mask pattern) formed thereon was formed by applying a solder resist composition on both sides of the substrate on which the build-up layer 30 was formed, drying, and exposing and developing (FIG. 7 ( a)). At this time, a substantially flat wiring portion of the wiring pattern 35a formed on the outermost periphery of the second conductor layer 35 is opened to form an external pad 41, and a pattern other than the outermost periphery of the second conductor layer 35 is formed. The via hole 36 and its peripheral portion were opened to form an internal pad 43. Next, after forming a nickel plating layer on the pads 41 and 43 and further forming an electroless gold plating layer thereon, a solder paste is printed on the pads 41 and 43 and reflowed to form solder bumps 51 and 53. Thus, the multilayer printed wiring board 10 was completed (see FIG. 7B). Then, an IC chip 70 was mounted on the multilayer printed wiring board 10 via an interposer 60. An underfill may be filled between the IC chip 70 and the interposer 60 and between the interposer 60 and the multilayer printed wiring board 10.

次に、インターポーザ６０の製造方法を図８及び図９を参照して説明する。ここでは、３２ｍｍ×３２ｍｍ×厚さ２００μｍの絶縁性基板であるジルコニア基板６４１を出発原料とした（図８（ａ）参照）。このジルコニア基板６４１のヤング率は、３点曲げ法にて測定したところ、２００ＧＰａであった。このジルコニア基板６４１の両面にウレタン系のレジスト６４２を形成し、通常の写真法により、将来、外側導体ビア６２ａとなる位置に開口６４２ａ（例えばφ１２０μｍ）を形成した（図８（ｂ）参照）。次いで、マキナ社製のサンドブラスト装置で両面にサンドブラスト処理を行うことにより、表裏両面からそれぞれ円錐台形の空洞を形成し、この２つの空洞が基板内部で繋がってクビレを持つ形状のスルーホール６４３ａとなった（図８（ｃ）参照）。その後、レジスト６４２を剥離し、再び両面にウレタン系のレジスト６４４を形成し、通常の写真法により、今度は内側導体ビア６２ｂとなる位置に開口６４４ｂ（例えばφ１００μｍ）を形成した（図８（ｄ）参照）。次いで、先ほどのサンドブラスト装置で両面にサンドブラスト処理を行うことにより、表裏両面からそれぞれ円錐台形の空洞を形成し、この２つの空洞が基板内部で繋がってクビレを持つ形状のスルーホール６４３ｂとなった（図８（ｅ）参照）。なお、スルーホール６４３ａは最大径１２０μｍ、最小径４０μｍ、高さ２００μｍ（アスペクト比Ｒａｓｐ＝５）、スルーホール６４３ｂは最大径１００μｍ、最小径５０μｍ、高さ２００μｍ（アスペクト比Ｒａｓｐ＝４）となるように、サンドブラスト装置の条件（砥粒の材質、砥粒の平均粒径、砥粒の噴出圧力及びショット数）を設定した。   Next, a method for manufacturing the interposer 60 will be described with reference to FIGS. Here, a zirconia substrate 641 which is an insulating substrate having a size of 32 mm × 32 mm × thickness 200 μm was used as a starting material (see FIG. 8A). The Young's modulus of this zirconia substrate 641 was 200 GPa as measured by a three-point bending method. A urethane resist 642 was formed on both surfaces of the zirconia substrate 641, and an opening 642a (for example, φ120 μm) was formed at a position to be the outer conductor via 62a in the future by a normal photographic method (see FIG. 8B). Next, by performing sandblast processing on both sides with a sandblasting device manufactured by Makina, a frustoconical cavity is formed from both the front and back surfaces, and these two cavities are connected inside the substrate to form a through hole 643a having a constriction. (See FIG. 8C). Thereafter, the resist 642 is peeled off, and a urethane-based resist 644 is formed again on both surfaces, and an opening 644b (for example, φ100 μm) is formed at a position to become the inner conductor via 62b by a normal photographic method (FIG. 8D). )reference). Next, by performing sandblast processing on both sides with the sandblasting device, the frustoconical cavities were formed from both the front and back surfaces, and these two cavities were connected inside the substrate to form a through hole 643b having a constriction ( (Refer FIG.8 (e)). The through hole 643a has a maximum diameter of 120 μm, a minimum diameter of 40 μm, and a height of 200 μm (aspect ratio Rasp = 5), and the through hole 643b has a maximum diameter of 100 μm, a minimum diameter of 50 μm, and a height of 200 μm (aspect ratio Rasp = 4). The conditions of the sandblasting device (abrasive material, abrasive grain average particle size, abrasive jetting pressure and number of shots) were set.

その後、レジスト６４４を剥離し（図９（ａ）参照）、スルーホール６４３ａ，６４３ｂを形成したジルコニア基板６４１に、金属皮膜６４５を形成した（図９（ｂ）参照）。この金属皮膜６４５は、ジルコニア基板６４１の表面とスルーホール６４３ａ，６４３ｂの内壁に、まずスパッタにより０．１μｍのクロム皮膜を形成し、続いてそのクロム皮膜上に０．１４μｍのニッケル被膜を蒸着し、更にこの基板６４１を無電解銅めっき水溶液中に浸漬して基板６４１の表面とスルーホール６４３ａ，６４３ｂの内壁に厚さ０．６〜３．０μｍの無電解銅めっき膜を形成することにより、形成した。このときの無電解銅めっき液の組成は以下の通りである。硫酸銅０．０３ｍｏｌ／ｌ、ＥＤＴＡ０．２００ｍｏｌ／ｌ、ＨＣＨＯ０．１８ｇ／ｌ、ＮａＯＨ０．１００ｍｏｌ／ｌ、α、α’−ビピリジル １００ｍｇ／ｌ、ポリエチレングリコール（ＰＥＧ）０．１０ｇ／ｌ。また、無電解銅めっきの条件は、３４℃の液温度で４０分とした。続いて、金属皮膜６４５上に、スルーホール６４３ａ，６４３ｂ内に優先的に析出するめっき液とめっき条件を用いて、スルーホール６４３ａ，６４３ｂ内の充填と基板６４１の表面に電解銅めっき膜６４６を形成した（図９（ｃ）参照）。このときの電解めっき液の組成は次の通りである。硫酸１５０ｇ／ｌ、硫酸銅１６０ｇ／ｌ、添加剤１９．５ｍｌ／ｌ。また、電解めっきの条件は、電流密度を６．５Ａ／ｄｍ2、時間を８０分、温度を２２±２℃、攪拌を噴流攪拌とした。 Thereafter, the resist 644 was peeled off (see FIG. 9A), and a metal film 645 was formed on the zirconia substrate 641 on which the through holes 643a and 643b were formed (see FIG. 9B). The metal film 645 is formed by first forming a 0.1 μm chromium film on the surface of the zirconia substrate 641 and the inner walls of the through holes 643a and 643b by sputtering, and then depositing a 0.14 μm nickel film on the chromium film. Further, the substrate 641 is immersed in an electroless copper plating aqueous solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the surface of the substrate 641 and the inner walls of the through holes 643a and 643b. Formed. The composition of the electroless copper plating solution at this time is as follows. Copper sulfate 0.03 mol / l, EDTA 0.200 mol / l, HCHO 0.18 g / l, NaOH 0.100 mol / l, α, α′-bipyridyl 100 mg / l, polyethylene glycol (PEG) 0.10 g / l. The electroless copper plating was performed at a liquid temperature of 34 ° C. for 40 minutes. Subsequently, an electrolytic copper plating film 646 is formed on the surface of the substrate 641 by filling the through holes 643a and 643b using a plating solution and plating conditions preferentially deposited in the through holes 643a and 643b on the metal film 645. It formed (refer FIG.9 (c)). The composition of the electrolytic plating solution at this time is as follows. 150 g / l sulfuric acid, 160 g / l copper sulfate, 19.5 ml / l additive. The electrolytic plating conditions were a current density of 6.5 A / dm 2 , a time of 80 minutes, a temperature of 22 ± 2 ° C., and stirring as jet stirring.

その後、両面を基板６４１の表面が露出するまで研磨し（図９（ｄ）参照）、両面に露出したバイアホールの銅めっき上にニッケル（５μｍ）、金めっき（０．０３μｍ）を施すことにより、表側にランド６３を形成し裏側にランド６４を形成して、インターポーザ６０を完成させた（図９（ｅ）参照）。なお、ニッケルめっきは、塩化ニッケル３０ｇ／ｌ、次亜リン酸ナトリウム１０ｇ／ｌ、クエン酸ナトリウム１０ｇ／ｌからなるｐＨ５の無電解ニッケルめっき液に２０分間浸漬することにより行った。また、金めっきは、シアン化金カリウム２ｇ／ｌ、塩化アンモニウム７５ｇ／ｌ、クエン酸ナトリウム５０ｇ／ｌ、次亜リン酸ナトリウム１０ｇ／ｌからなる無電解金めっき液に９３℃の条件で２３秒間浸漬することにより行った。図９（ｅ）において、周縁部に位置するスルーホール６４３ａ内の金属皮膜６４５及び電解銅めっき膜６４６が外側導体ビア６２ａに相当し、中央部に位置するスルーホール６４３ｂに形成された金属皮膜６４５及び電解銅めっき膜６４６が内側導体ビア６２ｂに相当し、基板６４１がベース基板６１に相当する。この後、ランド６３，６４上にはんだをマスク印刷し、その後２３０℃でリフローしてはんだバンプを形成してもよい。ただし、特にはんだバンプを形成しなくてもよい。   Thereafter, both surfaces are polished until the surface of the substrate 641 is exposed (see FIG. 9D), and nickel (5 μm) and gold plating (0.03 μm) are applied on the copper plating of via holes exposed on both surfaces. The land 63 was formed on the front side and the land 64 was formed on the back side to complete the interposer 60 (see FIG. 9E). The nickel plating was performed by immersing in an electroless nickel plating solution having a pH of 5 consisting of nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g / l for 20 minutes. Gold plating is performed on an electroless gold plating solution composed of 2 g / l potassium gold cyanide, 75 g / l ammonium chloride, 50 g / l sodium citrate, and 10 g / l sodium hypophosphite at 93 ° C. for 23 seconds. This was done by dipping. In FIG. 9E, the metal film 645 and the electrolytic copper plating film 646 in the through hole 643a located at the peripheral portion correspond to the outer conductor via 62a, and the metal film 645 formed in the through hole 643b located in the center. The electrolytic copper plating film 646 corresponds to the inner conductor via 62 b, and the substrate 641 corresponds to the base substrate 61. Thereafter, solder bumps may be formed on the lands 63 and 64 by mask printing and then reflowing at 230 ° C. However, it is not particularly necessary to form solder bumps.

以上詳述した本実施形態では、インターポーザ６０のベース基板６１のうち導体ビア６２の周り（特に導体ビア６２とベース基板６１との界面）には、加熱・冷却が繰り返されると多層プリント配線板１０に起因する応力と導体ビア６２に起因する応力が加わるが、各導体ビア６２のアスペクト比Ｒａｓｐは４以上のため、各導体ビア６２に起因する応力は比較的小さい。また、多層プリント配線板１０に起因する応力は中央部よりも周縁部が大きくなるが、外側導体ビア６２ａのアスペクト比Ｒａｓｐが内側導体ビア６２ｂのアスペクト比Ｒａｓｐ以上のため、導体ビア６２に起因する応力は逆に中央部よりも周縁部が小さくなる。この結果、多層プリント配線板１０に起因する応力と導体ビア６２に起因する応力との和は中央部と周縁部とで差が小さくなるので、周縁部に応力が集中することがなくなる。また、各導体ビア６２は直径が３０μｍを超えているため、応力が加えられたとしても電気的接続を確保しやすい。したがって、このインターポーザ６０によれば、多層プリント配線板１０と接続された状態で加熱・冷却が繰り返されたとしても、ベース基板６１の周縁部に熱膨張・熱収縮によるクラックが発生するおそれがなく、ＩＣチップ７０へ安定して電源を供給することができる。また、導体ビア６２の直径が３０μｍを超えているため、導体ビア６２の電気抵抗が低くなる。   In the present embodiment described in detail above, the multilayer printed wiring board 10 is repeatedly heated and cooled around the conductor via 62 (particularly, at the interface between the conductor via 62 and the base substrate 61) in the base substrate 61 of the interposer 60. However, since the aspect ratio Rasp of each conductor via 62 is 4 or more, the stress caused by each conductor via 62 is relatively small. Further, the stress caused by the multilayer printed wiring board 10 is larger in the peripheral portion than in the central portion, but is caused by the conductor via 62 because the aspect ratio Rasp of the outer conductor via 62a is greater than the aspect ratio Rasp of the inner conductor via 62b. On the contrary, the stress is smaller at the periphery than at the center. As a result, the difference between the stress caused by the multilayer printed wiring board 10 and the stress caused by the conductor via 62 is small between the central portion and the peripheral portion, so that the stress is not concentrated on the peripheral portion. Moreover, since each conductor via 62 has a diameter exceeding 30 μm, it is easy to ensure electrical connection even if stress is applied. Therefore, according to this interposer 60, there is no possibility that cracks due to thermal expansion / contraction will occur in the peripheral portion of the base substrate 61 even if heating / cooling is repeated while being connected to the multilayer printed wiring board 10. The IC chip 70 can be supplied with stable power. Further, since the diameter of the conductor via 62 exceeds 30 μm, the electrical resistance of the conductor via 62 is lowered.

また、外側導体ビア６２ａのアスペクト比Ｒａｓｐは内側導体ビア６２ｂのアスペクト比Ｒａｓｐの１．２５倍以上２倍以下であるため、上述した効果を一層得やすくなる。更に、導体ビア６２は、クビレを持つ形状に形成されているため、略ストレート形状に形成されている場合に比べて、加熱・冷却を繰り返したときの電気抵抗の変化率を一層抑えることができる。更にまた、導体ビア６２のうち最外周から１０列目まで（つまり全体（１５列）の２／３まで）の範囲を外側導体ビア６２ａとしているが、この範囲の導体ビア６２に起因する応力は他の導体ビア６２に起因する応力に比べて大きいため、本発明を適用する意義が大きい。そしてまた、外側導体ビア６２ａは、多層プリント配線板１０上にて略平坦形状に形成されたエクスターナルパッド４１と接続されているため、窪んだ形状に形成されたインターパッド４３と接続する場合に比べてはんだバンプの内部にボイド（空隙）が形成されたり角部が形成されたりすることがないことから、この接合部分は容易に破壊されず、長期にわたって接合信頼性を維持することができる。そして更に、ベース基板６１の厚さは２００μｍでプリント配線板の厚さ１．０２ｍｍの０．１倍以上であるため、セラミック製のベース基板６１は割れにくい。   Further, since the aspect ratio Rasp of the outer conductor via 62a is not less than 1.25 times and not more than twice the aspect ratio Rasp of the inner conductor via 62b, the above-described effect can be more easily obtained. Furthermore, since the conductor via 62 is formed in a shape having a constriction, the rate of change in electrical resistance when heating and cooling are repeated can be further suppressed as compared with the case where the conductor via 62 is formed in a substantially straight shape. . Furthermore, the range of the conductor vias 62 from the outermost periphery to the 10th row (that is, 2/3 of the entire (15 rows)) is defined as the outer conductor via 62a. The stress caused by the conductor vias 62 in this range is Since the stress is larger than the stress caused by the other conductor vias 62, the significance of applying the present invention is great. Further, since the outer conductor via 62a is connected to the external pad 41 formed in a substantially flat shape on the multilayer printed wiring board 10, it is compared with the case where it is connected to the interpad 43 formed in a recessed shape. Since no voids (voids) or corners are formed inside the solder bumps, the joining portion is not easily broken, and the joining reliability can be maintained for a long time. Furthermore, since the thickness of the base substrate 61 is 200 μm and is 0.1 times or more the thickness of the printed wiring board 1.02 mm, the ceramic base substrate 61 is difficult to break.

特に、インターポーザ６０のうち外側導体ビア６２ａを主に半導体チップ７０のシグナル端子と接続し、内側導体ビア６２ｂを半導体チップ７０の電源端子に接続するものと半導体チップ７０のグランド端子に接続するものとを交互に千鳥状又は格子状に並べてもよい。こうすれば、電源端子に接続されたものとグランド端子に接続されたものとが近接した状態で交互に並ぶため、相互インダクタンスが減少し、電源電位の変動が小さくなる。この結果、トランジスタの電源不足が起こりやすい３ＧＨｚ以上の高周波領域の半導体チップ７０であっても、電源不足が起こりにくくなる。   Particularly, in the interposer 60, the outer conductor via 62a is mainly connected to the signal terminal of the semiconductor chip 70, the inner conductor via 62b is connected to the power supply terminal of the semiconductor chip 70, and the outer conductor via 62b is connected to the ground terminal of the semiconductor chip 70. May be alternately arranged in a staggered pattern or a lattice pattern. By doing so, since the one connected to the power supply terminal and the one connected to the ground terminal are alternately arranged close to each other, the mutual inductance is reduced and the fluctuation of the power supply potential is reduced. As a result, even if the semiconductor chip 70 is in a high frequency region of 3 GHz or more, where power shortage of the transistor is likely to occur, power shortage is less likely to occur.

なお、本発明は上述した実施形態に何ら限定されることはなく、本発明の技術的範囲に属する限り種々の態様で実施し得ることはいうまでもない。   It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

例えば、上述した実施形態では、セラミック基板であるジルコニア基板を出発材料としてインターポーザ６０を作製したが、グリーンシートを出発材料としてインターポーザ６０を作製してもよく、その一例を図１０に示す。まず、平均粒径が１．４μｍのＡｌＮ粉末１ｋｇに、アクリル系バインダ２２０ｇ、焼結助剤としてのＹ2Ｏ3を５０ｇ及びアルコール系溶剤を４００ｍＬ混合した。この混合物をボールミルで均一に混練することにより、高粘度の原料スラリーを作成した。そして、ドクターブレード法に従って、原料スラリーからグリーンシート６５１を成形した（図１０（ａ）参照）。次に、外側導体ビア６２ａ（図１参照）を形成するために先端が円錐形に成形されたスタンパー６５２ａと、内側導体ビア６２ｂ（図１参照）を形成するために先端が円錐形に成形されたスタンパー６５２ｂを用意し、グリーンシート６５１の表面のうち外側導体ビア６２ａの位置にスタンパー６５２ａを配置すると共に内側導体ビア６２ｂの位置にスタンパー６５２ｂを配置し、両スタンパー６５２ａ，６５２ｂを押圧して円錐形の部分を上から貫通させた（図１０（ｂ）参照）。次いで、グリーンシート６５１の裏面のうち外側導体ビア６２ａの位置にスタンパー６５２ａを配置すると共に内側導体ビア６２ｂの位置にスタンパー６５２ｂを配置し、両スタンパー６５２ａ，６５２ｂを押圧して円錐形の部分を下から貫通させた（図１０（ｃ）参照）。これにより、グリーンシート６５１のうち周縁部にクビレを持つ形状のスルーホール６５３ａを透設すると同時に中央部にスルーホール６５３ｂを透設した（図１０（ｄ）参照）。次に、平均粒径が３μｍのタングステン粉末１００ｇに、アクリル系バインダ２ｇ、エーテル系溶剤３ｍＬ、及びエーテル系分散剤０．１ｇを混合した。この混合物を三本ロール混合機で均一に混練して、導体回路形成用のタングステンペーストＰとした。そして、スクリーン印刷機を用いて、グリーンシート６５１にペーストＰを印刷した。これにより、図１０（ｅ）に示すように、スルーホール６５３ａ，６５３ｂ内がペーストＰで充填されると共に、スルーホール６５３ａ，６５３ｂの上下面にペーストＰで円盤部分が形成された。次に、グリーンシート６５１を乾燥機内に装入し、そのグリーンシート６５１を５．０℃／分の昇温速度で加熱した。そして、乾燥機内の温度が１５０℃に達してから約２４時間その温度を保持して、グリーンシート６５１を十分に乾燥させ、その後、室温になるまで放冷した。続いて、グリーンシート６５１を不活性雰囲気下にて１６００℃、５時間の脱脂・仮焼成を施した。さらに、仮焼成されたグリーンシート６５１を同雰囲気下にて１８５０℃、３時間で本焼成した。これにより、ＡｌＮ製のインターポーザ６０を得た（図１０（ｆ）参照）。このインターポーザ６０では、グリーンシート６５１がベース基板６１（厚さ２００μｍ）となり、スルーホール６５３ａに充填されたペーストＰが外側導体ビア６２ａ（最大径１２０μｍ、最小径４０μｍ、高さ２００μｍ）となり、スルーホール６５３ｂに充填されたペーストＰが内側導体ビア６２ｂ（最大径１００μｍ、最小径５０μｍ、高さ２００μｍ）となり、スルーホール６５３ａ，６５３ｂの上下面に形成された円盤部分がランド６３，６４となる。なお、焼成前のグリーンシート６５１の段階では、厚み及びスルーホール６５３ａ，６５３ｂの形状は、目的とする数値に収縮率を見込んだ値に設定する。 For example, in the embodiment described above, the interposer 60 is manufactured using a zirconia substrate, which is a ceramic substrate, as a starting material. However, the interposer 60 may be manufactured using a green sheet as a starting material, and an example is shown in FIG. First, 1 kg of AlN powder having an average particle size of 1.4 μm was mixed with 220 g of an acrylic binder, 50 g of Y 2 O 3 as a sintering aid, and 400 mL of an alcohol solvent. This mixture was uniformly kneaded with a ball mill to prepare a highly viscous raw material slurry. And according to the doctor blade method, the green sheet 651 was shape | molded from the raw material slurry (refer Fig.10 (a)). Next, a stamper 652a whose tip is formed in a conical shape to form the outer conductor via 62a (see FIG. 1) and a tip that is shaped in a conical shape to form the inner conductor via 62b (see FIG. 1). The stamper 652b is prepared, the stamper 652a is disposed at the position of the outer conductor via 62a on the surface of the green sheet 651, the stamper 652b is disposed at the position of the inner conductor via 62b, and both the stampers 652a and 652b are pressed to form a cone. The shape portion was penetrated from above (see FIG. 10B). Next, a stamper 652a is disposed at the position of the outer conductor via 62a on the back surface of the green sheet 651, and a stamper 652b is disposed at the position of the inner conductor via 62b, and both the stampers 652a and 652b are pressed to lower the conical portion. (See FIG. 10 (c)). As a result, a through hole 653a having a shape with a crease at the peripheral edge of the green sheet 651 was made transparent, and at the same time, a through hole 653b was made transparent at the center (see FIG. 10D). Next, 2 g of an acrylic binder, 3 mL of an ether solvent, and 0.1 g of an ether dispersant were mixed with 100 g of tungsten powder having an average particle size of 3 μm. This mixture was uniformly kneaded with a three-roll mixer to obtain a tungsten paste P for forming a conductor circuit. And the paste P was printed on the green sheet 651 using the screen printer. As a result, as shown in FIG. 10E, the through holes 653a and 653b were filled with the paste P, and disc portions were formed with the paste P on the upper and lower surfaces of the through holes 653a and 653b. Next, the green sheet 651 was placed in a dryer, and the green sheet 651 was heated at a temperature increase rate of 5.0 ° C./min. And after the temperature in a dryer reached 150 degreeC, the temperature was hold | maintained for about 24 hours, the green sheet 651 was fully dried, and it stood to cool to room temperature after that. Subsequently, the green sheet 651 was degreased and pre-baked at 1600 ° C. for 5 hours in an inert atmosphere. Further, the temporarily fired green sheet 651 was fired at 1850 ° C. for 3 hours in the same atmosphere. Thereby, an interposer 60 made of AlN was obtained (see FIG. 10F). In this interposer 60, the green sheet 651 becomes the base substrate 61 (thickness 200 μm), and the paste P filled in the through hole 653a becomes the outer conductor via 62a (maximum diameter 120 μm, minimum diameter 40 μm, height 200 μm). The paste P filled in 653b becomes the inner conductor via 62b (maximum diameter 100 μm, minimum diameter 50 μm, height 200 μm), and the disk portions formed on the upper and lower surfaces of the through holes 653a and 653b become the lands 63 and 64, respectively. In the stage of the green sheet 651 before firing, the thickness and the shape of the through holes 653a and 653b are set to values that allow for the shrinkage rate in the target numerical values.

また、上述した実施形態では、外側導体ビア６２ａ及び内側導体ビア６２ｂをクビレを持つ形状としたが、略ストレート形状としてもよい。この場合も、導体ビア６２はアスペクト比Ｒａｓｐが４以上で直径が３０μｍを超え、導体ビア６２のうち外側導体ビア６２ａのアスペクト比Ｒａｓｐは内側導体ビア６２ｂのアスペクト比Ｒａｓｐ以上となるようにする（図１１（ｆ）参照）。略ストレート形状の導体ビア６２を備えたインターポーザの作製手順の一例を図１１に基づいて説明する。まず、上述した実施形態と同様のジルコニア基板６６１を出発原料とし（図１１（ａ）参照）、このジルコニア基板６６１の上面にウレタン系のレジスト６６２を形成し、通常の写真法により、将来外側導体ビア６２ａとなる位置に開口６６２ａ（例えばφ３３μｍ）を形成すると共に将来内側導体ビア６２ｂとなる位置に開口６６２ｂ（例えばφ５０μｍ）を形成した（図１１（ｂ）参照）。次いで、マキナ社製のサンドブラスト装置で上面にサンドブラスト処理を行うことにより、開口６６２ａから略ストレート形状で小径のスルーホール６６３ａを形成すると共に開口６６２ｂから略ストレート形状で大径のスルーホール６６３ｂを形成し、その後レジスト６６２を剥離した（図１１（ｃ）参照）。その後の手順は、図９（ａ）〜（ｅ）に準じて行った。即ち、スルーホール６６３ａ，６６３ｂを形成したジルコニア基板６６１に金属皮膜６６５を形成し（図１１（ｄ）参照）、スルーホール６６３ａ，６６３ｂ内に優先的に析出するめっき液とめっき条件を用いて、スルーホール６６３ａ，６６３ｂ内の充填と基板６６１の表面に電解銅めっき膜６６６を形成し（図１１（ｅ）参照）、その後両面を基板６６１の表面が露出するまで研磨し、露出した両面のバイアホールの銅めっき上にランド６３，６４を形成して、インターポーザ６０を得た（図１１（ｆ）参照）。図１１（ｆ）において、周縁部に位置するスルーホール６６３ａ内の金属皮膜６６５及び電解銅めっき膜６６６が外側導体ビア６２ａに相当し、中央部に位置するスルーホール６６３ｂに形成された金属皮膜６６５及び電解銅めっき膜６６６が内側導体ビア６２ｂに相当し、基板６６１がベース基板６１に相当する。   In the above-described embodiment, the outer conductor via 62a and the inner conductor via 62b have a shape with a neck, but may have a substantially straight shape. Also in this case, the conductor via 62 has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and among the conductor vias 62, the aspect ratio Rasp of the outer conductor via 62a is equal to or larger than the aspect ratio Rasp of the inner conductor via 62b ( (Refer FIG.11 (f)). An example of a manufacturing procedure of an interposer provided with a substantially straight conductor via 62 will be described with reference to FIG. First, a zirconia substrate 661 similar to that of the above-described embodiment is used as a starting material (see FIG. 11A), and a urethane-based resist 662 is formed on the upper surface of the zirconia substrate 661. An opening 662a (for example, φ33 μm) was formed at a position to be the via 62a, and an opening 662b (for example, φ50 μm) was formed at a position to be the inner conductor via 62b in the future (see FIG. 11B). Next, sandblasting is performed on the upper surface with a sandblasting device manufactured by Makina Co., thereby forming a through hole 663a having a substantially straight shape and a small diameter from the opening 662a, and forming a through hole 663b having a substantially straight shape and a large diameter from the opening 662b. Thereafter, the resist 662 was peeled off (see FIG. 11C). Subsequent procedures were performed according to FIGS. 9 (a) to 9 (e). That is, a metal film 665 is formed on the zirconia substrate 661 in which the through holes 663a and 663b are formed (see FIG. 11D), and using a plating solution and plating conditions preferentially deposited in the through holes 663a and 663b, Filling the through holes 663a and 663b and forming an electrolytic copper plating film 666 on the surface of the substrate 661 (see FIG. 11E), then polishing both surfaces until the surface of the substrate 661 is exposed, and exposing both exposed vias. Lands 63 and 64 were formed on the hole copper plating to obtain an interposer 60 (see FIG. 11F). In FIG. 11 (f), the metal film 665 and the electrolytic copper plating film 666 in the through hole 663a located at the peripheral portion correspond to the outer conductor via 62a, and the metal film 665 formed in the through hole 663b located at the center. The electrolytic copper plating film 666 corresponds to the inner conductor via 62b, and the substrate 661 corresponds to the base substrate 61.

略ストレート形状の導体ビア６２の別の作製手順として、グリーンシートを出発材料として用いる場合を図１２に基づいて説明する。まず、図１０（ａ）と同様にしてグリーンシート６７１を成形し（図１２（ａ）参照）、パンチング加工かレーザ加工かドリル穿孔により、将来外側導体ビア６２ａとなる位置に略ストレート形状のスルーホール６７３ａ（例えばφ３３μｍ）を形成すると共に将来内側導体ビア６２ｂとなる位置に略ストレート形状のスルーホール６７３ｂ（例えばφ５０μｍ）を形成した（図１２（ｂ）参照）。その後の手順は、図１０（ｄ）〜（ｆ）に準じて行うため、ここでは説明を省略する。   As another manufacturing procedure of the substantially straight conductor via 62, a case where a green sheet is used as a starting material will be described with reference to FIG. First, a green sheet 671 is formed in the same manner as in FIG. 10A (see FIG. 12A), and a substantially straight through-hole is formed at a position to be the outer conductor via 62a in the future by punching, laser processing, or drilling. A hole 673a (for example, φ33 μm) was formed, and a substantially straight through hole 673b (for example, φ50 μm) was formed at a position that will become the inner conductor via 62b in the future (see FIG. 12B). Since the subsequent procedure is performed in accordance with FIGS. 10D to 10F, description thereof is omitted here.

以下に、本実施形態のインターポーザ６０の効果を実証するための実験例について説明する。まず、導体ビアのアスペクト比Ｒａｓｐと加熱・冷却を繰り返したあとの電気抵抗の変化率との関係について説明する。ここでは、表１に示す実験例１〜２４の導体ビア（縦３０×横３０つまり最外周から１５列目まで多重に形成されている）を備えたインターポーザを作製した。表１において、実験例１〜１２のインターポーザは最小径と最大径とが同じ導体ビアつまり略ストレートな柱状の導体ビアを有するものであり、これらは図８及び図９の作製手順に準じて作製した。また、実験例１３〜２４のインターポーザは最小径と最大径が異なる導体ビアつまりクビレを持つ形状の導体ビアを有するものであり、これらは図１１の作製手順に準じて作製した。このようにして得られた各実験例のインターポーザを介して、ポーラス化した層間絶縁膜を有するＩＣチップを多層プリント配線板に実装し、その後ＩＣチップとインターポーザの間やインターポーザと多層プリント配線板との間に封止樹脂を充填しＩＣ搭載基板とした。そして、ＩＣチップを介した特定回路の電気抵抗（ＩＣ搭載基板のＩＣチップ搭載面とは反対側の面に露出しＩＣチップと導通している一対の電極間の電気抵抗）を測定し、その値を初期値とした。その後、それらのＩＣ搭載基板に、−５５℃×５分、１２５℃×５分を１サイクルとしこれを２０００サイクル繰り返すヒートサイクル試験を行った。このヒートサイクル試験において、２５０サイクル目、５００サイクル目、７５０サイクル目、１０００サイクル目、１２５０サイクル目、１５００サイクル目、２０００サイクル目の電気抵抗を測定し、初期値との変化率（１００×（測定値−初期値）／初期値（％））を求めた。その結果を表１に示す。このテーブル中、電気抵抗の変化率が±５％以内のものを「優」（◎）、±５〜１０％のものを「良」（○）、±１０％を超えたものを「不良」（×）とした。ここで、電気抵抗の変化率が小さければインターポーザの導体ビア特に外側導体ビアやその周辺のダメージが小さくＩＣチップへ安定して電源供給できることを意味し、電気抵抗の変化率が大きければインターポーザの外側導体ビアやその周辺にクラックが発生して大きなダメージを受けておりＩＣチップへ安定して電源供給できないことを意味する。なお、目標スペックは１０００サイクル目の変化率が±１０％以内（つまり評価で「良」か「優」）とした。   Below, the experiment example for demonstrating the effect of the interposer 60 of this embodiment is demonstrated. First, the relationship between the conductor via aspect ratio Rasp and the rate of change in electrical resistance after repeated heating and cooling will be described. Here, an interposer provided with conductor vias of Experimental Examples 1 to 24 shown in Table 1 (length 30 × width 30, that is, formed in multiple layers from the outermost periphery to the 15th column) was produced. In Table 1, the interposers of Experimental Examples 1 to 12 have conductor vias having the same minimum diameter and maximum diameter, that is, substantially straight columnar conductor vias, which are manufactured according to the manufacturing procedures of FIGS. 8 and 9. did. In addition, the interposers of Experimental Examples 13 to 24 have conductor vias having different minimum and maximum diameters, that is, conductor vias having a shape, which were manufactured according to the manufacturing procedure of FIG. An IC chip having a porous interlayer insulating film is mounted on a multilayer printed wiring board through the interposer of each experimental example thus obtained, and then between the IC chip and the interposer, and between the interposer and the multilayer printed wiring board. A sealing resin was filled in between to form an IC mounting substrate. Then, the electrical resistance of the specific circuit through the IC chip (the electrical resistance between the pair of electrodes exposed to the surface opposite to the IC chip mounting surface of the IC mounting substrate and conducting to the IC chip) is measured, The value was taken as the initial value. Thereafter, a heat cycle test was performed on these IC-mounted substrates, with −55 ° C. × 5 minutes and 125 ° C. × 5 minutes as one cycle, and this was repeated 2000 cycles. In this heat cycle test, the electrical resistance at 250th cycle, 500th cycle, 750th cycle, 1000th cycle, 1250th cycle, 1500th cycle, and 2000th cycle was measured, and the rate of change from the initial value (100 × (100 × ( (Measured value−initial value) / initial value (%)). The results are shown in Table 1. In this table, when the rate of change in electrical resistance is within ± 5%, “excellent” (◎), when ± 5 to 10%, “good” (◯), and when it exceeds ± 10%, “bad” (X). Here, if the rate of change of electrical resistance is small, it means that the conductor vias of the interposer, particularly the outer conductor vias and their surroundings, are small and power can be stably supplied to the IC chip. If the rate of change of electrical resistance is large, the outside of the interposer This means that cracks are generated in the conductor via and its periphery, and the IC chip is damaged so that power cannot be stably supplied to the IC chip. Note that the target specification was such that the rate of change at the 1000th cycle was within ± 10% (that is, “good” or “excellent” in the evaluation).

Figure 2005317790
表１から明らかなように、外側導体ビア及び内側導体ビアはいずれもアスペクト比Ｒａｓｐが４以上で直径が３０μｍを超え、しかも外側導体ビアのアスペクト比Ｒａｓｐが内側導体ビアのアスペクト比Ｒａｓｐ以上という条件を満足するもの（実験例２〜４，６〜１０，１４〜１６，１８〜２０，２４）については、いずれも１０００サイクル目まで評価が「良」以上であったのに対して、この条件を満足しないもの（実験例１，５，１１〜１３，１７，２１，２２）については、いずれも１０００サイクル目までのいずれかの段階で評価が「不良」であった。また、外側導体ビアのアスペクト比が内側導体ビアのアスペクト比の２倍を超える実験例２３では、７５０サイクル目までは評価が「良」で１０００サイクル目以降は「不良」、外側導体ビアのアスペクト比が内側導体ビアのアスペクト比の２倍である実験例２４では、１０００サイクル目までは評価が「良」で１２５０サイクル目以降は「不良」であった。なお、かっこ内の数値は抵抗変化率を示している。
Figure 2005317790
 As is apparent from Table 1, the outer conductor via and the inner conductor via both have an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and the outer conductor via aspect ratio Rasp is greater than or equal to the inner conductor via aspect ratio Rasp. For those satisfying the above conditions (Experimental Examples 2 to 4, 6 to 10, 14 to 16, 18 to 20, 24), the evaluation was “good” or higher up to the 1000th cycle. For those not satisfying (Experimental Examples 1, 5, 11 to 13, 17, 21, 22), the evaluation was “bad” at any stage up to the 1000th cycle. In Experimental Example 23, the aspect ratio of the outer conductor via exceeds twice the aspect ratio of the inner conductor via, the evaluation is “good” until the 750th cycle, “bad” after the 1000th cycle, and the aspect of the outer conductor via. In Experimental Example 24 in which the ratio was twice the aspect ratio of the inner conductor via, the evaluation was “good” until the 1000th cycle, and “bad” after the 1250th cycle. The numbers in parentheses indicate the rate of resistance change.

また、例えば実験例２と実験例３，４とを比較すると、外側導体ビアのアスペクト比Ｒａｓｐが内側導体ビアのアスペクト比Ｒａｓｐの１．２５倍以上２倍以下である後２者は、外側導体ビアのアスペクト比Ｒａｓｐと内側導体ビアのアスペクト比Ｒａｓｐが等しい前者に比べて、より長いサイクル数まで評価が「良」であった。同様のことは、実験例６と実験例７，８とを比較したり、実験例１４と実験例１５，１６とを比較したり、実験例１８と実験例１９，２０とを比較してもいえる。   Further, for example, when Experimental Example 2 is compared with Experimental Examples 3 and 4, the outer conductor via aspect ratio Rasp is 1.25 times to twice the aspect ratio Rasp of the inner conductor via. The evaluation was “good” up to a longer cycle number than the former in which the aspect ratio Rasp of the via and the aspect ratio Rasp of the inner conductor via were equal. The same is true even if Experimental Example 6 and Experimental Examples 7 and 8 are compared, Experimental Example 14 and Experimental Examples 15 and 16 are compared, or Experimental Example 18 and Experimental Examples 19 and 20 are compared. I can say that.

更に、例えば実験例２と実験例１４とを比較すると、これらはいずれも外側導体ビアが最外周１列だけであるが、導体ビアがクビレを有する後者は導体ビアがストレート形状の前者に比べて、より長いサイクル数まで評価が「良」であった。同様のことは、実験例３と実験例１５とを比較したり，実験例４と実験例１６とを比較してもいえる。また、外側導体ビアが最外周から１０列目までの実験例６と実験例１８とを比較したり、実験例７と実験例１９とを比較したり、実験例８と実験例２０とを比較しても、より長いサイクル数まで評価が「優」又は「良」であった。   Further, for example, when Experimental Example 2 and Experimental Example 14 are compared with each other, the outer conductor vias are only one row at the outermost periphery, but the latter in which the conductor vias are constricted as compared with the former in which the conductor vias are straight. The evaluation was “good” up to a longer cycle number. The same can be said by comparing Experimental Example 3 and Experimental Example 15 or comparing Experimental Example 4 and Experimental Example 16. Also, the experimental example 6 and the experimental example 18 in which the outer conductor vias are from the outermost circumference to the tenth row are compared, the experimental example 7 and the experimental example 19 are compared, and the experimental example 8 and the experimental example 20 are compared. Even so, the evaluation was “excellent” or “good” up to a longer cycle number.

更にまた、例えば実験例３，７，９，１０を比較すると、これらはいずれも外側導体ビアのアスペクト比Ｒａｓｐが５で内側導体ビアのアスペクト比Ｒａｓｐが４であるが、導体ビアのうち最外周１列だけを外側導体ビアとした実験例３、最外周から３列目までを外側導体ビアとした実験例９、最外周から６列目までを外側導体ビアとした実験例１０、最外周から１０列目までを外側導体ビアとした実験例７の順に、より長いサイクル数まで評価が「良」となる傾向にあった。   Furthermore, for example, when Experimental Examples 3, 7, 9, and 10 are compared, all of these have an outer conductor via aspect ratio Rasp of 5 and an inner conductor via aspect ratio Rasp of 4, but the outermost outer periphery of the conductor vias. Experimental example 3 in which only one row is an outer conductor via, Experimental example 9 in which the outermost via to the third row are outer conductive vias, Experimental example 10 in which the outermost via to the sixth row are outer conductive vias, From the outermost periphery The evaluation tends to be “good” up to a longer cycle number in the order of Experimental Example 7 in which up to the 10th row is the outer conductor via.

次に、インターポーザの導体ビアの位置とその位置にかかる応力との関係について説明する。インターポーザを介して、ポーラス化した層間絶縁膜を有するＩＣチップを多層プリント配線板に実装したＩＣ搭載基板について、３Ｄストリップシミュレーションを行い、導体ビアの列数と、導体ビアとインターポーザのベース基板との界面にかかる応力との関係を計算した。なお、インターポーザの導体ビアは、多層プリント配線板のパッドと１対１に対応するように最外周から１５列目まで多重に形成されているものとした。また、導体ビアのアスペクト比はすべて同一で１とし、インターポーザや導体ビア、ＩＣチップ、多層プリント配線板、はんだ等の材質は同じとした。そして、それらのヤング率、ポアソン比、熱膨張係数を入力して計算した。その結果を図１３のテーブル及びグラフに示す。このテーブル及びグラフから明らかなように、インターポーザの導体ビアの位置が最外周から１０列目（全列数×２／３列目）までは比較的大きな応力がかかり、最外周から６列目（全列数×２／５列目）までは特に大きな応力がかかることがわかる。この結果、導体ビアのうち最外周から全列数×２／３列目を超える位置（２／３列目より内側の導体ビア）では応力を緩和する必要性が乏しいことから、最外周から全列数×２／３列目までの範囲内で外側導体ビアを設定するのが好ましく、特に最外周から全列数×２／５列目までの範囲内で外側導体ビアを設定するのが好ましい。   Next, the relationship between the position of the conductor via of the interposer and the stress applied to the position will be described. A 3D strip simulation is performed on an IC mounting substrate in which an IC chip having a porous interlayer insulating film is mounted on a multilayer printed wiring board via an interposer, and the number of conductor vias and the number of conductor vias and the base substrate of the interposer are determined. The relationship with the stress applied to the interface was calculated. Note that the conductor vias of the interposer were formed in multiple layers from the outermost periphery to the 15th row so as to correspond one-to-one with the pads of the multilayer printed wiring board. Also, the conductor vias had the same aspect ratio of 1, and the materials such as interposer, conductor via, IC chip, multilayer printed wiring board, and solder were the same. And it calculated by inputting those Young's modulus, Poisson's ratio, and thermal expansion coefficient. The results are shown in the table and graph of FIG. As is apparent from this table and graph, a relatively large stress is applied to the position of the conductor via of the interposer from the outermost circumference to the 10th column (the total number of rows × 2/3 rows), and the sixth row from the outermost circumference ( It can be seen that particularly large stress is applied up to the total number of rows × 2 / 5th column). As a result, since there is little need to relieve stress at the positions exceeding the total number of rows × 2/3 rows from the outermost circumference (conductor vias inside the 2/3 rows) of the conductor vias, It is preferable to set the outer conductor via within the range up to the number of columns × 2/3, and it is particularly preferable to set the outer conductor via within the range from the outermost circumference to the total number of columns × 2/5 columns. .

本実施形態の半導体搭載用基板の断面図である。It is sectional drawing of the board | substrate for semiconductor mounting of this embodiment. 本実施形態の多層プリント配線板のパッド群の配置図である。It is a layout view of the pad group of the multilayer printed wiring board of the present embodiment. 本実施形態のインターポーザの導体ビアの配置図である。It is a layout view of conductor vias of the interposer of the present embodiment. 他の導体ビアの配置図である。It is an arrangement plan of other conductor vias. 本実施形態の多層プリント配線板の作製手順を表す断面図である。It is sectional drawing showing the preparation procedures of the multilayer printed wiring board of this embodiment. 本実施形態の多層プリント配線板の作製手順を表す断面図である。It is sectional drawing showing the preparation procedures of the multilayer printed wiring board of this embodiment. 本実施形態の多層プリント配線板の別の作製手順を表す断面図である。It is sectional drawing showing another preparation procedure of the multilayer printed wiring board of this embodiment. 本実施形態のインターポーザ作製手順を表す断面図である。It is sectional drawing showing the interposer preparation procedure of this embodiment. 本実施形態のインターポーザ作製手順を表す断面図である。It is sectional drawing showing the interposer preparation procedure of this embodiment. 他のインターポーザ作製手順を表す断面図である。It is sectional drawing showing the other interposer preparation procedure. 他のインターポーザ作製手順を表す断面図である。It is sectional drawing showing the other interposer preparation procedure. 他のインターポーザ作製手順を表す断面図である。It is sectional drawing showing the other interposer preparation procedure. インターポーザの導体ビアの位置とその位置にかかる応力との関係を表すテーブル及びグラフである。It is a table and a graph showing the relationship between the position of the conductor via of an interposer, and the stress concerning that position.

符号の説明Explanation of symbols

１０…多層プリント配線板、２０…コア基板、２１…コア基板本体、２２…配線パターン、２４…スルーホール導体、３０…ビルドアップ層、３１…第１の樹脂絶縁層、３２…第１の導体層、３３…第１のバイアホール、３４…第２の樹脂絶縁層、３５…第２の導体層、３６…第２のバイアホール、４０…パッド群、４１…エクスターナルパッド、４３…インターナルパッド、４５…ソルダーレジスト層、５１，５３…はんだバンプ、６０…インターポーザ、６２…導体ビア、６２ａ…外側導体ビア、６２ｂ…内側導体ビア、６３，６４…ランド、７０…ＩＣチップ、７１…はんだバンプ、８０…半導体搭載用基板、２０１…銅張り積層板、２０３…絶縁性基板、２０５…銅箔、２０７…スルーホール、２０９…めっき層、２１０…スルーホール充填用樹脂組成物、２１１…無電解銅めっき膜、２１３…電解銅めっき膜、３０１…絶縁層用樹脂フィルム、３０３…スルーホール、３０５…無電解銅めっき膜、３０７…めっきレジスト、３０９…電解銅めっき膜、６４１…ジルコニア基板、６４２，６４４…レジスト、６４２ａ，６４４ｂ…開口、６４３ａ，６３４ｂ…スルーホール、６４５…金属皮膜、６４６…電解銅めっき膜、６５１…グリーンシート、６５２ａ，６５２ｂ…スタンパー、６５３ａ，６５３ｂ…スルーホール、６６１…ジルコニア基板、６６２…レジスト、６６２ａ，６６２ｂ…開口、６６３ａ，６６３ｂ…スルーホール、６６５…金属皮膜、６６６…電解銅めっき膜、６７１…グリーンシート、６７３ａ，６７３ｂ…スルーホール。 DESCRIPTION OF SYMBOLS 10 ... Multilayer printed wiring board, 20 ... Core board | substrate, 21 ... Core board | substrate body, 22 ... Wiring pattern, 24 ... Through-hole conductor, 30 ... Build-up layer, 31 ... 1st resin insulation layer, 32 ... 1st conductor Layer, 33 ... first via hole, 34 ... second resin insulating layer, 35 ... second conductor layer, 36 ... second via hole, 40 ... pad group, 41 ... external pad, 43 ... internal pad 45 ... solder resist layer, 51, 53 ... solder bump, 60 ... interposer, 62 ... conductor via, 62a ... outside conductor via, 62b ... inside conductor via, 63,64 ... land, 70 ... IC chip, 71 ... solder bump 80 ... Semiconductor mounting substrate, 201 ... Copper-clad laminate, 203 ... Insulating substrate, 205 ... Copper foil, 207 ... Through hole, 209 ... Plating layer, 210 ... Through-hole ,... Electroless copper plating film, 213. Electrolytic copper plating film, 301... Resin film for insulating layer, 303... Through hole, 305... Electroless copper plating film, 307. Electrolytic copper plating film, 641 ... Zirconia substrate, 642, 644 ... Resist, 642a, 644b ... Opening, 643a, 634b ... Through hole, 645 ... Metal film, 646 ... Electrolytic copper plating film, 651 ... Green sheet, 652a, 652b ... Stamper, 653a, 653b ... through hole, 661 ... zirconia substrate, 662 ... resist, 662a, 662b ... opening, 663a, 663b ... through hole, 665 ... metal film, 666 ... electrolytic copper plating film, 671 ... green sheet, 673a, 673b ... through hole.

Claims (7)

セラミックにより形成されたベース基板と、
前記ベース基板の表裏両面を貫通し該表裏両面の一方に接続される電子部品と該表裏両面の他方に接続されるプリント配線板とを電気的に接続する複数の導体ビアと、
を備えたインターポーザであって、
前記導体ビアはアスペクト比Ｒａｓｐが４以上で直径が３０μｍを超え、しかも前記導体ビアのうち前記ベース基板の周縁部に配置された外側導体ビアのアスペクト比Ｒａｓｐは前記ベース基板の中央部に配置された内側導体ビアのアスペクト比Ｒａｓｐ以上である、インターポーザ。 A base substrate made of ceramic;
A plurality of conductive vias that electrically connect an electronic component that penetrates both the front and back surfaces of the base substrate and is connected to one of the front and back surfaces; and a printed wiring board that is connected to the other of the front and back surfaces;
An interposer with
The conductor via has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and the aspect ratio Rasp of the outer conductor via disposed in the peripheral portion of the base substrate in the conductor via is disposed in the central portion of the base substrate. An interposer having an inner conductor via aspect ratio Rasp or greater. 前記導体ビアのうち前記外側導体ビアのアスペクト比Ｒａｓｐは前記内側導体ビアのアスペクト比Ｒａｓｐの１．２５倍以上２倍以下である、請求項１に記載のインターポーザ。   2. The interposer according to claim 1, wherein an aspect ratio Rasp of the outer conductor via among the conductor vias is not less than 1.25 times and not more than two times an aspect ratio Rasp of the inner conductor via. 前記導体ビアのうち少なくとも前記外側導体ビアは、クビレを持つ形状に形成されている、請求項１又は２に記載のインターポーザ。   The interposer according to claim 1 or 2, wherein at least the outer conductor via among the conductor vias is formed in a shape having a constriction. 前記クビレを持つ形状に形成された前記外側導体ビアは、最大径／最小径が２以上４以下である、請求項３に記載のインターポーザ。   4. The interposer according to claim 3, wherein the outer conductor via formed in a shape having a constriction has a maximum diameter / minimum diameter of 2 or more and 4 or less. 前記導体ビアが最外周からＮ列目（Ｎは２以上の整数）まで多重に形成されているときには前記外側導体ビアは最外周からＮ×２／３列までの範囲内で定められている、請求項１〜４のいずれかに記載のインターポーザ。   When the conductor vias are formed in multiples from the outermost circumference to the Nth row (N is an integer of 2 or more), the outer conductor vias are defined within a range from the outermost circumference to N × 2/3 rows, The interposer according to any one of claims 1 to 4. 前記外側導体ビアは、前記プリント配線板上にて略平坦形状に形成されたパッドと接続される、請求項１〜５のいずれかに記載のインターポーザ。   The interposer according to any one of claims 1 to 5, wherein the outer conductor via is connected to a pad formed in a substantially flat shape on the printed wiring board. 前記ベース基板の厚さは、前記プリント配線板の厚さの少なくとも０．１倍である、請求項１〜６のいずれかに記載のインターポーザ。   The interposer according to any one of claims 1 to 6, wherein the thickness of the base substrate is at least 0.1 times the thickness of the printed wiring board.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015076564A (en) * 2013-10-11 2015-04-20 日本特殊陶業株式会社 Ceramic wiring board
CN105280604A (en) * 2010-05-26 2016-01-27 台湾积体电路制造股份有限公司 Package system
WO2020204493A1 (en) * 2019-04-01 2020-10-08 주식회사 아모센스 Interposer and method for manufacturing same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274213A (en) * 1995-03-30 1996-10-18 Matsushita Electric Ind Co Ltd Chip carrier and its mounting member
JPH11176998A (en) * 1997-12-08 1999-07-02 Kyocera Corp Wiring board
JP2004047667A (en) * 2002-07-11 2004-02-12 Dainippon Printing Co Ltd Multilayer wiring board and its manufacturing method
JP2004111915A (en) * 2002-07-11 2004-04-08 Dainippon Printing Co Ltd Multilayered wiring board and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274213A (en) * 1995-03-30 1996-10-18 Matsushita Electric Ind Co Ltd Chip carrier and its mounting member
JPH11176998A (en) * 1997-12-08 1999-07-02 Kyocera Corp Wiring board
JP2004047667A (en) * 2002-07-11 2004-02-12 Dainippon Printing Co Ltd Multilayer wiring board and its manufacturing method
JP2004111915A (en) * 2002-07-11 2004-04-08 Dainippon Printing Co Ltd Multilayered wiring board and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280604A (en) * 2010-05-26 2016-01-27 台湾积体电路制造股份有限公司 Package system
JP2015076564A (en) * 2013-10-11 2015-04-20 日本特殊陶業株式会社 Ceramic wiring board
WO2020204493A1 (en) * 2019-04-01 2020-10-08 주식회사 아모센스 Interposer and method for manufacturing same

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