JP2005294722A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2005294722A
JP2005294722A JP2004110864A JP2004110864A JP2005294722A JP 2005294722 A JP2005294722 A JP 2005294722A JP 2004110864 A JP2004110864 A JP 2004110864A JP 2004110864 A JP2004110864 A JP 2004110864A JP 2005294722 A JP2005294722 A JP 2005294722A
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insulating film
film
edge
wiring
semiconductor device
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Shunichi Shibuki
俊一 澁木
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To preventing separation of a film between insulating films by improving adhesion between the insulating films for use in a multilayer wiring structure, thereby improving a yield and reliability. <P>SOLUTION: A semiconductor device 1 has an insulating film for via layer 21 for forming a via on a substrate 11, and an insulating film for wiring layer 22 for forming a wiring layer on the insulating film 21. The insulating film 22 comprises a stacked film of a first insulating film 23 and a second insulating film 24, an edge of the first insulating film 23 is formed such that it is situated at a more inner side than an edge of the second insulating film 24, and edges of the insulating films 22 and 21 are formed at positions corresponding to each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、配線材料の銅を配線溝やビアホール内に埋め込むように形成する化学的機械研磨（以下、ＣＭＰという）時に絶縁膜の剥がれを発生しないようにした半導体装置の製造方法およびその製造方法により製造された半導体装置に関するものである。   The present invention relates to a method of manufacturing a semiconductor device and a method of manufacturing the same, in which peeling of an insulating film does not occur at the time of chemical mechanical polishing (hereinafter referred to as CMP) in which copper as a wiring material is embedded in a wiring groove or via hole. The present invention relates to a semiconductor device manufactured by:

多層配線構造の半導体装置の製造方法では、配線間を電気的に絶縁する絶縁膜を２種類以上の絶縁膜を積層した構造に形成している。特に、絶縁膜の誘電率（ｋ）の値を小さくするために、従来から使用されていた酸化シリコン膜や窒化シリコン膜に比べ、密着性の弱い種々の絶縁膜が使われている。   In the manufacturing method of a semiconductor device having a multilayer wiring structure, an insulating film that electrically insulates between wirings is formed in a structure in which two or more kinds of insulating films are stacked. In particular, in order to reduce the value of dielectric constant (k) of the insulating film, various insulating films having weaker adhesion than those of conventionally used silicon oxide films and silicon nitride films are used.

上記多層配線構造を製造する技術としては、絶縁層に形成した溝および穴に導電材料となる銅を埋め込んで形成する、いわゆるデュアル（二重）ダマシン方法について開示されている（例えば、特許文献１参照。）。この特許文献に開示されている絶縁層は、配線が形成される配線絶縁層とビアが形成されるビア絶縁層とが別層ではなく単層の絶縁層で形成されている。   As a technique for manufacturing the multilayer wiring structure, a so-called dual damascene method in which copper serving as a conductive material is embedded in grooves and holes formed in an insulating layer is disclosed (for example, Patent Document 1). reference.). In the insulating layer disclosed in this patent document, a wiring insulating layer in which wiring is formed and a via insulating layer in which a via is formed are formed as a single insulating layer, not as separate layers.

また、別の公知文献には、配線（ライン）層の絶縁膜とビア層の絶縁膜との積層構造を有し、ビア層の絶縁膜がＴＥＯＳ酸化膜／有機ポリマー系スピンオン材料膜の積層膜であり、配線層の絶縁膜がＴＥＯＳ酸化膜／有機ポリマー系スピンオン材料膜の積層膜である半導体装置が開示されている（例えば、非特許文献１参照。）。   Another known document has a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, and the insulating film of the via layer is a laminated film of a TEOS oxide film / organic polymer spin-on material film. A semiconductor device in which the insulating film of the wiring layer is a laminated film of a TEOS oxide film / organic polymer spin-on material film is disclosed (for example, see Non-Patent Document 1).

また、配線（ライン）層の絶縁膜とビア層の絶縁膜との積層構造を有し、さらに配線層の絶縁膜が第１の絶縁膜上に第２の絶縁膜を形成した積層構造である半導体装置が開示されている（例えば、特許文献２参照。）。具体的には、ビア層の絶縁膜として、パッシベーション膜１１１を窒化シリコン膜で形成し、その上に第１の層間絶縁膜１１２を酸化シリコン膜で形成すること、および配線層の絶縁膜として、第２の層間絶縁膜１１４を有機ポリマーで形成することおよびマスク層１１５を酸化シリコン膜で形成することが開示されている。   The wiring layer has a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, and the insulating film of the wiring layer has a laminated structure in which a second insulating film is formed on the first insulating film. A semiconductor device is disclosed (for example, refer to Patent Document 2). Specifically, as the insulating film for the via layer, the passivation film 111 is formed of a silicon nitride film, the first interlayer insulating film 112 is formed of a silicon oxide film thereon, and the insulating film of the wiring layer is It is disclosed that the second interlayer insulating film 114 is formed of an organic polymer and the mask layer 115 is formed of a silicon oxide film.

しかしながら、上記絶縁膜に溝配線構造を形成する工程において、配線溝、ビアホール等に埋め込んだ銅の絶縁膜上に形成された余剰部分をＣＭＰによって除去する際に、絶縁膜のエッジ部分で膜剥がれが発生していた。この膜剥がれについては対策がなされていなかった。   However, in the step of forming the trench wiring structure in the insulating film, when the excess portion formed on the copper insulating film buried in the wiring trench, via hole, etc. is removed by CMP, the film is peeled off at the edge portion of the insulating film. Had occurred. No measures have been taken for this film peeling.

また、「ウエハ上に、第１の低誘電率膜を、そのエッジが、ウエハ円周に沿った第１エッジ位置に一致するように形成するステップと、前記第１の低誘電率膜よりもガス透過率の低い第１保護膜を、そのエッジが、前記第１エッジ位置より外側の第２エッジ位置を一致するように、前記第１の低誘電率膜およびウエハ上に形成するステップと、前記第１保護膜上に、第２の低誘電率膜を、そのエッジが前記第１エッジ位置にほぼ一致するように形成するステップとを含む」半導体装置の製造方法が開示されている（例えば、特許文献３参照。）。この特許文献３によって開示された技術は、チップの有効面積を最大に維持したままＬｏｗ−ｋ膜の側壁が露出しないようにすることが目的であり、ＣＭＰ等の外圧が絶縁膜にかかった際に生じる膜剥がれについては、全く記載されておらず、考慮すらも全くなされていない。   Further, “a step of forming a first low dielectric constant film on a wafer so that an edge thereof coincides with a first edge position along a circumference of the wafer; Forming a first protective film having a low gas permeability on the first low dielectric constant film and the wafer so that an edge thereof coincides with a second edge position outside the first edge position; Forming a second low dielectric constant film on the first protective film so that an edge thereof substantially coincides with the position of the first edge ”(for example, a semiconductor device manufacturing method is disclosed) , See Patent Document 3). The technique disclosed in Patent Document 3 aims to prevent the sidewall of the Low-k film from being exposed while maintaining the effective area of the chip at the maximum, and when an external pressure such as CMP is applied to the insulating film. The film peeling that occurs is not described at all, and is not even considered at all.

上記特許文献３に開示された技術において、第１の低誘電率膜が例えばビア層の絶縁膜に相当するとし、第２の低誘電率膜が例えば配線層の絶縁膜に相当するとした場合、第１、第２の低誘電率膜の各エッジ位置がほぼ等しく形成される。このため、ＣＭＰ時にかかる圧力は、配線層または第１保護膜のエッジ部に集中するため、膜剥がれ発生の要因となる。   In the technique disclosed in Patent Document 3, when the first low dielectric constant film corresponds to an insulating film of a via layer, for example, and the second low dielectric constant film corresponds to an insulating film of a wiring layer, for example, The edge positions of the first and second low dielectric constant films are formed substantially equal. For this reason, the pressure applied at the time of CMP is concentrated on the edge of the wiring layer or the first protective film, which causes film peeling.

特許第３０５７０５４号公報Japanese Patent No. 3057054 特開２００１−４４１８９号公報JP 2001-44189 A 特開２００３−７８００５号公報JP 2003-78005 A 西岡康隆著 「ＣＤ制御に基づいた有機Ｌｏｗ−ｋ／Ｃｕインテグレーション技術」、グローバルネット株式会社主催“ｋ＜２．５に向けたＬｏｗ−ｋ膜ダマシンプロセスの基礎理論と配線応用技術”p．４-１-１〜４-１-８、２００２年２月２０日Yasutaka Nishioka "Organic Low-k / Cu integration technology based on CD control", sponsored by Global Net Co., Ltd. “Basic theory and wiring application technology of low-k film damascene process for k <2.5” p. 4-1-1 to 4-1-8, February 20, 2002

解決しようとする問題点は、ＣＭＰ工程で絶縁膜が剥がれる点である。特に、ＣＭＰ時に圧力が集中するウエハのエッジ近傍または絶縁膜のエッジ近傍での絶縁膜の剥がれを防止することが難しい点である。   The problem to be solved is that the insulating film is peeled off in the CMP process. In particular, it is difficult to prevent peeling of the insulating film near the edge of the wafer or the edge of the insulating film where pressure is concentrated during CMP.

本発明の半導体装置は、基板上にビアを形成するビア層絶縁膜と、前記ビア層絶縁膜上に配線層を形成する配線層絶縁膜とを備えた半導体装置であって、前記配線層絶縁膜は第１絶縁膜と第２絶縁膜との積層膜からなり、前記第１絶縁膜のエッジは前記第２絶縁膜のエッジより内側になるように形成されていて、前記配線層絶縁膜のエッジと前記ビア層絶縁膜のエッジとが一致した位置に形成されていることを最も主要な特徴とする。   The semiconductor device of the present invention is a semiconductor device comprising a via layer insulating film for forming a via on a substrate and a wiring layer insulating film for forming a wiring layer on the via layer insulating film, the wiring layer insulating The film is formed of a laminated film of a first insulating film and a second insulating film, and the edge of the first insulating film is formed so as to be inside the edge of the second insulating film. The most important feature is that the edge and the edge of the via layer insulating film are formed at the same position.

本発明に半導体装置の製造方法は、基板上にビアを形成するビア層絶縁膜を形成する工程と、前記ビア層絶縁膜上に配線層を形成する配線層絶縁膜を形成する工程と、前記配線層絶縁膜に凹部を形成して、該凹部に埋め込むように配線材料膜を形成した後、前記配線層絶縁膜上の余剰な配線材料膜を化学的機械研磨によって除去することで、前記凹部のみに前記配線材料膜を残して配線を形成する工程とを備えた半導体装置の製造方法であって、前記配線層絶縁膜を第１絶縁膜と第２絶縁膜との積層膜で形成し、その際、前記第１絶縁膜のエッジが前記第２絶縁膜のエッジより内側になるように形成し、前記配線層絶縁膜のエッジと前記ビア層絶縁膜のエッジとを一致した位置に形成することを最も主要な特徴とする。   The method of manufacturing a semiconductor device according to the present invention includes a step of forming a via layer insulating film that forms a via on a substrate, a step of forming a wiring layer insulating film that forms a wiring layer on the via layer insulating film, After forming a recess in the wiring layer insulating film and forming a wiring material film so as to be embedded in the recess, the excess wiring material film on the wiring layer insulating film is removed by chemical mechanical polishing, thereby forming the recess And forming a wiring by leaving the wiring material film only, wherein the wiring layer insulating film is formed of a laminated film of a first insulating film and a second insulating film, At this time, the edge of the first insulating film is formed so as to be inside the edge of the second insulating film, and the edge of the wiring layer insulating film and the edge of the via layer insulating film are formed at the same position. This is the main feature.

本発明の半導体装置は、配線層絶縁膜は第１絶縁膜と第２絶縁膜との積層膜からなり、第１絶縁膜のエッジは第２絶縁膜のエッジより内側になるように形成されているため、外圧、例えばＣＭＰの加工圧が絶縁膜にかかった時、その絶縁膜のエッジにかかる圧力を第１絶縁膜のエッジと第２絶縁膜のエッジとに分散させることができるので、密着性の弱い絶縁膜のエッジ部分での膜剥がれを抑制することができるという利点がある。また、第１絶縁膜とビア層絶縁膜の密着性が弱い場合であっても、第２絶縁膜がビア層絶縁膜との密着性を有する膜であれば、第１絶縁膜のエッジは第２絶縁膜のエッジより内側になるように形成されていることから第２絶縁膜とビア層絶縁膜との接触面積を大きくとれるため、第２絶縁膜とビア層絶縁膜との密着性を向上させることができる。この点からも、絶縁膜のエッジ部分での膜剥がれを抑制することができる。   In the semiconductor device of the present invention, the wiring layer insulating film is formed of a laminated film of the first insulating film and the second insulating film, and the edge of the first insulating film is formed to be inside the edge of the second insulating film. Therefore, when an external pressure, for example, a CMP processing pressure is applied to the insulating film, the pressure applied to the edge of the insulating film can be dispersed between the edge of the first insulating film and the edge of the second insulating film. There is an advantage that peeling of the film at the edge portion of the insulating film having low property can be suppressed. Even if the adhesion between the first insulating film and the via layer insulating film is weak, the edge of the first insulating film is the first insulating film as long as the second insulating film is a film having adhesiveness with the via layer insulating film. Since the contact area between the second insulating film and the via layer insulating film can be increased because it is formed to be inside the edge of the two insulating films, the adhesion between the second insulating film and the via layer insulating film is improved. Can be made. Also from this point, film peeling at the edge portion of the insulating film can be suppressed.

本発明の半導体装置の製造方法は、配線層絶縁膜を第１絶縁膜と第２絶縁膜との積層膜で形成し、その際、第１絶縁膜のエッジが第２絶縁膜のエッジより内側になるように形成し、配線層絶縁膜のエッジとビア層絶縁膜のエッジとを一致した位置に形成するため、外圧、例えばＣＭＰの加工圧が絶縁膜にかかった時、その絶縁膜のエッジにかかる圧力を第１絶縁膜のエッジと第２絶縁膜のエッジとに分散させることができるので、密着性の弱い絶縁膜のエッジ部分での膜剥がれを抑制することができるという利点がある。また、第１絶縁膜とビア層絶縁膜の密着性が弱い場合であっても、第２絶縁膜がビア層絶縁膜との密着性を有する膜であれば、第１絶縁膜のエッジは第２絶縁膜のエッジより内側になるように形成されていることから第２絶縁膜とビア層絶縁膜との接触面積を大きくとれるため、第２絶縁膜とビア層絶縁膜との密着性を向上させることができる。この点からも、絶縁膜のエッジ部分での膜剥がれを抑制することができる。   In the method of manufacturing a semiconductor device according to the present invention, the wiring layer insulating film is formed of a laminated film of a first insulating film and a second insulating film, and the edge of the first insulating film is inside the edge of the second insulating film. When the external pressure, for example, the processing pressure of CMP is applied to the insulating film, the edge of the insulating film is formed so that the edge of the wiring layer insulating film and the edge of the via layer insulating film coincide with each other. Since the pressure applied to the first insulating film can be distributed to the edge of the first insulating film and the edge of the second insulating film, there is an advantage that film peeling at the edge portion of the insulating film having low adhesion can be suppressed. Even if the adhesion between the first insulating film and the via layer insulating film is weak, the edge of the first insulating film is the first insulating film as long as the second insulating film is a film having adhesiveness with the via layer insulating film. Since the contact area between the second insulating film and the via layer insulating film can be increased because it is formed to be inside the edge of the two insulating films, the adhesion between the second insulating film and the via layer insulating film is improved. Can be made. Also from this point, film peeling at the edge portion of the insulating film can be suppressed.

ＣＭＰ時に圧力が集中するウエハのエッジ近傍または絶縁膜のエッジ近傍での絶縁膜の剥がれを防止するという目的を、絶縁膜のエッジ位置を特定することで、絶縁膜の密着性を改善して、ＣＭＰ工程での膜はがれの防止を実現した。   By specifying the edge position of the insulating film for the purpose of preventing the peeling of the insulating film near the edge of the wafer or the edge of the insulating film where the pressure is concentrated during CMP, the adhesion of the insulating film is improved, The prevention of film peeling in the CMP process was realized.

本発明の半導体装置に係る第１実施例を、図１の概略構成断面図によって説明する。   A first embodiment of the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

図１に示すように、図示はしない例えばトランジスタ、配線等が形成された基板（ウエハ）１１上に絶縁膜１２が形成されている。上記基板１１には、例えばシリコン基板が用いられる。また上記絶縁膜１２は、酸化シリコン膜からなり、例えば５００ｎｍの厚さに形成されている。上記絶縁膜１２上にはビアが形成されるビア層絶縁膜２１が形成されている。ここではビア層絶縁膜２１は例えばＳｉＯＣ系の膜で形成する。例えば、ＳｉＯＣ膜、ＳｉＯＣ膜中に窒素もしくは水素が含まれた膜である。上記ビア層絶縁膜２１は、例えばプラズマＣＶＤ法により２００ｎｍの厚さに成膜されているものである。上記絶縁膜１２およびビア層絶縁膜２１の成膜の具体例としては、平行平板型プラズマＣＶＤ装置を用い、その際使用する原料ガスのうちシリコン源としてメチルシランを用いた。また成膜条件としては基板温度を３００℃〜４００℃に設定し、プラズマパワーを１５０〜３５０Ｗ、成膜雰囲気の圧力を１００Ｐａ〜１０００Ｐａ程度に設定する。   As shown in FIG. 1, an insulating film 12 is formed on a substrate (wafer) 11 on which transistors, wirings, and the like (not shown) are formed. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. A via layer insulating film 21 in which vias are formed is formed on the insulating film 12. Here, the via layer insulating film 21 is formed of, for example, a SiOC-based film. For example, a SiOC film or a film containing nitrogen or hydrogen in the SiOC film. The via layer insulating film 21 is formed to a thickness of 200 nm by, for example, plasma CVD. As a specific example of the film formation of the insulating film 12 and the via layer insulating film 21, a parallel plate type plasma CVD apparatus was used, and methylsilane was used as a silicon source among the source gases used at that time. As film forming conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 to 350 W, and the pressure of the film forming atmosphere is set to about 100 Pa to 1000 Pa.

さらに、ビア層絶縁膜２１上には配線層絶縁膜２２が形成されている。この配線層絶縁膜２２は、第１絶縁膜２３と第２絶縁膜２４との積層構造をなしている。上記第１絶縁膜２３には例えば有機膜が用いられ、例えば１００ｎｍの厚さに形成されている。この有機膜としては、ポリアリールエーテル膜があり、例えば、ダウケミカル社製のＳｉＬＫ−Ｊ、アライドシグナル社製のＦＬＡＲＥ等が知られている。また、上記第２絶縁膜２４は、例えば酸化シリコン（ＳｉＯ2）膜が用いられ、その膜厚は例えば２００ｎｍとした。 Further, a wiring layer insulating film 22 is formed on the via layer insulating film 21. The wiring layer insulating film 22 has a laminated structure of a first insulating film 23 and a second insulating film 24. For example, an organic film is used as the first insulating film 23 and is formed to a thickness of, for example, 100 nm. As this organic film, there is a polyaryl ether film, for example, SiLK-J manufactured by Dow Chemical Co., FLARE manufactured by Allied Signal, etc. are known. The second insulating film 24 is made of, for example, a silicon oxide (SiO 2 ) film and has a thickness of 200 nm, for example.

上記第２絶縁膜２４のエッジ位置に対して上記第１絶縁膜２３のエッジ位置は内側に形成されている。また、上記第２絶縁膜２４のエッジ位置に対して上記第１絶縁膜２３のエッジ位置は、例えば０．５ｍｍ以上５ｍｍ以下の範囲（図面ｗ３で示す）で内側に形成されている。好ましくは、１．５ｍｍ以上５ｍｍ以下の範囲で内側に形成され、より好ましくは、１．５ｍｍ以上２ｍｍ以下の範囲で内側に形成される。また、上記ビア層絶縁膜２１のエッジ位置に対して上記配線層絶縁膜２２の第２絶縁膜２４のエッジ位置は、同位置に形成されている。   The edge position of the first insulating film 23 is formed inside the edge position of the second insulating film 24. The edge position of the first insulating film 23 is formed on the inner side in the range of 0.5 mm or more and 5 mm or less (shown in the drawing w3) with respect to the edge position of the second insulating film 24, for example. Preferably, it forms inward in the range of 1.5 mm or more and 5 mm or less, More preferably, it forms inward in the range of 1.5 mm or more and 2 mm or less. The edge position of the second insulating film 24 of the wiring layer insulating film 22 is formed at the same position as the edge position of the via layer insulating film 21.

上記半導体装置１は、基板１１上にビアを形成するビア層絶縁膜２１が形成され、ビア層絶縁膜２１上に第１絶縁膜２３と第２絶縁膜２４との積層構造からなるもので配線層を形成する配線層絶縁膜２２が形成されており、第１絶縁膜２３のエッジは第２絶縁膜２４のエッジより内側に形成されているため、外圧、例えばＣＭＰの加工圧が絶縁膜にかかった時、その絶縁膜のエッジにかかる圧力を第２絶縁膜２４のエッジと第１絶縁膜２３のエッジとに分散させることができるので、密着性の弱い絶縁膜のエッジ部分での膜剥がれを抑制できるという利点がある。また、第１絶縁膜２３とビア層絶縁膜２１の密着性が弱い場合であっても、第２絶縁膜２４がビア層絶縁膜２１との密着性を有する膜であれば、第１絶縁膜２３のエッジは第２絶縁膜２４のエッジより内側に形成されていることから第２絶縁膜２４とビア層絶縁膜２１との接触面積を大きくとれるため、第２絶縁膜２４とビア層絶縁膜２１との密着性を向上させることができる。この点からも、絶縁膜のエッジ部分での膜剥がれを抑制することができる。さらに、第２絶縁膜２４のエッジはビア層絶縁膜２１のエッジと同一位置に形成されていることから、第１絶縁膜２３のエッジ部分に対して力がかかりにくくなるので、たとえビア層絶縁膜２１に対して第１絶縁膜２３の密着性の弱くとも、第１絶縁膜２３のエッジ部分での膜剥がれが抑制される。このように、特に膜剥がれが発生しやすい膜周辺部の膜剥がれ耐性が高められるので、膜剥がれの防止には効果的である。したがって、歩留りの向上が図れるとともに、絶縁膜の信頼性の向上が図れる。   In the semiconductor device 1, a via layer insulating film 21 for forming a via is formed on a substrate 11, and the semiconductor device 1 has a laminated structure of a first insulating film 23 and a second insulating film 24 on the via layer insulating film 21. A wiring layer insulating film 22 for forming a layer is formed, and the edge of the first insulating film 23 is formed on the inner side of the edge of the second insulating film 24. Therefore, an external pressure, for example, a CMP processing pressure is applied to the insulating film. When applied, the pressure applied to the edge of the insulating film can be distributed to the edge of the second insulating film 24 and the edge of the first insulating film 23, so that the film peels off at the edge portion of the insulating film having low adhesion. There is an advantage that can be suppressed. Further, even if the adhesion between the first insulating film 23 and the via layer insulating film 21 is weak, the first insulating film can be used as long as the second insulating film 24 is a film having an adhesiveness with the via layer insulating film 21. Since the edge of 23 is formed on the inner side of the edge of the second insulating film 24, the contact area between the second insulating film 24 and the via layer insulating film 21 can be increased, so the second insulating film 24 and the via layer insulating film Adhesion with 21 can be improved. Also from this point, film peeling at the edge portion of the insulating film can be suppressed. Further, since the edge of the second insulating film 24 is formed at the same position as the edge of the via layer insulating film 21, it is difficult to apply a force to the edge portion of the first insulating film 23. Even if the adhesion of the first insulating film 23 to the film 21 is weak, film peeling at the edge portion of the first insulating film 23 is suppressed. In this way, the film peeling resistance in the peripheral portion of the film where the film peeling is particularly likely to occur is enhanced, which is effective in preventing the film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

次に、本発明の半導体装置に係る第２実施例を、図２の概略構成断面図によって説明する。   Next, a second embodiment of the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

図２に示すように、前記図１によって説明した構成の半導体装置１において、第１絶縁膜２３および第２絶縁膜２４を積層してなる配線層絶縁膜２２に配線溝（図示せず）を形成するとともに、ビア層絶縁膜２１にビアホール（図示せず）を形成した後、配線溝およびビアホールを埋め込むように上記配線層絶縁膜２２を覆う配線材料層２５を形成する。上記配線材料層２５には、通常、銅（Ｃｕ）を用いる。なお、図示はしないが、配線材料膜２５を形成する前に、配線溝およびビアホールの内面には銅の拡散を防止するバリア膜が形成され、またバリア膜と絶縁膜との間には必要に応じて密着性を高める密着膜が形成される。上記バリア膜には、例えば、タンタル、窒化タンタル等の膜が用いられる。例えば、バリア膜としてタンタル膜が１５ｎｍの厚さに形成されている。また、配線材料膜２５として、５０ｎｍの厚さの銅シード膜を含めて１０５０ｎｍの厚さに銅膜が形成されている。   As shown in FIG. 2, in the semiconductor device 1 having the configuration described with reference to FIG. 1, a wiring groove (not shown) is formed in a wiring layer insulating film 22 formed by laminating a first insulating film 23 and a second insulating film 24. At the same time, a via hole (not shown) is formed in the via layer insulating film 21, and then a wiring material layer 25 covering the wiring layer insulating film 22 is formed so as to fill the wiring trench and the via hole. For the wiring material layer 25, copper (Cu) is usually used. Although not shown, before the wiring material film 25 is formed, a barrier film for preventing copper diffusion is formed on the inner surfaces of the wiring groove and the via hole, and it is necessary between the barrier film and the insulating film. Accordingly, an adhesion film that enhances adhesion is formed. For example, a film of tantalum, tantalum nitride, or the like is used as the barrier film. For example, a tantalum film having a thickness of 15 nm is formed as the barrier film. Further, as the wiring material film 25, a copper film is formed to a thickness of 1050 nm including a copper seed film having a thickness of 50 nm.

上記第２絶縁膜２４のエッジ位置は上記配線材料膜２５のエッジ位置より内側になるように形成されることがより好ましいが、上記第２絶縁膜２４のエッジ位置より上記配線材料膜２５のエッジ位置が内側であってもよい。ウエハ中心からウエハ外周方向に向かって正とし、第２絶縁膜２４のエッジ位置を規準にすると、第２絶縁膜２４のエッジ位置と配線材料膜２５のエッジ位置との距離ｗ４は、−１．５ｍｍ以上２．５ｍｍ以下であればよく、より好ましくは０ｍｍ以上２．５ｍｍ以下であればよい。このｗ４の正方向の値はウエハ（基板１）外形によって決定される。またｗ４の負方向の値が大きくなりすぎると、配線材料膜が埋め込まれない配線溝やビアホールが発生することになるので好ましくはない。そこで、上記値とした。   It is more preferable that the edge position of the second insulating film 24 is formed so as to be inside the edge position of the wiring material film 25, but the edge of the wiring material film 25 is more than the edge position of the second insulating film 24. The position may be inside. If the wafer center is positive in the wafer outer peripheral direction and the edge position of the second insulating film 24 is used as a reference, the distance w4 between the edge position of the second insulating film 24 and the edge position of the wiring material film 25 is -1. It may be 5 mm or more and 2.5 mm or less, and more preferably 0 mm or more and 2.5 mm or less. The value of w4 in the positive direction is determined by the outer shape of the wafer (substrate 1). Further, if the value of w4 in the negative direction becomes too large, wiring grooves and via holes in which the wiring material film is not embedded are generated, which is not preferable. Therefore, the above values were used.

次に、本発明の半導体装置の製造方法に係る第１実施例を、図３〜図５の概略構成斜視図および概略構成断面図によって説明する。各図３〜図５では、（１）に概略構成斜視図を示し、（２）に基板直径方向の概略構成断面図を示した。なお、概略構成断面図は分かり易くするため、厚さ方向に拡大されている。また、図中の基板上に描かれている矢印は基板の回転方向の一例を示すもので、この回転方向は逆方向であってもよい。   Next, a first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to schematic configuration perspective views and schematic configuration cross-sectional views of FIGS. 3 to 5, (1) shows a schematic configuration perspective view, and (2) shows a schematic configuration sectional view in the substrate diameter direction. The schematic cross-sectional view is enlarged in the thickness direction for easy understanding. Moreover, the arrow drawn on the board | substrate in a figure shows an example of the rotation direction of a board | substrate, This rotation direction may be a reverse direction.

図３に示すように、基板１１上に絶縁膜１２を形成する。上記基板１１には、例えばシリコン基板が用いられ、図示しない半導体素子、配線等が形成されていてもよい。また上記絶縁膜１２は、酸化シリコン膜からなり、例えば５００ｎｍの厚さに形成されている。その成膜方法は、例えばプラズマＣＶＤ法による。次に、上記絶縁膜１２上にビア層絶縁膜２１を形成する。ここではビア層絶縁膜２１はＳｉＯＣ系の膜で形成する。例えば、ＳｉＯＣ膜、ＳｉＯＣ膜中に窒素もしくは水素が含まれた膜等である。上記ビア層絶縁膜２１は、例えば２００ｎｍの厚さに成膜する。この成膜方法は、一例として、平行平板型プラズマＣＶＤ装置を用い、原料ガスのシリコン源としてメチルシランを用いた。また成膜条件としては基板温度を３００℃〜４００℃に設定し、プラズマパワーを１５０Ｗ〜３５０Ｗ、成膜雰囲気の圧力を１００Ｐａ〜１０００Ｐａ程度に設定する。以下、各種絶縁膜形成した基板１１をウエハという。   As shown in FIG. 3, an insulating film 12 is formed on the substrate 11. As the substrate 11, for example, a silicon substrate is used, and a semiconductor element, wiring, etc. (not shown) may be formed. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. The film forming method is based on, for example, a plasma CVD method. Next, a via layer insulating film 21 is formed on the insulating film 12. Here, the via layer insulating film 21 is formed of a SiOC-based film. For example, a SiOC film, a film containing nitrogen or hydrogen in the SiOC film, and the like. The via layer insulating film 21 is formed to a thickness of 200 nm, for example. In this film forming method, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane is used as a silicon source of the source gas. As film forming conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film forming atmosphere is set to about 100 Pa to 1000 Pa. Hereinafter, the substrate 11 on which various insulating films are formed is referred to as a wafer.

次に上記ビア層絶縁膜２１上に第１絶縁膜２３を成膜する。この第１絶縁膜２３には、有機膜を用いた。例えば有機膜として、ポリアリールエーテル膜を、例えば１００ｎｍの厚さに形成した。上記ポリアリールエーテル膜は、例えばＳｉＬＫ（例えばＳｉＬＫ−Ｊ）（ダウケミカル社）があり、その他には、例えばアライドシグナル社製のＦＬＡＲＥ、シューマッカー社製のＶＥＲＯＸ等が知られている。例えば、上記ポリアリールエーテル膜をＳｉＬＫで形成する場合には、前駆体をスピンコート法により堆積した後、４００℃〜４５０℃のキュア処理を行って形成することができる。   Next, a first insulating film 23 is formed on the via layer insulating film 21. An organic film was used for the first insulating film 23. For example, as an organic film, a polyaryl ether film is formed to a thickness of, for example, 100 nm. Examples of the polyaryl ether film include SiLK (for example, SiLK-J) (Dow Chemical Co.), and other examples include FLARE manufactured by Allied Signal, VEROX manufactured by Schumacker, and the like. For example, when the polyaryl ether film is formed of SiLK, it can be formed by depositing the precursor by spin coating and then performing a curing process at 400 ° C. to 450 ° C.

次に、上記第１絶縁膜２３のエッジ部分を除去する。このエッジ部分の除去方法は、基板１１を図面矢印ア方向に回転させながら、ノズル４１より第１絶縁膜２３の溶剤３１を第１絶縁膜２３の除去領域（斜視図の斜線領域が除去領域となる。）上に供給するとともに、上記ノズル４１をエッジカット範囲（例えば図面矢印イ方向）内でスキャニングンすることによる。この時、図示しない純水を基板１１中心部上方より第１絶縁膜２３上に供給することにより、第１絶縁膜２３の周辺部以外の第１絶縁膜２３表面に薬液３１がかからないように保護する。上記第１絶縁膜２３がポリアリールエーテル膜である場合には、上記溶剤にはシクロヘキサノンを使用することができる。上記第１絶縁膜２３の周辺部の除去幅ｗ１は、ノズル４１のスキャニング幅を変更することにより容易に変更できる。今回、第１絶縁膜２３のエッジ除去幅ｗ１は、例えば５ｍｍに設定した。   Next, the edge portion of the first insulating film 23 is removed. In this edge portion removal method, while the substrate 11 is rotated in the direction of the arrow A, the solvent 31 of the first insulating film 23 is removed from the nozzle 41 by the removal region of the first insulating film 23 (the hatched region in the perspective view is the removal region). And the above-mentioned nozzle 41 is scanned within an edge cut range (for example, in the direction of arrow A in the drawing). At this time, pure water (not shown) is supplied onto the first insulating film 23 from above the center of the substrate 11 to protect the chemical solution 31 from being applied to the surface of the first insulating film 23 other than the peripheral portion of the first insulating film 23. To do. When the first insulating film 23 is a polyaryl ether film, cyclohexanone can be used as the solvent. The removal width w1 of the peripheral portion of the first insulating film 23 can be easily changed by changing the scanning width of the nozzle 41. This time, the edge removal width w1 of the first insulating film 23 is set to 5 mm, for example.

次に、図４に示すように、上記ビア層絶縁膜２１上および上記第１絶縁膜２３上に第２絶縁膜２４を成膜する。上記第１絶縁膜２３およびこの第２絶縁膜２４で配線層絶縁膜２２が構成される。上記第２絶縁膜２４には、酸化シリコン（ＳｉＯ2）膜を用いた。この酸化シリコン膜は、例えばプラズマＣＶＤ法によって成膜することができ、例えば２００ｎｍの厚さに成膜した。 Next, as shown in FIG. 4, a second insulating film 24 is formed on the via layer insulating film 21 and the first insulating film 23. The first insulating film 23 and the second insulating film 24 constitute a wiring layer insulating film 22. A silicon oxide (SiO 2 ) film was used as the second insulating film 24. This silicon oxide film can be formed by plasma CVD, for example, and has a thickness of 200 nm, for example.

次に、塗布法によって、上記配線層絶縁膜２２（第２絶縁膜２４）上にフォトレジスト膜５１を形成する。そして、フォトレジスト膜５１のエッジ部分を除去する。フォトレジスト膜５１のエッジ部分の除去方法は、上記フォトレジスト５１にポジ型レジストを用いた場合には、基板１１を図面矢印ウ方向に回転させながら除去したいエッジ部分のみ光Ｌを照射してフォトレジスト膜５１を感光させる（斜視図の斜線領域が感光領域となる。）。その後現像処理、リンス処理、ベーキング工程を経て、図示はしないが、エッジ部分を除去したフォトレジスト膜５１が得られる。上記フォトレジスト膜５１をネガレジストで形成した場合には、除去しない領域のみ感光処理を行い、その後、現像、リンス処理、ベーキング工程を経れば、エッジ部分が除去されたフォトレジスト膜５１が得られる。上記エッジ除去幅ｗ２は、例えば４ｍｍに設定した。   Next, a photoresist film 51 is formed on the wiring layer insulating film 22 (second insulating film 24) by a coating method. Then, the edge portion of the photoresist film 51 is removed. When a positive resist is used for the photoresist 51, the edge portion of the photoresist film 51 is irradiated with light L only on the edge portion to be removed while rotating the substrate 11 in the direction of the arrow c. The resist film 51 is exposed (the shaded area in the perspective view is the photosensitive area). Thereafter, through a development process, a rinsing process, and a baking process, although not shown, a photoresist film 51 from which an edge portion has been removed is obtained. When the photoresist film 51 is formed of a negative resist, only a region that is not to be removed is subjected to a photosensitive process, and then a development, a rinsing process, and a baking process are performed to obtain a photoresist film 51 from which the edge portion has been removed. It is done. The edge removal width w2 is set to 4 mm, for example.

次に、図５に示すように、上記第２絶縁膜２４、ビア層絶縁膜２１の順でエッチングを行い、第２絶縁膜２４およびビア層絶縁膜２１のエッジ部分を除去した。その後、上記フォトレジスト膜５１〔前記図４参照〕をアッシング処理もしくは剥離処理等により除去した。図面では、フォトレジスト膜５１を除去した後の状態を示した。この結果、基板１１のエッジより内側にｗ２だけ入った位置に上記配線層絶縁膜２２の第２絶縁膜２４およびビア層絶縁膜２１の各エッジが形成される。上記エッジ除去幅ｗ２は、ｗ１−ｗ２＝ｗ３が、例えば０．５ｍｍ以上５ｍｍ以下となるように設定される。好ましくは、ｗ３が１．５ｍｍ以上５ｍｍ以下の範囲となるように設定され、より好ましくは、１．５ｍｍ以上２ｍｍ以下の範囲となるように設定される。例えば、ｗ３が０．３ｍｍよりも小さい場合には、第２絶縁膜２４とビア層絶縁膜２１との密着性が十分に得られなくなり、ｗ３が５ｍｍを超えるとチップの理収が悪化する。このため、ｗ３は上記範囲に設定される。   Next, as shown in FIG. 5, the second insulating film 24 and the via layer insulating film 21 were etched in this order, and the edge portions of the second insulating film 24 and the via layer insulating film 21 were removed. Thereafter, the photoresist film 51 [see FIG. 4] was removed by ashing or stripping. In the drawing, the state after removing the photoresist film 51 is shown. As a result, each edge of the second insulating film 24 of the wiring layer insulating film 22 and the via layer insulating film 21 is formed at a position where only w2 enters inside the edge of the substrate 11. The edge removal width w2 is set so that w1−w2 = w3 is, for example, not less than 0.5 mm and not more than 5 mm. Preferably, w3 is set to be in a range of 1.5 mm or more and 5 mm or less, and more preferably set to be in a range of 1.5 mm or more and 2 mm or less. For example, when w3 is smaller than 0.3 mm, sufficient adhesion between the second insulating film 24 and the via layer insulating film 21 cannot be obtained, and when w3 exceeds 5 mm, the yield of the chip deteriorates. Therefore, w3 is set in the above range.

上記ビア層絶縁膜２１および配線層絶縁膜２２に溝配線およびビアを形成する場合には、上記ビア層絶縁膜２１および配線層絶縁膜２２のエッジ部分の除去を行ういずれかもしくは両方の露光工程を行った後でその露光工程に対する現像工程を行う前に、例えば配線溝、ビアホール等のパターニングを行えばよい。この場合、前記図５によって説明した第２絶縁膜２４のエッチング時には第１絶縁膜２３も同時にエッチングされる。また、溝配線とビアとを同時形成する、いわゆるデュアルダマシン構造の絶縁膜についても、本発明の構成を用いることができる。例えば、ビア層絶縁膜２１に配線間の接続を行う接続部（ビア）を形成し、配線層絶縁膜２２に溝配線を形成する。溝配線とビアとを同時形成する技術については、多くの公知例があり、例えば特開２００１−４４１８９号公報などに詳細な記述がある。これらの公知技術の絶縁膜についても、本発明の如く、ビアが形成されるビア層絶縁膜２１および配線層絶縁膜２２を構成する第１絶縁膜２３、第２絶縁膜２４の各エッジ位置を規定する構成を採用することができる。   When forming trench wirings and vias in the via layer insulating film 21 and the wiring layer insulating film 22, either or both exposure processes for removing the edge portions of the via layer insulating film 21 and the wiring layer insulating film 22 For example, wiring grooves, via holes, etc. may be patterned before performing the developing process for the exposure process. In this case, the first insulating film 23 is also etched simultaneously with the etching of the second insulating film 24 described with reference to FIG. The structure of the present invention can also be used for an insulating film having a so-called dual damascene structure in which a trench wiring and a via are formed simultaneously. For example, a connection portion (via) for connecting wirings is formed in the via layer insulating film 21, and a trench wiring is formed in the wiring layer insulating film 22. There are many known examples of the technology for simultaneously forming the trench wiring and the via. For example, JP 2001-44189A discloses a detailed description. Also for these known insulating films, the edge positions of the first insulating film 23 and the second insulating film 24 constituting the via layer insulating film 21 and the wiring layer insulating film 22 in which vias are formed, as in the present invention. A defined configuration can be employed.

次に、本発明の効果を確認した。確認方法は、前記図５に示したように、基板１１上に上記ビア層絶縁膜２１および第１絶縁膜２３と第２絶縁膜２４からなる配線層絶縁膜２２を形成したサンプルを用意し、サンプルの配線層絶縁膜２２に対してＣＭＰを行った。上記第１の絶縁膜２３としては、ＳｉＬＫ、ＦＬＡＲＥ、ｐｏｒｏｕｓ−ＳｉＬＫの３種のポリアリールエーテル膜を用い、上記第２の絶縁膜としては、ＳｉＯ2（酸化シリコン）膜、およびＢＤ（ＡＭＡＴ社製のＢＤ（ブラックダイヤモンド）でＣＶＤ法により形成した誘電率ｋ＝３．０程度のＳｉＯＣ膜）、ＢＤ２（ＡＭＡＴ社製のＢＤ（ブラックダイヤモンド）でＣＶＤ法により形成した誘電率ｋ＝２．５程度のＳｉＯＣ膜）の２種のＳｉＯＣ膜を用い、上記ビア層絶縁膜２１としては、ＳｉＯ2（酸化シリコン）膜、およびＢＤ、Ｃｏｒａｌ（Ｎｏｖｅｌｌｕｓ社製のＳｉＯＣ膜でＣＶＤ法により形成したｋ＝３．０程度のＳｉＯＣ膜）、ＢＤ２の４種のＳｉＯＣ膜を用い、それらのすべての組み合わせについて調査した。 Next, the effect of the present invention was confirmed. As a confirmation method, as shown in FIG. 5, a sample is prepared in which the via layer insulating film 21 and the wiring layer insulating film 22 including the first insulating film 23 and the second insulating film 24 are formed on the substrate 11. CMP was performed on the sample wiring layer insulating film 22. As the first insulating film 23, three kinds of polyaryl ether films of SiLK, FLARE, and porous-SiLK are used. As the second insulating film, a SiO 2 (silicon oxide) film and a BD (AMAT Corporation) are used. SiOC film having a dielectric constant k = 3.0 formed by CVD with BD (black diamond) manufactured by BD, and BD2 (dielectric constant k = 2.5 formed by CVD with BD (black diamond) manufactured by AMAT). The SiO 2 (silicon oxide) film and the BD, Coral (a novel Novellus SiOC film) are used as the via layer insulating film 21 by the CVD method. All types of SiOC films of about 3.0) and four types of SiOC films of BD2 were investigated.

また、上記各サンプルは、第２絶縁膜２４およびビア層絶縁膜２１のエッジ除去幅ｗ２は４ｍｍとし、第１絶縁膜２１のエッジカット幅ｗ１は４ｍｍ以上６ｍｍ以下の範囲で０．１ｍｍ刻みに作製した。したがって、上記サンプルは、配線層絶縁膜２２（第２絶縁膜２４）のエッジ位置とビア層絶縁膜２１のエッジ位置とが同一位置に作製されたことになり、また、第１絶縁膜２３のエッジ位置と第２絶縁膜２４のエッジ位置のとの差ｗ３＝ｗ１−ｗ２の値が０ｍｍ以上２ｍｍ以下の範囲で０．１ｍｍ刻みで作製されたことになる。   In each sample, the edge removal width w2 of the second insulating film 24 and the via layer insulating film 21 is 4 mm, and the edge cut width w1 of the first insulating film 21 is in the range of 4 mm to 6 mm in increments of 0.1 mm. Produced. Therefore, in the above sample, the edge position of the wiring layer insulating film 22 (second insulating film 24) and the edge position of the via layer insulating film 21 are formed at the same position. The difference w3 = w1−w2 between the edge position and the edge position of the second insulating film 24 is manufactured in increments of 0.1 mm within a range of 0 mm to 2 mm.

次に、上記各サンプルのそれぞれの配線層絶縁膜２２をＣＭＰした。このＣＭＰでは、研磨パッドに、例えば上層が発泡ポリウレタン製で下層がＰＥＴ（ポリエチレンテレフタレート）製のものを用いた。このような研磨パッドとしては、一例として、上層がロデール社製の厚さ１．２ｍｍのＩＣ１０００で下層が同社製の厚さ１．２ｍｍのＳＵＢＡ４００よりなる積層された研磨パッドがある。研磨液（研磨スラリー）には、アルカリ溶媒に分散したコロイダルシリカに酸化剤として過酸化水素水（Ｈ2Ｏ2）を添加したものを用いる。例えばＪＳＲ社製のＣＭＳ８３０１がある。上記研磨液の供給流量は例えば１５０ｍｌ／ｍｉｎとして、研磨パッドの回転数は例えば１００ｒｐｍ、ウエハ（基板）回転数は例えば：１１０ｒｐｍ、研磨圧力は例えば３００g／ｃｍ2,研磨時間は例えば６０ｓｅｃとした。これにより、配線層絶縁膜２２のＳｉＯ2膜の表層およそ７０ｎｍの厚さが除去された。 Next, each wiring layer insulating film 22 of each sample was subjected to CMP. In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is made of Rodale IC1000 having a thickness of 1.2 mm and the lower layer is made of SUBA400 having a thickness of 1.2 mm made by the same company. A polishing liquid (polishing slurry) obtained by adding hydrogen peroxide (H 2 O 2 ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS8301 manufactured by JSR. The polishing liquid supply flow rate is, for example, 150 ml / min, the polishing pad rotation speed is, for example, 100 rpm, the wafer (substrate) rotation speed is, for example, 110 rpm, the polishing pressure is, for example, 300 g / cm 2 , and the polishing time is, for example, 60 seconds. As a result, the thickness of the surface layer of the SiO 2 film of the wiring layer insulating film 22 was approximately 70 nm.

膜剥がれの検査は顕微鏡による目視検査により実施した。検査の結果を表１〜表４に示す。   The film peeling was inspected by visual inspection using a microscope. The results of the inspection are shown in Tables 1 to 4.

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

表１〜表４中、◎印は剥がれ無し、○印は２％以下の領域で剥がれあり、△印は２％を超え２０％以下の領域で剥がれあり、×印は２０％を超える領域で剥がれがあることを示している。上記評価において、２０％を境界にした理由は、経験的に２０％を超える領域での剥がれは、剥がれの再現性が良く、本質的なものであると考えられるためである。実際に剥がれ状態を観察すると、「剥がれ無し」、「ほぼ剥がれないが、１％程度の領域で剥がれる」、「５％〜１０％程度の領域で剥がれる」、「ほぼ全ての領域で剥がれる」の４段階にはっきりと分かれて観察され、◎，○，△，×の差は、はっきりした違いとして認められた。   In Tables 1 to 4, ◎ indicates no peeling, ○ indicates peeling in an area of 2% or less, Δ indicates peeling in an area exceeding 2% and 20% or less, and X indicates an area exceeding 20%. It shows that there is peeling. In the above evaluation, the reason why 20% is used as the boundary is that empirical peeling in an area exceeding 20% is considered to be essential because of good reproducibility of peeling. When actually observing the peeling state, “no peeling”, “almost not peeled but peeled in about 1% area”, “peeled in about 5% to 10% area”, “peeled in almost all areas” Observed in four distinct stages, the difference between ◎, ○, △, and X was recognized as a clear difference.

また、第２絶縁膜２４のエッジ位置および第１絶縁膜２３のエッジ位置は、ウエハの中心ずれ等により１枚のウエハでも設定より０．５ｍｍ程度ずれることがある。そこで、剥がれ位置における第１絶縁膜２３と第２絶縁膜２４のエッジ位置を実測することにより、第１絶縁膜２３のエッジ位置と第２絶縁膜２４のエッジ位置のとの差ｗ３の値を求めた。   In addition, the edge position of the second insulating film 24 and the edge position of the first insulating film 23 may be shifted by about 0.5 mm from the setting even for one wafer due to a wafer center shift or the like. Therefore, by actually measuring the edge positions of the first insulating film 23 and the second insulating film 24 at the peeling position, the value of the difference w3 between the edge position of the first insulating film 23 and the edge position of the second insulating film 24 is obtained. Asked.

上記表１〜表４に示すように、いずれのサンプルでもｗ３が０ｍｍ以上０．３ｍｍ未満では、剥がれの確率が２０％以上であることがわかった。また、いずれのサンプルでもｗ３が０．３ｍｍ以上０．５ｍｍ未満では、剥がれの確率が２％を超え２０％以下であることがわかった。そして、いずれのサンプルでもｗ３が０．５ｍｍ以上では、膜剥がれが２％以下であり、ｗ３が１．５ｍｍ以上では、膜剥がれが起こらないことがわかった。   As shown in the above Tables 1 to 4, it was found that in any sample, when w3 was 0 mm or more and less than 0.3 mm, the probability of peeling was 20% or more. Moreover, in any sample, when w3 was 0.3 mm or more and less than 0.5 mm, it was found that the probability of peeling was more than 2% and 20% or less. And in any sample, when w3 was 0.5 mm or more, it was found that film peeling was 2% or less, and when w3 was 1.5 mm or more, film peeling did not occur.

本発明の半導体装置の製造方法は、配線層絶縁膜２２を第１絶縁膜２３と第２絶縁膜２４との積層膜で形成し、その際、第１絶縁膜２３のエッジが第２絶縁膜２４のエッジより内側になるように形成し、第２絶縁膜２４のエッジとビア層絶縁膜２１のエッジとを一致した位置に形成するため、外圧、例えばＣＭＰの加工圧が絶縁膜にかかった時、その絶縁膜のエッジにかかる圧力を第１絶縁膜２３のエッジ部分に集中させることなく、第１絶縁膜２３のエッジと第２絶縁膜２４のエッジとに分散させることができるので、密着性の弱い絶縁膜のエッジ部分での膜剥がれを抑制することができるという利点がある。特に、第１の絶縁膜２３のエッジが第２の絶縁膜２４のエッジより０．５ｍｍ以上内側になるように形成し、第２の絶縁膜のエッジがビア層のエッジと同じになるように形成すると、剥がれが効果的に抑制することができる。なお、ウエハ上におけるチップの理収を考慮すると、ｗ３を５ｍｍ以下とすることが好ましい。また、第１絶縁膜２３とビア層絶縁膜２１の密着性が弱い場合であっても、第２絶縁膜２４がビア層絶縁膜２１との密着性を有する膜、例えば同種の膜であれば、第１絶縁膜２３のエッジは第２絶縁膜２４のエッジより内側になるように形成されていることから第２絶縁膜２４とビア層絶縁膜２１との接触面積を大きくとれるため、第２絶縁膜２４とビア層絶縁膜２１との密着性を向上させることができる。この点からも、絶縁膜のエッジ部分での膜剥がれを抑制することができる。   In the method of manufacturing a semiconductor device according to the present invention, the wiring layer insulating film 22 is formed of a laminated film of a first insulating film 23 and a second insulating film 24, and at this time, the edge of the first insulating film 23 is the second insulating film. 24, the edge of the second insulating film 24 and the edge of the via layer insulating film 21 are formed at the same position, so that an external pressure, for example, a CMP processing pressure is applied to the insulating film. At this time, the pressure applied to the edge of the insulating film can be distributed to the edge of the first insulating film 23 and the edge of the second insulating film 24 without concentrating on the edge portion of the first insulating film 23, so There is an advantage that peeling of the film at the edge portion of the insulating film having low property can be suppressed. In particular, the edge of the first insulating film 23 is formed so as to be 0.5 mm or more inside the edge of the second insulating film 24 so that the edge of the second insulating film is the same as the edge of the via layer. When formed, peeling can be effectively suppressed. In consideration of chip profit on the wafer, w3 is preferably 5 mm or less. Even if the adhesion between the first insulating film 23 and the via layer insulating film 21 is weak, if the second insulating film 24 is a film having adhesion with the via layer insulating film 21, for example, the same kind of film. Since the edge of the first insulating film 23 is formed so as to be inside the edge of the second insulating film 24, the contact area between the second insulating film 24 and the via layer insulating film 21 can be increased. The adhesion between the insulating film 24 and the via layer insulating film 21 can be improved. Also from this point, film peeling at the edge portion of the insulating film can be suppressed.

次に、本発明の半導体装置の製造方法に係る第２実施例を、図６の概略構成斜視図および概略構成断面図によって説明する。図６では、（１）に概略構成斜視図を示し、（２）に基板直径方向の概略構成断面図を示した。なお、概略構成断面図は分かり易くするため、厚さ方向に拡大されている。また、図中の基板上に描かれている矢印は基板の回転方向の一例を示すもので、この回転方向は逆方向であってもよい。   Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the schematic configuration perspective view and schematic configuration cross-sectional view of FIG. In FIG. 6, (1) shows a schematic configuration perspective view, and (2) shows a schematic configuration sectional view in the substrate diameter direction. The schematic cross-sectional view is enlarged in the thickness direction for easy understanding. Moreover, the arrow drawn on the board | substrate in a figure shows an example of the rotation direction of a board | substrate, This rotation direction may be a reverse direction.

上記第３実施例で説明したようにして、基板１１上に絶縁膜１２、ビア層絶縁膜２１、第１絶縁膜２３および第２絶縁膜２４からなる配線層絶縁膜２２を形成する。   As described in the third embodiment, the wiring layer insulating film 22 including the insulating film 12, the via layer insulating film 21, the first insulating film 23, and the second insulating film 24 is formed on the substrate 11.

次に、図示はしないが、上記配線層絶縁膜２２に溝配線を形成するとともに上記ビア層絶縁膜２１にビアホールを形成する。この配線溝およびビアホールの加工は、上記第２絶縁膜２４のエッジ部分の除去を行う露光工程を行った後で現像工程前に、例えばビアホールのパターニングを行い、そのレジストマスクを用いてエッチングを行って、第２絶縁膜２４とビア層絶縁膜２１のエッジ部分の除去とビアホールの形成を行う。その後、再度、リソグラフィー技術とエッチング技術によって、配線層絶縁膜２２に配線溝を加工する。   Next, although not shown, a trench wiring is formed in the wiring layer insulating film 22 and a via hole is formed in the via layer insulating film 21. For the processing of the wiring groove and the via hole, for example, the via hole is patterned after the exposure process for removing the edge portion of the second insulating film 24 and before the developing process, and etching is performed using the resist mask. Then, the edge portions of the second insulating film 24 and the via layer insulating film 21 are removed and via holes are formed. Thereafter, wiring grooves are processed again in the wiring layer insulating film 22 by lithography and etching techniques.

その後、図６に示すように、上記配線溝（図示せず）およびビアホール（図示せず）内にバリア膜（図示せず）を形成し、さらに配線材料膜２５を形成する。この配線材料膜２５は、例えば銅膜で形成される。   Thereafter, as shown in FIG. 6, a barrier film (not shown) is formed in the wiring trench (not shown) and via hole (not shown), and a wiring material film 25 is further formed. The wiring material film 25 is formed of, for example, a copper film.

次いで、基板１１を例えば矢印エ方向に回転させるとともにノズル４３より配線材料膜２５の溶剤３３を配線材料膜２５の除去領域（概略構成斜視図における斜線で示す領域）上に供給するとともに、上記ノズル４３をエッジ除去範囲内で例えば矢印オ方向にスキャニングンすることによる。上記溶剤３３としては、硫酸と過酸化水素水との混合液を使用することができる。この時、図示しない純水を基板１１中心部上方より第２絶縁膜２４上に供給することにより、配線材料膜２５の周辺部以外の配線材料膜２５表面に溶剤３３がかからないように保護する。上記配線材料膜２５の周辺部の除去幅ｗ５は、ノズル４３のスキャニング幅を変更することにより容易に変更できる。その後、図示はしないが、ＣＭＰによって、余剰な配線材料膜２５、バリアメタル層を除去して、溝配線とビアとを形成する。   Next, the substrate 11 is rotated in the direction of arrow D, for example, and the solvent 33 of the wiring material film 25 is supplied from the nozzle 43 onto the removal region of the wiring material film 25 (the region indicated by the oblique lines in the schematic configuration perspective view). By scanning 43 in the edge removal range, for example, in the direction of arrow E. As the solvent 33, a mixed solution of sulfuric acid and hydrogen peroxide water can be used. At this time, pure water (not shown) is supplied onto the second insulating film 24 from above the center of the substrate 11 to protect the surface of the wiring material film 25 other than the periphery of the wiring material film 25 from being exposed to the solvent 33. The removal width w5 of the peripheral portion of the wiring material film 25 can be easily changed by changing the scanning width of the nozzle 43. Thereafter, although not shown, the excess wiring material film 25 and the barrier metal layer are removed by CMP to form a trench wiring and a via.

その後、通常の研磨（ＣＭＰ）技術により、第２絶縁膜２４上の配線材料膜、バリア膜等の余剰部分を除去して、配線層絶縁膜２２に配線層（図示せず）を形成するとともにビア層絶縁膜２１にビア（図示せず）を形成する。   Thereafter, an excess portion such as a wiring material film and a barrier film on the second insulating film 24 is removed by a normal polishing (CMP) technique to form a wiring layer (not shown) on the wiring layer insulating film 22. A via (not shown) is formed in the via layer insulating film 21.

前記実施例１で説明したように、第１絶縁膜２３のエッジ位置が第２絶縁膜２４のエッジ位置より０．５ｍｍ以上〜１．５ｍｍ未満の範囲で内側になる場合、剥がれの確率は２％以下ではあるが、剥がれの発生が認められた。第１絶縁膜２３のエッジが第２絶縁膜２４のエッジより１．５ｍｍ以上内側になるようにすれば剥がれは発生しなかった。しかしながら、チップの理収の観点からエッジ除去はできるだけウエハの外側に設定したいことを考慮すると、エッジ領域はでき得る限り有効に利用したい。そこで、最適な配線材料膜２５のエッジ除去位置について調べた。   As described in the first embodiment, when the edge position of the first insulating film 23 is inward within the range of 0.5 mm to less than 1.5 mm from the edge position of the second insulating film 24, the probability of peeling is 2. The occurrence of peeling was observed although it was less than%. If the edge of the first insulating film 23 was 1.5 mm or more inside the edge of the second insulating film 24, no peeling occurred. However, considering that the edge removal should be set as much as possible outside the wafer from the viewpoint of chip acquisition, the edge region should be used as effectively as possible. Therefore, the optimum edge removal position of the wiring material film 25 was examined.

上記実施例２で説明したように、配線材料膜２５を銅膜で形成する。その際、バリア膜にはスパッタリングにより成膜した厚さが１５ｎｍのタンタル膜を用い、配線材料膜２５には、シード膜の厚さが５０ｎｍの銅膜を含めて厚さが１０５０ｎｍの銅膜を用いた。なお、第１絶縁膜２３としてＳｉＬＫ、第２絶縁膜２４として酸化シリコン（ＳｉＯ2）、ビア層絶縁膜２１として酸化シリコン（ＳｉＯ2）、ＢＤ（ＳｉＯＣ）、ＢＤ２（ＳｉＯＣ）を用いた。 As described in the second embodiment, the wiring material film 25 is formed of a copper film. At that time, a tantalum film having a thickness of 15 nm formed by sputtering is used as the barrier film, and a copper film having a thickness of 1050 nm including a copper film having a thickness of 50 nm is included in the wiring material film 25. Using. SiLK was used as the first insulating film 23, silicon oxide (SiO 2 ) was used as the second insulating film 24, and silicon oxide (SiO 2 ), BD (SiOC), and BD2 (SiOC) were used as the via layer insulating film 21.

その後、配線材料膜２５のエッジ部分を除去した。今回、配線材料膜２５のエッジ除去幅は２ｍｍ以上５ｍｍ以下で、０．５ｍｍきざみに設定した。また、第２絶縁膜２４およびビア層絶縁膜２１のエッジ除去幅ｗ２は４ｍｍに設定し、第１絶縁膜２３のエッジ除去幅ｗ１を５ｍｍに設定した。この設定により、誤差を含めても、第１絶縁膜２３のエッジ除去は、第２絶縁膜２４およびビア層絶縁膜２１のエッジ除去よりも０．５ｍｍ以上内側に設定された。   Thereafter, the edge portion of the wiring material film 25 was removed. At this time, the edge removal width of the wiring material film 25 is set to 0.5 mm in steps of 2 mm to 5 mm. The edge removal width w2 of the second insulating film 24 and the via layer insulating film 21 was set to 4 mm, and the edge removal width w1 of the first insulating film 23 was set to 5 mm. With this setting, even if an error is included, the edge removal of the first insulating film 23 is set 0.5 mm or more inside the edge removal of the second insulating film 24 and the via layer insulating film 21.

次に、上記サンプルのそれぞれの配線材料膜２５をＣＭＰした。このＣＭＰでは、研磨パッドに、例えば上層が発泡ポリウレタン製で下層がＰＥＴ（ポリエチレンテレフタレート）製のものを用いた。このような研磨パッドとしては、一例として、上層がロデール社製の厚さ１．２ｍｍのＩＣ１０００で下層が同社製の厚さ１．２ｍｍのＳＵＢＡ４００よりなる積層された研磨パッドがある。研磨液には、アルカリ溶媒に分散したコロイダルシリカに酸化剤として過酸化水素水（Ｈ2Ｏ2）を添加したものを用いる。例えばＪＳＲ社製のＣＭＳ７３０１がある。上記研磨液の供給流量は例えば２００ｍｌ／ｍｉｎとして、研磨パッドの回転数は例えば１００ｒｐｍ、ウエハ（基板）回転数は例えば：１１０ｒｐｍ、研磨圧力は例えば３００g／ｃｍ2,研磨時間は例えば１２０ｓｅｃとした。これにより、第２絶縁膜２４上の配線材料膜を完全に除去した。 Next, each wiring material film 25 of the sample was subjected to CMP. In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is made of Rodale IC1000 having a thickness of 1.2 mm and the lower layer is made of SUBA400 having a thickness of 1.2 mm made by the same company. As the polishing liquid, one obtained by adding hydrogen peroxide (H 2 O 2 ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS7301 manufactured by JSR. The polishing liquid supply flow rate is, for example, 200 ml / min, the polishing pad rotation speed is, for example, 100 rpm, the wafer (substrate) rotation speed is, for example: 110 rpm, the polishing pressure is, for example, 300 g / cm 2 , and the polishing time is, for example, 120 seconds. Thereby, the wiring material film on the second insulating film 24 was completely removed.

さらに、第２絶縁膜２４上の余剰なバリア膜をＣＭＰした。このＣＭＰでは、研磨パッドに、例えば上層が発泡ポリウレタン製で下層がＰＥＴ（ポリエチレンテレフタレート）製のものを用いた。このような研磨パッドとしては、一例として、上層がロデール社製の厚さ１．２ｍｍのＩＣ１０００で下層が同社製の厚さ１．２ｍｍのＳＵＢＡ４００よりなる積層された研磨パッドがある。研磨液には、アルカリ溶媒に分散したコロイダルシリカに酸化剤として過酸化水素水（Ｈ2Ｏ2）を添加したものを用いる。例えばＪＳＲ社製のＣＭＳ８３０１がある。上記研磨液の供給流量は例えば１５０ｍｌ／ｍｉｎとして、研磨パッドの回転数は例えば１００ｒｐｍ、ウエハ（基板）回転数は例えば：１１０ｒｐｍ、研磨圧力は例えば３００g／ｃｍ2,研磨時間は例えば６０ｓｅｃとした。これにより、第２絶縁膜２４上のバリア膜を完全に除去され、酸化シリコンからなる第２絶縁膜２４の表層およそ５０ｎｍの厚さ分だけ除去された。 Further, the excess barrier film on the second insulating film 24 was subjected to CMP. In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is made of Rodale IC1000 having a thickness of 1.2 mm and the lower layer is made of SUBA400 having a thickness of 1.2 mm made by the same company. As the polishing liquid, one obtained by adding hydrogen peroxide (H 2 O 2 ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS8301 manufactured by JSR. The polishing liquid supply flow rate is, for example, 150 ml / min, the polishing pad rotation speed is, for example, 100 rpm, the wafer (substrate) rotation speed is, for example, 110 rpm, the polishing pressure is, for example, 300 g / cm 2 , and the polishing time is, for example, 60 seconds. As a result, the barrier film on the second insulating film 24 was completely removed, and the surface layer of the second insulating film 24 made of silicon oxide was removed by a thickness of about 50 nm.

膜剥がれの検査は顕微鏡による目視検査により実施した。検査の結果を表５に示す。   The film peeling was inspected by visual inspection using a microscope. Table 5 shows the results of the inspection.

Figure 2005294722
Figure 2005294722

表５中、剥がれの評価判定規準は前記実施例１と同様であり、◎印は剥がれ無し、○印は２％以下の領域で剥がれがあることを示している。また、第２絶縁膜２４のエッジ位置および配線材料膜２５のエッジ位置ｗ４は、ウエハの中心ずれ等により１枚のウエハでも設定より０．５ｍｍ程度ずれることがある。そこで、剥がれ位置における第２絶縁膜２４と配線材料膜２５のエッジ位置を実測することにより、第２絶縁膜２４のエッジ位置と配線材料膜２５のエッジ位置のとの差ｗ４の値を求めた。   In Table 5, the evaluation criteria for peeling are the same as in Example 1. The symbol ◎ indicates no peeling, and the symbol ◯ indicates that there is peeling in an area of 2% or less. Further, the edge position w4 of the second insulating film 24 and the edge position w4 of the wiring material film 25 may be shifted by about 0.5 mm from the setting even for one wafer due to the center shift of the wafer or the like. Therefore, by measuring the edge positions of the second insulating film 24 and the wiring material film 25 at the peeling position, the value of the difference w4 between the edge position of the second insulating film 24 and the edge position of the wiring material film 25 was obtained. .

上記表５に示すように、いずれのサンプルでもｗ４が−１．５ｍｍ以上０ｍｍ未満では、剥がれが発生し、その確率が２％以下であることがわかった。また、いずれのサンプルでもｗ４が０ｍｍ以上２．５ｍｍ以下では、剥がれが起こらないことがわかった。   As shown in Table 5 above, it was found that in any sample, when w4 was −1.5 mm or more and less than 0 mm, peeling occurred and the probability thereof was 2% or less. Further, it was found that no peeling occurred in any sample when w4 was 0 mm or more and 2.5 mm or less.

上記結果から、実施例１で説明したように、第１絶縁膜２３のエッジが第２絶縁膜２４のエッジより０．５ｍｍ以上内側になるように形成し、第２絶縁膜２４のエッジがビア層絶縁膜２１のエッジと同じになるように形成し、上記実施例２で示したように、配線材料膜２５のエッジより第２絶縁膜２４のエッジが内側になるように形成すると、剥がれが効果的に抑制されることがわかった。これは、配線材料膜２５を除去した後に、第１絶縁膜２３の外側、第２絶縁膜２４の外側のそれぞれの段差部に配線材料膜２５の銅が残り、バリア膜のタンタル膜および第２絶縁膜２４の酸化シリコン膜表層のＣＭＰ時に圧力が分散し、第１絶縁膜２３のエッジに圧力が集中しないためと考えられる。よって、第１絶縁膜２３のエッジが第２絶縁膜２４のエッジより０．５ｍｍ以上内側になるように形成すればよいので、絶縁膜の剥がれを防止するとともにウエハ内のチップの理収を高めることができる。   From the above results, as described in the first embodiment, the edge of the first insulating film 23 is formed to be 0.5 mm or more inside from the edge of the second insulating film 24, and the edge of the second insulating film 24 is a via. When the layer insulating film 21 is formed so as to be the same as the edge of the layer insulating film 21 and formed so that the edge of the second insulating film 24 is inward of the edge of the wiring material film 25 as shown in the second embodiment, peeling occurs. It was found that it was effectively suppressed. This is because after the wiring material film 25 is removed, the copper of the wiring material film 25 remains at the step portions outside the first insulating film 23 and outside the second insulating film 24, and the tantalum film and the second film of the barrier film are left. This is because the pressure is dispersed during the CMP of the surface layer of the silicon oxide film of the insulating film 24 and the pressure does not concentrate on the edge of the first insulating film 23. Accordingly, the edge of the first insulating film 23 may be formed so as to be 0.5 mm or more inward from the edge of the second insulating film 24, so that the insulating film can be prevented from peeling and the yield of chips in the wafer can be increased. be able to.

次に、各種絶縁膜の密着性を調査した。下層の膜としては、酸化シリコン（ＳｉＯ2）膜、窒化シリコン（ＳｉＮ）膜、窒化炭化シリコン（ＳｉＣＮ）膜、炭化シリコン（ＳｉＣ）膜、ＳｉＯＣ膜（ＢＤ）、ＳｉＯＣ膜（Ｃｏｒａｌ：Ｎｏｖｅｌｌｕｓ社製のＳｉＯＣ膜でＣＶＤ法により形成したｋ＝３．０程度のＳｉＯＣ膜）、ＳｉＯＣ膜（ＢＤ２）、ポーラスシリカ（ＬＫＤ５１０９：エルケーディー（ＪＳＲ）社製のＭＳＱ膜でスピンコート法により形成したＭＳＱ膜）、ポーラスシリカ（例えば、ナノグラス社製のＮａｎｏｇｌａｓｓ）、ポーラスシリカ（例えば、ナノグラス社製のＮａｎｏｇｌａｓｓ−Ｅ）、ポリアリールエーテル（ＳｉＬＫ）、ポリアリールエーテル（ＦＬＡＲＥ）、ポリアリールエーテル（ｐｏｒｏｕｓ−ＳｉＬＫ）を用いた。また、上層の膜としては、酸化シリコン（ＳｉＯ2）膜、窒化シリコン（ＳｉＮ）膜、窒化炭化シリコン（ＳｉＣＮ）膜、炭化シリコン（ＳｉＣ）膜、ＳｉＯＣ膜（ＢＤ）、ＳｉＯＣ膜（Ｃｏｒａｌ）、ＳｉＯＣ膜（ＢＤ２）、ポーラスシリカ（ＬＫＤ５１０９）、ポーラスシリカ（Ｎａｎｏｇｌａｓｓ）、ポーラスシリカ（Ｎａｎｏｇｌａｓｓ−Ｅ）、ポリアリールエーテル（ＳｉＬＫ）、ポリアリールエーテル（ＦＬＡＲＥ）、ポリアリールエーテル（ｐｏｒｏｕｓ−ＳｉＬＫ）を用いた。 Next, the adhesion of various insulating films was investigated. As a lower layer film, a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, a silicon nitride carbide (SiCN) film, a silicon carbide (SiC) film, a SiOC film (BD), a SiOC film (Coral: manufactured by Novellus) MSC film formed by spin coating with an MSQ film made by SiOC film of SiOC film of about k = 3.0), SiOC film (BD2), porous silica (LKD5109: LKD (JSR)). ), Porous silica (for example, Nanoglass manufactured by Nanoglass), porous silica (for example, Nanoglass-E manufactured by Nanoglass), polyaryl ether (SiLK), polyaryl ether (FLARE), polyaryl ether (porous-SiLK) Was used. Further, as an upper layer film, a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, a silicon nitride carbide (SiCN) film, a silicon carbide (SiC) film, a SiOC film (BD), a SiOC film (Coral), For SiOC film (BD2), porous silica (LKD5109), porous silica (Nanoglass), porous silica (Nanoglass-E), polyaryl ether (SiLK), polyaryl ether (FLARE), polyaryl ether (porous-SiLK) It was.

そして、上記下層の膜の１種と上記上層の膜の１種とを選択して、積層膜を形成し、下層の膜に対する上層の膜の密着性を調べた。   Then, one type of the lower layer film and one type of the upper layer film were selected to form a laminated film, and the adhesion of the upper layer film to the lower layer film was examined.

膜剥がれの検査は顕微鏡による目視検査により実施した。検査の結果を表６〜表９に示す。   The film peeling was inspected by visual inspection using a microscope. The results of the inspection are shown in Tables 6 to 9.

表６〜表９中、◎印は剥がれ無し、○印は２％以下の領域で剥がれあり、△印は２％を超え２０％以下の領域で剥がれあり、×印は２０％を超える領域で剥がれがあることを示している。上記評価において、２０％を境界にした理由は、経験的に２０％を超える領域での剥がれは、剥がれの再現性が良く、本質的なものであると考えられるためである。実際に剥がれ状態を観察すると、「剥がれ無し」、「ほぼ剥がれないが、１％程度の領域で剥がれる」、「５％〜１０％程度の領域で剥がれる」、「ほぼ全ての領域で剥がれる」の４段階にはっきりと分かれて観察され、◎，○，△，×の差は、はっきりした違いとして認められた。   In Tables 6 to 9, ◎ indicates no peeling, ○ indicates peeling in an area of 2% or less, Δ indicates peeling in an area exceeding 2% and 20% or less, and X indicates an area exceeding 20% It shows that there is peeling. In the above evaluation, the reason why 20% is used as the boundary is that empirical peeling in an area exceeding 20% is considered to be essential because of good reproducibility of peeling. When actually observing the peeling state, “no peeling”, “almost not peeled but peeled in about 1% area”, “peeled in about 5% to 10% area”, “peeled in almost all areas” Observed in four distinct stages, the difference between ◎, ○, △, and X was recognized as a clear difference.

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

Figure 2005294722
Figure 2005294722

表６〜表９に示すように、ＢＤ２／ＳｉＯ2の界面がＳｉＯ2／ＳｉＯ2界面より密着性が弱いことがわかる。したがって、例えば、第１絶縁膜２３にＢＤ２などの無機膜、第２絶縁膜２４およびビア層絶縁膜２１がＳｉＯ2などの無機膜であっても、本発明の効果が得られることは明らかである。また、この結果から、有機絶縁膜と他の絶縁膜との密着性が、特に弱いことがわかった。すなわち、第１絶縁膜２３として有機絶縁膜を用いた場合、特に剥がれやすいと言える。したがって、本発明は、第１絶縁膜２３が有機絶縁膜であるときに特に効果的であることがわかる。 As shown in Tables 6 to 9, it can be seen that the interface of BD2 / SiO 2 is weaker than the interface of SiO 2 / SiO 2 . Therefore, for example, even if the first insulating film 23 is an inorganic film such as BD2, and the second insulating film 24 and the via layer insulating film 21 are inorganic films such as SiO 2, it is apparent that the effects of the present invention can be obtained. is there. Further, from this result, it was found that the adhesion between the organic insulating film and another insulating film was particularly weak. That is, when an organic insulating film is used as the first insulating film 23, it can be said that it is particularly easy to peel off. Therefore, it can be seen that the present invention is particularly effective when the first insulating film 23 is an organic insulating film.

次に、本発明の構成および製造方法を適用して、多層配線構造を形成した一例を、図７の概略構成断面図によって説明する。   Next, an example in which a multilayer wiring structure is formed by applying the configuration and manufacturing method of the present invention will be described with reference to the schematic configuration cross-sectional view of FIG.

図７に示すように、ビア層絶縁膜２１としてＳｉＯＣ（例えばＢＤ）膜（厚さが例えば２００ｎｍ）／ＳｉＣＮ膜（厚さが例えば３５ｎｍ）を用い、配線層絶縁膜２２として第１絶縁膜２３に有機膜を用い、第２絶縁膜２４に酸化シリコン（ＳｉＯ2）膜（成膜時の厚さが例えば２００ｎｍ、ＣＭＰ後の厚さが約１５０ｎｍ）を用いる。上記有機膜としては、ポリアリールエーテル膜を用い、ポリアリールエーテル膜としてはここではＳｉＬＫ膜（厚さが例えば１００ｎｍ）を用いた。上記第１絶縁膜２３（ＳｉＬＫ膜）のエッジ部分の除去幅は５ｍｍに設定し、第２絶縁膜２４（ＳｉＯ2膜）およびビア層絶縁膜２１のエッジ部分の除去幅は４ｍｍに設定した。また配線材料層２５のエッジ部分の除去幅を３ｍｍに設定した。そして上記実施例３および４によって説明した製造方法を用いて、図示したような５層の溝配線７１および接続部（ビア）７２を有する半導体装置の形成を行った。この結果、エッジ剥がれを起こすこと無く半導体装置を製造することができた。 As shown in FIG. 7, a SiOC (for example, BD) film (thickness, for example, 200 nm) / SiCN film (for example, 35 nm) is used as the via layer insulating film 21, and the first insulating film 23 is used as the wiring layer insulating film 22. An organic film is used for the second insulating film 24, and a silicon oxide (SiO 2 ) film (thickness at the time of film formation is, for example, 200 nm, and a thickness after CMP is about 150 nm) is used. A polyaryl ether film was used as the organic film, and a SiLK film (with a thickness of, for example, 100 nm) was used here as the polyaryl ether film. The removal width of the edge portion of the first insulating film 23 (SiLK film) was set to 5 mm, and the removal width of the edge portion of the second insulating film 24 (SiO 2 film) and the via layer insulating film 21 was set to 4 mm. The removal width of the edge portion of the wiring material layer 25 was set to 3 mm. Then, using the manufacturing method described in the third and fourth embodiments, a semiconductor device having the five-layer groove wiring 71 and the connecting portion (via) 72 as illustrated was formed. As a result, the semiconductor device could be manufactured without causing edge peeling.

本発明の半導体装置の製造方法および半導体装置は、各種半導体装置の多層配線という用途に適用することが好適である。   The semiconductor device manufacturing method and the semiconductor device of the present invention are preferably applied to the use of multilayer wiring of various semiconductor devices.

本発明の半導体装置に係る第１実施例を示した概略構成断面図である。1 is a schematic cross-sectional view showing a first embodiment of the semiconductor device of the present invention. 本発明の半導体装置に係る第２実施例を示した概略構成断面図である。FIG. 5 is a schematic cross-sectional view showing a second embodiment of the semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る一実施例を示した概略構成斜視図および概略構成断面図である。1A and 1B are a schematic configuration perspective view and a schematic configuration cross-sectional view showing an embodiment according to a method for manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る第１実施例を示した概略構成斜視図および概略構成断面図である。1A and 1B are a schematic configuration perspective view and a schematic configuration cross-sectional view showing a first embodiment according to a method of manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る第１実施例を示した概略構成斜視図および概略構成断面図である。1A and 1B are a schematic configuration perspective view and a schematic configuration cross-sectional view showing a first embodiment according to a method of manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る第２実施例を示した概略構成斜視図および概略構成断面図である。It is the schematic structure perspective view and schematic structure sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置に係る一実施例を示した概略構成断面図である。1 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention.

符号の説明Explanation of symbols

１…半導体装置、１１…基板、２１…ビア層絶縁膜、２２…配線層絶縁膜、２３…第１絶縁膜、２４…第２絶縁膜、   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Board | substrate, 21 ... Via layer insulating film, 22 ... Wiring layer insulating film, 23 ... 1st insulating film, 24 ... 2nd insulating film,

Claims (9)

基板上にビアを形成するビア層絶縁膜と、前記ビア層絶縁膜上に配線層を形成する配線層絶縁膜とを備えた半導体装置であって、
前記配線層絶縁膜は第１絶縁膜と第２絶縁膜との積層膜からなり、
前記第１絶縁膜のエッジは前記第２絶縁膜のエッジより内側になるように形成されていて、
前記配線層絶縁膜のエッジと前記ビア層絶縁膜のエッジとが一致した位置に形成されている
ことを特徴とする半導体装置。 A semiconductor device comprising a via layer insulating film for forming a via on a substrate and a wiring layer insulating film for forming a wiring layer on the via layer insulating film,
The wiring layer insulating film comprises a laminated film of a first insulating film and a second insulating film,
The edge of the first insulating film is formed to be inside the edge of the second insulating film,
The semiconductor device is characterized in that the edge of the wiring layer insulating film and the edge of the via layer insulating film coincide with each other. 前記第１絶縁膜のエッジは前記第２絶縁膜のエッジより０．５ｍｍ以上５．０ｍｍ以下の範囲で内側に形成されている
ことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein an edge of the first insulating film is formed on an inner side within a range of 0.5 mm to 5.0 mm from an edge of the second insulating film. 前記第１絶縁膜は誘電率が３未満の低誘電率膜からなる
ことを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the first insulating film is a low dielectric constant film having a dielectric constant of less than 3. 前記第１絶縁膜は有機絶縁膜で形成されている
ことを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the first insulating film is formed of an organic insulating film. 基板上にビアを形成するビア層絶縁膜を形成する工程と、
前記ビア層絶縁膜上に配線層を形成する配線層絶縁膜を形成する工程と、
前記配線層絶縁膜に凹部を形成して、該凹部に埋め込むように配線材料膜を形成した後、前記配線層絶縁膜上の余剰な配線材料膜を化学的機械研磨によって除去することで、前記凹部のみに前記配線材料膜を残して配線を形成する工程と
を備えた半導体装置の製造方法であって、
前記配線層絶縁膜を第１絶縁膜と第２絶縁膜との積層膜で形成し、
その際、前記第１絶縁膜のエッジが前記第２絶縁膜のエッジより内側になるように形成し、
前記配線層絶縁膜のエッジと前記ビア層絶縁膜のエッジとを一致した位置に形成する
ことを特徴とする半導体装置の製造方法。 Forming a via layer insulating film for forming a via on the substrate;
Forming a wiring layer insulating film on the via layer insulating film to form a wiring layer;
After forming a recess in the wiring layer insulating film and forming a wiring material film so as to be embedded in the recess, the excess wiring material film on the wiring layer insulating film is removed by chemical mechanical polishing, A method of manufacturing a semiconductor device comprising: forming a wiring leaving the wiring material film only in a recess,
Forming the wiring layer insulating film as a laminated film of a first insulating film and a second insulating film;
At that time, the edge of the first insulating film is formed to be inside the edge of the second insulating film,
The method of manufacturing a semiconductor device, wherein the edge of the wiring layer insulating film and the edge of the via layer insulating film are formed to coincide with each other. 前記第１絶縁膜のエッジを前記第２絶縁膜のエッジより０．５ｍｍ以上５ｍｍ以下の範囲で内側に形成する
ことを特徴とする請求項５記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein an edge of the first insulating film is formed on an inner side within a range of 0.5 mm or more and 5 mm or less from an edge of the second insulating film. 前記配線材料膜を形成する前に、前記第２絶縁膜のエッジが形成しようとする配線材料膜のエッジより内側になるように、前記第２絶縁膜およびビア層絶縁膜を加工する
ことを特徴とする請求項５記載の半導体装置の製造方法。 Before forming the wiring material film, the second insulating film and the via layer insulating film are processed so that the edge of the second insulating film is inside the edge of the wiring material film to be formed. A method for manufacturing a semiconductor device according to claim 5. 前記第１絶縁膜を誘電率が３未満の低誘電率膜で形成する
ことを特徴とする請求項５記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is formed of a low dielectric constant film having a dielectric constant of less than 3. 前記第１絶縁膜を有機絶縁膜で形成する
ことを特徴とする請求項５記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5, wherein the first insulating film is formed of an organic insulating film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038061A (en) * 2007-07-31 2009-02-19 Renesas Technology Corp Semiconductor wafer and manufacturing method of semiconductor device
JP2009206241A (en) * 2008-02-27 2009-09-10 Renesas Technology Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038061A (en) * 2007-07-31 2009-02-19 Renesas Technology Corp Semiconductor wafer and manufacturing method of semiconductor device
JP2009206241A (en) * 2008-02-27 2009-09-10 Renesas Technology Corp Semiconductor device
JP4646993B2 (en) * 2008-02-27 2011-03-09 ルネサスエレクトロニクス株式会社 Semiconductor device

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