JP2005251873A - 半導体集積回路およびその製造方法 - Google Patents
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Abstract
Description
タ形成すると、高精度に電流マッチングの取れたCMOSインバータをより小さい面積で構成することができる。また、本発明の製造方法は、通常使われているプロセスのみを用いているので、高集積・高密度化された半導体集積回路を安価に提供することが可能になる。
VD酸化膜15を平坦化する。この時、CVD酸化膜がシリコン層の厚い領域に残るようにする。
膜 9a 選択酸化領域 10 酸化保護膜 11 レジスト膜 12 コンタクトメタル層 13、15、16 CVD酸化膜 14 シリコン支持基板
Claims (18)
- 起立した半導体よりなる起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して形成されたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル領域の両側面に形成されたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを同一基板上に複数個有する半導体集積回路において、2種類の異なる高さの起立薄膜横方向チャネル領域の二重ゲートMOS電界効果トランジスタを含むことを特徴とする半導体集積回路。
- 高さの高い方の起立薄膜横方向チャネル領域を有するトランジスタがpチャネルMOS電界効果トランジスタであり、高さの低い方の起立薄膜横方向チャネル領域を有するトランジスタがnチャネルMOS電界効果トランジスタであることを特徴とする請求項1に記載の半導体集積回路。
- 高さの高い方の起立薄膜横方向チャネル領域を有する二重ゲートMOS電界効果トランジスタの一対のゲート電極は互いに電気的に独立であり、高さの低い方の起立薄膜横方向チャネル領域を有する二重ゲートMOS電界効果トランジスタの一対のゲート電極は電気的に接続されていることを特徴とする請求項1または2に記載の半導体集積回路。
- 高さの異なる起立薄膜横方向チャネル領域の頂部が同じ平面上にあることを特徴とする請求項1または2に記載の半導体集積回路。
- 各二重ゲートMOS電界効果トランジスタの一対のゲート電極は互いに電気的に独立であることを特徴とする請求項1、2または4に記載の半導体集積回路。
- 各二重ゲートMOS電界効果トランジスタの一対のゲート絶縁膜の膜厚が異なることを特徴とする請求項1から5のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域、前記ソース領域および前記ドレイン領域が結晶シリコンにより形成されていることを特徴とする請求項1から6のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域、前記ソース領域および前記ドレイン領域がSOI基板のシリコン層により形成されていることを特徴とする請求項1から6のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域のゲート絶縁膜に接する面が(111)方位の面であることを特徴とする請求項7または8に記載の半導体集積回路。
- 請求項1から9のいずれかに記載された半導体集積回路を重ねて多層構造としたことを特徴とする半導体集積回路。
- 支持基板上に形成された所定の層厚を有する半導体層を部分的に除去して層厚の薄い低高さ領域を部分的に形成する工程と、所定の層厚を有する半導体層領域と前記低高さ領域とにそれぞれ起立した半導体層よりなる起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して設けられたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル両側面に設けられたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを形成する工程と、を有することを特徴とする半導体集積回路の製造方法。
- 支持基板上に形成された所定の層厚を有する半導体層を部分的に除去して層厚の薄い低高さ領域を部分的に形成する工程と、絶縁膜を堆積し、該絶縁膜を研磨して該絶縁膜の表面を平坦化する工程と、前記絶縁膜上に第2支持基板を貼り合わせる工程と、前記支持基板を除去する工程と、所定の層厚を有する半導体層領域と前記低高さ領域とにそれぞれ起立した半導体層よりなる起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して設けられたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル両側面に設けられたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを形成する工程と、を有することを特徴とする半導体集積回路の製造方法。
- 支持基板上に形成された所定の層厚を有する半導体層を部分的に除去して層厚の薄い低高さ領域を部分的に形成する工程と、所定の層厚を有する半導体層領域と前記低高さ領域とにそれぞれ起立した半導体層よりなる起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して設けられたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル両側面に設けられたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを形成する工程と、絶縁層を堆積し、該絶縁層を研磨して該絶縁層の表面を平坦化する工程と、二つの前記絶縁層を貼り合わせることにより前記二重ゲートMOS電界効果トランジスタを多層化する工程と、を有することを特徴とする半導体集積回路の製造方法。
- 前記低高さ領域を部分的に形成する工程と前記二重ゲートMOS電界効果トランジスタを形成する工程との間に、絶縁膜を堆積し、該絶縁膜を研磨して該絶縁膜の表面を平坦化する工程と、前記絶縁膜上に第2支持基板を貼り合わせる工程と、前記支持基板を除去する工程と、が挿入されることを特徴とする請求項13に記載の半導体集積回路の製造方法。
- 前記低高さ領域を部分的に形成する工程が、部分的に熱酸化膜を形成する工程と、該熱酸化膜を除去する工程とを含むことを特徴とする請求項11から14のいずれかに記載の半導体集積回路の製造方法。
- 前記二重ゲートMOS電界効果トランジスタを形成する工程が、起立薄膜横方向チャネル領域、ソース領域およびドレイン領域の形成予定領域上を覆うマスクを形成する工程と、該マスクにより保護されない領域をエッチング除去して起立薄膜横方向チャネル領域、ソース領域およびドレイン領域を形成する工程と、前記起立薄膜横方向チャネル領域の両側面にゲート絶縁膜を形成する工程と、前記起立薄膜横方向チャネル領域の両側面に形成されたゲート絶縁膜上にそれぞれゲート電極を形成する工程と、を含むことを特徴とする請求項11から15のいずれかに記載の半導体集積回路の製造方法。
- 所定の層厚を有する半導体層の領域に形成されるソース・ドレイン領域にp型の不純物を、低高さ領域に形成されるソース・ドレイン領域にn型の不純物を導入する工程が付加されることを特徴とする請求項16に記載の半導体集積回路の製造方法。
- 前記半導体層が(110)面を主面とする単結晶シリコン層であって、前記起立薄膜横方向チャネル領域のチャネル方向が<112>方向であることを特徴とする請求項11から17のいずれかに記載の半導体集積回路の製造方法。
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Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
KR100576361B1 (ko) * | 2004-03-23 | 2006-05-03 | 삼성전자주식회사 | 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법 |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US7723805B2 (en) * | 2006-01-10 | 2010-05-25 | Freescale Semiconductor, Inc. | Electronic device including a fin-type transistor structure and a process for forming the electronic device |
US7754560B2 (en) * | 2006-01-10 | 2010-07-13 | Freescale Semiconductor, Inc. | Integrated circuit using FinFETs and having a static random access memory (SRAM) |
US7709303B2 (en) * | 2006-01-10 | 2010-05-04 | Freescale Semiconductor, Inc. | Process for forming an electronic device including a fin-type structure |
JP4490927B2 (ja) * | 2006-01-24 | 2010-06-30 | 株式会社東芝 | 半導体装置 |
WO2008007331A2 (en) * | 2006-07-11 | 2008-01-17 | Nxp B.V. | Semiconductor devices and methods of manufacture thereof |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8368144B2 (en) * | 2006-12-18 | 2013-02-05 | Infineon Technologies Ag | Isolated multigate FET circuit blocks with different ground potentials |
FR2911004B1 (fr) * | 2006-12-28 | 2009-05-15 | Commissariat Energie Atomique | Procede de realisation de transistors a double-grille asymetriques permettant la realisation de transistors a double-grille asymetriques et symetriques sur un meme substrat |
US7838948B2 (en) * | 2007-01-30 | 2010-11-23 | Infineon Technologies Ag | Fin interconnects for multigate FET circuit blocks |
US7612405B2 (en) * | 2007-03-06 | 2009-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication of FinFETs with multiple fin heights |
US7575976B2 (en) * | 2007-03-28 | 2009-08-18 | Intel Corporation | Localized spacer for a multi-gate transistor |
US7560785B2 (en) * | 2007-04-27 | 2009-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having multiple fin heights |
US8048723B2 (en) * | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
US8106459B2 (en) | 2008-05-06 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having dielectric punch-through stoppers |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8263462B2 (en) * | 2008-12-31 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric punch-through stoppers for forming FinFETs having dual fin heights |
US8293616B2 (en) | 2009-02-24 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of fabrication of semiconductor devices with low capacitance |
US8420455B2 (en) | 2010-05-12 | 2013-04-16 | International Business Machines Corporation | Generation of multiple diameter nanowire field effect transistors |
US8298913B2 (en) | 2010-10-12 | 2012-10-30 | International Business Machines Corporation | Devices with gate-to-gate isolation structures and methods of manufacture |
US8455330B2 (en) * | 2010-10-12 | 2013-06-04 | International Business Machines Corporation | Devices with gate-to-gate isolation structures and methods of manufacture |
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US9530654B2 (en) * | 2013-04-15 | 2016-12-27 | Globalfoundaries Inc. | FINFET fin height control |
TWI552232B (zh) * | 2013-11-25 | 2016-10-01 | Nat Applied Res Laboratories | The Method and Structure of Fin - type Field Effect Transistor |
US9418903B2 (en) * | 2014-05-21 | 2016-08-16 | Globalfoundries Inc. | Structure and method for effective device width adjustment in finFET devices using gate workfunction shift |
KR102255174B1 (ko) * | 2014-10-10 | 2021-05-24 | 삼성전자주식회사 | 활성 영역을 갖는 반도체 소자 및 그 형성 방법 |
US10177240B2 (en) * | 2015-09-18 | 2019-01-08 | International Business Machines Corporation | FinFET device formed by a replacement metal-gate method including a gate cut-last step |
CN105336766A (zh) * | 2015-10-22 | 2016-02-17 | 上海华虹宏力半导体制造有限公司 | 局部减薄soi顶层硅厚度的方法 |
KR102480447B1 (ko) | 2015-11-20 | 2022-12-22 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN105489637B (zh) * | 2015-11-27 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | 半导体结构的形成方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS648662A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Supplementary semiconductor device |
JP3607431B2 (ja) | 1996-09-18 | 2005-01-05 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPH11145481A (ja) | 1997-11-06 | 1999-05-28 | Denso Corp | 半導体基板およびその製造方法 |
US6448615B1 (en) | 1998-02-26 | 2002-09-10 | Micron Technology, Inc. | Methods, structures, and circuits for transistors with gate-to-body capacitive coupling |
JP4332925B2 (ja) | 1999-02-25 | 2009-09-16 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP2000340795A (ja) | 1999-05-26 | 2000-12-08 | Sony Corp | 半導体論理素子およびそれを用いた論理回路 |
JP3616534B2 (ja) | 1999-09-30 | 2005-02-02 | 沖電気工業株式会社 | 半導体基板の製造方法 |
JP3543117B2 (ja) | 2001-03-13 | 2004-07-14 | 独立行政法人産業技術総合研究所 | 二重ゲート電界効果トランジスタ |
JP4870288B2 (ja) | 2001-09-11 | 2012-02-08 | シャープ株式会社 | 半導体装置およびその製造方法と集積回路と半導体システム |
JP4265882B2 (ja) | 2001-12-13 | 2009-05-20 | 忠弘 大見 | 相補型mis装置 |
JP4137459B2 (ja) | 2002-02-07 | 2008-08-20 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
US6632712B1 (en) | 2002-10-03 | 2003-10-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating variable length vertical transistors |
US6842048B2 (en) * | 2002-11-22 | 2005-01-11 | Advanced Micro Devices, Inc. | Two transistor NOR device |
US7087499B2 (en) * | 2002-12-20 | 2006-08-08 | International Business Machines Corporation | Integrated antifuse structure for FINFET and CMOS devices |
US6911383B2 (en) * | 2003-06-26 | 2005-06-28 | International Business Machines Corporation | Hybrid planar and finFET CMOS devices |
US7709303B2 (en) * | 2006-01-10 | 2010-05-04 | Freescale Semiconductor, Inc. | Process for forming an electronic device including a fin-type structure |
-
2004
- 2004-03-02 JP JP2004058110A patent/JP4852694B2/ja not_active Expired - Lifetime
-
2005
- 2005-02-15 KR KR1020050012377A patent/KR100758759B1/ko not_active IP Right Cessation
- 2005-03-01 US US11/067,699 patent/US7382020B2/en not_active Expired - Fee Related
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JP2008141177A (ja) * | 2006-11-30 | 2008-06-19 | Internatl Business Mach Corp <Ibm> | 異なる垂直寸法のフィンを有するトリプル・ゲート・フィンfetおよびダブル・ゲート・フィンfet |
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US8537603B2 (en) | 2009-07-29 | 2013-09-17 | National Institute Of Advanced Industrial Science And Technology | SRAM cell |
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US7382020B2 (en) | 2008-06-03 |
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KR100758759B1 (ko) | 2007-09-14 |
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