JP2005243689A - Method of manufacturing semiconductor chip and semiconductor device - Google Patents

Method of manufacturing semiconductor chip and semiconductor device Download PDF

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JP2005243689A
JP2005243689A JP2004047940A JP2004047940A JP2005243689A JP 2005243689 A JP2005243689 A JP 2005243689A JP 2004047940 A JP2004047940 A JP 2004047940A JP 2004047940 A JP2004047940 A JP 2004047940A JP 2005243689 A JP2005243689 A JP 2005243689A
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recess
insulating film
film
semiconductor
manufacturing
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Makoto Hasegawa
真 長谷川
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Canon Inc
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Canon Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor chip having a semiconductor element which assures good property without undergoing the influence of a heat treatment when an insulating film is formed for insulating a through electrode and a silicon substrate. <P>SOLUTION: To form the semiconductor chip 50 having the through electrode 33a, a recess 20 is formed in a predetermined depth to a silicon substrate 10. Then, a side wall insulating film 21 is formed for insulating through electrode 33a and a silicon substrate 10 exposed in the recess 20. After the side wall insulating film 21 is formed, the semiconductor element 6 is formed on the front surface of the silicon substrate 10. Then, the recess 20 is filled up with the through electrode film 33 made of a conductive material, and by grinding from the rear surface side of the silicon substrate 10, the conductive material in the recess 20 is exposed to the rear surface, and the through hold 33a is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、積層されたチップ同士を電気的に接続するための貫通電極を備えた半導体チップの製造方法および半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor chip and a semiconductor device having a through electrode for electrically connecting stacked chips.

従来、複数の半導体チップを三次元的に積層して高集積化を図った半導体装置が知られている。その一例として、特許文献１がある。   Conventionally, a semiconductor device in which a plurality of semiconductor chips are three-dimensionally stacked to achieve high integration is known. One example is Patent Document 1.

図６は、特許文献１において示されている半導体チップが積層されて構成された半導体装置の一例を示す模式図である。図６において、１０はＳｉウエハ、１７は貫通電極、２６はチップ裏面に設けられたパッシベーション層、３１はチップ、３２はバリアメタル、３３はハンダ、３４は下部基板である。支持基板として用意された基板３４上に２枚の異なる機能を有する半導体チップ３１が積層され、それらが例えば樹脂材料(不図示)によってパッケージングされている。各半導体チップ３１には、その基板を貫通する貫通孔に導電性材料を充填することにより設けられた貫通電極１７が形成されており、この貫通電極１７および貫通電極１７の端部に設けられたハンダ３３を介して半導体チップ３１同士の電気的な接続が行われている。なお、このような貫通電極１３３は、「スループラグ」と呼ばれることもある。このような構成によれば、半導体チップの外周部に形成されたパッドをワイヤーボンドして電気的な接続を行っていた従来の構成と比較して配線の短縮化が図られるため、ワイヤーの寄生容量に起因した誤作動が発生しにくくなるという利点がある。   FIG. 6 is a schematic diagram illustrating an example of a semiconductor device configured by stacking the semiconductor chips disclosed in Patent Document 1. In FIG. In FIG. 6, 10 is a Si wafer, 17 is a through electrode, 26 is a passivation layer provided on the back surface of the chip, 31 is a chip, 32 is a barrier metal, 33 is solder, and 34 is a lower substrate. Two semiconductor chips 31 having different functions are stacked on a substrate 34 prepared as a support substrate, and these are packaged by, for example, a resin material (not shown). Each semiconductor chip 31 is provided with a through electrode 17 provided by filling a through hole penetrating the substrate with a conductive material. The through electrode 17 and the end of the through electrode 17 are provided. The semiconductor chips 31 are electrically connected to each other through the solder 33. Such a through electrode 133 is sometimes called a “through plug”. According to such a configuration, the wiring can be shortened as compared with the conventional configuration in which the pads formed on the outer peripheral portion of the semiconductor chip are wire-bonded to perform electrical connection. There is an advantage that malfunction caused by the capacity is less likely to occur.

このような半導体装置の製造方法において、特許文献１には、図７、８に示すような工程により製造される例が示されている。   In such a method of manufacturing a semiconductor device, Patent Document 1 shows an example of manufacturing by a process as shown in FIGS.

まず、図７（ａ）に示すように、Ｓｉウェハ１０に素子分離絶縁膜１１および半導体素子１２を形成した後、半導体素子１２を保護する絶縁膜１３を形成する。   First, as shown in FIG. 7A, after the element isolation insulating film 11 and the semiconductor element 12 are formed on the Si wafer 10, the insulating film 13 for protecting the semiconductor element 12 is formed.

次いで、図７（ｂ）に示すように、スループラグを形成するため、絶縁膜１３上にレジスト膜１４を形成する。レジスト膜１４は、開口部内にレジスト膜が形成され、開口部がリング状の形状である。そして、レジスト膜１４をマスクに絶縁膜１３およびＳｉウェハ１０をエッチングして、内部に凸状のＳｉウェハ１０ａが残存する凹部１５を形成する。   Next, as shown in FIG. 7B, a resist film 14 is formed on the insulating film 13 in order to form a through plug. The resist film 14 has a resist film formed in the opening, and the opening has a ring shape. Then, the insulating film 13 and the Si wafer 10 are etched using the resist film 14 as a mask to form a recess 15 in which the convex Si wafer 10a remains.

次いで、図７（ｃ）に示すように、レジスト膜１４を除去した後、ＣＶＤ法等を用いて、凹部１５の表面を覆うシリコン酸化膜１６を堆積する。   Next, as shown in FIG. 7C, after the resist film 14 is removed, a silicon oxide film 16 that covers the surface of the recess 15 is deposited by CVD or the like.

次いで、図７（ｄ）に示すように、スパッタ法等を用いて、ＴａＮ膜（不図示）、およびシード層となるＣｕ膜を堆積した後、電解メッキ法を用いて凹部１５内が埋め込まれるようにＣｕ膜１７を形成する。   Next, as shown in FIG. 7D, after depositing a TaN film (not shown) and a Cu film to be a seed layer using a sputtering method or the like, the inside of the recess 15 is embedded using an electrolytic plating method. Thus, the Cu film 17 is formed.

次いで、図８（ｅ）に示すように、ダマシン技術を用いて絶縁膜１３上のシリコン酸化膜１６、ＴａＮ膜およびＣｕ膜１７を除去して、凹部１５内にチップスループラグ（接続プラグ）１７を埋め込み形成する。   Next, as shown in FIG. 8E, the silicon oxide film 16, the TaN film, and the Cu film 17 on the insulating film 13 are removed using damascene technology, and a chip through plug (connection plug) 17 is formed in the recess 15. Embedded.

次いで、図８（ｆ）に示すように、絶縁膜１３上にチップスループラグ１７および半導体素子１２に接続する配線１８を形成する。そして、層間絶縁膜１９を堆積した後、配線１８に接続するプラグ２０を形成する。層間絶縁膜１９上に配線２１、層間絶縁膜２２およびプラグ２３を形成した後、パッド２４およびポリイミドからなる保護膜２５を形成する。   Next, as illustrated in FIG. 8F, the chip through plug 17 and the wiring 18 connected to the semiconductor element 12 are formed on the insulating film 13. Then, after depositing the interlayer insulating film 19, a plug 20 connected to the wiring 18 is formed. After the wiring 21, the interlayer insulating film 22, and the plug 23 are formed on the interlayer insulating film 19, a pad 24 and a protective film 25 made of polyimide are formed.

チップのダイソートおよびバーインをウェハ状態で行った後、図７（ｇ）に示すように、Ｓｉウェハ１０の裏面側に対して研削およびＲＩＥを行って、チップスループラグ１７を露出させる。そして、Ｓｉウェハ１０の裏面にパッシベーション層２６を形成した後、パッシベーション層２６をエッチングしチップスループラグ１７を露出させる。このような工程によって、図６の半導体装置を得ることができる。
特開２００２−１１００８９７号公報 After die sort and burn-in of the chip are performed in the wafer state, as shown in FIG. 7G, the back side of the Si wafer 10 is ground and RIE to expose the chip through plug 17. Then, after forming a passivation layer 26 on the back surface of the Si wafer 10, the passivation layer 26 is etched to expose the chip through plug 17. Through such steps, the semiconductor device in FIG. 6 can be obtained.
JP 2002-10000897 A

しかしながら、上述した従来の製造方法は、予め半導体素子が形成された半導体基板に凹部を形成した後、凹部の内壁に絶縁材料からなる側壁絶縁膜を形成し、貫通電極用の導電性材料を充填するものであるため、側壁絶縁膜を形成する際の熱処理によって半導体素子が損傷し、または、半導体素子を構成する各構造部の特性が変化して、半導体素子の特性が劣化するおそれがあった。これに対して、半導体素子の特性を劣化させない程度の温度で熱処理を行った場合、良好な絶縁性を備える側壁絶縁膜を形成することが困難である。   However, in the conventional manufacturing method described above, a recess is formed in a semiconductor substrate on which a semiconductor element has been formed in advance, and then a sidewall insulating film made of an insulating material is formed on the inner wall of the recess and filled with a conductive material for a through electrode. As a result, the semiconductor element may be damaged by the heat treatment in forming the sidewall insulating film, or the characteristics of each structural part constituting the semiconductor element may be changed to deteriorate the characteristics of the semiconductor element. . On the other hand, when heat treatment is performed at a temperature that does not deteriorate the characteristics of the semiconductor element, it is difficult to form a sidewall insulating film having good insulating properties.

そこで本発明の目的は、貫通電極と半導体基板とを絶縁するための絶縁膜を形成する際の熱処理の影響を受けることなく良好な特性を確保した半導体素子を有する半導体チップの製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor chip having a semiconductor element that ensures good characteristics without being affected by heat treatment when forming an insulating film for insulating a through electrode and a semiconductor substrate. There is.

上記目的を達成するため、本発明による半導体チップの製造方法は、半導体基板に、複数の半導体素子と、絶縁膜で絶縁された貫通電極とが形成された半導体チップの製造方法において、前記絶縁膜を成膜する工程を、前記半導体素子を形成する工程より前に行うことを特徴とする。   In order to achieve the above object, a method for manufacturing a semiconductor chip according to the present invention includes: a method for manufacturing a semiconductor chip in which a plurality of semiconductor elements and a through electrode insulated by an insulating film are formed on a semiconductor substrate; The step of forming a film is performed before the step of forming the semiconductor element.

本発明の半導体チップの製造方法によれば、従来、半導体素子を形成した後に行っていた絶縁膜の形成を、半導体素子を形成する前に行うようにしたため、絶縁膜を形成する際の熱処理の影響を受けることなく半導体素子が形成される。   According to the method for manufacturing a semiconductor chip of the present invention, since the formation of the insulating film, which has been conventionally performed after the semiconductor element is formed, is performed before the semiconductor element is formed, the heat treatment at the time of forming the insulating film is performed. The semiconductor element is formed without being affected.

上述したように本発明の半導体チップの製造方法によれば、貫通電極を少なくとも周辺の半導体領域との絶縁を取るための絶縁膜を形成する際の熱処理の影響を受けることなく半導体素子が形成されるため、半導体チップの半導体素子の特性が良好に確保される。   As described above, according to the semiconductor chip manufacturing method of the present invention, the semiconductor element is formed without being affected by the heat treatment when forming the insulating film for insulating the through electrode from at least the surrounding semiconductor region. Therefore, the characteristics of the semiconductor element of the semiconductor chip are ensured satisfactorily.

以下、本発明の実施の形態について図面を参照して説明する。また半導体基板として、シリコンを例にあげて説明する。
（第１の実施形態）
図１は、本発明の第１の実施形態による、半導体チップを製造する工程を説明するための断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The semiconductor substrate will be described using silicon as an example.
(First embodiment)
FIG. 1 is a cross-sectional view for explaining a process of manufacturing a semiconductor chip according to the first embodiment of the present invention.

以下に説明する製造方法によって製造される半導体チップ５０は、図１（ｆ）に示すように、シリコン基板１０の表面に形成された複数の半導体素子６（図では１つのみが示されている）と、シリコン基板１０を貫通する貫通孔の内壁に順次形成された側壁絶縁膜２１、層間絶縁膜２３、および金属膜３２と、同貫通孔内に充填された導電性材料からなる貫通電極３３aとを有している。   As shown in FIG. 1F, a semiconductor chip 50 manufactured by the manufacturing method described below has a plurality of semiconductor elements 6 (only one is shown in the figure) formed on the surface of the silicon substrate 10. ), A sidewall insulating film 21, an interlayer insulating film 23, and a metal film 32 sequentially formed on the inner wall of the through hole penetrating the silicon substrate 10, and a through electrode 33a made of a conductive material filled in the through hole. And have.

このような半導体チップ５０を製造するため、まず、図１（ａ）に示すように、シリコン基板１０（以下、単に「基板１０」という）上に形成したレジスト１１をマスクとして、シリコン基板１０に所定の深さで凹部２０を形成する。   In order to manufacture such a semiconductor chip 50, first, as shown in FIG. 1A, a resist 11 formed on a silicon substrate 10 (hereinafter simply referred to as “substrate 10”) is used as a mask to form a silicon substrate 10. The recess 20 is formed with a predetermined depth.

凹部２０の形成には、フッ素系あるいは塩素系ガスを用いた汎用的なドライエッチング技術を適用できるが、高速な深堀（Deep）エッチングが可能なＩＣＰ−ＲＩＥ（inductively coupled plasma reactive ion etching ：誘導結合プラズマ‐反応性イオンエッチング）がより好ましい。ＩＣＰエッチングを利用する場合、高いアスペクト比で凹部２０を高速に加工することができるボッシュプロセスや、−１００℃以下の低温条件でスムーズに側壁を形成することができるクライオジェニックプロセスを適用してもよい。   A general-purpose dry etching technique using a fluorine-based or chlorine-based gas can be applied to form the recess 20, but ICP-RIE (inductively coupled plasma reactive ion etching) capable of high-speed deep etching (inductive coupling) Plasma-reactive ion etching) is more preferred. When using ICP etching, a Bosch process that can process the recess 20 at a high speed with a high aspect ratio or a cryogenic process that can smoothly form sidewalls at a low temperature of −100 ° C. or lower can be applied. Good.

次いで、図１（ｂ）に示すように、基板１０の表面の一部、具体的には、半導体素子６が形成される領域に対応する位置に素子被覆膜２１ａを形成した後、凹部２０の内壁全体と基板１０の表面全体とに、絶縁材料からなる側壁絶縁膜２１を形成する。   Next, as shown in FIG. 1B, after forming an element coating film 21 a at a part of the surface of the substrate 10, specifically, at a position corresponding to a region where the semiconductor element 6 is formed, the recess 20 A sidewall insulating film 21 made of an insulating material is formed on the entire inner wall and the entire surface of the substrate 10.

側壁絶縁膜２１は、熱酸化処理を行うことによって熱酸化膜として形成してもよい。また、熱酸化の一種であるＰＹＲＯ酸化を適用することにより、比較的厚い膜厚の熱酸化膜を形成することができる。より具体的には、例えば、１１５０℃の温度条件で３０分間ＰＹＲＯ酸化を行うことにより、０．４μｍ程度の熱酸化膜を形成してもよい。側壁絶縁膜２１を熱酸化膜として形成する場合、素子被覆膜２１ａは例えば窒化膜として形成すればよい。このように、窒化膜からなる素子被覆膜２１ａを形成した後に熱酸化を行って側壁絶縁膜２１を形成することにより、側壁絶縁膜２１が素子被覆膜２１ａ上に形成されない。なお、側壁絶縁膜２１の膜厚（特に凹部２０内の側壁に形成される部分の膜厚）は、良好な絶縁特性を有し、ピンホールのない膜厚であれば特に限定されるものではないが、０．１μｍ〜５μｍ程度が好ましい。この理由は、膜厚が０．１μｍ未満ではピンホールのない膜を得ることが困難であり、逆に、５μｍを超える場合では膜自体の材料の内部応力や、シリコンかならなる基板１０との線膨張係数の差に起因してクラックが発生するといった問題が起こりやすいためである。   The sidewall insulating film 21 may be formed as a thermal oxide film by performing a thermal oxidation process. Further, by applying PYRO oxidation, which is a kind of thermal oxidation, a relatively thick thermal oxide film can be formed. More specifically, for example, a thermal oxide film of about 0.4 μm may be formed by performing PYRO oxidation for 30 minutes under a temperature condition of 1150 ° C. When the sidewall insulating film 21 is formed as a thermal oxide film, the element coating film 21a may be formed as a nitride film, for example. As described above, the sidewall insulating film 21 is not formed on the element covering film 21a by forming the sidewall insulating film 21 by performing thermal oxidation after forming the element covering film 21a made of a nitride film. The film thickness of the side wall insulating film 21 (particularly the film thickness of the portion formed on the side wall in the recess 20) is not particularly limited as long as it has good insulating properties and no pinholes. However, it is preferably about 0.1 μm to 5 μm. This is because if the film thickness is less than 0.1 μm, it is difficult to obtain a film without a pinhole. Conversely, if it exceeds 5 μm, the internal stress of the material of the film itself or the substrate 10 made of silicon This is because a problem that cracks occur due to the difference in linear expansion coefficient is likely to occur.

次いで、図１（ｃ）に示すように、前工程で形成した素子被覆膜２１ａを除去して側壁絶縁膜２１に開口部を形成し、それにより露出した基板１０の表面に、例えばＭＯＳトランジスタやパイボーラトランジスタ等の半導体素子６を形成する。その後、半導体素子６を覆うように層間絶縁膜２３を形成する。   Next, as shown in FIG. 1C, the element coating film 21a formed in the previous step is removed to form an opening in the sidewall insulating film 21, and an MOS transistor, for example, is formed on the surface of the substrate 10 exposed thereby. Then, a semiconductor element 6 such as a bipolar transistor is formed. Thereafter, an interlayer insulating film 23 is formed so as to cover the semiconductor element 6.

層間絶縁膜２３は、例えば常温ＣＶＤを利用してＢＰＳＧ膜として形成可能であり、常温ＣＶＤは例えば４８０℃の温度条件で６０秒間の処理で行われる。このように半導体素子６の形成を、側壁絶縁膜２１を形成した後に行うことによって、半導体素子６は、側壁絶縁膜２１を形成する際の熱処理の影響を受けることなく形成される。   The interlayer insulating film 23 can be formed as a BPSG film using, for example, room temperature CVD, and room temperature CVD is performed, for example, at a temperature condition of 480 ° C. for 60 seconds. As described above, the semiconductor element 6 is formed after the sidewall insulating film 21 is formed, so that the semiconductor element 6 is formed without being affected by the heat treatment when the sidewall insulating film 21 is formed.

次いで、図１（ｄ）に示すように、凹部２０内に導電性材料を充填する。ここで、導電性材料としては、たとえばアルミ、タングステン、銅、銀、金等の金属材料を用いることができ、また、その充填方法としては、メッキ法やメタルＣＶＤ、金属の樹脂分散ペーストを塗布する方法を利用することが可能である。メッキ法を利用する場合、メッキのベースとなる金属をスパッタリング法などにより成膜し、その後に電解メッキを行うことにより、凹部２０内に導電性材料が充填される。   Next, as shown in FIG. 1 (d), the recess 20 is filled with a conductive material. Here, as the conductive material, for example, a metal material such as aluminum, tungsten, copper, silver, or gold can be used. As the filling method, a plating method, metal CVD, or a metal resin dispersion paste is applied. It is possible to use the method to do. When the plating method is used, a metal serving as a plating base is formed by sputtering or the like, and then electrolytic plating is performed to fill the recess 20 with a conductive material.

本実施形態では、層間絶縁膜２３の表面全体にスパッタリング法で金属膜３２（例えば、Ｔｉ／ＴｉＮ膜）を成膜し、その後、電解メッキを行って導電性材料が凹部２０内に充填されるように、金属膜３２の表面全体に貫通電極膜３３を形成している。Ｔｉ／ＴｉＮ膜として金属膜３２を形成する場合、基板温度を５０℃として、Ｔｉ／ＴｉＮ＝１２ｋＷ／２０ｋＷの条件でスパッタリングを行ってもよい。   In this embodiment, a metal film 32 (for example, a Ti / TiN film) is formed on the entire surface of the interlayer insulating film 23 by a sputtering method, and then electroplating is performed to fill the recess 20 with the conductive material. Thus, the through electrode film 33 is formed on the entire surface of the metal film 32. When the metal film 32 is formed as a Ti / TiN film, the substrate temperature may be 50 ° C., and sputtering may be performed under the conditions of Ti / TiN = 12 kW / 20 kW.

次いで、図１（ｅ）に示すように、基板１０を半導体素子６が形成された表面側から例えばＣＭＰによって研磨することにより、貫通電極膜３３および金属膜３２の不要な部分を除去する。   Next, as shown in FIG. 1E, unnecessary portions of the through electrode film 33 and the metal film 32 are removed by polishing the substrate 10 from the surface side where the semiconductor element 6 is formed by, for example, CMP.

次いで、図１（ｆ）に示すように、基板１０を半導体素子６が形成された表面の反対側（裏面側）から研磨して、基板１０を薄膜化すると共に、凹部２０内に充填された貫通電極膜３３の導電性材料を基板１０の裏面に露出させる。これにより、シリコン基板１０を貫通する貫通電極３３ａが形成される。   Next, as shown in FIG. 1 (f), the substrate 10 is polished from the opposite side (back side) of the surface on which the semiconductor element 6 is formed to reduce the thickness of the substrate 10 and fill the recess 20. The conductive material of the through electrode film 33 is exposed on the back surface of the substrate 10. Thereby, the through electrode 33a penetrating the silicon substrate 10 is formed.

以上の一連の工程により、貫通電極３３ａを備えた半導体チップ５０が製造される。   The semiconductor chip 50 including the through electrode 33a is manufactured through the series of steps described above.

本実施形態の半導体チップ５０の製造方法によれば、従来、半導体素子６を形成した後に行っていた側壁絶縁膜２１の形成を、半導体素子６を形成する前に行うようにしたため、側壁絶縁膜２１を形成する際の熱処理の影響を受けることなく半導体素子６が形成される。   According to the method for manufacturing the semiconductor chip 50 of the present embodiment, the sidewall insulating film 21 that has been conventionally formed after the semiconductor element 6 is formed is formed before the semiconductor element 6 is formed. The semiconductor element 6 is formed without being affected by the heat treatment when forming 21.

なお、上述したような熱酸化膜からなる側壁絶縁膜２１は、半導体素子６を形成する工程におけるフィールド酸化工程で形成されるものであってもよい。このように、フィールド酸化工程と側壁絶縁膜２１を形成する工程とを共通化することによって、製造工程の簡略化が図られる。   Note that the sidewall insulating film 21 made of the thermal oxide film as described above may be formed in a field oxidation process in the process of forming the semiconductor element 6. Thus, by simplifying the field oxidation step and the step of forming the sidewall insulating film 21, the manufacturing process can be simplified.

また、側壁絶縁膜２１の材料は熱酸化膜に限られるものではなく、窒化シリコン等のシリコン化合物やＨＴＯ酸化膜であってもよく、また、その形成方法も熱酸化処理の他にも各種のＣＶＤ法、スパッタリング法、蒸着法、ソルベントコート法等であってもよい。より具体的には、例えば、ＬＰ−ＣＶＤで、ＳｉＨ2ＣＬ2を９０ｓｃｃｍ、ＮＨ3を９００ｓｃｃｍ、圧力０．５Ｔｏｒｒ、７７０℃の温度条件で６０分間のデポジット処理を行って０．１５μｍ程度の窒化膜を形成してもよいし、ＬＰ−ＣＶＤで、ＳｉＨ4を５０ｓｃｃｍ、Ｎ2Ｏを３０００ｓｃｃｍ、圧力１．１Ｔｏｒｒ、７８０℃の温度条件で９０分間のデポジット処理を行って０．１７程度のＨＴＯ膜を形成してもよい。ＨＴＯ膜は、熱酸化膜や窒化膜と比較して内部応力が小さいものとなる。
（第２の実施形態）
図２は、本発明の第２の実施形態による、半導体チップを製造する工程を説明するための断面図である。なお、図２において、図１と同一機能の構造部には図１と同一の符号を付し、その詳細な説明は省略する。また、第１の実施形態と同様の工程で形成可能な構造部については、その形成方法の詳細な説明は省略する。 The material of the sidewall insulating film 21 is not limited to the thermal oxide film, and may be a silicon compound such as silicon nitride or an HTO oxide film. A CVD method, a sputtering method, a vapor deposition method, a solvent coating method, or the like may be used. More specifically, for example, a deposit process is performed for 60 minutes under LP-CVD under conditions of 90 sccm of SiH 2 CL 2 , 900 sccm of NH 3 , pressure of 0.5 Torr, and 770 ° C. A film may be formed, or an HTO of about 0.17 may be formed by LP-CVD and depositing for 90 minutes under the conditions of 50 sccm SiH 4 , 3000 sccm N 2 O, 1.1 Torr pressure, 780 ° C. A film may be formed. The HTO film has a smaller internal stress than the thermal oxide film or the nitride film.
(Second Embodiment)
FIG. 2 is a cross-sectional view for explaining a process of manufacturing a semiconductor chip according to the second embodiment of the present invention. In FIG. 2, the same reference numerals as those in FIG. 1 are assigned to the structural parts having the same functions as those in FIG. Further, the detailed description of the formation method of the structure portion that can be formed in the same process as in the first embodiment will be omitted.

まず、図２（ａ）に示すように、図１（ａ）、（ｂ）と同様の工程により、シリコン基板１０（以下、単に「基板１０」という）に凹部２０を形成し、基板１０の表面に素子被覆膜２１ａを形成した後、凹部２０の内壁全体と基板１０の表面全体とに、絶縁材料からなる側壁絶縁膜２１を形成する。   First, as shown in FIG. 2A, a recess 20 is formed in a silicon substrate 10 (hereinafter simply referred to as “substrate 10”) by the same process as in FIGS. After the element coating film 21 a is formed on the surface, the sidewall insulating film 21 made of an insulating material is formed on the entire inner wall of the recess 20 and the entire surface of the substrate 10.

次いで、図２（ｂ）に示すように、凹部２０内を充填するように、側壁絶縁膜２１の表面全体に犠牲膜２２を形成する。犠牲膜２２は、例えばＳＯＧによって材料を塗布して熱処理することにより形成可能である。次に、犠牲膜２２の表面側（図中の矢印参照）を例えばＣＭＰによって研磨することにより、側壁絶縁膜２１および素子被覆膜２１ａを再び露出させる。   Next, as shown in FIG. 2B, a sacrificial film 22 is formed on the entire surface of the sidewall insulating film 21 so as to fill the recess 20. The sacrificial film 22 can be formed, for example, by applying a material by SOG and performing a heat treatment. Next, the side wall insulating film 21 and the element coating film 21a are exposed again by polishing the surface side of the sacrificial film 22 (see the arrow in the drawing) by CMP, for example.

次いで、図２（ｃ）に示すように、素子被覆膜２１ａを除去することにより露出した基板１０の表面に半導体素子６を形成する。その後、半導体素子６を覆うように層間絶縁膜２３を形成する。   Next, as shown in FIG. 2C, the semiconductor element 6 is formed on the surface of the substrate 10 exposed by removing the element coating film 21a. Thereafter, an interlayer insulating film 23 is formed so as to cover the semiconductor element 6.

次いで、図２（ｄ）に示すように、層間絶縁膜２３と犠牲膜２２とを貫通する凹部２０ａを形成する。凹部２０ａの形成は、例えば上述したＩＣＰエッチングにより実施可能であり、例えば側壁絶縁膜２１をエッチングストップ層としてエッチングしてもよい。凹部２０ａの開口面積は特に限定されるものではないが、本実施形態では、側壁絶縁膜２１が形成された凹部２０の開口面積より小さくなっている。その結果、凹部２０ａの側壁の一部には、犠牲膜２２が露出している。   Next, as shown in FIG. 2D, a recess 20 a that penetrates the interlayer insulating film 23 and the sacrificial film 22 is formed. The recess 20a can be formed by, for example, the above-described ICP etching. For example, the recess 20a may be etched using the sidewall insulating film 21 as an etching stop layer. Although the opening area of the recess 20a is not particularly limited, in this embodiment, it is smaller than the opening area of the recess 20 in which the sidewall insulating film 21 is formed. As a result, the sacrificial film 22 is exposed at a part of the side wall of the recess 20a.

次いで、図２（ｅ）に示すように、凹部２０ａ内に導電性材料を充填する。なお、図２（ｅ）では、図面を簡略にするため貫通電極膜３３のみを示し、金属膜３２（図１参照）は図示していない。この工程は図１（ｄ）と同様の工程であり、例えばスパッタリング法で、不図示の金属膜を凹部２０ａの内壁全体および層間絶縁膜２３の表面全体に成膜し、その後、電解メッキを行って、導電性材料からなる貫通電極膜３３を形成している。次に、貫通電極膜３３の表面側（図中の矢印参照）を例えばＣＭＰによって研磨することにより貫通電極膜３３の不要な部分を除去する。   Next, as shown in FIG. 2E, the recess 20a is filled with a conductive material. In FIG. 2E, only the through electrode film 33 is shown to simplify the drawing, and the metal film 32 (see FIG. 1) is not shown. This step is the same as FIG. 1D, and a metal film (not shown) is formed on the entire inner wall of the recess 20a and the entire surface of the interlayer insulating film 23 by, for example, sputtering, and then electrolytic plating is performed. Thus, the through electrode film 33 made of a conductive material is formed. Next, unnecessary portions of the through electrode film 33 are removed by polishing the surface side of the through electrode film 33 (see the arrow in the drawing) by CMP, for example.

次いで、図２（ｆ）に示すように、基板１０を裏面側から研磨することにより、貫通電極膜３３の導電性材料を基板１０裏面に露出させ、貫通電極３３ａを形成することにより、半導体チップ５１が形成される。   Next, as shown in FIG. 2 (f), the substrate 10 is polished from the back surface side to expose the conductive material of the through electrode film 33 on the back surface of the substrate 10, thereby forming the through electrode 33 a, thereby forming the semiconductor chip. 51 is formed.

本実施形態の半導体チップ５１の製造方法によれば、第１の実施形態と同様に、半導体素子６を形成する前に側壁絶縁膜２１が形成されるものであるため、側壁絶縁膜２１を形成する際の熱処理の影響を受けることなく半導体素子６が形成される。   According to the method for manufacturing the semiconductor chip 51 of the present embodiment, the sidewall insulating film 21 is formed before the semiconductor element 6 is formed, as in the first embodiment. The semiconductor element 6 is formed without being affected by the heat treatment during the process.

ところで、第１の実施形態の製造方法は、凹部２０が閉塞されていない状態で半導体素子６を形成する（図１（ｃ）参照）ものであるため、半導体素子６を形成する工程のうちの１つである洗浄工程において基板１０全体を洗浄液に浸して洗浄した場合に、その洗浄液が凹部２０内に付着して残留する可能性がある。このように凹部２０内に残留した洗浄液等の汚染物は、その後の工程で形成される膜の密着強度を低下させる可能性がある。また、基板１０全体を熱処理する場合、残留した洗浄液等が加熱により膨張して貫通電極３３ａ等の構造部を破損する可能性がある。これに対して、本実施形態の製造方法によれば、図２（ｃ）に示すように、凹部２０内に犠牲膜２２を充填した状態で半導体素子６を形成するものであり、凹部２０内に洗浄液等の汚染物が残留することが防止されているため、上述のような不具合の発生が防止され、製造される半導体チップはより高信頼性なものとなる。   By the way, since the manufacturing method of 1st Embodiment forms the semiconductor element 6 in the state which the recessed part 20 is not obstruct | occluded (refer FIG.1 (c)), it is among the processes of forming the semiconductor element 6. When the entire substrate 10 is immersed in a cleaning solution and cleaned in one cleaning step, the cleaning solution may adhere to the recess 20 and remain. In this way, contaminants such as cleaning liquid remaining in the recess 20 may reduce the adhesion strength of the film formed in the subsequent process. In addition, when the entire substrate 10 is heat-treated, there is a possibility that the remaining cleaning liquid or the like expands due to heating and damages the structure portion such as the through electrode 33a. In contrast, according to the manufacturing method of the present embodiment, as shown in FIG. 2C, the semiconductor element 6 is formed in a state where the recess 20 is filled with the sacrificial film 22. Therefore, the occurrence of the above-described problems is prevented, and the manufactured semiconductor chip becomes more reliable.

なお、犠牲膜２２は、凹部２０内に完全に充填されるものに限らず例えば図３に示すようなものであってもよい。図３に示す犠牲膜２２ａは、例えばプラズマＣＶＤを利用して形成された窒化膜であり、凹部２０内にボイドが形成されているが、凹部２０の上端開口部側で窒化膜同士が密着することにより凹部２０を閉塞している。このような犠牲膜２２ａは、凹部２０を完全に充填する犠牲膜２２と比較して薄い膜厚で形成可能であるため、犠牲膜２２ａを形成するための処理時間の短縮を図ることができる。   Note that the sacrificial film 22 is not limited to being completely filled in the concave portion 20, and may be, for example, as shown in FIG. The sacrificial film 22a shown in FIG. 3 is a nitride film formed using, for example, plasma CVD, and voids are formed in the recess 20, but the nitride films are in close contact with each other at the upper end opening side of the recess 20. This closes the recess 20. Such a sacrificial film 22a can be formed with a thin film thickness as compared with the sacrificial film 22 that completely fills the recess 20, so that the processing time for forming the sacrificial film 22a can be shortened.

また、図４に示すように、例えば半導体基板や酸化膜基板で構成された板状の閉塞部材２４を基板１０の表面に貼り合わせることによって凹部２０を閉塞するものであってもよい。なお、閉塞部材２４を貼り合わせる方法は特に限定されるものではないが、例えば、酸化膜基板で構成された閉塞部材２４を基板１０上に配置して熱処理することにより貼り合わせてもよい。なお当然ながら、閉塞部材２４の形状および配置位置は、その後の工程で基板１０の表面に半導体素子を形成できるようなものとすることが必要である。   Further, as shown in FIG. 4, the recess 20 may be closed by bonding a plate-like closing member 24 made of, for example, a semiconductor substrate or an oxide film substrate to the surface of the substrate 10. The method for bonding the closing member 24 is not particularly limited. For example, the closing member 24 formed of an oxide film substrate may be disposed on the substrate 10 and heat-treated. Needless to say, the shape and arrangement position of the closing member 24 must be such that a semiconductor element can be formed on the surface of the substrate 10 in a subsequent process.

また、本実施形態では凹部２０ａ（図２（ｄ）参照）の開口面積が凹部２０より小さいものであったが本発明はそれに限られるものではない。図５は、凹部２０より大きな開口面積に開口したレジスト４０をマスクとして凹部２０ｂを形成する工程を説明するための断面図である。   In this embodiment, the opening area of the recess 20a (see FIG. 2D) is smaller than that of the recess 20, but the present invention is not limited to this. FIG. 5 is a cross-sectional view for explaining a process of forming the recess 20b using the resist 40 having an opening area larger than that of the recess 20 as a mask.

図５（ａ）は、図２（ｃ）に相当する状態、すなわち、凹部２０内に犠牲膜２２ｂが充填され、その犠牲膜２２ｂを覆うように側壁絶縁膜２１上に層間絶縁膜２３が形成され、さらに、層間絶縁膜２３上にレジスト４０が形成されている状態を示している。レジスト４０には、凹部２０よりも大きな開口面積に形成された開口部４０ａがパターニングされている。また、犠牲膜２２ｂの材料は、側壁絶縁膜２１よりもエッチングレートの小さいものとなっている。   FIG. 5A shows a state corresponding to FIG. 2C, that is, the sacrificial film 22b is filled in the recess 20, and an interlayer insulating film 23 is formed on the sidewall insulating film 21 so as to cover the sacrificial film 22b. Further, a state is shown in which a resist 40 is formed on the interlayer insulating film 23. The resist 40 is patterned with an opening 40 a formed in an opening area larger than that of the recess 20. The material of the sacrificial film 22b is a material having an etching rate smaller than that of the sidewall insulating film 21.

次いで、図５（ｂ）に示すように、レジスト４０をマスクとして、例えばドライエッチングによって層間絶縁膜２３および犠牲膜２２ｂをエッチングすると、開口部４０ａを介して露出した層間絶縁膜２３の一部と、凹部２０内の犠牲膜２２ｂがエッチングされ、凹部２０ｂが形成される。ここで、犠牲膜２２ｂは側壁絶縁膜２１よりエッチングレートが小さい材料であるため、側壁絶縁膜２１と比較して犠牲膜２２ｂが優先的にエッチングされ、その結果、凹部２０ｂの下側は凹部２０と同形状に形成される。このように層間絶縁膜２３と犠牲膜２２ｂとのエッチングレートの差を利用した自己整合プロセスとすることにより、レジスト４０の開口部４０ａが多少ずれた場合であっても凹部２０ｂの下側は凹部２０と同形状に形成される。すなわち、開口部４０ａの位置精度が緩和されるため、製造歩留まりの向上を図ることが可能となる。なお、犠牲膜２２ｂは、側壁絶縁膜２１よりもエッチングレートの小さい窒化膜としてもよく、この場合、リン酸によるウェットエッチングや、He、ＳＦ6、ＣＨＦ3の混合ガスを用いたドライエッチングを利用して凹部２０ｂを形成することができる。 Next, as shown in FIG. 5B, when the interlayer insulating film 23 and the sacrificial film 22b are etched by, for example, dry etching using the resist 40 as a mask, a part of the interlayer insulating film 23 exposed through the opening 40a is formed. The sacrificial film 22b in the recess 20 is etched to form the recess 20b. Here, since the sacrificial film 22b is made of a material having an etching rate smaller than that of the side wall insulating film 21, the sacrificial film 22b is preferentially etched as compared with the side wall insulating film 21, and as a result, the lower side of the concave portion 20b is the concave portion 20b. And the same shape. As described above, the self-alignment process using the difference in etching rate between the interlayer insulating film 23 and the sacrificial film 22b allows the lower side of the recess 20b to be a recess even when the opening 40a of the resist 40 is slightly shifted. 20 and the same shape. That is, since the positional accuracy of the opening 40a is relaxed, it is possible to improve the manufacturing yield. The sacrificial film 22b may be a nitride film having an etching rate smaller than that of the sidewall insulating film 21. In this case, wet etching using phosphoric acid or dry etching using a mixed gas of He, SF 6 , and CHF 3 is used. Thus, the recess 20b can be formed.

本発明によれば、基板内を貫通する電極を有するチップの特性を良好に保つことができるため、集積度を高めた半導体装置に用いることができる。   According to the present invention, since the characteristics of a chip having an electrode penetrating through the substrate can be kept good, it can be used for a semiconductor device with an increased degree of integration.

本発明の第１の実施形態による、半導体チップを製造する工程を説明するための断面図である。It is sectional drawing for demonstrating the process of manufacturing a semiconductor chip by the 1st Embodiment of this invention. 本発明の第２の実施形態による、半導体チップを製造する工程を説明するための断面図である。It is sectional drawing for demonstrating the process of manufacturing a semiconductor chip by the 2nd Embodiment of this invention. 犠牲膜の変形例を示す断面図である。It is sectional drawing which shows the modification of a sacrificial film. 閉塞部材を用いて凹部を閉塞する工程を説明するための断面図である。It is sectional drawing for demonstrating the process of obstruct | occluding a recessed part using an obstruction | occlusion member. 自己整合プロセスにより凹部を形成する工程を説明するための断面図である。It is sectional drawing for demonstrating the process of forming a recessed part by a self-alignment process. 半導体チップが積層されて構成された半導体装置の一例を示す模式図である。It is a schematic diagram which shows an example of the semiconductor device comprised by laminating | stacking a semiconductor chip. 貫通電極を備えた半導体チップを製造するための従来の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the conventional manufacturing method for manufacturing the semiconductor chip provided with the penetration electrode. 貫通電極を備えた半導体チップを製造するための従来の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the conventional manufacturing method for manufacturing the semiconductor chip provided with the penetration electrode.

符号の説明Explanation of symbols

６ 半導体素子
１０ シリコン基板
１１ レジスト
２０、２０ａ、２０ｂ 凹部
２１ 側壁絶縁膜
２１ａ 素子被覆膜
２２、２２ａ、２２ｂ 犠牲膜
２３ 層間絶縁膜
２４ 閉塞部材
３２ 金属膜
３３ 貫通電極膜
３３ａ 貫通電極
４０ レジスト
５０、５１ 半導体チップ 6 Semiconductor element 10 Silicon substrate 11 Resist 20, 20a, 20b Recess 21 Side wall insulating film 21a Element covering film 22, 22a, 22b Sacrificial film 23 Interlayer insulating film 24 Closing member 32 Metal film 33 Through electrode film 33a Through electrode 40 Resist 50 , 51 Semiconductor chip

Claims (10)

半導体基板に、複数の半導体素子と、絶縁膜によって、少なくとも周囲の半導体領域と絶縁された貫通電極とが形成された半導体チップの製造方法において、
前記絶縁膜を成膜する工程を、前記半導体素子を形成する工程より前に行うことを特徴とする半導体チップの製造方法。 In a semiconductor chip manufacturing method in which a plurality of semiconductor elements and a through electrode insulated from at least a surrounding semiconductor region by an insulating film are formed on a semiconductor substrate.
A method of manufacturing a semiconductor chip, wherein the step of forming the insulating film is performed before the step of forming the semiconductor element. 前記半導体基板を、前記半導体素子が形成される表面側からエッチングすることにより第１の凹部を形成する工程と、
前記第１の凹部の内壁に前記絶縁膜を成膜する工程と、
前記絶縁膜が成膜された前記第１の凹部内に導電性材料を充填する工程と、
前記半導体基板を、前記半導体素子が形成される表面の反対側の裏面から研磨し、前記第１の凹部内に充填された前記導電性材料を前記裏面に露出させることにより前記貫通電極を形成する工程とを有する、請求項１に記載の半導体チップの製造方法。 Forming the first recess by etching the semiconductor substrate from the surface side where the semiconductor element is formed;
Forming the insulating film on the inner wall of the first recess;
Filling the first recess in which the insulating film is formed with a conductive material;
The through electrode is formed by polishing the semiconductor substrate from the back surface opposite to the surface on which the semiconductor element is formed and exposing the conductive material filled in the first recess to the back surface. The method of manufacturing a semiconductor chip according to claim 1, further comprising a step. 前記絶縁膜を成膜する工程は、前記第１の凹部の内壁全体と前記半導体基板の表面全体とに前記絶縁膜を成膜することを含み、
前記半導体素子を形成する工程は、前記半導体基板の表面に成膜された前記絶縁膜の一部に、前記半導体基板の前記半導体素子が形成される領域を露出させるための開口部を形成することをさらに含む、請求項２に記載の半導体チップの製造方法。 The step of forming the insulating film includes forming the insulating film on the entire inner wall of the first recess and the entire surface of the semiconductor substrate,
The step of forming the semiconductor element includes forming an opening for exposing a region of the semiconductor substrate where the semiconductor element is to be formed in a part of the insulating film formed on the surface of the semiconductor substrate. The method for manufacturing a semiconductor chip according to claim 2, further comprising: 前記絶縁膜を成膜する工程と前記半導体素子を形成する工程との間に行われる前記第１の凹部を閉塞する工程と、
前記半導体素子を形成する工程の後に、前記閉塞された第１の凹部を再度開放する工程とをさらに有する、請求項２または３に記載の半導体チップの製造方法。 Closing the first recess between the step of forming the insulating film and the step of forming the semiconductor element;
The method for manufacturing a semiconductor chip according to claim 2, further comprising a step of reopening the closed first concave portion after the step of forming the semiconductor element. 前記第１の凹部を閉塞する工程は、犠牲膜を前記第１の凹部内に充填することを含み、
前記第１の凹部を再度開放する工程は、前記第１の凹部内に充填された犠牲膜をエッチングすることにより第２の凹部を形成することを含み、
前記導電性材料を充填する工程は、前記第２の凹部内に前記導電性材料を充填することを含む、請求項４に記載の半導体チップの製造方法。 The step of closing the first recess includes filling a sacrificial film in the first recess,
Re-opening the first recess includes forming a second recess by etching a sacrificial film filled in the first recess;
The method of manufacturing a semiconductor chip according to claim 4, wherein the step of filling the conductive material includes filling the second recess with the conductive material. 前記犠牲膜は、前記第１の凹部の内壁に成膜された前記絶縁膜よりエッチングレートの小さい材料からなり、
前記第１の凹部を再度開放する工程は、前記第１の凹部より大きな開口面積の開口部を備えるレジストをマスクとして、前記開口部からエッチングすることにより前記第１の凹部内に充填された前記犠牲膜を全て除去することを含む、請求項５に記載の半導体チップの製造方法。 The sacrificial film is made of a material having a lower etching rate than the insulating film formed on the inner wall of the first recess,
The step of re-opening the first concave portion includes filling the first concave portion by etching from the opening portion using a resist having an opening portion having an opening area larger than that of the first concave portion as a mask. The method for manufacturing a semiconductor chip according to claim 5, comprising removing all of the sacrificial film. 前記凹部を閉塞する工程は、板状部材を前記半導体基板の表面に貼り合わせることにより前記凹部の上端開口部を閉塞することを含む、請求項４に記載の半導体チップの製造方法。   The method for manufacturing a semiconductor chip according to claim 4, wherein the step of closing the recess includes closing an upper end opening of the recess by bonding a plate-like member to the surface of the semiconductor substrate. 前記絶縁膜は、熱酸化、フィールド酸化、ＬＰ‐ＣＶＤのうちのいずれか１つによって形成される、請求項１ないし7のいずれか１項に記載の半導チップの製造方法。   8. The method of manufacturing a semiconductor chip according to claim 1, wherein the insulating film is formed by any one of thermal oxidation, field oxidation, and LP-CVD. 前記絶縁膜は、ＬＰ‐ＣＶＤによって形成されたＨＴＯ酸化膜または窒化膜である、請求項１ないし7のいずれか１項に記載の半導体チップの製造方法。   8. The method of manufacturing a semiconductor chip according to claim 1, wherein the insulating film is an HTO oxide film or a nitride film formed by LP-CVD. 請求項１〜９のいずれか１項に記載の半導体チップの製造方法を用いて製造した半導体チップを、複数個積層して、前記貫通電極同士を接続した半導体装置。 The semiconductor device which laminated | stacked the semiconductor chip manufactured using the manufacturing method of the semiconductor chip of any one of Claims 1-9, and connected the said penetration electrodes.
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