JP2005217446A - Group iii nitride semiconductor light emitting element - Google Patents

Group iii nitride semiconductor light emitting element Download PDF

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JP2005217446A
JP2005217446A JP2005118792A JP2005118792A JP2005217446A JP 2005217446 A JP2005217446 A JP 2005217446A JP 2005118792 A JP2005118792 A JP 2005118792A JP 2005118792 A JP2005118792 A JP 2005118792A JP 2005217446 A JP2005217446 A JP 2005217446A
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layer
light emitting
diode
light
electrode layer
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Michinari Sasa
道成 佐々
Norikatsu Koide
典克 小出
Naoki Shibata
直樹 柴田
Isamu Akasaki
勇 赤崎
Hiroshi Amano
浩 天野
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Toyoda Gosei Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body

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Abstract

<P>PROBLEM TO BE SOLVED: To improve the dielectric breakdown resistivity against reverse voltage. <P>SOLUTION: A light emitting diode 110, which is formed by the group III nitride semiconductor consisting of an n-conductive type high carrier density n+ layer 3, a light emitting layer 5 and a p-conductive type p-layer 61, and a compensatory diode 320, having the same structure as above, are formed on the same sapphire substrate 1. An n-electrode layer 8 and the p-electrode layer 321 of the second layer 62 of the p-conductive type of the compensating diode 320 are connected. Similarly, a p-electrode 7 and the n-electrode layer 322 of the first layer 3 of an n-conductive type of the compensating diode 320 are connected. At this point, even when a reverse voltage is applied to the light emitting diode 110, i.e., even when the n-electrode 8 becomes higher than the p-electrode layer 7, the reverse voltage is not applied to the light emitting diode 110 because the compensating diode 320 is conductive. As a result, the breakdown by the reverse voltage can be prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は逆方向の静電耐圧を向上させた３族窒化物半導体を用いた発光素子に関する。   The present invention relates to a light emitting device using a group III nitride semiconductor with improved reverse electrostatic withstand voltage.

従来、３族窒化物半導体発光素子として、ZnとSiとを添加したIn1-XGaXNから成る発光層をホール濃度1×1018/cm3以下のｐ伝導型のAlGaNからなるｐ層と電子濃度2×1018/cm3のGaNから成るｎ層とで挟んだダブルヘテロ構造のものが知られている。この発光素子は、420〜520nmの青色の発光が得られている。 Conventionally, as a group 3 nitride semiconductor light-emitting device, a light-emitting layer made of In 1-X Ga X N doped with Zn and Si is made of a p-type AlGaN layer having a hole concentration of 1 × 10 18 / cm 3 or less. And a double hetero structure sandwiched between n layers of GaN having an electron concentration of 2 × 10 18 / cm 3 are known. This light emitting element emits blue light of 420 to 520 nm.

しかし、上記の構成の発光素子は、静電気に対する正、逆方向の耐電圧が低いという問題がある。   However, the light-emitting element having the above-described structure has a problem that the withstand voltage in the forward and reverse directions against static electricity is low.

本発明は上記の課題を解決するために成されたものであり、その目的は、静電気に対する耐絶縁破壊性を向上させることである。   The present invention has been made to solve the above-described problems, and an object thereof is to improve the dielectric breakdown resistance against static electricity.

本発明は、３族窒化物半導体から成るｐ層、そのｐ層に接続するｐ電極層、ｎ層及びそのｎ層に接続するｎ電極層とから成る発光部を有した発光素子において、発光部のｐ電極層に電気的に接続されるｎ伝導型の第１層と、発光部のｎ電極層に電気的に接続されるｐ伝導型の第２層とが接合された逆耐圧補償用の補償ダイオードを設けたことを特徴とする。
請求項２、３の発明は、補償ダイオードと発光部とを別々の基板に形成し、両者の接続をリードで行ったものであり、特に、請求項３の発明は、共通に樹脂で封止したものである。 The present invention relates to a light emitting device having a light emitting portion comprising a p layer made of a group 3 nitride semiconductor, a p electrode layer connected to the p layer, an n layer, and an n electrode layer connected to the n layer. The first layer of n-conduction type electrically connected to the p-electrode layer and the second layer of p-conduction type electrically connected to the n-electrode layer of the light emitting part are joined for reverse withstand voltage compensation A compensation diode is provided.
The inventions of claims 2 and 3 are formed by forming the compensation diode and the light emitting part on separate substrates and connecting them with leads. In particular, the invention of claim 3 is commonly sealed with resin. It is a thing.

請求項４、５、６の発明は、補償ダイオードと発光部とを同一基板に形成したものである。
特に、請求項５の発明は、補償ダイオードの層構造と発光部の層構造と同一に形成し、発光部と補償ダイオードとの間に絶縁分離の溝を形成し、発光部と補償ダイオードとの電気的接続をリードワイヤにより行ったものである。
又、請求項６の発明は、発光部の上に補償ダイオードを積層したものである。 According to the inventions of claims 4, 5, and 6, the compensation diode and the light emitting portion are formed on the same substrate.
In particular, the invention according to claim 5 is formed in the same manner as the layer structure of the compensation diode and the layer structure of the light-emitting portion, and an insulating separation groove is formed between the light-emitting portion and the compensation diode. Electrical connection is made with lead wires.
According to a sixth aspect of the present invention, a compensation diode is laminated on the light emitting portion.

補償ダイオードの作用により、発光部に逆方向に印加される静電気による破壊を防止することができる。
また、発光層と第１のｎ層との間に、電子濃度が発光層及び第１のｎ層よりも低い第２のｎ層を設けたために、正方向の正電圧による各層及び各層間での電界が小さくなるため、正方向に500Vの静電圧を印加しても絶縁破壊は見られない。
請求項４、５、６の発明は、発光部の層形成工程において補償ダイオードを製造することができる。
特に、請求項５の発明では、発光部の３族窒化物半導体の層形成により補償ダイオードを構成する層を形成されるので、製造が極めて簡単化される。
又、請求項６の発明は、発光部を形成する工程に続いて補償ダイオードを形成できるため、製造が簡単となる。 Due to the action of the compensation diode, breakdown due to static electricity applied in the reverse direction to the light emitting portion can be prevented.
In addition, since the second n layer having an electron concentration lower than that of the light emitting layer and the first n layer is provided between the light emitting layer and the first n layer, the positive voltage in the positive direction causes each layer and each layer to pass between the light emitting layer and the first n layer. Therefore, even if a static voltage of 500 V is applied in the positive direction, no dielectric breakdown is observed.
According to the fourth, fifth and sixth aspects of the invention, a compensation diode can be manufactured in the layer forming process of the light emitting portion.
In particular, in the invention of claim 5, since the layer constituting the compensation diode is formed by the formation of the group 3 nitride semiconductor layer of the light emitting portion, the manufacturing is extremely simplified.
According to the invention of claim 6, since the compensation diode can be formed following the step of forming the light emitting portion, the manufacture is simplified.

実施例を記載する。   Examples will be described.

図１において、本発明の発光部に該当する発光ダイオード１００は、サファイア基板１を有しており、そのサファイア基板１上に500ÅのAlNのバッファ層２が形成されている。そのバッファ層２の上には、順に、膜厚約2.0μｍ、電子濃度2×1018/cm3のシリコンドープGaNから成る高キャリア濃度ｎ+層３、膜厚3000Å、電子濃度1×1017/cm3のシリコンドープのGaNから成るｎ層４、膜厚約0.05μｍのIn0.08Ga0.92Nから成る発光層５、膜厚約1.0μｍ、ホール濃度5×1017/cm3、濃度1×1020/cm3にマグネシウムがドープされたAl0.08Ga0.92Nから成るｐ層６１、膜厚約0.2μｍ、ホール濃度7×1017/cm3、マグネシウム濃度2×1020/cm3のマグネシウムドープのGaNから成るコンタクト層６２が形成されている。そして、コンタクト層６２上にはその層６２に接合するNiから成るｐ電極層７が形成されている。さらに、高キャリア濃度ｎ+層３の表面の一部は露出しており、その露出部上にその層３に接合するNiから成るｎ電極層８が形成されている。 In FIG. 1, a light emitting diode 100 corresponding to a light emitting unit of the present invention has a sapphire substrate 1, and a 500 Al AlN buffer layer 2 is formed on the sapphire substrate 1. Of On the buffer layer 2, in turn, a film thickness of about 2.0 .mu.m, the electron concentration of 2 × 10 18 / cm high carrier concentration comprising a silicon-doped GaN of 3 n + layer 3, the thickness 3000 Å, electron concentration 1 × 10 17 n-layer 4 made of silicon-doped GaN of / cm 3 , light-emitting layer 5 made of In 0.08 Ga 0.92 N with a film thickness of about 0.05 μm, film thickness of about 1.0 μm, hole concentration 5 × 10 17 / cm 3 , concentration 1 × Magnesium-doped p layer 61 made of Al 0.08 Ga 0.92 N doped with magnesium at 10 20 / cm 3 , film thickness of about 0.2 μm, hole concentration 7 × 10 17 / cm 3 , magnesium concentration 2 × 10 20 / cm 3 A contact layer 62 made of GaN is formed. On the contact layer 62, a p-electrode layer 7 made of Ni bonded to the layer 62 is formed. Further, a part of the surface of the high carrier concentration n + layer 3 is exposed, and an n electrode layer 8 made of Ni bonded to the layer 3 is formed on the exposed portion.

次に、この構造の発光ダイオード１００の製造方法について説明する。
上記発光ダイオード１００は、有機金属化合物気相成長法(以下「M0VPE」と記す)による気相成長により製造された。
用いられたガスは、NH3とキャリアガスH2又はＮ2とトリメチルガリウム(Ga(CH3)3)（以下「TMG」と記す)とトリメチルアルミニウム(Al(CH3)3)（以下「TMA」と記す)とトリメチルインジウム(In(CH3)3)（以下「TMI」と記す)と、シラン(SiH4)とシクロペンタジエニルマグネシウム(Mg(C5H5)2)(以下「CP2Mg」と記す）である。 Next, a method for manufacturing the light emitting diode 100 having this structure will be described.
The light emitting diode 100 was manufactured by vapor phase growth using an organic metal compound vapor phase growth method (hereinafter referred to as “M0VPE”).
The gases used were NH 3 and carrier gas H 2 or N 2 , trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”) and trimethylaluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMA”). ), Trimethylindium (In (CH 3 ) 3 ) (hereinafter referred to as “TMI”), silane (SiH 4 ) and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ) (hereinafter referred to as “CP”). 2 Mg ”).

まず、有機洗浄及び熱処理により洗浄したａ面を主面とする厚さ100〜400μｍの単結晶のサファイア基板１をM0VPE装置の反応室に載置されたサセプタに装着する。次に、常圧でH2を流速2Liter/分で反応室に流しながら温度1100℃でサファイア基板１を気相エッチングした。 First, a single-crystal sapphire substrate 1 having a thickness of 100 to 400 μm whose main surface is cleaned by organic cleaning and heat treatment is mounted on a susceptor mounted in a reaction chamber of an M0VPE apparatus. Next, the sapphire substrate 1 was vapor-phase etched at a temperature of 1100 ° C. while flowing H 2 into the reaction chamber at a flow rate of 2 Liter / min at normal pressure.

次に、温度を400℃まで低下させて、H2を20Liter／分、NH3を10Liter／分、TMAを1.8×10-5モル／分で供給してAlNのバッファ層２が約500Åの厚さに形成された。次に、サファイア基板１の温度を1150℃に保持し、H2を20Liter／分、NH3を10Liter／分、TMGを1.7×10-4モル／分、H2ガスにより0.86ppmに希釈されたシランを20×10-8mol/分で30分供給して、膜厚約2.2μｍ、電子濃度2×1018/cm3のシリコンドープのGaNから成る高キャリア濃度ｎ+層３を形成した。 Next, the temperature is lowered to 400 ° C., H 2 is supplied at 20 Liters / minute, NH 3 is supplied at 10 Liters / minute, and TMA is supplied at 1.8 × 10 −5 mol / minute, so that the buffer layer 2 of AlN is about 500 mm thick. Formed. Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., and H 2 was diluted to 20 Liter / min, NH 3 was 10 Liter / min, TMG was 1.7 × 10 −4 mol / min, and H 2 gas was diluted to 0.86 ppm. Silane was supplied at 20 × 10 −8 mol / min for 30 minutes to form a high carrier concentration n + layer 3 made of silicon-doped GaN having a film thickness of about 2.2 μm and an electron concentration of 2 × 10 18 / cm 3 .

次に、サファイア基板１の温度を1150℃に保持し、N2又はH2を10Liter／分、NH3を10Liter／分、TMGを1.12×10-4モル／分、及び、H2ガスにより0.86ppmに希釈されたシランを1×10-8mol/分で、4分供給して、膜厚約3000Å、濃度1×1017/cm3のシリコンドープのGaNから成るｎ層４を形成した。 Next, the temperature of the sapphire substrate 1 is maintained at 1150 ° C., N 2 or H 2 is 10 Liter / min, NH 3 is 10 Liter / min, TMG is 1.12 × 10 −4 mol / min, and H 2 gas is 0.86. Silane diluted to ppm was supplied at 1 × 10 −8 mol / min for 4 minutes to form an n layer 4 made of silicon-doped GaN having a thickness of about 3000 mm and a concentration of 1 × 10 17 / cm 3 .

続いて、温度を850℃に保持し、N2又はH2を20Liter／分、NH3を10Liter／分、TMGを1.53×10-4モル／分、及び、TMIを0.02×10-4モル／分で、6分間供給して0.05μｍのIn0.08Ga0.92Nから成る発光層５を形成した。 Subsequently, the temperature is maintained at 850 ° C., N 2 or H 2 is 20 Liter / min, NH 3 is 10 Liter / min, TMG is 1.53 × 10 −4 mol / min, and TMI is 0.02 × 10 −4 mol / min. For 6 minutes, the light emitting layer 5 made of 0.05 μm In 0.08 Ga 0.92 N was formed.

続いて、温度を1100℃に保持し、N2又はH2を20Liter／分、NH3を10Liter／分、TMGを1.12×10-4モル／分、TMAを0.47×10-4モル／分、及び、CP2Mgを2×10-4モル／分で60分間導入し、膜厚約1.0μｍのマグネシウム(Mg)ドープのAl0.08Ga0.92Nから成るｐ層６１を形成した。ｐ層６１のマグネシウムの濃度は1×1020/cm3である。この状態では、ｐ層６１は、まだ、抵抗率108Ωcm以上の絶縁体である。 Subsequently, the temperature is maintained at 1100 ° C., N 2 or H 2 is 20 Liter / min, NH 3 is 10 Liter / min, TMG is 1.12 × 10 −4 mol / min, TMA is 0.47 × 10 −4 mol / min, Then, CP 2 Mg was introduced at 2 × 10 −4 mol / min for 60 minutes to form a p layer 61 made of magnesium (Mg) -doped Al 0.08 Ga 0.92 N having a thickness of about 1.0 μm. The concentration of magnesium in the p layer 61 is 1 × 10 20 / cm 3 . In this state, the p layer 61 is still an insulator having a resistivity of 10 8 Ωcm or more.

続いて、温度を1100℃に保持し、N2又はH2を20Liter／分、NH3を10Liter／分、TMGを1.12×10-4モル／分、及び、CP2Mgを4×10-4モル／分の割合で4分間導入し、膜厚約0.2μｍのマグネシウム(Mg)ドープのGaNから成るコンタクト層６２を形成した。コンタクト層６２のマグネシウムの濃度は2×1020/cm3である。この状態では、コンタクト層６２は、まだ、抵抗率108Ωcm以上の絶縁体である。 Subsequently, the temperature is maintained at 1100 ° C., N 2 or H 2 is 20 Liter / min, NH 3 is 10 Liter / min, TMG is 1.12 × 10 −4 mol / min, and CP 2 Mg is 4 × 10 −4. A contact layer 62 made of GaN doped with magnesium (Mg) having a thickness of about 0.2 μm was formed by introducing it at a rate of mol / min for 4 minutes. The concentration of magnesium in the contact layer 62 is 2 × 10 20 / cm 3 . In this state, the contact layer 62 is still an insulator having a resistivity of 10 8 Ωcm or more.

このようにして、図２に示す断面構造のウエハが得られた。次に、このウエハを、４５０℃で４５分間、熱処理した。この熱処理により、コンタクト層６２、ｐ層６１は、それぞれ、ホール濃度7×1017/cm3，5×1017/cm3、抵抗率2Ωcm，0.8Ωcmのｐ伝導型半導体となった。このようにして、多層構造のウエハが得られた。 In this way, a wafer having a cross-sectional structure shown in FIG. 2 was obtained. Next, this wafer was heat-treated at 450 ° C. for 45 minutes. By this heat treatment, the contact layer 62 and the p layer 61 became p-conduction type semiconductors having a hole concentration of 7 × 10 17 / cm 3 , 5 × 10 17 / cm 3 , and resistivity of 2 Ωcm and 0.8 Ωcm, respectively. In this way, a wafer having a multilayer structure was obtained.

次に、図３に示すように、コンタクト層６２の上に、スパッタリングによりSiO2層９を2000Åの厚さに形成し、そのSiO2層９上にフォトレジスト１０を塗布した。そして、フォトリソグラフにより、図３に示すように、コンタクト層６２上において、高キャリア濃度ｎ+層３に対するｎ電極層形成部位Ａ'のフォトレジスト１０を除去した。次に、図４に示すように、フォトレジスト１０によって覆われていないSiO2層９をフッ化水素酸系エッチング液で除去した。 Next, as shown in FIG. 3, a SiO 2 layer 9 having a thickness of 2000 mm was formed on the contact layer 62 by sputtering, and a photoresist 10 was applied on the SiO 2 layer 9. Then, by photolithography, as shown in FIG. 3, the photoresist 10 at the n-electrode layer forming portion A ′ with respect to the high carrier concentration n + layer 3 was removed on the contact layer 62. Next, as shown in FIG. 4, the SiO 2 layer 9 not covered with the photoresist 10 was removed with a hydrofluoric acid etching solution.

次に、フォトレジスト１０及びSiO2層９によって覆われていない部位のコンタクト層６２、ｐ層６１、発光層５、ｎ層４を、真空度0.04Torr、高周波電力0.44W/cm2、BCl3ガスを10ml/分の割合で供給しドライエッチングした後、Arでドライエッチングした。この工程で、図５に示すように、高キャリア濃度ｎ+層３に対するｎ電極層取出しのための孔Ａが形成された。 Next, the contact layer 62, the p layer 61, the light emitting layer 5, and the n layer 4 at portions not covered with the photoresist 10 and the SiO 2 layer 9 are subjected to a degree of vacuum of 0.04 Torr, a high frequency power of 0.44 W / cm 2 , and BCl 3. Gas was supplied at a rate of 10 ml / min for dry etching, followed by dry etching with Ar. In this step, as shown in FIG. 5, a hole A for taking out the n-electrode layer for the high carrier concentration n + layer 3 was formed.

次に、試料の上全面に、一様にNiを蒸着し、フォトレジストの塗布、フォトリソグラフィ工程、エッチング工程を経て、図１に示すように、高キャリア濃度ｎ+層３及びコンタクト層６２に対するｎ電極層８，ｐ電極層７を形成した。その後、上記の如く処理されたウエハを各チップに切断して、発光ダイオードチップを得た。 Next, Ni is uniformly vapor-deposited on the entire upper surface of the sample, and after applying a photoresist, a photolithography process, and an etching process, as shown in FIG. 1, the high carrier concentration n + layer 3 and the contact layer 62 are applied. An n electrode layer 8 and a p electrode layer 7 were formed. Thereafter, the wafer processed as described above was cut into each chip to obtain a light emitting diode chip.

このようにして形成された発光ダイオード１００は、図６に示すように、リード２０１の上部の平坦部２０３に取り付けられ、ｎ電極層８とリード２０１がワイヤ２０４で接続され、ｐ電極層７とリード２０２がワイヤ２０５で接続された後、レンズ２０６を形成するために樹脂成形される。一方、補償ダイオード３００のアノード３０１がリード２０１に接続され、補償ダイオード３００のカソード３０２がリード２０２に接続されている。   As shown in FIG. 6, the light emitting diode 100 formed in this way is attached to the flat portion 203 on the top of the lead 201, the n electrode layer 8 and the lead 201 are connected by the wire 204, and the p electrode layer 7 After the lead 202 is connected by the wire 205, resin molding is performed to form the lens 206. On the other hand, the anode 301 of the compensation diode 300 is connected to the lead 201, and the cathode 302 of the compensation diode 300 is connected to the lead 202.

これにより、発光ダイオード１００のｎ電極層８が補償ダイオード３００のｐ伝導型の第２層に接続され、ｐ電極層７がｎ伝導型の第１層に接続されることになる。よって、発光ダイオード１００にとって逆電圧となるリード２０２に対してリード２０１が高い電圧が印加される時、補償ダイオード３００が導通することになり、発光ダイオード１００には逆電圧が印加されないため、絶縁破壊は起こらない。   As a result, the n-electrode layer 8 of the light emitting diode 100 is connected to the p-conduction type second layer of the compensation diode 300, and the p-electrode layer 7 is connected to the n-conduction type first layer. Therefore, when a high voltage is applied to the lead 201 with respect to the lead 202, which is a reverse voltage for the light emitting diode 100, the compensation diode 300 becomes conductive, and no reverse voltage is applied to the light emitting diode 100. Does not happen.

図７に示すように、補償ダイオード３１０を発光ダイオード１００と共に樹脂成形し、レンズ２０６の中に組み込んでも良い。   As shown in FIG. 7, the compensation diode 310 may be resin-molded together with the light emitting diode 100 and incorporated in the lens 206.

本実施例は、図８に示すように、発光ダイオード１１０と補償ダイオード３２０とを同一基板、即ち、サファイア基板１上に形成した例である。
上述したように、バッファ層２からコンタクト層６２まで形成する。その後、ｎ電極層８を形成するための層６２から層４までのエッチング工程において、補償ダイオード３２０のｎ電極層３２２を形成するための溝４１０を形成する。次に、補償ダイオード３２０を発光ダイオード１１０から絶縁分離するために、コンタクト層６２、ｐ層６１、発光層５、ｎ層４、高キャリア濃度ｎ+層３、バッファ層２をエッチングして溝４００を形成してサファイア基板１を露出させる。 In the present embodiment, as shown in FIG. 8, the light emitting diode 110 and the compensation diode 320 are formed on the same substrate, that is, the sapphire substrate 1.
As described above, the buffer layer 2 to the contact layer 62 are formed. Thereafter, in an etching process from the layer 62 to the layer 4 for forming the n-electrode layer 8, a groove 410 for forming the n-electrode layer 322 of the compensation diode 320 is formed. Next, in order to insulate and isolate the compensation diode 320 from the light emitting diode 110, the contact layer 62, the p layer 61, the light emitting layer 5, the n layer 4, the high carrier concentration n + layer 3, and the buffer layer 2 are etched to form the groove 400. To expose the sapphire substrate 1.

次に、第１実施例と同様に、発光ダイオード１１０のｐ電極層７、ｎ電極層８、補償ダイオード３２０のｐ電極層３２１、ｎ電極層３２２を形成する。このようにして形成された発光素子は図９に示すようにリード２０１の平坦部２０３に取り付けられる。そして、発光ダイオード１１０のｐ電極層７はリード２０２にワイヤ２１０で電気的に接続され、補償ダイオード３２０のｎ電極層３２２（カソード）はワイヤ２１１によりリード２０２に電気的に接続される。同様に、発光ダイオード１１０のｎ電極層８はリード２０１にワイヤ２１２で電気的に接続され、補償ダイオード３２０のｐ電極層３２１はワイヤ２１３によりリード２０１に電気的に接続される。   Next, as in the first embodiment, the p electrode layer 7 and the n electrode layer 8 of the light emitting diode 110, the p electrode layer 321 and the n electrode layer 322 of the compensation diode 320 are formed. The light emitting element formed in this manner is attached to the flat portion 203 of the lead 201 as shown in FIG. The p electrode layer 7 of the light emitting diode 110 is electrically connected to the lead 202 with a wire 210, and the n electrode layer 322 (cathode) of the compensation diode 320 is electrically connected to the lead 202 with a wire 211. Similarly, the n-electrode layer 8 of the light-emitting diode 110 is electrically connected to the lead 201 via a wire 212, and the p-electrode layer 321 of the compensation diode 320 is electrically connected to the lead 201 via a wire 213.

これにより、発光ダイオード１１０のｐ電極層７は補償ダイオード３２０のｎ伝導型である高キャリア濃度ｎ+層３（第１層）に電気的に接続され、発光ダイオード１１０のｎ電極層８は補償ダイオード３２０のｐ伝導型であるコンタクト層６２（第２層）に電気的に接続される。よって、発光ダイオード１１０にとって逆電圧となるリード２０２に対してリード２０１が高い電圧が印加される時、補償ダイオード３２０が導通することになり、発光ダイオード１１０には逆電圧が印加されないため、絶縁破壊は起こらない。 As a result, the p-electrode layer 7 of the light-emitting diode 110 is electrically connected to the n-conducting high carrier concentration n + layer 3 (first layer) of the compensation diode 320, and the n-electrode layer 8 of the light-emitting diode 110 is compensated. The diode 320 is electrically connected to the contact layer 62 (second layer) which is p-type. Therefore, when a high voltage is applied to the lead 201 with respect to the lead 202, which is a reverse voltage for the light emitting diode 110, the compensation diode 320 becomes conductive, and the reverse voltage is not applied to the light emitting diode 110. Does not happen.

本実施例は、図１０に示すように、発光ダイオード１２０のコンタクト層６２の上に補償ダイオード３３０を形成した例である。
上述したように、バッファ層２からコンタクト層６２まで形成する。その後、補償ダイオード３３０を形成するために、ｎ型のGaNから成る第１層３３３とｐ型のGaNから成る第２層３３４を形成する。 In this embodiment, as shown in FIG. 10, a compensation diode 330 is formed on the contact layer 62 of the light emitting diode 120.
As described above, the buffer layer 2 to the contact layer 62 are formed. Thereafter, in order to form the compensation diode 330, a first layer 333 made of n-type GaN and a second layer 334 made of p-type GaN are formed.

そして、第１実施例と同様な工程により、エッチングした後、発光ダイオード１２０のｐ電極層７、ｎ電極層８、補償ダイオード３３０のｐ電極層３３１、ｎ電極層３３２を形成する。このようにして形成された発光素子は図１０に示すようにリード２０１の平坦部２０３に取り付けられる。そして、発光ダイオード１２０のｐ電極層７は補償ダイオード３３０のｎ電極層３３２（カソード）にワイヤ２２０で電気的に接続されると共にワイヤ２２１によりリード２０２に電気的に接続される。同様に、発光ダイオード１２０のｎ電極層８はリード２０１にワイヤ２２２で電気的に接続され、補償ダイオード３３０のｐ電極層３３１はワイヤ２２３によりリード２０１に電気的に接続される。   Then, after etching by the same process as in the first embodiment, the p electrode layer 7 and the n electrode layer 8 of the light emitting diode 120, the p electrode layer 331 and the n electrode layer 332 of the compensation diode 330 are formed. The light emitting element formed in this manner is attached to the flat portion 203 of the lead 201 as shown in FIG. The p electrode layer 7 of the light emitting diode 120 is electrically connected to the n electrode layer 332 (cathode) of the compensation diode 330 through a wire 220 and electrically connected to the lead 202 through a wire 221. Similarly, the n-electrode layer 8 of the light emitting diode 120 is electrically connected to the lead 201 via a wire 222, and the p-electrode layer 331 of the compensation diode 330 is electrically connected to the lead 201 via a wire 223.

これにより、発光ダイオード１２０のｐ電極層７は補償ダイオード３３０のｎ伝導型である第１層３３３に電気的に接続され、発光ダイオード１２０のｎ電極層８は補償ダイオード３３０のｐ伝導型である第２層３３４に電気的に接続される。よって、発光ダイオード１２０にとって逆電圧となるリード２０２に対してリード２０１が高い電圧が印加される時、補償ダイオード３３０が導通することになり、発光ダイオード１２０には逆電圧が印加されないため、絶縁破壊は起こらない。   Accordingly, the p-electrode layer 7 of the light-emitting diode 120 is electrically connected to the first layer 333 that is the n-conducting type of the compensation diode 330, and the n-electrode layer 8 of the light-emitting diode 120 is the p-conducting type of the compensating diode 330. It is electrically connected to the second layer 334. Therefore, when a high voltage is applied to the lead 201 with respect to the lead 202 that is a reverse voltage for the light emitting diode 120, the compensation diode 330 is turned on, and the reverse voltage is not applied to the light emitting diode 120. Does not happen.

又、上記の第１〜第４の実施例において、発光ダイオード１００、１１０、１２０に正方向にも静電圧を印加して、その静電耐圧を測定した。500Vの静電圧を印加しても絶縁破壊は見られなかった。
これは、発光層５とｎ+層３との間に、電子濃度が発光層やｎ+層３よりも低いｎ層を設けたために、正方向の正電圧による各層及び各層間での電界が小さくなるためと思われる。 In the first to fourth embodiments, a static voltage was also applied to the light emitting diodes 100, 110, 120 in the positive direction, and the electrostatic withstand voltage was measured. Dielectric breakdown was not observed even when a static voltage of 500 V was applied.
This is because the n-layer having an electron concentration lower than that of the light-emitting layer or the n + layer 3 is provided between the light-emitting layer 5 and the n + layer 3, so that the electric field between each layer and each layer due to a positive voltage in the positive direction. It seems to be smaller.

上記のいずれの実施例においても、発光層５のバンドギャップが両側に存在するｐ層６１とｎ層４のバンドギャップよりも小さくなるようなダブルヘテロ接合に形成されている。又、発光層５とｐ層６１の成分比は、GaNの高キャリア濃度ｎ+層の格子定数に一致するように選択されている。
又、上記実施例ではダブルヘテロ接合構造を用いたが、シングルヘテロ接合構造であっても良い。
さらに、上記実施例は、発光ダイオードの例を示したが、レーザダイオードであっても同様に構成可能である。
又、上記の第３、第４実施例において、補償ダイオード３２０，３３０は３族窒化物半導体を用いたが他の物質であっても良い。 In any of the above embodiments, the light emitting layer 5 is formed in a double heterojunction so that the band gap of the light emitting layer 5 becomes smaller than the band gap of the p layer 61 and the n layer 4 existing on both sides. The component ratio between the light emitting layer 5 and the p layer 61 is selected to match the lattice constant of the high carrier concentration n + layer of GaN.
In the above embodiment, a double heterojunction structure is used, but a single heterojunction structure may be used.
Furthermore, although the said Example showed the example of the light emitting diode, even if it is a laser diode, it can comprise similarly.
In the third and fourth embodiments, the compensation diodes 320 and 330 are made of a group III nitride semiconductor, but other materials may be used.

本発明の具体的な第１実施例に係る発光ダイオードの構成を示した構成図。The block diagram which showed the structure of the light emitting diode which concerns on the specific 1st Example of this invention. 同実施例の発光ダイオードの製造工程を示した断面図。Sectional drawing which showed the manufacturing process of the light emitting diode of the Example. 同実施例の発光ダイオードの製造工程を示した断面図。Sectional drawing which showed the manufacturing process of the light emitting diode of the Example. 同実施例の発光ダイオードの製造工程を示した断面図。Sectional drawing which showed the manufacturing process of the light emitting diode of the Example. 同実施例の発光ダイオードの製造工程を示した断面図。Sectional drawing which showed the manufacturing process of the light emitting diode of the Example. 第１実施例に係る発光素子の機構を示した構成図。The block diagram which showed the mechanism of the light emitting element which concerns on 1st Example. 第２実施例に係る発光素子の機構を示した構成図。The block diagram which showed the mechanism of the light emitting element which concerns on 2nd Example. 第３実施例に係る発光素子の層構造を示した断面図。Sectional drawing which showed the layer structure of the light emitting element which concerns on 3rd Example. 第３実施例に係る発光素子の機構を示した構成図。The block diagram which showed the mechanism of the light emitting element which concerns on 3rd Example. 第４実施例に係る発光素子の層構造及び機構を示した構成図。The block diagram which showed the layer structure and mechanism of the light emitting element which concern on 4th Example.

符号の説明Explanation of symbols

１００，１１０，１２０…発光ダイオード
１…サファイア基板
２…バッファ層
３…高キャリア濃度ｎ+層
４…ｎ層
５…発光層
６１…ｐ層
６２…コンタクト層
７…ｐ電極層
８…ｎ電極層
３００，３１０，３２０，３３０…補償ダイオード
３２１，３３１…ｐ電極層
３２２，３３２…ｎ電極層
２０１，２０２…リード
２１０，２１１，２１２，２１３…ワイヤ
２２０，２２１，２２２，２２３…ワイヤ DESCRIPTION OF SYMBOLS 100,110,120 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n + layer 4 ... n layer 5 ... Light emitting layer 61 ... p layer 62 ... Contact layer 7 ... p electrode layer 8 ... n electrode layer 300, 310, 320, 330 ... compensation diode 321, 331 ... p electrode layer 322, 332 ... n electrode layer 201, 202 ... lead 210, 211, 212, 213 ... wire 220, 221, 222, 223 ... wire

Claims (6)

３族窒化物半導体から成るｐ層、そのｐ層に接続するｐ電極層、ｎ層及びそのｎ層に接続するｎ電極層とから成る発光部を有した発光素子において、
前記発光部の前記ｐ電極層に電気的に接続されるｎ伝導型の第１層と、前記発光部の前記ｎ電極層に電気的に接続されるｐ伝導型の第２層とが接合された逆耐圧補償用の補償ダイオードを設け、
発光層と第１のｎ層との間に、電子濃度が発光層及び第１のｎ層よりも低い第２のｎ層を設けたことを特徴とする３族窒化物半導体発光素子。 In a light emitting device having a light emitting portion composed of a p layer made of a group III nitride semiconductor, a p electrode layer connected to the p layer, an n layer and an n electrode layer connected to the n layer,
An n-conduction type first layer electrically connected to the p-electrode layer of the light-emitting portion and a p-conduction type second layer electrically connected to the n-electrode layer of the light-emitting portion are joined. Compensation diode for reverse withstand voltage compensation
A group 3 nitride semiconductor light-emitting device, wherein a light emitting layer and a second n layer having a lower electron concentration than the first n layer are provided between the light emitting layer and the first n layer. 前記補償ダイオードは、前記発光部が形成されている基板と別の基板に形成され、前記発光部と前記補償ダイオードとの電気的接続はリードにより行われていることを特徴とする請求項１に記載の３族窒化物半導体発光素子。 The compensation diode is formed on a substrate different from the substrate on which the light emitting unit is formed, and electrical connection between the light emitting unit and the compensation diode is made by a lead. The group III nitride semiconductor light-emitting device described. 前記補償ダイオードは、前記発光部が形成されている基板と別の基板に形成され、前記発光部と前記補償ダイオードとの電気的接続はリードにより行われ、前記発光部と前記補償ダイオードとが同一樹脂で封止されていることを特徴とする請求項２に記載の３族窒化物半導体発光素子。 The compensation diode is formed on a substrate different from the substrate on which the light emitting unit is formed, and the light emitting unit and the compensation diode are electrically connected by leads, and the light emitting unit and the compensation diode are the same. The group 3 nitride semiconductor light-emitting device according to claim 2, which is sealed with a resin. 前記補償ダイオードは、前記発光部が形成されている基板と同一基板に形成されていることを特徴とする請求項１に記載の３族窒化物半導体発光素子。 The group III nitride semiconductor light-emitting device according to claim 1, wherein the compensation diode is formed on the same substrate as the substrate on which the light-emitting portion is formed. 前記補償ダイオードの層構造は、前記発光部の層構造と同一に形成されており、前記発光部と前記補償ダイオードとの間に絶縁分離の溝が形成され、前記発光部と前記補償ダイオードとの電気的接続はリードワイヤにより行われいることを特徴とする請求項４に記載の３族窒化物半導体発光素子。 The layer structure of the compensation diode is formed to be the same as the layer structure of the light emitting unit, and an insulating separation groove is formed between the light emitting unit and the compensation diode, and the light emitting unit and the compensation diode are separated from each other. The group III nitride semiconductor light-emitting device according to claim 4, wherein the electrical connection is made by a lead wire. 前記補償ダイオードは、前記発光部の前記ｐ層の上に積層された前記第１層とその第１層の上に積層された第２層とで構成されていることを特徴とする請求項４に記載の３族窒化物半導体発光素子。 5. The compensation diode is configured by the first layer stacked on the p layer of the light emitting unit and the second layer stacked on the first layer. 3. The group III nitride semiconductor light-emitting device described in 1.
JP2005118792A 2005-04-15 2005-04-15 Group iii nitride semiconductor light emitting element Pending JP2005217446A (en)

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