JP2005191064A - 樹脂封止方法および樹脂封止装置 - Google Patents
樹脂封止方法および樹脂封止装置 Download PDFInfo
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- JP2005191064A JP2005191064A JP2003427124A JP2003427124A JP2005191064A JP 2005191064 A JP2005191064 A JP 2005191064A JP 2003427124 A JP2003427124 A JP 2003427124A JP 2003427124 A JP2003427124 A JP 2003427124A JP 2005191064 A JP2005191064 A JP 2005191064A
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- 229920005989 resin Polymers 0.000 title claims abstract description 168
- 238000007789 sealing Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000001721 transfer moulding Methods 0.000 claims description 8
- 230000002452 interceptive effect Effects 0.000 abstract description 2
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 20
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- 238000004519 manufacturing process Methods 0.000 description 8
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- 210000000078 claw Anatomy 0.000 description 5
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- 230000006866 deterioration Effects 0.000 description 3
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- 230000000593 degrading effect Effects 0.000 description 1
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- 238000010438 heat treatment Methods 0.000 description 1
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- 238000005580 one pot reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】 半製品24を載せて中間プレート2を上金型1と中間プレート2との間に挿入して型締め動作を行うと、樹脂供給手段17が接続されているポット12、カル4、ランナー5、ゲート6、キャビティ7によって上側の樹脂流路が、樹脂供給手段18が接続されているポット13、カル10、ランナー11,14、ゲート9、キャビティ8によって下側の樹脂流路がそれぞれ構成される。これらは互いに独立し、合流や干渉する部分は全く存在しない。この状態で、樹脂供給手段17およびプランジャー15によって上側の樹脂流路に樹脂を供給して樹脂封止し、樹脂供給手段18およびプランジャー16によって下側の樹脂流路に樹脂を供給して樹脂封止する。上側と下側の樹脂流路にそれぞれ異なる樹脂を用いて異なる条件下で同時に封止が行える。
【選択図】図1
Description
なお、上金型1のエジェクト機構は、フィルムによって離型させる構成にすることもできる。中間プレート2は、半製品を適温に保持しながら搬送するように温度調節機構を有していてもよい。
2 中間プレート
3 下金型
4 カル
5,11,14 ランナー
6,9 ゲート
7,8 キャビティ
10 カル
12,13 ポット
15,16 プランジャー
17,18 樹脂供給手段
19,20 基板
21 仮固定板
22,23 半導体素子
24 半製品
25 保持爪
26a,26b 凹部
27,28 切り欠き部
29 上パッケージ用エジェクターピン
30 ばね
31 中間プレートエジェクト用リターンピン
32 下パッケージ用エジェクターピン
33 ランナー保持ピン
34 ランナーエジェクターピン
35 プレス機構
36 トランスファーユニット
37 アジャスター機構
Claims (12)
- 基板の両面を実質的に同時に樹脂で封止する樹脂封止方法において、
前記基板の両面にそれぞれ設けられている少なくとも2系統の樹脂流路が互いに干渉せずかつ合流せず独立した状態で、前記各樹脂流路にそれぞれ異なる条件によって樹脂を供給し、供給された樹脂を前記基板の両面にて固化させることを特徴とする樹脂封止方法。 - 前記各樹脂流路にはそれぞれ異なる樹脂を供給する、請求項1に記載の樹脂封止方法。
- 上金型と下金型を接合させることによって、両金型と前記基板の間に前記樹脂流路を形成する、請求項1または2に記載の樹脂封止方法。
- 上金型と中間プレートと下金型とを接合させることによって、両金型と前記中間プレートと前記基板との間に前記樹脂流路を形成する、請求項1または2に記載の樹脂封止方法。
- 前記中間プレートを、前記基板を搭載した状態で前記両金型間に進入させ、前記基板の両面に樹脂を供給して封止を行った後、前記中間プレートを、樹脂封止された前記基板を搭載した状態で前記両金型間から退出させる、請求項4に記載の樹脂封止方法。
- 前記基板の両面の樹脂封止をいずれもトランスファーモールディングによって行う、請求項1〜5のいずれか1項に記載の樹脂封止方法。
- 基板の両面を樹脂で封止する樹脂封止装置において、
少なくともポットとカルとランナーとキャビティとからなる樹脂流路を、少なくとも2系統有しており、
前記各樹脂流路は互いに干渉せずかつ合流せず独立していることを特徴とする樹脂封止装置。 - 前記各樹脂流路の前記ポットにはそれぞれ異なる樹脂供給手段が接続されている、請求項7に記載の樹脂封止装置。
- 上金型と下金型とを有し、型締め時に両金型と前記基板との間に前記樹脂流路が形成される、請求項7または8に記載の樹脂封止装置。
- 上金型と中間プレートと下金型とを有し、型締め時に両金型と前記中間プレートと前記基板との間に前記樹脂流路が形成される、請求項7または8に記載の樹脂封止装置。
- 前記中間プレートは、前記基板を搭載した状態で前記両金型間に進入可能であり、かつ前記両金型間から退出可能である、請求項10に記載の樹脂封止装置。
- 前記基板の両面の樹脂封止をいずれもトランスファーモールディングによって行う、請求項7〜11のいずれか1項に記載の樹脂封止装置。
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009078479A (ja) * | 2007-09-27 | 2009-04-16 | Tokai Rubber Ind Ltd | 金具付きゴム製品の成形方法及び成形用型並びに成形装置 |
KR101087031B1 (ko) | 2010-10-19 | 2011-11-28 | 신한다이아몬드공업 주식회사 | 봉지재 성형장치 및 방법 |
KR101108500B1 (ko) * | 2009-08-28 | 2012-01-31 | 주식회사 참테크 | 2단 적층 성형몰드구조 |
KR101147211B1 (ko) | 2010-02-22 | 2012-05-25 | 주식회사 참테크 | 수지성형물 성형몰드 |
WO2012096354A1 (ja) * | 2011-01-14 | 2012-07-19 | ミツミ電機株式会社 | 高周波モジュール |
JP2013089668A (ja) * | 2011-10-14 | 2013-05-13 | Apic Yamada Corp | 樹脂封止装置 |
CN103262226A (zh) * | 2010-12-14 | 2013-08-21 | 罗伯特·博世有限公司 | 用于制造具有成型体的电子组件的方法 |
JP2014086609A (ja) * | 2012-10-25 | 2014-05-12 | Renesas Electronics Corp | 半導体装置の製造方法 |
WO2016053600A1 (en) * | 2014-10-01 | 2016-04-07 | Apple Inc. | Simultaneous independently controlled dual side pcb molding technique |
JP2016167583A (ja) * | 2015-03-04 | 2016-09-15 | アピックヤマダ株式会社 | 樹脂モールド方法及び樹脂モールド装置 |
JP2018014412A (ja) * | 2016-07-21 | 2018-01-25 | アピックヤマダ株式会社 | 樹脂モールド装置 |
US10099411B2 (en) * | 2015-05-22 | 2018-10-16 | Infineon Technologies Ag | Method and apparatus for simultaneously encapsulating semiconductor dies with layered lead frame strips |
WO2020059349A1 (ja) * | 2018-09-21 | 2020-03-26 | 日立オートモティブシステムズ株式会社 | 電子制御装置、及び、電子制御装置の製造方法 |
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Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009078479A (ja) * | 2007-09-27 | 2009-04-16 | Tokai Rubber Ind Ltd | 金具付きゴム製品の成形方法及び成形用型並びに成形装置 |
KR101108500B1 (ko) * | 2009-08-28 | 2012-01-31 | 주식회사 참테크 | 2단 적층 성형몰드구조 |
KR101147211B1 (ko) | 2010-02-22 | 2012-05-25 | 주식회사 참테크 | 수지성형물 성형몰드 |
KR101087031B1 (ko) | 2010-10-19 | 2011-11-28 | 신한다이아몬드공업 주식회사 | 봉지재 성형장치 및 방법 |
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JP2013512807A (ja) * | 2010-10-19 | 2013-04-18 | 新韓鑽石工業股▲ふん▼有限公司 | 封止材成形装置及び方法 |
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CN103262226A (zh) * | 2010-12-14 | 2013-08-21 | 罗伯特·博世有限公司 | 用于制造具有成型体的电子组件的方法 |
WO2012096354A1 (ja) * | 2011-01-14 | 2012-07-19 | ミツミ電機株式会社 | 高周波モジュール |
JP2013089668A (ja) * | 2011-10-14 | 2013-05-13 | Apic Yamada Corp | 樹脂封止装置 |
JP2014086609A (ja) * | 2012-10-25 | 2014-05-12 | Renesas Electronics Corp | 半導体装置の製造方法 |
KR101968429B1 (ko) * | 2014-10-01 | 2019-04-11 | 애플 인크. | 동시에 독립적으로 제어되는 양면 pcb 몰딩 기법 |
WO2016053600A1 (en) * | 2014-10-01 | 2016-04-07 | Apple Inc. | Simultaneous independently controlled dual side pcb molding technique |
US9484228B2 (en) | 2014-10-01 | 2016-11-01 | Apple Inc. | Simultaneous independently controlled dual side PCB molding technique |
KR20170051464A (ko) * | 2014-10-01 | 2017-05-11 | 애플 인크. | 동시에 독립적으로 제어되는 양면 pcb 몰딩 기법 |
CN106715075A (zh) * | 2014-10-01 | 2017-05-24 | 苹果公司 | 同步独立控制的双侧pcb模塑技术 |
JP2017530038A (ja) * | 2014-10-01 | 2017-10-12 | アップル インコーポレイテッド | 同時に独立制御された両面pcb型成形技法 |
TWI620480B (zh) * | 2014-10-01 | 2018-04-01 | 蘋果公司 | 同時獨立地控制之雙側印刷電路板模製技術 |
JP2016167583A (ja) * | 2015-03-04 | 2016-09-15 | アピックヤマダ株式会社 | 樹脂モールド方法及び樹脂モールド装置 |
US10099411B2 (en) * | 2015-05-22 | 2018-10-16 | Infineon Technologies Ag | Method and apparatus for simultaneously encapsulating semiconductor dies with layered lead frame strips |
JP2018014412A (ja) * | 2016-07-21 | 2018-01-25 | アピックヤマダ株式会社 | 樹脂モールド装置 |
WO2020059349A1 (ja) * | 2018-09-21 | 2020-03-26 | 日立オートモティブシステムズ株式会社 | 電子制御装置、及び、電子制御装置の製造方法 |
JPWO2020059349A1 (ja) * | 2018-09-21 | 2021-06-03 | 日立Astemo株式会社 | 電子制御装置、及び、電子制御装置の製造方法 |
JP7026254B2 (ja) | 2018-09-21 | 2022-02-25 | 日立Astemo株式会社 | 電子制御装置、及び、電子制御装置の製造方法 |
US11956908B2 (en) | 2018-09-21 | 2024-04-09 | Hitachi Astemo, Ltd. | Electronic control unit and method for manufacturing electronic control unit |
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