JP2005183443A - Printed circuit board comprising capacitor - Google Patents

Printed circuit board comprising capacitor Download PDF

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Publication number
JP2005183443A
JP2005183443A JP2003417972A JP2003417972A JP2005183443A JP 2005183443 A JP2005183443 A JP 2005183443A JP 2003417972 A JP2003417972 A JP 2003417972A JP 2003417972 A JP2003417972 A JP 2003417972A JP 2005183443 A JP2005183443 A JP 2005183443A
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capacitor
electric double
carbon nanotube
double layer
electrode
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Akiharu Kitamura
暁晴 北村
Hideki Shiozaki
秀喜 塩崎
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Hitachi Zosen Corp
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Hitachi Zosen Corp
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Priority to JP2003417972A priority Critical patent/JP2005183443A/en
Priority to PCT/JP2004/018107 priority patent/WO2005059934A1/en
Publication of JP2005183443A publication Critical patent/JP2005183443A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/30—Electrodes characterised by their material
    • H01G11/32—Carbon-based
    • H01G11/36—Nanostructures, e.g. nanofibres, nanotubes or fullerenes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/08—Structural combinations, e.g. assembly or connection, of hybrid or EDL capacitors with other electric components, at least one hybrid or EDL capacitor being the main component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/10—Multiple hybrid or EDL capacitors, e.g. arrays or modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/78—Cases; Housings; Encapsulations; Mountings
    • H01G11/82—Fixing or assembling a capacitive element in a housing, e.g. mounting electrodes, current collectors or terminals in containers or encapsulations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a particular space for the provision of a capacitor and also eliminate longer wiring among high-speed operation elements in a printed circuit board comprising the capacitor, because an electric double-layer capacitor is assembled in each through-hole of an insulator frame having many through-holes in a predetermined pattern and can be connected to a necessary capacitor having a necessary capacity at an area near the high-speed operation element. <P>SOLUTION: In the printed circuit board, a pair of electrodes (24), (25) including many carbon nanotubes on the single surface thereof are arranged in a vessel (21) so that a carbon nanotube (22) of one electrode (24) is opposed to a carbon nanotube (23) of the other electrode (25) via a separator (26). An electrolyte is supplied to the vessel (21) and impregnated in the carbon nanotubes (22), (23). This electric double-layer capacitor shows a capacity value as large as 3 mF per 1 cm<SP>2</SP>. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、大容量の電気を蓄えることが可能な、カーボンナノチューブを用いた電気二重層キャパシタ、および電気二重層キャパシタを組込んだ電子回路用プリント基板並びに同キャパシタ組込みプリント基板の製造方法に関するものである。   The present invention relates to an electric double layer capacitor using carbon nanotubes capable of storing a large amount of electricity, a printed circuit board for an electronic circuit incorporating the electric double layer capacitor, and a method of manufacturing the printed circuit board incorporating the capacitor. It is.

高速動作の電子回路素子（高速動作素子）で電子回路を構成するとき、プリント基板には高速動作に必要な大電流を高速動作素子に供給しなければならない。このため同素子の近くに蓄電用のキャパシタを配置する必要がある。   When an electronic circuit is constituted by a high-speed operation electronic circuit element (high-speed operation element), a large current necessary for high-speed operation must be supplied to the high-speed operation element. For this reason, it is necessary to arrange a capacitor for storing electricity near the element.

高速動作の電子回路をプリント基板で構成するとき、上記従来技術では必要な電流の供給を補うためにキャパシタを高速動作素子の近傍に配置すると共に、高速動作素子間の配線長を可能な限り短くすることが求められる。しかし、高速動作素子の近傍にキャパシタを設置するとその設置スペースが必要である上に配線長が長くなり、上記要望と矛盾することになる。さらに電源供給ラインのインピーダンスが高くなるためにＥＭＩ(Electro Magnetic Interference)などの電磁放射も問題となっている。   When a high-speed electronic circuit is configured with a printed circuit board, the above-described conventional technology places a capacitor in the vicinity of the high-speed operation element in order to compensate for the supply of necessary current, and shortens the wiring length between the high-speed operation elements as much as possible. It is required to do. However, if a capacitor is installed in the vicinity of the high-speed operation element, the installation space is required and the wiring length becomes long, which contradicts the above-mentioned demand. Furthermore, since the impedance of the power supply line is increased, electromagnetic radiation such as EMI (Electro Magnetic Interference) is also a problem.

本発明は、上記矛盾点を解決することを課題とする。   This invention makes it a subject to solve the said contradiction.

請求項１の発明は、片面に多数のカーボンナノチューブを有する一対の電極が、セパレータを介して、一方の電極のカーボンナノチューブ群と他方の電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタである。   According to the first aspect of the present invention, a pair of electrodes having a large number of carbon nanotubes on one side are disposed so that a carbon nanotube group of one electrode and a carbon nanotube group of the other electrode face each other with a separator interposed therebetween. This is an electric double layer capacitor in which a group is impregnated with an electrolytic solution.

請求項２の発明は、両面に多数のカーボンナノチューブを有する１枚の内部電極が、片面に多数のカーボンナノチューブを有する一対の側部電極で、セパレータを介してサンドイッチされ、一対の側部電極は、一方の側部電極のカーボンナノチューブ群と他方の側部電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタである。   In the invention of claim 2, one internal electrode having a large number of carbon nanotubes on both sides is sandwiched by a pair of side electrodes having a large number of carbon nanotubes on one side via a separator. This is an electric double layer capacitor in which the carbon nanotube group of one side electrode and the carbon nanotube group of the other side electrode are arranged to face each other, and the carbon nanotube group is impregnated with an electrolytic solution.

請求項３の発明は、両面に多数のカーボンナノチューブを有する複数枚の内部電極がセパレータを介して多層状に配置され、この多層内部電極群が、片面に多数のカーボンナノチューブを有する一対の側部電極で、側部セパレータを介してサンドイッチされ、一対の側部電極は、一方の側部電極のカーボンナノチューブ群と他方の側部電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタである。   According to the invention of claim 3, a plurality of internal electrodes having a large number of carbon nanotubes on both sides are arranged in a multilayer shape via a separator, and the multilayer internal electrode group is a pair of side portions having a large number of carbon nanotubes on one side. The electrodes are sandwiched via a side separator, and the pair of side electrodes are arranged so that the carbon nanotube group of one side electrode and the carbon nanotube group of the other side electrode are opposed to each other. This is an electric double layer capacitor impregnated with an electrolytic solution.

請求項４の発明は、請求項１〜３のいずれかに記載の電気二重層キャパシタが、所定パターンで多数の透孔を有する絶縁板枠の各透孔に嵌込まれ、両側に回路層が積層されてなる、キャパシタ組込みプリント基板である。   According to a fourth aspect of the present invention, the electric double layer capacitor according to any one of the first to third aspects is fitted into each through hole of an insulating plate frame having a plurality of through holes in a predetermined pattern, and circuit layers are provided on both sides. This is a printed circuit board with a built-in capacitor.

請求項５の発明は、請求項１〜３のいずれかに記載の電気二重層キャパシタを、所定パターンで多数の透孔を有する未硬化絶縁板枠の各透孔に嵌込み、次いで同絶縁板枠を硬化させ、硬化絶縁板枠の両側に回路層を積層する、キャパシタ組込みプリント基板の製造方法である。   According to a fifth aspect of the present invention, the electric double layer capacitor according to any one of the first to third aspects is fitted into each through hole of an uncured insulating plate frame having a large number of through holes in a predetermined pattern, and then the same insulating plate. This is a method for manufacturing a capacitor-embedded printed circuit board in which a frame is cured and circuit layers are laminated on both sides of a cured insulating plate frame.

請求項６の発明は、請求項１〜３のいずれかに記載の電気二重層キャパシタを、所定パターンで多数の透孔を有する硬化絶縁板枠の各透孔に嵌込み、次いで、硬化絶縁板枠の両側に回路層を積層する、キャパシタ組込みプリント基板の製造方法である。   According to a sixth aspect of the present invention, the electric double layer capacitor according to any one of the first to third aspects is fitted into each through hole of a cured insulating plate frame having a plurality of through holes in a predetermined pattern, and then the cured insulating plate. This is a method for manufacturing a printed circuit board with a built-in capacitor, in which circuit layers are laminated on both sides of a frame.

請求項１〜３の電気二重層キャパシタは、いずれも小さな面積で大きなキャパシタ容量を示す。例えば請求項１の電気二重層キャパシタは１ｃｍ２当り３ｍＦと大きなキャパシタ容量を示す。 The electric double layer capacitors according to claims 1 to 3 each have a large capacitor capacity with a small area. For example, the electric double layer capacitor of claim 1 has a large capacitor capacity of 3 mF per 1 cm 2 .

絶縁板枠は、炭素繊維、ガラス繊維等の強化繊維の織物に熱硬化樹脂を含浸させてなるシート、例えばプリプレグを硬化させて構成したものであってよい。絶縁板枠(10)に設けられる透孔(9) のパターンは、図１３に示すように、通常は複数の透孔(9) が縦横に並んだ碁盤目である。複数の透孔(9) は絶縁板枠(10)の全体に亘って設けられても、図１４に示すように、絶縁板枠(10)の必要部分に偏在して設けられてもよい。後者の場合、複数の透孔(9) に嵌込まれた電気二重層キャパシタ(8) をカバーして１つの高速動作素子(19)を配置することができる。   The insulating plate frame may be configured by curing a sheet, for example, a prepreg, obtained by impregnating a woven fabric of reinforcing fibers such as carbon fiber and glass fiber with a thermosetting resin. As shown in FIG. 13, the pattern of the through holes (9) provided in the insulating plate frame (10) is usually a grid with a plurality of through holes (9) arranged vertically and horizontally. The plurality of through holes (9) may be provided over the entire insulating plate frame (10) or may be provided unevenly at a necessary portion of the insulating plate frame (10) as shown in FIG. In the latter case, one high-speed operation element (19) can be arranged to cover the electric double layer capacitor (8) fitted in the plurality of through holes (9).

本発明において、基本になるキャパシタのサイズをプリント基板の配線ピッチに合うようにすることにより配線層とキャパシタ層を繋ぐスルーホールの配置を簡素化することができる。複数のキャパシタを直列または並列に接続することにより所望のキャパシタ容量を実現することができる。   In the present invention, the arrangement of the through holes connecting the wiring layer and the capacitor layer can be simplified by matching the basic capacitor size with the wiring pitch of the printed circuit board. A desired capacitor capacity can be realized by connecting a plurality of capacitors in series or in parallel.

カーボンナノチューブの構造は単層すなわち単一のチューブであってもよいし、多層すなわち同心状の複数の異径チューブであってもよい。カーボンナノチューブの直径は好ましくは１〜１００ｎｍである。   The structure of the carbon nanotube may be a single layer, that is, a single tube, or may be a multilayer, that is, a plurality of different diameter tubes that are concentric. The diameter of the carbon nanotube is preferably 1 to 100 nm.

カーボンナノチューブは、カーボン原子が網目状に結合してできた穴径ナノ（１ナノは１０億分の１）メートルサイズの極微細な筒（チューブ）状の物質である。通常の電解液の電解質イオン直径は約０．４〜０．６ｎｍであるので、穴径１〜２ｎｍのカーボンナノチューブがイオンの吸脱着に好ましい。また、カーボンナノチューブを実質上垂直に配向させることでイオンの吸脱着がさらにスムーズとなり、放電電流が増加した場合でも容量の低下が少ないため、長時間の使用が可能となる。   A carbon nanotube is an extremely fine tube (tube) substance having a hole diameter of nanometers (one nano is one billionth of a meter) formed by bonding carbon atoms in a network. Since the electrolyte ion diameter of a normal electrolytic solution is about 0.4 to 0.6 nm, carbon nanotubes having a hole diameter of 1 to 2 nm are preferable for adsorption and desorption of ions. Further, by aligning the carbon nanotubes substantially vertically, ions can be absorbed and desorbed more smoothly, and even when the discharge current is increased, the capacity is hardly lowered, so that it can be used for a long time.

電極を構成するカーボンナノチューブは、公知の方法で作製できる。例えば、シリコン基板の少なくとも片面上にＦｅ膜をフォトリソグラフィーでパターン化し、この面にアセチレン（Ｃ２Ｈ２）ガスを用いて一般的な化学蒸着法（ＣＶＤ法）を施すことにより作製できる。この方法では、直径１２〜３８ｎｍのカーボンナノチューブが多層構造で基板上に実質上垂直に起毛される。こうして成長させたカーボンナノチューブをシリコン基板から接着剤を施した集電体に転写し接着する。接着層は導電性ペーストからなるものであることが好ましい。集電体は、アルミニウムのような導電材からなる。 The carbon nanotube constituting the electrode can be produced by a known method. For example, it can be produced by patterning an Fe film on at least one surface of a silicon substrate by photolithography and applying a general chemical vapor deposition method (CVD method) using acetylene (C 2 H 2 ) gas on this surface. In this method, carbon nanotubes having a diameter of 12 to 38 nm are raised in a multilayer structure substantially vertically on a substrate. The carbon nanotubes thus grown are transferred from a silicon substrate to a current collector provided with an adhesive and bonded. The adhesive layer is preferably made of a conductive paste. The current collector is made of a conductive material such as aluminum.

電気二重層キャパシタの電解液は、プロピレンカーボネート、１−ブチレンカーボネート、スルホラン、アセトニトリル、γ−ブチルラクトン、ジメチルホルムアミドなどの非プロトン性溶媒に、テトラエチルアンモニウムテトラフルオロボレートやテトラエチルアンモニウムヘキサフルオロホスファート、テトラブチルアンモニウム過塩素酸塩などの有機溶質、または、リチウム、第４級ホスホニウム等のカチオンとＢＦ４ −、ＰＦ６ −、ＣｌＯ４ −、ＣＦ２ＳＯ２ −などのアニオンからなる無機溶質を溶解したものや、ランタノイド元素の塩等を含む希硫酸などの水溶液系電解液、またはこれらに高分子物質を加えたポリマー型電解液などを使用することができる。 The electrolytic solution of the electric double layer capacitor is composed of an aprotic solvent such as propylene carbonate, 1-butylene carbonate, sulfolane, acetonitrile, γ-butyllactone, dimethylformamide, tetraethylammonium tetrafluoroborate, tetraethylammonium hexafluorophosphate, tetra An organic solute such as butylammonium perchlorate or an inorganic solute composed of a cation such as lithium or quaternary phosphonium and an anion such as BF 4 − , PF 6 − , ClO 4 − or CF 2 SO 2 − was dissolved. Or an aqueous electrolyte solution such as dilute sulfuric acid containing a salt of a lanthanoid element, or a polymer electrolyte solution obtained by adding a polymer substance to these.

本発明によれば、電気二重層キャパシタは、所定パターンで多数の透孔を有する絶縁板枠の各透孔に組み込まれているので、高速動作素子の近傍でこれを必要な容量のキャパシタと繋ぐことができる。したがって、キャパシタ設置のための特別なスペースは必要でなく、高速動作素子間の長い接続配線も必要でない。   According to the present invention, since the electric double layer capacitor is incorporated in each through hole of the insulating plate frame having a large number of through holes in a predetermined pattern, the electric double layer capacitor is connected to a capacitor having a necessary capacity in the vicinity of the high speed operation element. be able to. Therefore, a special space for installing the capacitor is not necessary, and a long connection wiring between the high-speed operation elements is not necessary.

つぎに、本発明を実施例に基づいて具体的に説明する。   Next, the present invention will be specifically described based on examples.

実施例１
請求項１の電気二重層キャパシタを示す図１において、容器(21)内にて、片面に多数のカーボンナノチューブを有する一対の電極(24)(25)が、セパレータ(26)を介して、一方の電極(24)のカーボンナノチューブ(22)と他方の電極(25)のカーボンナノチューブ(23)が対向するように配置されている。容器(21)内に電解液が注入され、カーボンナノチューブ(22)(23)に含浸されている。この電気二重層キャパシタは１ｃｍ２当り３ｍＦと大きなキャパシタ容量を示す。 Example 1
In FIG. 1 showing the electric double layer capacitor according to claim 1, a pair of electrodes (24), (25) having a large number of carbon nanotubes on one side in a container (21) are connected via a separator (26). The carbon nanotubes (22) of the electrode (24) and the carbon nanotubes (23) of the other electrode (25) are arranged to face each other. An electrolytic solution is injected into the container (21) and impregnated in the carbon nanotubes (22) and (23). This electric double layer capacitor exhibits a large capacitance of 3 mF per 1 cm 2 .

実施例２
請求項２の電気二重層キャパシタを示す図２において、容器(21)内にて、両面に多数のカーボンナノチューブ(27)を有する１枚の内部電極(28)が、片面に多数のカーボンナノチューブを有する一対の側部電極(24)(25)で、セパレータ(26)を介してサンドイッチされている。一対の側部電極(24)(25)は、一方の側部電極(24)のカーボンナノチューブ(22)と他方の側部電極(25)のカーボンナノチューブ(23)が対向するように配置されている。容器(21)内に電解液が注入され、カーボンナノチューブ(22)(23)(27)に含浸されている。 Example 2
In FIG. 2 which shows the electric double layer capacitor of Claim 2, in the container (21), one internal electrode (28) which has many carbon nanotubes (27) on both surfaces has many carbon nanotubes on one side. A pair of side electrodes (24) and (25) are sandwiched through a separator (26). The pair of side electrodes (24) and (25) are arranged so that the carbon nanotube (22) of one side electrode (24) and the carbon nanotube (23) of the other side electrode (25) face each other. Yes. An electrolytic solution is injected into the container (21) and impregnated in the carbon nanotubes (22), (23), and (27).

実施例３
請求項３の電気二重層キャパシタを示す図３において、容器(21)内にて、両面に多数のカーボンナノチューブ(27)を有する複数枚の内部電極(29)が内部セパレータ(26)を介して多層状に配置され、こうして構成された多層内部電極群(30)が、片面に多数のカーボンナノチューブを有する一対の側部電極(24)(25)で、セパレータ(26)を介してサンドイッチされている。一対の側部電極(24)(25)は、一方の側部電極(24)のカーボンナノチューブ(22)と他方の側部電極(25)のカーボンナノチューブ(23)が対向するように配置されている。容器(21)内に電解液が注入され、カーボンナノチューブ(22)(23)(27)に含浸されている。 Example 3
In FIG. 3 showing the electric double layer capacitor according to claim 3, a plurality of internal electrodes (29) having a large number of carbon nanotubes (27) on both sides are disposed in the container (21) via the internal separator (26). A multilayer internal electrode group (30) arranged in a multilayered manner in this way is sandwiched via a separator (26) with a pair of side electrodes (24) (25) having a large number of carbon nanotubes on one side. Yes. The pair of side electrodes (24) and (25) are arranged so that the carbon nanotube (22) of one side electrode (24) and the carbon nanotube (23) of the other side electrode (25) face each other. Yes. An electrolytic solution is injected into the container (21) and impregnated in the carbon nanotubes (22), (23), and (27).

実施例４
第１工程
図４において、１０ｍｍ×１０ｍｍ×０．５ｍｍ厚の低抵抗Ｎ型半導体シリコン基板の片面にフォトリソグラフィーでＦｅ膜をパターン化した後、アセチレンを流量３０ｍｌ／ｍｉｎ、温度７００℃で１５分流して化学蒸着法により基板上に無数のカーボンナノチューブをブラシ状に成長させた。得られたカーボンナノチューブは多層構造であり、直径は１２ｎｍで、長さは５０μｍであった。 Example 4
First Step In FIG. 4, after patterning an Fe film by photolithography on one side of a low resistance N-type semiconductor silicon substrate having a thickness of 10 mm × 10 mm × 0.5 mm, acetylene was flowed at a flow rate of 30 ml / min and a temperature of 700 ° C. for 15 minutes. An infinite number of carbon nanotubes were grown in a brush shape on the substrate by chemical vapor deposition. The obtained carbon nanotubes had a multi-layer structure, a diameter of 12 nm, and a length of 50 μm.

こうして成長させたカーボンナノチューブをシリコン基板から、表面に導電性ペーストからなる接着層を施したアルミニウム薄板からなる集電体上に１５０℃／４９Ｎｃｍ２で加熱・加圧することで転写した。こうして片面に多数のカーボンナノチューブ(3) (4) を有する一対の電極(1) (2) を得た。 The carbon nanotubes thus grown were transferred from a silicon substrate by heating and pressurizing at 150 ° C./49 Ncm 2 onto a current collector made of an aluminum thin plate having an adhesive layer made of a conductive paste on the surface. Thus, a pair of electrodes (1) (2) having a large number of carbon nanotubes (3) (4) on one side was obtained.

第２工程
図５において、容器(6) 内で、露点下（温度−６０℃、水分なし）の窒素雰囲気で、片面に多数のカーボンナノチューブを有する一対の電極(1) (2) を、セパレータ(5) を介して、一方の電極(1) のカーボンナノチューブ(3) と他方の電極(2) のカーボンナノチューブ(4) が対向するように配置し、サンドイッチ体(17)を作製した。その後、１５０〜２００℃で２４時間乾燥を行った。 Second Step In FIG. 5, a pair of electrodes (1) (2) having a number of carbon nanotubes on one side in a nitrogen atmosphere at a dew point (temperature −60 ° C., no moisture) in a container (6) Via (5), the carbon nanotube (3) of one electrode (1) and the carbon nanotube (4) of the other electrode (2) were arranged to face each other, and a sandwich body (17) was produced. Then, it dried at 150-200 degreeC for 24 hours.

第３工程
同じく図５において、乾燥窒素雰囲気下にグローブボックス内で電解液（テトラエチルアンモニウムテトラフルオロボレートのプロピレンカーボネート溶液（濃度＝１ｍｏｌ／ｌ））を容器(6) 内に注入し、カーボンナノチューブ(3) (4) に含浸させた。電解液の量は１ｃｍ２当たり１〜３ｃｃとした。 Step 3 Similarly, in FIG. 5, an electrolytic solution (a solution of tetraethylammonium tetrafluoroborate in propylene carbonate (concentration = 1 mol / l)) was poured into a container (6) in a glove box under a dry nitrogen atmosphere, and carbon nanotubes ( 3) Impregnation into (4). The amount of the electrolyte was 1 to 3 cc per 1 cm 2 .

その後、ポリプロピレン製ガスケットを用いて容器(6) の口部をステンレス鋼製の蓋材(7) でかしめ封口した。こうして、上側電極(1) が陽極で下側電極(2) が陰極である電気二重層キャパシタ(8) を作製した。   Thereafter, the mouth of the container (6) was caulked with a stainless steel lid (7) using a polypropylene gasket. Thus, an electric double layer capacitor (8) in which the upper electrode (1) was an anode and the lower electrode (2) was a cathode was produced.

第４工程
図６に示すように、複数の長方形の透孔(9) を有する未硬化絶縁板枠(10)を用意した。未硬化絶縁板枠(10)はプリプレグで構成されたものである。透孔(9) は、図１３に示すように、複数の透孔(9) は縦横に並んだ碁盤目状のパターンをなす。 Fourth Step As shown in FIG. 6, an uncured insulating plate frame (10) having a plurality of rectangular through holes (9) was prepared. The uncured insulating plate frame (10) is composed of a prepreg. As shown in FIG. 13, the through holes (9) have a grid pattern in which the plurality of through holes (9) are arranged vertically and horizontally.

未硬化絶縁板枠(10)の各透孔(9) に前工程で得られた電気二重層キャパシタ(8) を嵌込んだ。こうしてキャパシタ組込み未硬化絶縁板枠(10)を作製した。未硬化絶縁板枠(10)の厚さは電気二重層キャパシタ(8) の厚さと同じであり、したがってキャパシタ組込み未硬化絶縁板枠(11)の両側面はそれぞれ面一となった。   The electric double layer capacitor (8) obtained in the previous step was fitted into each through hole (9) of the uncured insulating plate frame (10). In this way, an uncured insulating frame (10) with a built-in capacitor was produced. The thickness of the uncured insulating board frame (10) was the same as the thickness of the electric double layer capacitor (8). Therefore, both side surfaces of the capacitor built-in uncured insulating board frame (11) were flush with each other.

第５工程
同じく図６において、キャパシタ組込み絶縁板枠(11)の両側に、アルミニウムまたは銅製の回路(13)を有する回路層(12)を積層し、上側回路層(12)の上に電子部品設置層(14)を積層した。 Step 5 Similarly, in FIG. 6, a circuit layer (12) having an aluminum or copper circuit (13) is laminated on both sides of the capacitor built-in insulating plate frame (11), and an electronic component is formed on the upper circuit layer (12). The installation layer (14) was laminated.

第６工程
その後、図７に示すように、未硬化絶縁板枠(10)を構成するプリプレグを熱硬化させ、電気二重層キャパシタ(8) を硬化絶縁板枠(10)に固定し、キャパシタ組込み絶縁板枠(11)を得た。 Step 6 After that, as shown in FIG. 7, the prepreg constituting the uncured insulating plate frame (10) is thermally cured, and the electric double layer capacitor (8) is fixed to the cured insulating plate frame (10), and the capacitor is incorporated. An insulating plate frame (11) was obtained.

第７工程
図８に示すように、キャパシタ組込み絶縁板枠(11)、回路層(12)および電子部品設置層(14)を貫通して所要位置で回路(13)に接続するスルーホール(15)を開けた。こうしてキャパシタ組込みプリント基板(16)を作製した。電子部品設置層(14)の上に高速動作素子が配置されスルーホール(15)に接続される。 Seventh Step As shown in FIG. 8, through holes (15) that penetrate through the capacitor built-in insulating plate frame (11), the circuit layer (12), and the electronic component installation layer (14) and connect to the circuit (13) at a required position. ) Was opened. Thus, a capacitor-embedded printed circuit board (16) was produced. A high-speed operation element is disposed on the electronic component installation layer (14) and connected to the through hole (15).

なお、硬化絶縁板枠(10)と回路層(12)の接着強度を上げるために、硬化絶縁板枠(10)と回路層(12)の間に絶縁板を介在させ、回路(13)と電気二重層キャパシタ(8) を接続する構成としてもよい。   In order to increase the adhesive strength between the cured insulating frame (10) and the circuit layer (12), an insulating plate is interposed between the cured insulating frame (10) and the circuit layer (12), and the circuit (13) An electric double layer capacitor (8) may be connected.

実施例５
第１工程
実施例４の第１工程と同じ操作により片面に多数のカーボンナノチューブを有する一対の電極(1) (2) を得た。 Example 5
First Step By the same operation as in the first step of Example 4, a pair of electrodes (1) (2) having a large number of carbon nanotubes on one side was obtained.

第２工程
実施例４の第２工程と同じ操作によりサンドイッチ(17)を得た。これを図９に示す。 Second Step A sandwich (17) was obtained by the same operation as in the second step of Example 4. This is shown in FIG.

第３工程
図１３に示すように、多数の長方形の透孔(1) を有する硬化絶縁板枠(20)を用意した。硬化絶縁板枠(20)はプリプレグを硬化させて構成したものであり、複数１の透孔(9) は縦横に並んだ碁盤目状のパターンをなす。 Third Step As shown in FIG. 13, a cured insulating plate frame (20) having a number of rectangular through holes (1) was prepared. The cured insulating plate frame (20) is formed by curing a prepreg, and the plurality of through holes (9) form a grid pattern arranged vertically and horizontally.

図１０において、硬化絶縁板枠(20)の各透孔(9) に前工程で得られたサンドイッチ(17)を嵌込んで、キャパシタ組込み硬化絶縁板枠(18)を作製した。硬化絶縁板枠(20)の厚さはサンドイッチ(17)の厚さと同じであり、したがってキャパシタ組込み絶縁板枠(18)の両側面はそれぞれ面一となった。   In FIG. 10, the sandwich (17) obtained in the previous step was fitted into each through hole (9) of the cured insulating plate frame (20) to produce a capacitor built-in cured insulating plate frame (18). The thickness of the cured insulating plate frame (20) was the same as that of the sandwich (17), and therefore both side surfaces of the capacitor built-in insulating plate frame (18) were flush with each other.

第４工程
図１１に示すように、キャパシタ組込み絶縁板枠(18)の両側に、アルミニウムまたは銅製の回路(13)を内装した回路層(12)を積層し、上側回路層(12)の上に電子部品設置層(14)を積層し、さらに、乾燥窒素雰囲気下に実施例１と同じ構成の電解液を各透孔(9) 内に注入し、カーボンナノチューブに含浸させた。電解液の量は１ｃｍ２当たり１〜３ｃｃとした。 Fourth Step As shown in FIG. 11, a circuit layer (12) with an aluminum or copper circuit (13) is laminated on both sides of the capacitor-embedded insulating plate frame (18), and the upper circuit layer (12) is formed. Then, an electronic component installation layer (14) was laminated, and an electrolytic solution having the same structure as in Example 1 was injected into each through-hole (9) in a dry nitrogen atmosphere to impregnate the carbon nanotubes. The amount of the electrolyte was 1 to 3 cc per 1 cm 2 .

第５工程
図１２に示すように、実施例４の第７工程と同じ操作によりキャパシタ組込みプリント基板(16)を作製した。 Fifth Step As shown in FIG. 12, a capacitor-embedded printed circuit board (16) was produced by the same operation as in the seventh step of Example 4.

図１は実施例１における電気二重層キャパシタを概略的に示す垂直断面図である。1 is a vertical sectional view schematically showing an electric double layer capacitor in Example 1. FIG. 図２は実施例２における電気二重層キャパシタを概略的に示す垂直断面図である。FIG. 2 is a vertical sectional view schematically showing the electric double layer capacitor in the second embodiment. 図３は実施例３における電気二重層キャパシタを概略的に示す垂直断面図である。FIG. 3 is a vertical sectional view schematically showing the electric double layer capacitor in the third embodiment. 図４は実施例４における第１工程を概略的に示す垂直断面図である。FIG. 4 is a vertical sectional view schematically showing a first step in the fourth embodiment. 図５は実施例４における第２工程および第３工程を概略的に示す垂直断面図である。FIG. 5 is a vertical sectional view schematically showing the second step and the third step in the fourth embodiment. 図６は実施例４における第４工程を概略的に示す垂直断面図である。FIG. 6 is a vertical sectional view schematically showing a fourth step in the fourth embodiment. 図７は実施例４における第６工程を概略的に示す垂直断面図である。FIG. 7 is a vertical sectional view schematically showing a sixth step in the fourth embodiment. 図８は実施例４における第７工程を概略的に示す垂直断面図である。FIG. 8 is a vertical sectional view schematically showing a seventh step in the fourth embodiment. 図９は実施例５における第１工程および第２工程を概略的に示す垂直断面図である。FIG. 9 is a vertical sectional view schematically showing a first step and a second step in the fifth embodiment. 図１０は実施例５における第３工程を概略的に示す垂直断面図である。FIG. 10 is a vertical sectional view schematically showing a third step in the fifth embodiment. 図１１は実施例５における第４工程を概略的に示す垂直断面図である。FIG. 11 is a vertical sectional view schematically showing a fourth step in the fifth embodiment. 図１２は実施例５における第５工程を概略的に示す垂直断面図である。FIG. 12 is a vertical sectional view schematically showing a fifth step in the fifth embodiment. 図１３は、複数の透孔が縦横に並んだ碁盤目状のパターンをなす例を概略的に示す平面図である。FIG. 13 is a plan view schematically showing an example of a grid pattern in which a plurality of through holes are arranged vertically and horizontally. 図１４は、複数の透孔が絶縁板枠の必要部分に偏在する例を概略的に示す平面図である。FIG. 14 is a plan view schematically showing an example in which a plurality of through holes are unevenly distributed in necessary portions of the insulating plate frame.

符号の説明Explanation of symbols

(1) (2) (24)(25)：電極
(3) (4) (22)(23)(27)：カーボンナノチューブ
(5) (26)：セパレータ
(6) (21)：容器
(7) ：蓋材
(8) ：電気二重層キャパシタ
(9) ：透孔
(10)：未硬化絶縁板枠
(11)：キャパシタ組込み未硬化絶縁板枠
(12)：回路層
(13)：回路
(14)：電子部品設置層
(15)：スルーホール
(16)：プリント基板
(17)：サンドイッチ体
(18)：キャパシタ組込み硬化絶縁板枠
(19)：高速動作素子＾
(20)：硬化絶縁板枠
(28)(29)：内部電極
(30)：多層内部電極群 (1) (2) (24) (25): Electrode
(3) (4) (22) (23) (27): Carbon nanotube
(5) (26): Separator
(6) (21): Container
(7): Cover material
(8): Electric double layer capacitor
(9): Through hole
(10): Uncured insulating frame
(11): Uncured insulating frame with built-in capacitor
(12): Circuit layer
(13): Circuit
(14): Electronic component installation layer
(15): Through hole
(16): Printed circuit board
(17): Sandwich body
(18): Hardened insulation board frame with built-in capacitor
(19): High-speed operation element
(20): Hardened insulation board frame
(28) (29): Internal electrode
(30): Multilayer internal electrode group

Claims (6)

片面に多数のカーボンナノチューブを有する一対の電極が、セパレータを介して、一方の電極のカーボンナノチューブ群と他方の電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタ。   A pair of electrodes having a large number of carbon nanotubes on one side are arranged so that the carbon nanotube group of one electrode and the carbon nanotube group of the other electrode face each other through a separator, and the carbon nanotube group is impregnated with an electrolytic solution. An electric double layer capacitor. 両面に多数のカーボンナノチューブを有する１枚の内部電極が、片面に多数のカーボンナノチューブを有する一対の側部電極で、セパレータを介してサンドイッチされ、一対の側部電極は、一方の側部電極のカーボンナノチューブ群と他方の側部電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタ。   One internal electrode having a large number of carbon nanotubes on both sides is sandwiched by a pair of side electrodes having a large number of carbon nanotubes on one side via a separator, and the pair of side electrodes is connected to one side electrode. An electric double layer capacitor in which a carbon nanotube group and a carbon nanotube group on the other side electrode are arranged to face each other, and the carbon nanotube group is impregnated with an electrolytic solution. 両面に多数のカーボンナノチューブを有する複数枚の内部電極がセパレータを介して多層状に配置され、この多層内部電極群が、片面に多数のカーボンナノチューブを有する一対の側部電極で、側部セパレータを介してサンドイッチされ、一対の側部電極は、一方の側部電極のカーボンナノチューブ群と他方の側部電極のカーボンナノチューブ群が対向するように配置され、カーボンナノチューブ群に電解液が含浸されてなる、電気二重層キャパシタ。   A plurality of internal electrodes having a large number of carbon nanotubes on both sides are arranged in a multilayer shape with a separator interposed therebetween, and this multi-layered internal electrode group is a pair of side electrodes having a large number of carbon nanotubes on one side. The pair of side electrodes are arranged so that the carbon nanotube group of one side electrode and the carbon nanotube group of the other side electrode face each other, and the carbon nanotube group is impregnated with an electrolytic solution. Electric double layer capacitor. 請求項１〜３のいずれかに記載の電気二重層キャパシタが、所定パターンで多数の透孔を有する絶縁板枠の各透孔に嵌込まれ、両側に回路層が積層されてなる、キャパシタ組込みプリント基板。   The electric double layer capacitor according to any one of claims 1 to 3, wherein the electric double layer capacitor is embedded in each through hole of an insulating plate frame having a plurality of through holes in a predetermined pattern, and a circuit layer is laminated on both sides. Printed board. 請求項１〜３のいずれかに記載の電気二重層キャパシタを、所定パターンで多数の透孔を有する未硬化絶縁板枠の各透孔に嵌込み、次いで同絶縁板枠を硬化させ、硬化絶縁板枠の両側に回路層を積層する、キャパシタ組込みプリント基板の製造方法。 The electric double layer capacitor according to any one of claims 1 to 3 is fitted into each through hole of an uncured insulating plate frame having a large number of through holes in a predetermined pattern, and then the insulating plate frame is cured and cured insulation A method of manufacturing a printed circuit board with a built-in capacitor, in which circuit layers are laminated on both sides of a board frame. 請求項１〜３のいずれかに記載の電気二重層キャパシタを、所定パターンで多数の透孔を有する硬化絶縁板枠の各透孔に嵌込み、次いで、硬化絶縁板枠の両側に回路層を積層する、キャパシタ組込みプリント基板の製造方法。 The electric double layer capacitor according to any one of claims 1 to 3 is fitted into each through hole of a cured insulating plate frame having a plurality of through holes in a predetermined pattern, and then a circuit layer is provided on both sides of the cured insulating plate frame. A method for manufacturing a printed circuit board with a built-in capacitor.
JP2003417972A 2003-12-16 2003-12-16 Printed circuit board comprising capacitor Pending JP2005183443A (en)

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JP2009267340A (en) * 2008-03-31 2009-11-12 Nippon Chemicon Corp Electrode for electric double layer capacitor and method for manufacturing the same
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