JP2005158848A - Method of manufacturing wiring circuit board - Google Patents

Method of manufacturing wiring circuit board Download PDF

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Publication number
JP2005158848A
JP2005158848A JP2003391862A JP2003391862A JP2005158848A JP 2005158848 A JP2005158848 A JP 2005158848A JP 2003391862 A JP2003391862 A JP 2003391862A JP 2003391862 A JP2003391862 A JP 2003391862A JP 2005158848 A JP2005158848 A JP 2005158848A
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Japan
Prior art keywords
thin film
metal thin
conductor layer
wiring circuit
conductor
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JP2003391862A
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Japanese (ja)
Inventor
Mitsuru Motogami
満 本上
Toshiki Naito
俊樹 内藤
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Nitto Denko Corp
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Nitto Denko Corp
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Priority to JP2003391862A priority Critical patent/JP2005158848A/en
Priority to US10/992,009 priority patent/US6996901B2/en
Publication of JP2005158848A publication Critical patent/JP2005158848A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0542—Continuous temporary metal layer over metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring circuit board which can prevent the peeling-off of a wiring circuit pattern by preventing a first metal thin film from being eaten away to the inside of a conductor layer due to the undercut of a plating resist. <P>SOLUTION: A base insulation layer 1 is prepared, and the first metal thin film 2 is formed on top of the base insulation layer 1. Then, on the first metal thin film 2, the pattern of the plating resist 3 which is the reverse of the wiring circuit pattern 4 is formed. On part of the metal thin film 2 not covered with the plating resist 3, the conductor layer 6 is formed in the same pattern as the wiring circuit pattern 4. Then, after removing the plating resist 3, a second metal thin film 8 is formed on the conductor layer 6 and on the first metal thin film 2, and then the second metal thin film 8 is removed. By removing the first metal thin film 2 except for part whereon the conductor layer 6 is formed, a flexible wiring circuit board is obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、配線回路基板の製造方法、詳しくは、フレキシブル配線回路基板の製造方法に関する。   The present invention relates to a method for manufacturing a printed circuit board, and more particularly to a method for manufacturing a flexible printed circuit board.

フレキシブル配線回路基板の製造において、配線回路パターンのパターンニング方法として、サブトラクティブ法と、アディティブ法とが知られている。これらのうち、携帯電話などの電子機器の液晶部分において必要とされる高精細パターンの形成には、アディティブ法が有利である。   In manufacturing a flexible printed circuit board, a subtractive method and an additive method are known as a patterning method for a printed circuit pattern. Of these, the additive method is advantageous for forming a high-definition pattern required in a liquid crystal portion of an electronic device such as a mobile phone.

このようなアディティブ法は、例えば、絶縁基板の表面全面に薄膜からなる第１導体を形成し、その第１導体上に導体パターンが開口するようにめっきレジストを形成し、第１導体上におけるめっきレジストに覆われていない部分に第２導体を形成し、その後、めっきレジストを除去し、次いで、第１導体における第２導体が形成されていない部分をエッチング処理により除去して導体パターンを形成する方法として知られている（例えば、特許文献１参照。）。   In such an additive method, for example, a first conductor made of a thin film is formed on the entire surface of an insulating substrate, a plating resist is formed on the first conductor so that a conductor pattern is opened, and plating on the first conductor is performed. The second conductor is formed on the portion not covered with the resist, and then the plating resist is removed, and then the portion of the first conductor where the second conductor is not formed is removed by etching to form a conductor pattern. It is known as a method (for example, refer to Patent Document 1).

特開２００３−３７１３７号公報JP 2003-37137 A

しかし、上記したアディティブ法では、図２（ａ）に示すように、絶縁基板２６上の第１導体２１上に形成しためっきレジスト２２において、第１導体２１に接触する底部に、下方に向かうに従って幅広となる裾引き部２３を生じるので、図２（ｂ）に示すように、第１導体２１上におけるめっきレジスト２２に覆われていない部分に第２導体２４を形成し、その後、図２（ｃ）に示すように、めっきレジスト２２を除去すると、第２導体２４には、裾引き部２３に起因して、第１導体２１に接触する底部に、下方に向かうに従って幅狭となるアンダーカット部２５を生じる。そのため、次いで、第１導体２１をエッチングにより除去すると、図２（ｄ）に示すように、そのアンダーカット部２５に起因して、第２導体２４の底部の第１導体２１が、第２導体２５の内側に大きくえぐられるようにエッチングされる。そうすると、絶縁基板２６と第１導体２１との接着力が大幅に低下して、絶縁基板２６から第１導体２１および第２導体２４からなる導体パターンが剥離するという不具合を生じる。   However, in the above-described additive method, as shown in FIG. 2A, in the plating resist 22 formed on the first conductor 21 on the insulating substrate 26, the bottom portion in contact with the first conductor 21 is directed downward. As shown in FIG. 2B, the second conductor 24 is formed on the portion of the first conductor 21 that is not covered with the plating resist 22, as shown in FIG. As shown in c), when the plating resist 22 is removed, the second conductor 24 has an undercut that becomes narrower toward the bottom at the bottom contacting the first conductor 21 due to the skirt 23. Part 25 is produced. Therefore, when the first conductor 21 is then removed by etching, the first conductor 21 at the bottom of the second conductor 24 is caused by the second conductor 24 due to the undercut portion 25 as shown in FIG. It is etched so that it can be greatly removed inside 25. As a result, the adhesive force between the insulating substrate 26 and the first conductor 21 is greatly reduced, causing a problem that the conductor pattern composed of the first conductor 21 and the second conductor 24 is peeled off from the insulating substrate 26.

本発明の目的は、めっきレジストのアンダーカット部に起因して、第１金属薄膜が導体層の内側に侵食されることを防止して、配線回路パターンの剥離を防止することのできる、配線回路基板の製造方法を提供することにある。   An object of the present invention is to prevent the first metal thin film from being eroded inside the conductor layer due to the undercut portion of the plating resist, thereby preventing the wiring circuit pattern from peeling off. It is to provide a method for manufacturing a substrate.

上記の目的を達成するため、本発明の配線回路基板の製造方法は、絶縁層を用意する工程、前記絶縁層の上に、第１金属薄膜を形成する工程、前記第１金属薄膜の上に、めっきレジストを配線回路パターンの反転パターンで形成する工程、前記めっきレジストから露出する前記第１金属薄膜の上に、導体層を配線回路パターンで形成する工程、前記めっきレジストを除去する工程、前記導体層および前記第１金属薄膜の上に、第２金属薄膜を形成する工程、前記第２金属薄膜を除去する工程、前記第１金属薄膜を、前記導体層が形成されている部分を除いて、除去する工程を備えていることを特徴としている。   In order to achieve the above object, a method for manufacturing a printed circuit board according to the present invention includes a step of preparing an insulating layer, a step of forming a first metal thin film on the insulating layer, and a step of forming on the first metal thin film. A step of forming a plating resist with a reversal pattern of a wiring circuit pattern, a step of forming a conductor layer with a wiring circuit pattern on the first metal thin film exposed from the plating resist, a step of removing the plating resist, A step of forming a second metal thin film on the conductor layer and the first metal thin film, a step of removing the second metal thin film, and the first metal thin film except for a portion where the conductor layer is formed. And a step of removing.

また、本発明の配線回路基板の製造方法においては、前記導体層および前記第２金属薄膜が、共に銅からなることが好適である。   In the method for manufacturing a wired circuit board according to the present invention, it is preferable that the conductor layer and the second metal thin film are both made of copper.

本発明の配線回路基板の製造方法において、めっきレジストにおいて、第１金属薄膜に接触する底部に、下方に向かうに従って幅広となる裾引き部が生じ、その裾引き部に起因して、導体層における金属薄膜に接触する底部に、下方に向かうに従って幅狭となるアンダーカット部が生じても、この方法では、第２金属薄膜の形成時において、第２金属薄膜を形成する金属がアンダーカット部に充填されるので、その後、第１金属薄膜の除去時に、アンダーカット部に起因して、導体層の底部の第１金属薄膜が、導体層の内側にえぐられるように侵食されることを防止することができる。その結果、絶縁層と第１金属薄膜との間の接着力の低下を防止することができ、絶縁層からの、第１金属薄膜および第２金属薄膜からなる配線回路パターンの剥離を有効に防止することができる。   In the method for manufacturing a printed circuit board according to the present invention, in the plating resist, a bottom portion that is widened toward the bottom is formed in the bottom portion that is in contact with the first metal thin film. Even if an undercut portion that becomes narrower toward the bottom is generated at the bottom portion that contacts the metal thin film, in this method, the metal that forms the second metal thin film is formed in the undercut portion when the second metal thin film is formed. After that, when the first metal thin film is removed, the first metal thin film at the bottom of the conductor layer is prevented from being eroded so as to get inside the conductor layer due to the undercut portion. be able to. As a result, it is possible to prevent a decrease in the adhesive force between the insulating layer and the first metal thin film, and effectively prevent peeling of the wiring circuit pattern composed of the first metal thin film and the second metal thin film from the insulating layer. can do.

また、本発明の配線回路基板の製造方法において、導体層および第２金属薄膜が、共に銅から形成されていれば、第２金属薄膜の形成時において、電気特性の良好な銅からなる導体層のアンダーカット部に、同じ金属である銅を充填することができる。そのため、配線回路パターンの剥離を防止しつつ、配線回路パターンの電気特性の低下を防止することができる。   In the method for manufacturing a printed circuit board according to the present invention, if both the conductor layer and the second metal thin film are made of copper, the conductor layer made of copper having good electrical characteristics when the second metal thin film is formed. The undercut portion can be filled with copper, which is the same metal. Therefore, it is possible to prevent the electrical characteristics of the wiring circuit pattern from being lowered while preventing the wiring circuit pattern from being peeled off.

図１は、本発明の配線回路基板の製造方法の一実施形態としての、フレキシブル配線回路基板の製造方法を示す製造工程図である。以下、図１を参照して、本発明の配線回路基板の製造方法の一実施形態であるフレキシブル配線回路基板の製造方法を説明する。   FIG. 1 is a manufacturing process diagram showing a method for manufacturing a flexible printed circuit board as an embodiment of a method for manufacturing a printed circuit board according to the present invention. Hereinafter, with reference to FIG. 1, the manufacturing method of the flexible wiring circuit board which is one Embodiment of the manufacturing method of the wiring circuit board of this invention is demonstrated.

この方法では、まず、図１（ａ）に示すように、ベース絶縁層１を用意する。ベース絶縁層１としては、例えば、ポリイミド樹脂、ポリアミドイミド樹脂、アクリル樹脂、ポリエーテルニトリル樹脂、ポリエーテルスルホン樹脂、ポリエチレンテレフタレート樹脂、ポリエチレンナフタレート樹脂、ポリ塩化ビニル樹脂、フッ素樹脂などの合成樹脂のフィルムが用いられ、好ましくは、ポリイミド樹脂のフィルムが用いられる。   In this method, first, an insulating base layer 1 is prepared as shown in FIG. Examples of the base insulating layer 1 include synthetic resins such as polyimide resin, polyamideimide resin, acrylic resin, polyether nitrile resin, polyether sulfone resin, polyethylene terephthalate resin, polyethylene naphthalate resin, polyvinyl chloride resin, and fluorine resin. A film is used, and a polyimide resin film is preferably used.

なお、ベース絶縁層１は、予めフィルムとして形成されているものを用いてもよく、また、感光性樹脂の溶液を成膜して、露光および現像することにより、所定パターンに形成した後に、硬化させたものを用いてもよい。   The insulating base layer 1 may be formed in advance as a film, or may be cured after being formed into a predetermined pattern by forming a photosensitive resin solution, exposing and developing the film. You may use what was made to do.

また、ベース絶縁層１の厚みは、通常、３〜１００μｍ、好ましくは、５〜５０μｍである。   The insulating base layer 1 has a thickness of usually 3 to 100 μm, preferably 5 to 50 μm.

次いで、この方法では、図１（ｂ）に示すように、ベース絶縁層１の上に、第１金属薄膜２を形成する。第１金属薄膜２を形成する金属は、例えば、クロム、ニッケル、銅などが好ましく用いられる。また、第１金属薄膜２の形成は、めっきや真空蒸着法などが用いられ、好ましくは、真空蒸着法、とりわけ、スパッタ蒸着法が用いられる。より具体的には、例えば、ベース絶縁層１の表面全面に、クロム薄膜と銅薄膜とをスパッタ蒸着法によって順次に形成する。   Next, in this method, as shown in FIG. 1B, the first metal thin film 2 is formed on the base insulating layer 1. As the metal forming the first metal thin film 2, for example, chromium, nickel, copper, or the like is preferably used. The first metal thin film 2 is formed by plating, vacuum vapor deposition, or the like, preferably vacuum vapor deposition, especially sputter vapor deposition. More specifically, for example, a chromium thin film and a copper thin film are sequentially formed on the entire surface of the base insulating layer 1 by sputtering deposition.

なお、第１金属薄膜２の厚みは、通常、１ｎｍ〜６μｍ、好ましくは、５０ｎｍ〜５μｍである。   In addition, the thickness of the 1st metal thin film 2 is 1 nm-6 micrometers normally, Preferably, it is 50 nm-5 micrometers.

次いで、この方法では、図１（ｃ）に示すように、第１金属薄膜２の上に、めっきレジスト３を配線回路パターン４の反転パターンで形成する。   Next, in this method, as shown in FIG. 1C, a plating resist 3 is formed on the first metal thin film 2 as an inverted pattern of the wiring circuit pattern 4.

めっきレジスト３は、特に制限されないが、例えば、ドライフィルムレジストを、第１金属薄膜２の全面に積層した後、露光および現像することにより、配線回路パターン４の反転パターンのレジストパターンとして形成する。なお、このようにして形成されるめっきレジスト３には、第１金属薄膜２に接触する底部において、下方に向かうに従って幅広となる断面略三角形状の裾引き部５を両側に生じる。   Although the plating resist 3 is not particularly limited, for example, a dry film resist is laminated on the entire surface of the first metal thin film 2 and then exposed and developed to form a resist pattern of an inverted pattern of the wiring circuit pattern 4. In the plating resist 3 formed in this manner, the bottom portions in contact with the first metal thin film 2 are provided with skirts 5 having a substantially triangular cross-section that become wider toward the lower side on both sides.

なお、めっきレジスト３の厚みは、通常、５〜３０μｍ、好ましくは、１０〜２０μｍである。各裾引き部５の最底部の幅Ｗ１は、通常、１〜５μｍである。   In addition, the thickness of the plating resist 3 is 5-30 micrometers normally, Preferably, it is 10-20 micrometers. The width W1 of the bottom of each skirt 5 is normally 1 to 5 μm.

その後、この方法では、図１（ｄ）に示すように、めっきレジスト３から露出する第１金属薄膜２の上に、導体層６を配線回路パターン４で形成する。   Thereafter, in this method, as shown in FIG. 1 (d), the conductor layer 6 is formed with the wiring circuit pattern 4 on the first metal thin film 2 exposed from the plating resist 3.

導体層６の導体としては、例えば、銅、ニッケル、金、はんだ、または、これらの合金などの金属が用いられ、好ましくは、銅が用いられる。また、導体層６の形成は、無電解めっき、電解めっきなどのめっきが用いられ、好ましくは、電解めっきが用いられる。より具体的には、第１金属薄膜２におけるめっきレジスト３が形成されていない部分に、電解銅めっきにより、銅からなる導体層６を配線回路パターン４として形成する。電解銅めっきのめっき液としては、例えば、硫酸銅めっき液、ピロ燐酸銅めっき液などが用いられる。   As the conductor of the conductor layer 6, for example, a metal such as copper, nickel, gold, solder, or an alloy thereof is used, and copper is preferably used. The conductor layer 6 is formed by plating such as electroless plating or electrolytic plating, preferably electrolytic plating. More specifically, the conductor layer 6 made of copper is formed as the wiring circuit pattern 4 by electrolytic copper plating on the portion of the first metal thin film 2 where the plating resist 3 is not formed. As a plating solution for electrolytic copper plating, for example, a copper sulfate plating solution, a copper pyrophosphate plating solution, or the like is used.

なお、導体層６の厚みは、通常、３〜２０μｍ、好ましくは、５〜１５μｍであり、導体層６の幅は、通常、１５〜５００μｍ、好ましくは、２０〜３００μｍ、各導体層６の間隔は、通常、１５〜２００μｍ、好ましくは、２０〜３００μｍである。   The thickness of the conductor layer 6 is usually 3 to 20 μm, preferably 5 to 15 μm. The width of the conductor layer 6 is usually 15 to 500 μm, preferably 20 to 300 μm, and the distance between the conductor layers 6. Is usually 15 to 200 μm, preferably 20 to 300 μm.

次いで、この方法では、図１（ｅ）に示すように、めっきレジスト３を除去する。めっきレジスト３の除去は、例えば、エッチング液として水酸化ナトリウム溶液などのアルカリ溶液を用いる化学エッチング（ウェットエッチング）などの公知のエッチング法または剥離が用いられる。   Next, in this method, the plating resist 3 is removed as shown in FIG. For removing the plating resist 3, for example, a known etching method such as chemical etching (wet etching) using an alkali solution such as a sodium hydroxide solution as an etching solution or peeling is used.

めっきレジスト３が除去されると、導体層６におけるめっきレジスト３の裾引き部５が形成されていた底部には、下方に向かうに従って幅狭となる断面略三角形状のアンダーカット部７を両側に生じる。各アンダーカット部７の最底部の幅Ｗ２は、通常、１〜５μｍである。   When the plating resist 3 is removed, the bottom portion of the conductor layer 6 where the skirting portion 5 of the plating resist 3 is formed is provided with an undercut portion 7 having a substantially triangular cross section on both sides. Arise. The width W2 of the bottom part of each undercut part 7 is usually 1 to 5 μm.

そして、この方法では、図１（ｆ）に示すように、導体層６および第１金属薄膜２の上に、第２金属薄膜８を形成する。   In this method, the second metal thin film 8 is formed on the conductor layer 6 and the first metal thin film 2 as shown in FIG.

第２金属薄膜８を形成する金属は、導体層６を形成する金属と同様のものが用いられ、好ましくは、銅が用いられる。導体層６および第２金属薄膜８が、共に銅から形成されていれば、第２金属薄膜８の形成時において、電気特性の良好な銅からなる導体層６のアンダーカット部７に、同じ金属である銅を充填して金属埋設部９を形成することができる。そのため、配線回路パターン４の剥離を防止しつつ、配線回路パターン４の電気特性の低下を防止することができる。   The metal that forms the second metal thin film 8 is the same as the metal that forms the conductor layer 6, and preferably copper. If the conductor layer 6 and the second metal thin film 8 are both made of copper, the same metal is applied to the undercut portion 7 of the conductor layer 6 made of copper having good electrical characteristics when the second metal thin film 8 is formed. The metal embedded portion 9 can be formed by filling copper. Therefore, it is possible to prevent the electrical characteristics of the wiring circuit pattern 4 from being lowered while preventing the wiring circuit pattern 4 from being peeled off.

また、第２金属薄膜８の形成は、無電解めっき、電解めっきなどのめっきが用いられ、好ましくは、電解めっきが用いられる。より具体的には、導体層６の表面全面および導体層６から露出する第１金属薄膜２の表面全面に、電解銅めっきにより、銅からなる第２金属薄膜８を形成する。電解銅めっきのめっき液としては、例えば、硫酸銅めっき液、ピロ燐酸銅めっき液、あるいは、ビアフィル用めっき液などが用いられる。   The second metal thin film 8 is formed by plating such as electroless plating or electrolytic plating, preferably electrolytic plating. More specifically, the second metal thin film 8 made of copper is formed by electrolytic copper plating on the entire surface of the conductor layer 6 and the entire surface of the first metal thin film 2 exposed from the conductor layer 6. As a plating solution for electrolytic copper plating, for example, a copper sulfate plating solution, a pyrophosphate copper plating solution, a via fill plating solution, or the like is used.

これによって、第２金属薄膜８の形成時において、第２金属薄膜８を形成する金属が、導体層６のアンダーカット部７に充填されることにより、金属埋設部９が形成される。   Thus, when the second metal thin film 8 is formed, the metal forming the second metal thin film 8 is filled in the undercut portion 7 of the conductor layer 6, thereby forming the metal buried portion 9.

なお、第２金属薄膜８の厚みは、通常、０．３〜１０μｍ、好ましくは、１〜５μｍである。   In addition, the thickness of the 2nd metal thin film 8 is 0.3-10 micrometers normally, Preferably, it is 1-5 micrometers.

次いで、この方法では、図１（ｇ）に示すように、第２金属薄膜８を除去する。第２金属薄膜８の除去は、例えば、エッチング液として塩化第二鉄溶液などを用いる化学エッチング（ウェットエッチング）などの公知のエッチング法が用いられる。なお、このエッチングでは、金属埋設部９以外の第２金属薄膜８が除去され、金属埋設部９は残存する。   Next, in this method, as shown in FIG. 1G, the second metal thin film 8 is removed. For the removal of the second metal thin film 8, for example, a known etching method such as chemical etching (wet etching) using a ferric chloride solution or the like as an etching solution is used. In this etching, the second metal thin film 8 other than the metal buried portion 9 is removed, and the metal buried portion 9 remains.

なお、この第２金属薄膜８の除去において、例えば、第２金属薄膜８が銅から形成され、第１金属薄膜２がクロム薄膜および銅薄膜から順次形成されている場合などでは、図示しないが、第２金属薄膜８の除去とともに、第１金属薄膜２における導体層６から露出する銅箔膜も同時に除去され、第１金属薄膜２として、クロム薄膜のみが残存する。   In the removal of the second metal thin film 8, for example, in the case where the second metal thin film 8 is formed from copper and the first metal thin film 2 is sequentially formed from a chrome thin film and a copper thin film, it is not illustrated. Along with the removal of the second metal thin film 8, the copper foil film exposed from the conductor layer 6 in the first metal thin film 2 is also removed at the same time, and only the chromium thin film remains as the first metal thin film 2.

その後、この方法では、図１（ｈ）に示すように、第１金属薄膜２を、導体層６が形成されている部分を除いて除去することにより、フレキシブル配線回路基板を得る。   Thereafter, in this method, as shown in FIG. 1 (h), the first metal thin film 2 is removed except for the portion where the conductor layer 6 is formed, thereby obtaining a flexible printed circuit board.

第１金属薄膜２の除去は、例えば、第１金属薄膜２がクロム薄膜である場合には、エッチング液としてフェロシアン酸カリウム溶液などを用いる化学エッチング（ウェットエッチング）などの公知のエッチング法を用いて、導体層６から露出する第１金属薄膜２を除去する。これによって、第１金属薄膜２および導体層６からなる配線回路パターン４が形成される。   For the removal of the first metal thin film 2, for example, when the first metal thin film 2 is a chromium thin film, a known etching method such as chemical etching (wet etching) using a potassium ferrocyanate solution or the like as an etching solution is used. Then, the first metal thin film 2 exposed from the conductor layer 6 is removed. As a result, a wiring circuit pattern 4 composed of the first metal thin film 2 and the conductor layer 6 is formed.

そして、この方法では、必要により、図１（ｉ）に示すように、ベース絶縁層１の上に、配線回路パターン４を被覆するように、カバー絶縁層１０を形成する。   In this method, if necessary, an insulating cover layer 10 is formed on the insulating base layer 1 so as to cover the wiring circuit pattern 4 as shown in FIG.

カバー絶縁層１０としては、ベース絶縁層１と同様の合成樹脂が用いられ、好ましくは、ポリイミド樹脂が用いられる。カバー絶縁層１０の形成は、例えば、配線回路パターン４を含むベース絶縁層１の上に、感光性樹脂の溶液を成膜して、露光および現像することにより、所定パターンに形成した後に、硬化させる。   As the insulating cover layer 10, the same synthetic resin as that of the insulating base layer 1 is used, and preferably, a polyimide resin is used. The insulating cover layer 10 is formed, for example, by forming a solution of a photosensitive resin on the insulating base layer 1 including the wiring circuit pattern 4 and exposing and developing it to form a predetermined pattern, followed by curing. Let

なお、カバー絶縁層１０の厚みは、通常、２〜５０μｍ、好ましくは、５〜３０μｍである。   The insulating cover layer 10 has a thickness of usually 2 to 50 μm, preferably 5 to 30 μm.

そして、このようなフレキシブル配線回路基板の製造方法によれば、めっきレジスト３の形成時に、めっきレジスト３における第１金属薄膜２に接触する底部に裾引き部７が生じ、その裾引き部７に起因して、導体層６における第１金属薄膜２に接触する底部にアンダーカット部７が生じても、第２金属薄膜８の形成時に、第２金属薄膜８を形成する金属がアンダーカット部７に充填されて金属埋設部９が形成される。そのため、その後、第１金属薄膜２の除去時に、アンダーカット部７に起因して、導体層６の底部の第１金属薄膜２が、導体層６の内側にえぐられるように侵食されることを防止することができる。その結果、ベース絶縁層１と第１金属薄膜２との間の接着力の低下を防止することができ、ベース絶縁層１からの、第１金属薄膜２および第２金属薄膜８からなる配線回路パターン４の剥離を有効に防止することができる。   According to such a method for manufacturing a flexible printed circuit board, when the plating resist 3 is formed, the bottom portion 7 is formed at the bottom portion of the plating resist 3 that contacts the first metal thin film 2, and the bottom portion 7 has the bottom portion 7. As a result, even if the undercut portion 7 is generated at the bottom portion of the conductor layer 6 that contacts the first metal thin film 2, the metal that forms the second metal thin film 8 is the undercut portion 7 when the second metal thin film 8 is formed. The metal burying portion 9 is formed. Therefore, after that, when the first metal thin film 2 is removed, the first metal thin film 2 at the bottom of the conductor layer 6 is eroded so as to be swept inside the conductor layer 6 due to the undercut portion 7. Can be prevented. As a result, a decrease in the adhesive force between the base insulating layer 1 and the first metal thin film 2 can be prevented, and the wiring circuit comprising the first metal thin film 2 and the second metal thin film 8 from the base insulating layer 1. The peeling of the pattern 4 can be effectively prevented.

そのため、このようなフレキシブル配線回路基板の製造方法は、携帯電話などの電子機器の液晶部分において必要とされる高精細の配線回路パターンの形成に有利であり、従って、そのような高精細の配線回路パターンの形成が要求されるフレキシブル配線回路基板の製造方法として、有効に用いることができる。   Therefore, such a method for manufacturing a flexible printed circuit board is advantageous for forming a high-definition wiring circuit pattern required in a liquid crystal part of an electronic device such as a mobile phone, and therefore, such a high-definition wiring is used. It can be effectively used as a method for manufacturing a flexible printed circuit board that requires formation of a circuit pattern.

なお、上記の説明において、例えば、第１金属薄膜２と第２金属薄膜８とが、同じ金属で形成されている場合などにおいては、図１（ｇ）に示す第２金属薄膜８の除去と、図１（ｈ）に示す第１金属薄膜２の除去とを、区別せずに同時に実施してもよい。   In the above description, for example, when the first metal thin film 2 and the second metal thin film 8 are formed of the same metal, the removal of the second metal thin film 8 shown in FIG. The removal of the first metal thin film 2 shown in FIG. 1 (h) may be performed simultaneously without distinction.

なお、上記の説明では、フレキシブル配線回路基板を、ベース絶縁層１の上に、配線回路パターン４およびカバー絶縁層１０を形成したが、例えば、ベース絶縁層１を、金属支持層の上に形成して、そのベース絶縁層１の上に、配線回路パターン４およびカバー絶縁層１０を形成してもよい。   In the above description, the flexible printed circuit board is formed on the insulating base layer 1 with the wiring circuit pattern 4 and the insulating cover layer 10. For example, the insulating base layer 1 is formed on the metal support layer. Then, the wiring circuit pattern 4 and the cover insulating layer 10 may be formed on the base insulating layer 1.

また、上記した製造方法は、工業的には、例えば、ロールツーロール法などの公知の方法により、製造することができる。   In addition, the above-described manufacturing method can be industrially manufactured by a known method such as a roll-to-roll method.

以下、実施例および比較例を挙げて、本発明をさらに具体的に説明する。   Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples.

実施例１
厚み２５μｍのポリイミド樹脂のフィルムからなるベース絶縁層を用意して（図１（ａ）参照）、このベース絶縁層の上に、厚み２０ｎｍのクロム薄膜および厚み２００ｎｍの銅箔をスパッタ蒸着法により順次形成することにより、第１金属薄膜を形成した（図１（ｂ）参照）。次いで、ドライフィルムレジストを、第１金属薄膜の全面に積層した後、露光および現像することにより、配線回路パターンの反転パターンのレジストパターンとして、厚み１５μｍのめっきレジストを形成した（図１（ｃ）参照）。なお、このようにして形成されためっきレジストには、第１金属薄膜に接触する底部において、下方に向かうに従って幅広となる断面略三角形状の裾引き部が両側に生じた。 Example 1
A base insulating layer made of a polyimide resin film having a thickness of 25 μm is prepared (see FIG. 1A), and a chromium thin film having a thickness of 20 nm and a copper foil having a thickness of 200 nm are sequentially formed on the insulating base layer by a sputtering deposition method. By forming, the 1st metal thin film was formed (refer FIG.1 (b)). Next, after depositing a dry film resist on the entire surface of the first metal thin film, exposure and development were performed to form a plating resist having a thickness of 15 μm as a resist pattern of an inversion pattern of the wiring circuit pattern (FIG. 1C). reference). In the plating resist formed in this manner, skirting portions having a substantially triangular cross-section that became wider toward the lower side were formed on both sides at the bottom portion in contact with the first metal thin film.

その後、めっきレジストから露出する第１金属薄膜の上に、硫酸銅めっき液を用いる電解銅めっきにより、厚み１０μｍの導体層を配線回路パターンで形成した（図１（ｄ）参照）。導体層の幅は２５μｍ、各導体層の間隔は２５μｍに設定した。その後、めっきレジストを、水酸化ナトリウム溶液を用いる化学エッチングにより除去した（図１（ｅ）参照）。そうすると、導体層におけるめっきレジストの裾引き部が形成されていた底部には、下方に向かうに従って幅狭となる断面略三角形状のアンダーカット部が両側それぞれ２μｍの幅（最底部幅）で生じた。   Thereafter, a conductor layer having a thickness of 10 μm was formed in a wiring circuit pattern on the first metal thin film exposed from the plating resist by electrolytic copper plating using a copper sulfate plating solution (see FIG. 1D). The width of the conductor layer was set to 25 μm, and the interval between the conductor layers was set to 25 μm. Thereafter, the plating resist was removed by chemical etching using a sodium hydroxide solution (see FIG. 1 (e)). As a result, an undercut portion having a substantially triangular cross-section that becomes narrower in the downward direction at the bottom portion where the skirt portion of the plating resist in the conductor layer was formed has a width of 2 μm on each side (bottom width). .

そして、導体層の表面全面および導体層から露出する第１金属薄膜の表面全面に、硫酸銅めっき液を用いる電解銅めっきにより、厚み２μｍの第２金属薄膜を形成した（図１（ｆ）参照）。この第２金属薄膜の形成時において、第２金属薄膜を形成する銅が、導体層のアンダーカット部に充填されることにより、金属埋設部が形成された。   Then, a 2 μm-thick second metal thin film was formed by electrolytic copper plating using a copper sulfate plating solution on the entire surface of the conductor layer and on the entire surface of the first metal thin film exposed from the conductor layer (see FIG. 1F). ). At the time of forming the second metal thin film, the copper forming the second metal thin film was filled in the undercut portion of the conductor layer, thereby forming the metal buried portion.

次いで、第２金属薄膜を、塩化第二鉄溶液を用いる化学エッチングにより除去した（図１（ｇ）参照）。なお、このエッチングでは、金属埋設部以外の第２金属薄膜が除去され、金属埋設部が残存した。   Next, the second metal thin film was removed by chemical etching using a ferric chloride solution (see FIG. 1 (g)). In this etching, the second metal thin film other than the metal buried portion was removed, and the metal buried portion remained.

その後、第１金属薄膜を、フェロシアン酸カリウム溶液を用いる化学エッチングにより除去することにより、フレキシブル配線回路基板を得た（図１（ｈ）参照）。   Thereafter, the first metal thin film was removed by chemical etching using a potassium ferrocyanate solution to obtain a flexible printed circuit board (see FIG. 1 (h)).

得られたフレキシブル配線回路基板では、導体層における第１金属薄膜に接触する底部のアンダーカット部に、金属埋設部が充填形成され、配線回路パターン１本当たりのピール強度が、２．０ｇであった。   In the obtained flexible printed circuit board, a metal buried portion is filled and formed in the bottom undercut portion that contacts the first metal thin film in the conductor layer, and the peel strength per wired circuit pattern was 2.0 g. It was.

比較例１
第２金属薄膜の形成工程およびその除去工程を省略した以外は、実施例１と同様の方法により、フレキシブル配線回路基板を得た。 Comparative Example 1
A flexible printed circuit board was obtained by the same method as in Example 1 except that the second metal thin film forming step and the removing step thereof were omitted.

得られたフレキシブル配線回路基板では、導体層における第１金属薄膜に接触する底部のアンダーカット部に起因して、導体層の底部の第１金属薄膜が、導体層の内側に大きくえぐられるようにエッチングされ、配線回路パターン１本当たりのピール強度が、０．５ｇであった。   In the obtained flexible printed circuit board, the first metal thin film at the bottom of the conductor layer is largely swept inside the conductor layer due to the undercut portion at the bottom contacting the first metal thin film in the conductor layer. Etching was performed, and the peel strength per wiring circuit pattern was 0.5 g.

本発明の配線回路基板の製造方法の一実施形態としての、フレキシブル配線回路基板の製造方法を示す製造工程図であって、（ａ）は、ベース絶縁層を用意する工程、（ｂ）は、ベース絶縁層の上に、第１金属薄膜を形成する工程、（ｃ）は、第１金属薄膜の上に、めっきレジストを配線回路パターンの反転パターンで形成する工程、（ｄ）は、めっきレジストから露出する第１金属薄膜の上に、導体層を配線回路パターンで形成する工程、（ｅ）は、めっきレジストを除去する工程、（ｆ）は、導体層および第１金属薄膜の上に、第２金属薄膜を形成する工程、（ｇ）は、第２金属薄膜を除去する工程、（ｈ）は、第１金属薄膜を、導体層が形成されている部分を除いて除去する工程（ｉ）は、ベース絶縁層の上に、配線回路パターンを被覆するように、カバー絶縁層を形成する工程を示す。It is a manufacturing process figure which shows the manufacturing method of the flexible printed circuit board as one embodiment of the manufacturing method of the printed circuit board of the present invention, (a) is the process of preparing a base insulating layer, (b) A step of forming a first metal thin film on the base insulating layer, (c) a step of forming a plating resist on the first metal thin film in an inverted pattern of the wiring circuit pattern, and (d) a plating resist. Forming a conductor layer with a wiring circuit pattern on the first metal thin film exposed from the step, (e) removing the plating resist, and (f) on the conductor layer and the first metal thin film, A step of forming a second metal thin film, (g) a step of removing the second metal thin film, and (h) a step of removing the first metal thin film except a portion where the conductor layer is formed (i). ) Cover the wiring circuit pattern on the base insulating layer. As to, a process of forming an insulating cover layer. 従来のフレキシブル配線回路基板の製造方法を示す製造工程図であって、（ａ）は、第１導体上にめっきレジストを形成する工程、（ｂ）は、第１導体上におけるめっきレジストに覆われていない部分に第２導体を形成する工程、（ｃ）は、めっきレジストを除去する工程、（ｄ）は、第１導体における第２導体が形成されていない部分を除去する工程を示す。It is a manufacturing process figure which shows the manufacturing method of the conventional flexible printed circuit board, Comprising: (a) is the process of forming a plating resist on a 1st conductor, (b) is covered with the plating resist on a 1st conductor. (C) shows a step of removing the plating resist, and (d) shows a step of removing a portion of the first conductor where the second conductor is not formed.

符号の説明Explanation of symbols

１ ベース絶縁層
２ 第１金属薄膜
３ めっきレジスト
４ 配線回路パターン
６ 導体層
８ 第２金属薄膜
DESCRIPTION OF SYMBOLS 1 Base insulating layer 2 1st metal thin film 3 Plating resist 4 Wiring circuit pattern 6 Conductor layer 8 2nd metal thin film

Claims (2)

絶縁層を用意する工程、
前記絶縁層の上に、第１金属薄膜を形成する工程、
前記第１金属薄膜の上に、めっきレジストを配線回路パターンの反転パターンで形成する工程、
前記めっきレジストから露出する前記第１金属薄膜の上に、導体層を配線回路パターンで形成する工程、
前記めっきレジストを除去する工程、
前記導体層および前記第１金属薄膜の上に、第２金属薄膜を形成する工程、
前記第２金属薄膜を除去する工程、
前記第１金属薄膜を、前記導体層が形成されている部分を除いて、除去する工程
を備えていることを特徴とする、配線回路基板の製造方法。 Preparing an insulating layer;
Forming a first metal thin film on the insulating layer;
Forming a plating resist in an inverted pattern of a wiring circuit pattern on the first metal thin film;
Forming a conductor layer with a wiring circuit pattern on the first metal thin film exposed from the plating resist;
Removing the plating resist;
Forming a second metal thin film on the conductor layer and the first metal thin film;
Removing the second metal thin film;
A method for producing a printed circuit board, comprising: removing the first metal thin film except for a portion where the conductor layer is formed. 前記導体層および前記第２金属薄膜が、ともに銅からなることを特徴とする、請求項１に記載の配線回路基板の製造方法。 The method for manufacturing a printed circuit board according to claim 1, wherein both the conductor layer and the second metal thin film are made of copper.
JP2003391862A 2003-11-21 2003-11-21 Method of manufacturing wiring circuit board Pending JP2005158848A (en)

Priority Applications (2)

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JP2003391862A JP2005158848A (en) 2003-11-21 2003-11-21 Method of manufacturing wiring circuit board
US10/992,009 US6996901B2 (en) 2003-11-21 2004-11-19 Production method of wired circuit board

Applications Claiming Priority (1)

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Publications (1)

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US20050115066A1 (en) 2005-06-02

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